CMOS集成器件的制造方法
By forming sidewall structures on both sides of the gate structure of a CMOS integrated device and adjusting the sidewall length using an etching compensation process, the problem of poor stability of CMOS devices is solved, and the stability and speed of the device are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI HUAHONG GRACE SEMICON MFG CORP
- Filing Date
- 2022-10-26
- Publication Date
- 2026-07-17
AI Technical Summary
In the prior art, the uneven thickness of the gate structure of CMOS integrated devices leads to poor device stability. Especially in the L90 process platform, when 1.5V and 3.3V CMOS devices share the same photomask and ion implantation conditions, the device stability cannot meet the design requirements.
An etching compensation process is used to form sidewall structures on both sides of the gate structure. By controlling the main etching and over-etching times, the length of the sidewall structures is adjusted to achieve uniformity of the gate material layer thickness and device stability.
The sidewall structure is formed by etching compensation process, which stabilizes the stability of CMOS integrated devices, shortens the channel length, and improves the device execution speed.
Smart Images
Figure CN115910929B_ABST