An insulating packaging structure and method for a power semiconductor device

Abstract

The application provides a power semiconductor device insulation packaging structure and an insulation packaging method, and the power semiconductor device insulation packaging structure comprises a conductive bottom plate, an insulation layer located on one side of the conductive bottom plate, a conductive layer located on the surface of the insulation layer away from the conductive bottom plate, and a shell located on one surface of the conductive bottom plate, wherein the shell and the conductive bottom plate form a containing space, the power semiconductor device, the insulation layer and the conductive layer are all located in the containing space, and the containing space is filled with an insulation filling medium; the difference between the dielectric constant of the contact area of the insulation layer and the dielectric constant of the insulation filling medium is 0-1, the small difference in the dielectric constant can improve the electric field distribution, thereby avoiding local discharge caused by the electric field concentration at the contact position, reducing the risk of breakdown of the insulation layer, and improving the insulation of the power semiconductor device insulation packaging structure.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor device packaging technology, and specifically to an insulating packaging structure and method for power semiconductor devices. Background Technology

[0002] To meet the needs of large-scale development and utilization of renewable energy, traditional power grids are evolving towards smart grids characterized by the widespread application of power electronics technology. This places higher demands on power semiconductor devices. To protect power semiconductor devices and facilitate their connection to external circuits, they are typically packaged, resulting in power semiconductor device package structures.

[0003] Differences in the dielectric constant of insulating materials in power semiconductor device packaging structures can easily lead to uneven electric field distribution. When the dielectric constant is distorted, electric field concentration occurs at the distorted location, resulting in partial discharge. The high-energy electrons and UV radiation generated by partial discharge can damage the surrounding insulating materials, increasing the risk of insulation breakdown and compromising the insulation performance of the power semiconductor device packaging structure. Specifically, the commonly used material for the insulating substrate in existing copper-clad laminates is ceramic, and the commonly used insulating filler is silicone gel. The dielectric constant of ceramic is 8-10, while that of silicone gel is around 2-3. This significant difference in dielectric constant between ceramic and silicone gel makes them prone to significant partial discharge at their contact points. Summary of the Invention

[0004] Therefore, the technical problem to be solved by the present invention is how to improve the insulation of the power semiconductor device packaging structure, thereby providing an insulating packaging structure and insulating packaging method for power semiconductor devices.

[0005] This invention provides an insulating package structure for a power semiconductor device, comprising: a conductive substrate; an insulating layer located on one side of the conductive substrate; a conductive layer located on the side surface of the insulating layer opposite to the conductive substrate; a housing located on one side surface of the conductive substrate, the housing and the conductive substrate forming an accommodating space, wherein the power semiconductor device, the insulating layer, and the conductive layer are all located within the accommodating space; and an insulating filling medium filling the accommodating space, wherein the difference between the dielectric constant of the contact region between the insulating layer and the insulating filling medium and the dielectric constant of the insulating filling medium is 0 to 1.

[0006] Optionally, the dielectric constant of the central region of the insulating layer is greater than the dielectric constant of the contact region between the insulating layer and the insulating filling medium.

[0007] Optionally, the insulating layer includes a polymer matrix and a dopant material dispersed in the polymer matrix. The difference between the dielectric constant of the polymer matrix and the dielectric constant of the insulating filling medium is 0 to 1. The dielectric constant of the dopant material is greater than that of the insulating filling medium. The doping concentration of the dopant material in the contact area between the insulating layer and the insulating filling medium is 0, and the doping concentration of the dopant material in the central region of the insulating layer is greater than 0.

[0008] Optionally, the side surface and central axis of the insulating layer are both perpendicular to the conductive layer and the conductive base plate, and the dielectric constant of the insulating layer increases from the side surface to the central axis.

[0009] Optionally, the doping concentration of the doped material increases from the side to the central axis, and the polymer matrix of the insulating layer is made of the same material.

[0010] Optionally, the conductive layer includes a first lead-out area, a second lead-out area, and a hollow area located between the first lead-out area and the second lead-out area, and a portion of the surface of the insulating layer facing away from the conductive base plate is exposed in the hollow area; the insulating layer includes a plurality of insulator layers stacked sequentially, and the dielectric constant of the plurality of insulator layers increases along the direction from the conductive layer to the conductive base plate.

[0011] Optionally, the polymer matrix of several of the insulator layers is made of the same material, and the doping concentration of the doped material increases in the direction from the conductive layer to the conductive substrate.

[0012] Optionally, the insulating filling medium is made of silicone gel, and the polymer matrix is ​​made of epoxy resin, polyphenylene sulfide, polyether ether ketone, or polyphenylene sulfone; the doping material includes nano zinc oxide, nano titanium dioxide, or carbon fiber.

[0013] Optionally, the dielectric constant is the same at all locations in the insulating layer.

[0014] Optionally, the insulating layer is made of a polymer material, and the difference between the dielectric constant of the polymer material and the dielectric constant of the insulating filling medium is 0 to 1.

[0015] Optionally, the insulating filling medium is made of silicone gel, and the polymer material includes epoxy resin, polyphenylene sulfide, polyether ether ketone, or polyphenylene sulfone.

[0016] Optionally, the insulating layer is distributed in a grid pattern, and the dielectric constants of adjacent grids are different.

[0017] Optionally, an electret is disposed inside the insulating layer.

[0018] Optionally, the insulating layer is also provided at the connection between the conductive base plate and the housing.

[0019] Optionally, the thickness of the insulating layer is 0.2mm-3mm.

[0020] Optionally, one side surface of the conductive substrate has a first region and a second region spaced apart, the power semiconductor device is located in the first region, the lower electrode of the power semiconductor device faces the first region and is electrically connected to the first region, and the insulating layer is located in the second region; the power semiconductor device insulating package structure further includes: a bonding member, one end of which is connected to the electrode of the power semiconductor device away from the conductive substrate, and the other end of which is connected to the side surface of the conductive layer away from the conductive substrate; a conductive terminal located on the side surface of the conductive layer away from the conductive substrate, one end of which is electrically connected to the conductive layer, and the other end of which extends outside the housing.

[0021] The present invention also provides an insulating packaging method for a power semiconductor device, comprising: providing a conductive substrate; fixing an insulating layer and a conductive layer respectively to oppositely disposed two sides of the conductive substrate, wherein the power semiconductor device is disposed on the surface of the conductive substrate or the surface of the conductive layer; fixing a housing to one side surface of the conductive substrate, wherein the housing and the conductive substrate form an accommodating space, wherein the power semiconductor device, the insulating layer, and the conductive layer are all located within the accommodating space; injecting an insulating filling medium into the accommodating space and curing the insulating filling medium, wherein the difference between the dielectric constant of the contact region of the insulating layer with the insulating filling medium and the dielectric constant of the insulating filling medium is 0 to 1.

[0022] Optionally, the insulating layer can be prepared using 3D printing technology.

[0023] Optionally, the raw material for preparing the insulating layer using 3D printing technology is a polymer material and / or a polymer composite material. The polymer composite material includes a polymer material and a dopant material dispersed in the polymer material. The difference between the dielectric constant of the polymer material and the dielectric constant of the insulating filling medium is 0 to 1. The dielectric constant of the dopant material is greater than the dielectric constant of the insulating filling medium. The doping concentration of the dopant material in the contact area between the insulating layer and the insulating filling medium is 0.

[0024] Optionally, the 3D printing equipment has at least two output units, each of which is adapted to output materials with different dielectric constants. By controlling the output amount in each output unit, the dielectric constant at any position in the insulating layer can be adjusted.

[0025] Optionally, during the 3D printing process, an electret is embedded into the insulating layer.

[0026] Optionally, the power semiconductor device is disposed on the surface of the conductive substrate, and the insulating encapsulation method for the power semiconductor device further includes: before fixing the housing to one side surface of the conductive substrate, using a bonding member to connect the electrode of the power semiconductor device away from the conductive substrate to the side surface of the conductive layer away from the conductive substrate; providing a conductive terminal on the side surface of the conductive layer away from the conductive substrate, and one end of the conductive terminal being electrically connected to the conductive layer; after fixing the housing to one side surface of the conductive substrate, the other end of the conductive terminal extends outside the housing, and the bonding member is located within the accommodating space.

[0027] The technical solution of this invention has the following advantages:

[0028] 1. The power semiconductor device insulating packaging structure and insulating packaging method provided by the present invention, by limiting the difference between the dielectric constant of the contact area between the insulating layer and the insulating filling medium and the dielectric constant of the insulating filling medium to 0 to 1, makes the difference in dielectric constant at the contact position smaller, improves the electric field distribution at the contact position, thereby avoiding partial discharge due to electric field concentration at the contact position, reducing the risk of the insulating layer being broken down, and improving the insulation of the power semiconductor device insulating packaging structure.

[0029] 2. The insulating package structure for power semiconductor devices provided by the present invention has a dielectric constant in the central region of the insulating layer that is greater than the dielectric constant in the contact region between the insulating layer and the insulating filling medium. This can improve the breakdown electric field of the insulating layer, thereby improving the overall withstand voltage capability of the insulating package structure for power semiconductor devices.

[0030] 3. The insulating package structure for power semiconductor devices provided by the present invention has an increasing dielectric constant from the side of the insulating layer to the central axis of the insulating layer. This can effectively alleviate electric field distortion, further improve the electric field distribution, thereby further reducing the risk of the insulating layer being broken down and further improving the insulation of the insulating package structure for power semiconductor devices.

[0031] 4. The power semiconductor device insulating package structure provided by the present invention has a portion of the insulating layer facing away from the conductive substrate exposed in the cutout area. By defining a certain number of insulating layers with increasing dielectric constant along the direction from the conductive layer to the conductive substrate, electric field distortion is effectively mitigated, and the electric field distribution is further improved. This further reduces the risk of the insulating layer being broken down and further improves the insulation of the power semiconductor device insulating package structure.

[0032] 5. The power semiconductor device insulating package structure provided by the present invention further includes an electret inside the insulating layer. The introduction of the electret can effectively improve the electric field distribution, thereby alleviating the electric field concentration inside the power semiconductor device insulating package structure and effectively improving the insulation of the power semiconductor device insulating package structure.

[0033] 6. The power semiconductor device insulating packaging structure provided by the present invention further includes an insulating layer at the connection between the conductive base plate and the housing, which can alleviate partial discharge at the connection between the conductive base plate and the housing and improve the insulation of the power semiconductor device insulating packaging structure.

[0034] 7. The power semiconductor device insulating packaging structure provided by the present invention has a first region and a second region spaced apart on one side surface of the conductive substrate. The power semiconductor device is located in the first region and the insulating layer is located in the second region. That is, the heat generated by the power semiconductor device during operation does not need to pass through the insulating layer and the conductive layer, but is directly transferred to the outside through the conductive substrate. This reduces the number of interfaces passed through during heat transfer, improves the heat transfer effect, enhances the heat dissipation capacity of the power semiconductor device insulating packaging structure, and is beneficial to the normal operation of the power semiconductor device.

[0035] 8. The insulating packaging method for power semiconductor devices provided by the present invention uses 3D printing technology to prepare the insulating layer. The 3D printing technology can adjust the amount of material output in each output unit to control the composition of the insulating layer at any position, thereby controlling the dielectric constant of the insulating layer at any position, and thus obtaining an insulating packaging structure that meets the insulation requirements of power semiconductor devices. The preparation method is simple and flexible; at the same time, it can prepare insulating layers of different sizes as needed, and is suitable for insulating packaging of different power semiconductor devices. Attached Figure Description

[0036] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0037] Figure 1 A cross-sectional view of the insulating package structure of a power semiconductor device provided in an embodiment of the present invention;

[0038] Figure 2 for Figure 1 The diagram shows a top view of the power semiconductor device's insulating package structure without a housing and insulating filler medium.

[0039] Figure 3 for Figure 1The top view shown is of a conductive base plate with an insulating layer and a conductive layer.

[0040] Figure 4 for Figure 1 The image shows a top view of an insulating layer.

[0041] Figure 5 for Figure 1 A longitudinal cross-sectional view of another insulating layer is shown;

[0042] Figure 6 for Figure 1 A longitudinal cross-sectional view of another insulating layer is shown;

[0043] Figure 7 for Figure 1 A longitudinal cross-sectional view of another insulating layer is shown;

[0044] Explanation of reference numerals in the attached figures:

[0045] 1-Conductive base plate; 11-First region; 12-Second region; 2-Insulating layer; 21-Grid; 3-Conductive layer; 31-First lead-out region; 32-Second lead-out region; 4-Power semiconductor device; 5-Housing; 6-Conductive terminal; 7-Bonding component; 8-Electret. Detailed Implementation

[0046] The technical solutions of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention. Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0047] In the description of this invention, it should be noted that the terms "upper," "lower," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0048] See Figures 1-3 This embodiment provides an insulating package structure for a power semiconductor device, including:

[0049] Conductive base plate 1;

[0050] Insulating layer 2 located on one side of conductive base plate 1;

[0051] The conductive layer 3 is located on the side of the insulating layer 2 facing away from the conductive base plate 1, and the power semiconductor device 4 is located on the surface of the conductive layer 3 or the surface of the conductive base plate 1.

[0052] The housing 5 is located on one side surface of the conductive base plate 1. The housing 5 and the conductive base plate 1 form an accommodating space. The power semiconductor device 4, the insulating layer 2 and the conductive layer 3 are all located in the accommodating space.

[0053] The insulating filling medium (not shown) that fills the accommodating space has a dielectric constant difference of 0 to 1 between the dielectric constant of the contact area between the insulating layer 2 and the insulating filling medium and the dielectric constant of the insulating filling medium.

[0054] A conductive terminal 6 is located on the surface of the conductive layer 3 facing away from the conductive base plate 1. One end of the conductive terminal 6 is electrically connected to the conductive layer 3, and the other end of the conductive terminal 6 extends outside the housing 5.

[0055] The bonding component 7 has one end connected to the electrode of the power semiconductor device 4 away from the conductive substrate 1, and the other end connected to the surface of the conductive layer 3 away from the conductive substrate 1. The other end of the bonding component 7 is not electrically connected to the electrode of the power semiconductor device 4 facing the conductive substrate 1.

[0056] The aforementioned insulating package structure for power semiconductor devices, by limiting the difference between the dielectric constant of the contact area between the insulating layer 2 and the insulating filling medium to 0-1, minimizes the difference in dielectric constant at the contact points, improves the electric field distribution at the contact points, and thus avoids partial discharge due to electric field concentration at the contact points. This reduces the risk of the insulating layer 2 being broken down and improves the insulation performance of the insulating package structure for power semiconductor devices. The function of the insulating layer 2 is the same as that of the insulating substrate in conventional copper-clad laminates.

[0057] See Figure 3 The conductive layer 3 covers the entire surface of the insulating layer 2 facing away from the conductive base plate 1; or, the conductive layer 3 includes a first lead-out area 31, a second lead-out area 32, and a hollow area located between the first lead-out area 31 and the second lead-out area 32, with a portion of the insulating layer 2 facing away from the conductive base plate 1 exposed in the hollow area. When the conductive layer 3 covers the entire surface of the insulating layer 2 facing away from the conductive base plate 1, the contact area between the insulating layer 2 and the insulating filling medium is located on the side of the insulating layer 2; when the conductive layer 3 has a hollow area, the contact area between the insulating layer 2 and the insulating filling medium is located on the side of the insulating layer 2 and in the hollow area.

[0058] Specifically, insulating layer 2 includes a polymer matrix and doped materials dispersed in the polymer matrix. The difference between the dielectric constant of the polymer matrix and the dielectric constant of the insulating filling medium is 0 to 1, and the dielectric constant of the doped material is greater than that of the insulating filling medium. When the insulating filling medium is a silica gel, the polymer matrix material includes, but is not limited to, epoxy resin, polyphenylene sulfide, polyetheretherketone, and polyphenylene sulfone, and the doped material includes, but is not limited to, nano-zinc oxide, nano-titanium dioxide, and carbon fiber.

[0059] See Figure 4 The insulating layer 2 may include several insulator layers stacked sequentially.

[0060] In one embodiment, the dielectric constant is the same at all locations in the insulating layer 2, and the difference between the dielectric constant at each location in the insulating layer 2 and the dielectric constant of the insulating filling medium is 0 to 1. Specifically, the polymer matrix material is the same at all locations in the insulating layer 2, and the doping concentration of the doped material in the insulating layer 2 is 0.

[0061] In another embodiment, see Figure 5 The dielectric constant of the central region of insulating layer 2 is greater than that of the contact region between insulating layer 2 and the insulating filling medium. This increases the breakdown electric field of insulating layer 2, thereby improving the overall withstand voltage capability of the insulating package structure of power semiconductor devices. Specifically, the polymer matrix material is the same at all locations in insulating layer 2, the doping concentration of the doped material in the contact region between insulating layer 2 and the insulating filling medium is 0, and the doping concentration of the doped material in the central region of insulating layer 2 is greater than 0 and less than 50%.

[0062] Furthermore, the sides and central axis of the insulating layer 2 are perpendicular to the conductive layer 3 and the conductive substrate 1. The dielectric constant of the insulating layer 2 increases from the sides to the central axis. This effectively alleviates electric field distortion and further improves the electric field distribution, thereby further reducing the risk of the insulating layer 2 being broken down and further improving the insulation of the power semiconductor device's insulating packaging structure. Specifically, the doping concentration of the doped material increases from the sides to the central axis, and the polymer matrix material is the same at all locations in the insulating layer 2.

[0063] Furthermore, when the conductive layer 3 includes a first lead-out area 31, a second lead-out area 32, and a hollow area located between the first lead-out area 31 and the second lead-out area 32, see [reference needed]. Figure 5The insulating layer 2 comprises several insulator layers stacked sequentially, with the dielectric constant of the insulator layers increasing from the conductive layer 3 to the conductive substrate 1. This effectively mitigates electric field distortion, further improves the electric field distribution, and thus further reduces the risk of the insulating layer 2 being broken down, thereby further improving the insulation performance of the power semiconductor device's insulating packaging structure. In this case, the polymer matrix material in the several insulator layers is the same, and the doping concentration of the doped material increases from the conductive layer 3 to the conductive substrate 1.

[0064] In other embodiments, see Figure 6 The insulating layer 2 can also be distributed in a grid pattern 21, with adjacent grids 21 having different dielectric constants. The dielectric constant distribution in the insulating layer 2 can be designed according to the electric field distribution. Specifically, the polymer matrix of adjacent grids 21 may be made of the same material, but the doping materials may be different, or the doping materials may be the same but the doping concentration of the doping materials in adjacent grids 21 may be different; or, the polymer matrix of adjacent grids 21 may be made of different materials, but the doping concentration of the doping materials may be 0.

[0065] In addition, see Figure 7 Furthermore, an electret 8 can be disposed inside the insulating layer 2. The electret 8 is a dielectric material carrying positive, negative, or equal and opposite charges. Electrets 8 with different charges can be disposed at different positions in the insulating layer 2 according to the electric field distribution. The introduction of the electret 8 can effectively improve the electric field distribution, thereby alleviating the electric field concentration inside the insulating package structure of the power semiconductor device and effectively improving the insulation of the insulating package structure of the power semiconductor device.

[0066] In this embodiment, the insulating layer 2 is also provided at the connection between the conductive base plate 1 and the housing 5. This can alleviate the partial discharge at the connection between the conductive base plate 1 and the housing 5 and is beneficial to improving the insulation of the insulating packaging structure of the power semiconductor device.

[0067] In this embodiment, the thickness of the insulating layer 2 is 0.2mm-3mm. For example, the thickness of the insulating layer 2 is 0.2mm, 0.5mm, 1mm, 1.5mm, 2mm, 2.5mm or 3mm.

[0068] In this embodiment, the power semiconductor device 4 includes diodes and transistors such as insulated gate bipolar transistors (IGBTs) and MOSFETs.

[0069] In a preferred embodiment, one side surface of the conductive substrate 1 has a first region 11 and a second region 12 spaced apart. The insulating layer 2 is located in the second region 12, and the power semiconductor device 4 is located in the first region 11. The lower electrode of the power semiconductor device 4 faces the first region 11 and is electrically connected to it. The electrode of the power semiconductor device 4 on the side surface away from the conductive substrate 1 is electrically connected to the side surface of the conductive layer 3 away from the insulating layer 2 via a bonding wire, and is led out through a conductive terminal 6 located on the side surface of the conductive layer 3 away from the insulating layer 2. The heat generated by the power semiconductor device 4 during operation does not need to pass through the insulating layer 2 and the conductive layer 3, but is directly transferred to the outside of the insulating package structure via the conductive substrate 1. This reduces the number of interfaces traversed during heat transfer, improves the heat transfer effect, enhances the heat dissipation capacity of the insulating package structure of the power semiconductor device, and is beneficial to the normal operation of the power semiconductor device 4. It should be understood that the commonly used materials for the insulating substrate in existing copper-clad laminates are ceramic materials such as alumina, aluminum nitride, and silicon nitride. To ensure the heat dissipation capacity of the copper-clad laminate, the thickness of the ceramic plate is usually small, which cannot meet the high-voltage insulation requirements. Since the insulating layer 2 is not located on the heat dissipation path of the power semiconductor device 4, the influence of the thickness of the insulating layer 2 on the heat dissipation effect does not need to be considered. Therefore, the insulating layer 2 can be made thicker, thereby improving the withstand voltage capability of the power semiconductor device's insulating package structure, reducing the breakdown risk of the power semiconductor device's insulating package structure, and enabling the power semiconductor device's insulating package structure to simultaneously meet the requirements of heat dissipation and insulation. Specifically, the lower electrode of the power semiconductor device 4 is welded to the conductive base plate 1.

[0070] Furthermore, a first zone 11 can be equipped with one or a row of power semiconductor devices 4.

[0071] When the power semiconductor device 4 is a diode, a second region 12 can be provided on the side of the first region 11. The conductive layer 3 and conductive terminal 6 located in the second region 12 can lead out the electrode located on the side surface of the diode away from the conductive base plate 1, and the conductive layer 3 covers the entire second region 12.

[0072] When the power semiconductor device 4 is an insulated-gate bipolar transistor (IGBT), MOSFET, or other transistor, one or two second regions 12 are provided on the side of the first region 11. When there is one second region 12, the conductive layer 3 has a first lead-out region 31, a second lead-out region 32, and a cutout region located between the first lead-out region 31 and the second lead-out region 32. The first lead-out region 31 and the second lead-out region 32 are provided with independent conductive terminals 6 to lead out the two electrodes located on the side surface of the transistor facing away from the conductive base plate 1, respectively. When there are two second regions 12, the conductive layer 3 located in the two second regions 12 is a full-surface conductive layer 3. The two conductive layers 3 are provided with independent conductive terminals 6 to lead out the two electrodes located on the side surface of the transistor facing away from the conductive base plate 1, respectively. Alternatively, see Figure 2 When there are two second regions 12, the conductive layer 3 located in one second region 12 is a full-surface conductive layer 3, and the conductive layer 3 located in the other second region 12 has a first lead-out area 31, a second lead-out area 32 and a hollow area. The full-surface conductive layer 3, the first lead-out area 31 and the second lead-out area 32 are respectively provided with conductive terminals 6. Among the two electrodes located on the side surface of the transistor away from the conductive base plate 1, one electrode is led out through the full-surface conductive layer 3, the first lead-out area 31 and the conductive terminal 6 located thereon, and the other electrode is led out through the second lead-out area 32 and the conductive terminal 6 located thereon.

[0073] It should be understood that copper-clad laminates with other structures can also use the insulating layer 2 provided in this embodiment as the insulating substrate.

[0074] In this embodiment, the conductive base plate 1 is made of materials including but not limited to aluminum diamond composite material, as well as refractory metal alloy materials such as tungsten copper alloy and molybdenum copper alloy. The conductive layer 3 is made of metal, including but not limited to copper. The insulating layer 2 is bonded to the conductive base plate 1, and the conductive layer 3 is bonded to the insulating layer 2. The bonding member 7 is a bonding bonding member 7 or a bonding tape. The housing 5 is an insulating housing. One end of the conductive terminal 6 extends from the top surface of the housing 5 to the outside.

[0075] Furthermore, the thickness of the conductive base plate 1 is 0.5mm-10mm, and the thickness of the conductive layer 3 is 0.1mm-5mm. For example, the thickness of the conductive base plate 1 can be 0.5mm, 1mm, 2mm, 3mm, 4mm, 5mm, 6mm, 7mm, 8mm, 9mm, or 10mm, and the thickness of the conductive layer 3 can be 0.1mm, 0.3mm, 0.5mm, 1mm, 2mm, 3mm, 4mm, or 5mm.

[0076] This embodiment also provides an insulating packaging method for power semiconductor devices, including the following steps:

[0077] S1. Provide conductive base plate 1;

[0078] S2. Fix the insulating layer 2 and the conductive layer 3 to the opposite sides of the conductive base plate 1 respectively. The fixing methods of the insulating layer 2 and the conductive layer 3 include, but are not limited to, bonding.

[0079] S3. The power semiconductor device 4 is disposed on the surface of the conductive substrate 1 or the surface of the conductive layer 3.

[0080] S4. The electrode of the power semiconductor device 4 away from the conductive substrate 1 is connected to the side surface of the conductive layer 3 away from the conductive substrate 1 using a bonding member 7, and the bonding member 7 is not electrically connected to the electrode of the power semiconductor device 4 facing the conductive substrate 1.

[0081] S5. A conductive terminal 6 is provided on the surface of the conductive layer 3 away from the conductive base plate 1, and one end of the conductive terminal 6 is electrically connected to the conductive layer 3.

[0082] S6. Fix the housing 5 to one side surface of the conductive base plate 1. The housing 5 and the conductive base plate 1 form an accommodating space. The power semiconductor device 4, the insulating layer 2, the conductive layer 3 and the bonding component 7 are all located in the accommodating space. The other end of the conductive terminal 6 extends outside the housing 5.

[0083] S7. Inject insulating filling medium into the accommodating space and cure the insulating filling medium. The difference between the dielectric constant of the contact area between the insulating layer 2 and the insulating filling medium and the dielectric constant of the insulating filling medium is 0 to 1.

[0084] In this embodiment, the insulating layer 2 is prepared using 3D printing technology such as fused layer deposition (FLD). The raw materials for preparing the insulating layer 2 using 3D printing technology are polymer materials and / or polymer composite materials. The polymer composite material includes the polymer material and dopants dispersed within it. The difference between the dielectric constant of the polymer material and the dielectric constant of the insulating filling medium is 0 to 1. The dielectric constant of the dopants is greater than that of the insulating filling medium. The doping concentration of the dopants in the contact area between the insulating layer 2 and the insulating filling medium is 0. When the insulating filling medium is silicone gel, the polymer material includes, but is not limited to, epoxy resin, polyphenylene sulfide, polyetheretherketone, or polyphenylene sulfone; the dopants include, but are not limited to, nano-zinc oxide, nano-titanium dioxide, or carbon fiber.

[0085] Furthermore, a blending process is employed during 3D printing. Specifically, the 3D printing equipment has at least two output units, each suitable for outputting materials with different dielectric constants. The output amount in each output unit is controlled based on simulation results to regulate the composition at any location in the insulating layer 2, thereby regulating the dielectric constant at any location in the insulating layer 2 and accurately reproducing the simulation results. Different output units output different polymer materials; or, at least one output unit outputs pure polymer materials, and at least one output unit outputs polymer composite materials, with different pure polymer materials from different output units, and different doping materials and / or doping concentrations in the polymer composite materials from different output units.

[0086] It is important to understand that the thickness of the ceramic plates commonly used in existing copper-clad laminates is generally less than 1 mm, which cannot meet the requirements for high-voltage insulation. Increasing the thickness of the ceramic plate is both technically challenging and costly. In contrast, 3D printing technology can flexibly control the size of the insulating layer 2, enabling the fabrication of insulating layers 2 with greater thicknesses, and the process is simple and cost-effective.

[0087] Furthermore, during the fabrication of the insulating layer 2 using 3D printing technology, at least one electret 8 can be embedded into the insulating layer 2 as needed, making the processing method flexible.

[0088] In a preferred embodiment, one side surface of the conductive substrate 1 has a first region 11 and a second region 12 spaced apart. An insulating layer 2 is disposed in the second region 12, and a power semiconductor device 4 is disposed in the first region 11. The lower electrode of the power semiconductor device 4 faces the first region 11 and is electrically connected to the first region 11. The electrode of the power semiconductor device 4 on the side surface away from the conductive substrate 1 is electrically connected to the side surface of the conductive layer 3 away from the insulating layer 2 via a bonding wire, and is led out through a conductive terminal 6 located on the side surface of the conductive layer 3 away from the insulating layer 2. By fixing the power semiconductor device 4 to the surface of the conductive substrate 1, the heat generated by the power semiconductor device 4 during operation does not need to pass through the insulating layer 2 and the conductive layer 3, but is directly transferred to the outside through the conductive substrate 1. This reduces the number of interfaces traversed during heat transfer, improves the heat transfer effect, enhances the heat dissipation capacity of the insulating package structure of the power semiconductor device, and is beneficial to the normal operation of the power semiconductor device 4.

[0089] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. An insulating packaging structure for a power semiconductor device, characterized in that, include: Conductive base plate; An insulating layer located on one side of the conductive substrate, the insulating layer comprising a polymer matrix and doped materials dispersed in the polymer matrix; The conductive layer located on the side of the insulating layer facing away from the conductive base plate; A housing located on one side surface of the conductive base plate, the housing and the conductive base plate forming an accommodating space, the power semiconductor device, the insulating layer and the conductive layer are all located within the accommodating space; An insulating filling medium that fills the accommodating space; Wherein, the difference between the dielectric constant of the polymer matrix and the dielectric constant of the insulating filling medium is 0~1, the dielectric constant of the doped material is greater than the dielectric constant of the insulating filling medium, the doping concentration of the doped material in the contact area between the insulating layer and the insulating filling medium is 0, and the doping concentration of the doped material in the central region of the insulating layer is greater than 0, so that the difference between the dielectric constant of the contact area between the insulating layer and the insulating filling medium and the dielectric constant of the insulating filling medium is 0~1, and the dielectric constant of the central region of the insulating layer is greater than the dielectric constant of the contact area between the insulating layer and the insulating filling medium.

2. The power semiconductor device insulating packaging structure according to claim 1, characterized in that, The side surface and central axis of the insulating layer are both perpendicular to the conductive layer and the conductive base plate, and the dielectric constant of the insulating layer increases from the side surface to the central axis.

3. The power semiconductor device insulating packaging structure according to claim 2, characterized in that, From the side to the central axis, the doping concentration of the doped material increases, and the polymer matrix of the insulating layer is made of the same material.

4. The power semiconductor device insulating packaging structure according to claim 1, characterized in that, The conductive layer includes a first lead-out area, a second lead-out area, and a hollow area located between the first lead-out area and the second lead-out area. A portion of the surface of the insulating layer facing away from the conductive base plate is exposed in the hollow area. The insulating layer includes a plurality of insulator layers stacked sequentially, and the dielectric constant of the plurality of insulator layers increases along the direction from the conductive layer to the conductive base plate.

5. The power semiconductor device insulating packaging structure according to claim 4, characterized in that, The polymer matrix of several of the insulator layers is made of the same material, and the doping concentration of the doped material increases from the conductive layer to the conductive substrate.

6. The power semiconductor device insulating packaging structure according to claim 1, characterized in that, The insulating filling medium is made of silicone gel, and the polymer matrix is ​​made of epoxy resin, polyphenylene sulfide, polyether ether ketone or polyphenylene sulfone; the doping material is made of nano zinc oxide, nano titanium dioxide or carbon fiber.

7. The power semiconductor device insulating packaging structure according to claim 1, characterized in that, The insulating layer is distributed in a grid pattern, and the dielectric constants of adjacent grids are different.

8. The power semiconductor device insulating packaging structure according to claim 1, characterized in that, An electret is disposed inside the insulating layer.

9. The power semiconductor device insulating package structure according to claim 1 or 8, characterized in that, The insulating layer is also provided at the connection between the conductive base plate and the housing.

10. The power semiconductor device insulating packaging structure according to claim 1, characterized in that, The thickness of the insulating layer is 0.2mm-3mm.

11. The power semiconductor device insulating package structure according to claim 1 or 8, characterized in that, The conductive substrate has a first region and a second region spaced apart on one side surface. The power semiconductor device is located in the first region, the lower electrode of the power semiconductor device faces the first region and is electrically connected to the first region, and the insulating layer is located in the second region. The power semiconductor device insulating package structure further includes: A bonding component, one end of which is connected to the electrode of the power semiconductor device away from the conductive substrate, and the other end of which is connected to the surface of the conductive layer away from the conductive substrate. A conductive terminal is located on the surface of the conductive layer opposite to the conductive base plate. One end of the conductive terminal is electrically connected to the conductive layer, and the other end of the conductive terminal extends outside the housing.

12. An insulating packaging method for a power semiconductor device, characterized in that, include: Provide conductive base plate; An insulating layer and a conductive layer are respectively fixed to the two oppositely arranged surfaces of the conductive base plate, and the power semiconductor device is disposed on the surface of the conductive base plate or the surface of the conductive layer. The housing is fixed to one side surface of the conductive base plate, and the housing and the conductive base plate form an accommodating space. The power semiconductor device, the insulating layer and the conductive layer are all located within the accommodating space. An insulating filling medium is injected into the accommodating space, and the insulating filling medium is then cured. The insulating layer is prepared on one side surface of the conductive substrate using 3D printing technology. The raw material for 3D printing is a polymer composite material, which includes a polymer material and a dopant material dispersed in the polymer material. The difference between the dielectric constant of the polymer material and the dielectric constant of the insulating filling medium is 0 to 1. The dielectric constant of the dopant material is greater than that of the insulating filling medium. The doping concentration of the dopant material in the contact area between the insulating layer and the insulating filling medium is 0, so that the difference between the dielectric constant of the contact area between the insulating layer and the insulating filling medium and the dielectric constant of the insulating filling medium is 0 to 1. The 3D printing equipment has at least two output units, each of which is adapted to output materials with different dielectric constants. By controlling the output amount in each output unit, the dielectric constant at any position in the insulating layer can be adjusted. During the 3D printing process, an electret is embedded into the insulating layer.

13. The insulating packaging method for power semiconductor devices according to claim 12, characterized in that, The power semiconductor device is disposed on the surface of the conductive substrate, and the insulating encapsulation method of the power semiconductor device further includes: Before fixing the housing to one side surface of the conductive base plate, a bonding component is used to connect the electrode of the power semiconductor device away from the conductive base plate to the side surface of the conductive layer away from the conductive base plate. A conductive terminal is provided on the surface of the conductive layer opposite to the conductive base plate, and one end of the conductive terminal is electrically connected to the conductive layer; after the housing is fixed to one side surface of the conductive base plate, the other end of the conductive terminal extends outside the housing, and the bonding member is located within the accommodating space.

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