Monolithic integration of multiple device types with shared electrical isolation

Abstract

This invention relates to a monolithic integration of multiple device types with shared electrical isolation. It includes structures of silicon-based devices and III-V compound semiconductor-based devices integrated on a semiconductor substrate, and methods for forming such structures. The structure includes a substrate having a device layer, a processing substrate, and a buried insulating layer between the processing substrate and the device layer. The structure includes: a first semiconductor layer on the device layer in a first device region; and a second semiconductor layer on the device layer in a second device region. The first semiconductor layer comprises a III-V compound semiconductor material, and the second semiconductor layer comprises silicon. The first device structure includes a gate structure on the first semiconductor layer; and the second device structure includes a doped region in the second semiconductor layer. The doped region and the second semiconductor layer define a p-n junction.

Description

Technical Field

[0001] This invention relates to semiconductor device manufacturing and integrated circuits, and more particularly, to structures including silicon-based devices and III-V compound semiconductor-based devices integrated on a semiconductor substrate, and methods for forming such structures. Background Technology

[0002] High-voltage power electronic devices, such as high electron mobility transistors (HEP transistors), can be fabricated using III-V compound semiconductors to take advantage of their material properties, such as carrier mobility greater than that of silicon and a wider bandgap. III-V compound semiconductors include group III elements (aluminum, gallium, indium) and group V elements combined with group III elements (nitrogen, phosphorus, arsenic, antimony). A common III-V compound semiconductor used as a base material in device construction is gallium nitride (GaN). High electron mobility transistors can comprise heterojunctions between crystalline III-V compound semiconductor materials with different bandgapes, such as a heterojunction between binary gallium nitride and ternary aluminum gallium nitride. During operation, a two-dimensional electron gas forms near the interface at the heterojunction and defines the channel of the high electron mobility transistor.

[0003] Integrating high electron mobility transistors (such as field-effect transistors or heterojunction bipolar transistors) with silicon-based devices on the same chip has proven challenging. Integration can be achieved through wafer bonding or by using hybrid substrates with portions having different crystal orientations, which inherently introduce significant complexity to the process of integrating high electron mobility transistors with these other types of transistors.

[0004] There is a need for improved structures for silicon-based devices and III-V compound semiconductor-based devices integrated on semiconductor substrates, as well as methods for forming such structures. Summary of the Invention

[0005] In one embodiment of the invention, a structure includes a substrate having a device layer, a processing substrate, and a buried insulating layer between the processing substrate and the device layer. The structure includes: a first semiconductor layer located on the device layer in a first device region; and a second semiconductor layer located on the device layer in a second device region. The first semiconductor layer is made of a III-V compound semiconductor material, and the second semiconductor layer is made of silicon. The first device structure includes a gate structure located on the first semiconductor layer, and the second device structure includes a doped region located in the second semiconductor layer. The doped region and the second semiconductor layer define a pn junction.

[0006] In one embodiment of the invention, a structure includes a substrate comprising a device layer, a processing substrate, and a buried insulating layer located between the processing substrate and the device layer. The structure includes: a semiconductor layer located on the device layer in a first device region; a first device structure including a gate structure located on the semiconductor layer; and a second device structure including a doped region of the device layer in a second device region. The device layer is made of monocrystalline silicon, and the semiconductor layer is made of a III-V compound semiconductor material. The doped region and the device layer define a pn junction.

[0007] In one embodiment of the present invention, a method includes: providing a substrate including a device layer, a processing substrate, and a buried insulating layer located between the processing substrate and the device layer; forming a first semiconductor layer on a first device region of the device layer; and forming a second semiconductor layer on a second device region of the device layer. The first semiconductor layer is made of a III-V compound semiconductor material, and the second semiconductor layer is made of silicon. The method further includes: forming a first device structure having a gate structure located on the first semiconductor layer; and forming a second device structure having a doped region located in the second semiconductor layer. The doped region and the second semiconductor layer define a pn junction. Attached Figure Description

[0008] The accompanying drawings, which are included in and form part of this specification, illustrate various embodiments of the invention and, together with the general description of the invention given above and the detailed description of the embodiments given below, serve to explain the embodiments of the invention. In the drawings, the same reference numerals indicate the same features in the various views.

[0009] Figure 1 This is a cross-sectional view of the structure during the initial manufacturing stage according to an embodiment of the present invention.

[0010] Figure 2 Is Figure 1 Cross-sectional view of the structure during the subsequent manufacturing stage.

[0011] Figure 3 This is a cross-sectional view of the structure according to an alternative embodiment of the present invention.

[0012] Figure 4 and 5 This is a cross-sectional view of the structure according to an alternative embodiment of the present invention.

[0013] Figure 6 This is a cross-sectional view of the structure according to an alternative embodiment of the present invention.

[0014] Figure 7This is a cross-sectional view of the structure according to an alternative embodiment of the present invention.

[0015] Figure 8 Is Figure 7 Cross-sectional view of the structure during the subsequent manufacturing stage.

[0016] Figure 9 This is a cross-sectional view of the structure according to an alternative embodiment of the present invention.

[0017] Figure 10 Is Figure 9 Cross-sectional view of the structure during the subsequent manufacturing stage. Detailed Implementation

[0018] refer to Figure 1 According to an embodiment of the invention, a substrate 10 is provided having a substrate stack including a device layer 12, a buried insulating layer 14, and a processing substrate 16. The device layer 12 is separated from the processing substrate 16 by an intermediate buried insulating layer 14. The device layer 12 has a top surface 18, which is flat. The buried insulating layer 14 may be composed of a buried oxide (BOX) layer, which is composed of a solid dielectric material layer such as silicon dioxide.

[0019] Device layer 12 and processing substrate 16 may comprise semiconductor materials, such as single-crystal silicon. In one embodiment, the single-crystal semiconductor material of device layer 12 may have a diamond lattice structure having a crystal structure specified by Miller indices. <111> Crystal orientation. In one embodiment, substrate 10 may comprise single-crystal silicon having a diamond lattice structure, the diamond lattice structure having <111> Crystal orientation. For those with <111> The device layer 12 is crystal-oriented, with (111) crystal planes parallel to the top surface 18 of the device layer 12, and the crystal direction of

[111] normal to the (111) plane. The (100) crystal axis is not located in the plane of the top surface 18. In one embodiment, the device layer 12 may be composed only of crystal planes with

[111] crystal orientation. <111> It is composed of a single-crystal semiconductor material with crystal orientation (e.g., single-crystal silicon).

[0020] A layer stack 20 is formed on the device layer 12 in device region 22, and a semiconductor layer 28 is formed on the device layer 12 in device region 30. The trench isolation region 32 is formed to cooperate with the buried insulating layer 14 to electrically isolate device region 22 from device region 30.

[0021] The layer stack 20 includes semiconductor layers, such as buffer layer 24 and barrier layer 26, each comprising one or more compound semiconductor layers. Buffer layer 24 and barrier layer 26 can be sequentially deposited using epitaxial growth processes such as metal-organic chemical vapor deposition, vapor phase epitaxy, or molecular beam epitaxy to form the layer stack. Prior to forming the layer stack 20, a thin nucleation layer, such as aluminum nitride, can be formed on device layer 12. Device layer 12 provides a seed for epitaxial growth. In one embodiment, the layer stack 20 can be epitaxially grown simultaneously in device regions 22 and 30 and removed from device region 30 by etching, wherein the layer stack 20 in device region 22 is covered and protected by a dielectric layer.

[0022] Buffer layer 24 and barrier layer 26 may each have a single-crystal crystal structure, or alternatively, a substantially single-crystal crystal structure with varying degrees of crystal defects. Buffer layer 24 may comprise a binary III-V compound semiconductor material, such as gallium nitride, aluminum nitride, aluminum gallium nitride, or a combination thereof, tailored in terms of material composition, doping, and / or layer thickness to accommodate lattice mismatch, thermal property differences, and mechanical property differences between the material of substrate 10 and the material of the channel layer included on top of the buffer layer. The barrier layer 26 disposed above buffer layer 24 may comprise a ternary III-V compound semiconductor, such as aluminum gallium nitride having 15 to 35 atomic percent aluminum, providing a heterogeneous interface with buffer layer 24 of different compositions. Buffer layer 24 may include an undoped III-V compound semiconductor (e.g., undoped gallium nitride) layer adjacent to barrier layer 26.

[0023] In one embodiment, the semiconductor layer 28 can be formed using a selective epitaxial growth (SEG) process, wherein semiconductor material is nucleated to allow epitaxial growth from the exposed surface of device layer 12. The layer stack 20 in device region 22 can be covered and protected by a dielectric layer, such as a silicon nitride layer, to prevent epitaxial growth. In one embodiment, a portion of device layer 12 in device region 30 can be doped to have n-type conductivity prior to the formation of semiconductor layer 28.

[0024] Semiconductor layer 28 may be made of a single-crystal semiconductor material such as single-crystal silicon and may be in-situ doped with an electroactive dopant such as an n-type dopant (e.g., phosphorus or arsenic) during epitaxial growth. In an alternative embodiment, semiconductor layer 28 may be grown non-selectively and then planarized using chemical mechanical polishing, which includes removal from device region 22.

[0025] A trench isolation region 32, which may be formed at the junction between the layer stack 20 and the semiconductor layer 28, may extend through the device layer 12 and into the buried insulating layer 14. The trench isolation region 32 may contain a dielectric material deposited into an etched trench by chemical vapor deposition and then polished and deglazed. The dielectric material contained in the trench isolation region 32 may include silicon dioxide.

[0026] The layer stack 20 in device region 22 has a top surface 21, and the semiconductor layer 28 in device region 30 has a top surface 27. In one embodiment, the top surface 21 of the layer stack 20 may be coplanar with the top surface 27 of the semiconductor layer 28. In another embodiment, the top surface 21 of the layer stack 20 may be substantially coplanar with the top surface 27 of the semiconductor layer 28. In yet another embodiment, the heights of the top surface 21 of the layer stack 20 and the top surface 27 of the semiconductor layer 28 may differ by approximately 100 nanometers (nm) to approximately 500 nm, which can be considered as constituting substantially coplanarity.

[0027] refer to Figure 2 The same reference numerals indicate Figure 1 The same features as those in the previous step, and in subsequent manufacturing stages, can be used to form device structure 40 in device region 30. In one embodiment, device structure 40 may be a Schottky diode, comprising a doped region 42, a silicide layer 44 providing a Schottky contact with the doped region 42 defining an anode, a doped region 46 defining a cathode, and a doped region 48 providing a guard ring around the doped region 42. Silicide layer 44 can be formed by a silicide process, doped regions 42 and 46 can be formed in semiconductor layer 28 by mask implantation, and doped region 48 can be formed in semiconductor layer 28 by separate mask implantation. Doped region 46 may have the same conductivity type as semiconductor layer 28 and contain a higher dopant concentration than semiconductor layer 28. Doped region 42 is doped to have a conductivity type opposite to that of semiconductor layer 28 to define pn junction 43, and doped region 48 is also doped to have a conductivity type opposite to that of semiconductor layer 28 to define pn junction 47. For example, if semiconductor layer 28 has n-type conductivity, doped regions 42 and 48 may be doped to have p-type conductivity.

[0028] Device structure 38 is formed in device region 22. During the formation of device structure 38, semiconductor layer 28 may be covered and protected by dielectric layer. In one embodiment, device structure 38 may be an enhancement-mode high electron mobility transistor (HEMT). In one embodiment, device structure 38 may include a gate structure 34 located on layer stack 20. Gate structure 34 may include a gate 36 positioned to contact barrier layer 26 and a gate metal layer 37 positioned on and above gate 36. Gate 36 may be made of a doped III-V compound semiconductor, such as magnesium-doped p-type aluminum gallium nitride or p-type gallium nitride, and gate metal layer 37 may be made of one or more metals, such as aluminum-copper, titanium nitride, titanium, etc. In one embodiment, gate 36 may be formed by patterning a doped III-V compound semiconductor layer epitaxially grown on layer stack 20 before or after the formation of semiconductor layer 28.

[0029] In a representative embodiment, the gate 36 is located on a barrier layer 26 at the top surface 21 of the layer stack 20. In an alternative embodiment, the barrier layer 26 may be thinned below the gate 36, wherein an optional insulating layer (e.g., a silicon nitride layer) is applied between the gate 36 and the thinned barrier layer 26. In one embodiment, the device structure 38 can operate in enhancement mode (E-mode) by adjusting a threshold voltage such that the device structure 38 is turned off when the gate 36 is not biased. In one embodiment, the device structure 38 can operate in depletion mode (D-mode) by adjusting a threshold voltage such that the device structure 38 is turned off when a negative voltage is applied to the gate 36. In an alternative embodiment, a mixture of E-mode and D-mode device structures 38 may be integrated in device region 22. In an alternative embodiment, a passive device structure such as a Schottky diode may be integrated into device region 22.

[0030] Subsequently, mid-stage and back-end processes are performed, including forming contacts, vias, and wiring for interconnect structures located above substrate 10 and connected to device structures 38, 40.

[0031] A buried insulating layer 14 electrically isolates device structures 38 and 40 from the processing substrate 16. Regarding the shared electrical isolation, the buried insulating layer 14 is located in the vertical direction between device structure 38 and the processing substrate 16, and also in the vertical direction between device structure 40 and the processing substrate 16. Device structures 38 and 40 are formed on the same device layer 12, wherein a layer stack 20 is formed on device layer 12 in device region 22, and a semiconductor layer 28 is also formed on device layer 12 in device region 30. Utilizing only... <111> The crystal-oriented device layer 12 allows the integration of device structures 38, 40 without complex manufacturing processes (e.g., wafer bonding) or the use of engineered substrates or hybrid substrates (e.g., SOI substrates with one or more crystal orientations for the device layer).

[0032] The monolithic co-integration of device structures 38 and 40 on the same device layer 12 provides both low-cost fabrication and high-performance devices with improved operating parameters. Compared to Schottky diodes formed using III-V compound semiconductor materials such as gallium nitride, the Schottky diode as a co-integrated device structure 40 exhibits low forward voltage drop and low stored charge. The parameter improvements provided by the smaller bandgap of silicon compared to gallium nitride can lead to reduced power consumption and improved reliability during operation.

[0033] In alternative embodiments, the device structure 40 formed using semiconductor layer 28 can be a junction diode, exhibiting low leakage due to its formation using semiconductor layer 28. In alternative embodiments, the device structure 40 formed using semiconductor layer 28 can be a bipolar junction transistor or a heterojunction bipolar transistor, wherein the collector, emitter, and base are arranged vertically or laterally, and the base is doped to have p-type or n-type conductivity. In alternative embodiments, the device structure 40 formed using semiconductor layer 28 can be a silicon controlled rectifier (SCR). In alternative embodiments, the device structure 40 can be an insulated gate bipolar transistor (IGBT). In alternative embodiments, the device structure 40 can be a diffused resistor. In alternative embodiments, the device structure 40 can be a junction field-effect transistor (JFET). In alternative embodiments, semiconductor layer 28 can be used to form various different types of device structures 40.

[0034] refer to Figure 3 The same reference numerals indicate Figure 2With the same features as described above, and according to an alternative embodiment, device structure 40 may be a lateral bipolar junction transistor, wherein doped region 42 defines an emitter, doped region 46 participates in defining a base, and doped region 48 provides a collector surrounding the emitter. Overlapping portions of doped regions 42 with different dopant concentrations are doped to have a conductivity type opposite to that of semiconductor layer 28 to define a pn junction. For example, if semiconductor layer 28 has n-type conductivity, doped region 42 may be doped to have p-type conductivity.

[0035] refer to Figure 4 , 5 The same reference numerals indicate Figure 2 The same features are present in the device region 30, and according to an alternative embodiment, the device layer 12 in the device region 30 can be used instead of the semiconductor layer 28 to form the device structure 40. In this case, the semiconductor layer 28 is not formed in the device region 30, thus leaving the device layer 12 for forming the device structure 40. The height difference between the top surface 21 of the layer stack 20 and the top surface 18 of the device layer 12 can exceed 500 nm.

[0036] like Figure 4 As shown, the device structure 40 formed using device layer 12 in device region 30 can be a Schottky diode. Figure 5 As shown, the device structure 40 formed using the device layer 12 in the device region 30 can be a bipolar junction transistor.

[0037] refer to Figure 6 The same reference numerals indicate Figure 4 With the same features as described above, and according to an alternative embodiment, the dielectric layer 50 may be formed on the device layer 12 in the device region 30. The dielectric layer 50 is made of a dielectric material such as silicon dioxide and has a top surface 52. The dielectric material of the dielectric layer 50 may be deposited, for example, by chemical vapor deposition and then planarized. Doped regions 42, 46, 48 may be accessed by trenches 51 in the dielectric layer 50 that are patterned in the dielectric layer 50 and extend completely through the top surface 52 to the device layer 12. In an alternative embodiment, the device structure 40 may be a bipolar junction transistor instead of a Schottky diode.

[0038] In one embodiment, the top surface 21 of the layer stack 20 and the top surface 52 of the dielectric layer 50 in the device region 30 may be coplanar. In another embodiment, the top surface 21 of the layer stack 20 and the top surface 52 of the dielectric layer 50 in the device region 30 may be substantially coplanar. In yet another embodiment, the heights of the top surface 21 of the layer stack 20 and the top surface 52 of the dielectric layer 50 in the device region 30 may differ by approximately 100 nm to approximately 500 nm, which can be considered as constituting substantially coplanarity.

[0039] refer to Figure 7 The same reference numerals indicate Figure 1 The same features are present in the device region 22, and according to an alternative embodiment, the device layer 12 in the device region 22 can be thinned from its original thickness before forming the layer stack. In the device region 30, the device layer 12 maintains its original thickness. In this case, the semiconductor layer 28 is not formed in the device region 30, and the original thickness of the device layer 12 is greater than the thickness of the layer stack 20.

[0040] In one embodiment, the top surface 21 of the layer stack 20 and the top surface 18 of the device layer 12 in the device region 30 may be coplanar. In another embodiment, the top surface 21 of the layer stack 20 and the top surface 18 of the device layer 12 in the device region 30 may be substantially coplanar. In yet another embodiment, the heights of the top surface 21 of the layer stack 20 and the top surface 18 of the device layer 12 in the device region 30 may differ by approximately 100 nm to approximately 500 nm, which can be considered as constituting substantially coplanarity.

[0041] refer to Figure 8 The same reference numerals indicate Figure 7 The same features are present in the subsequent manufacturing stages, and the processing continues to form device structures 38 and 40. In device region 30, device structure 40 is formed using the semiconductor material of device layer 12, which may be doped (e.g., n-type doping) to facilitate device formation.

[0042] refer to Figure 9 The same reference numerals indicate Figure 1 The same features are present in the above embodiments, and according to alternative embodiments, substrate 10 may be an engineered substrate comprising a processing substrate 56 made of a polycrystalline ceramic material whose thermal expansion characteristics closely match those of the material of layer stack 20. In one embodiment, processing substrate 56 may be made of polycrystalline aluminum nitride whose thermal expansion characteristics closely match those of gallium nitride. In another embodiment, processing substrate 56 may be made of polycrystalline silicon carbide, which also closely matches the thermal expansion characteristics of gallium nitride. Processing substrate 56 is covered by layer stack 54, which includes engineered layers, such as layers comprising silicon dioxide, silicon nitride, polycrystalline silicon, etc. Device layer 12 is located on layer stack 54.

[0043] refer to Figure 10 The same reference numerals indicate Figure 9 The same features are present in the subsequent manufacturing stages, and the processing continues to form a layer stack 20, optionally forming a semiconductor layer 28, and forming device structures 38, 40.

[0044] The methods described above are used in the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of raw wafers (e.g., as a single wafer with multiple unpackaged chips), as bare dies, or in packages. In the latter case, the chips are mounted in a single chip package (e.g., a plastic carrier in which leads are attached to a motherboard or other higher-level carrier) or multiple packages (e.g., a ceramic carrier with one or both of surface-mount or buried interconnects). In either case, the chips can be integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of an intermediate or final product.

[0045] References to terms modified by approximate language such as “approximately,” “roughly,” and “basically” are not limited to the specified precise values. Approximate language may correspond to the precision of the instrument used to measure the value and may indicate + / - 10% of the value unless dependent on the precision of the instrument.

[0046] The use of terms such as “vertical” and “horizontal” in this document is illustrative rather than restrictive, in order to establish a frame of reference. As used herein, the term “horizontal” is defined as a plane parallel to the conventional plane of the semiconductor substrate, regardless of its actual three-dimensional spatial orientation. As just defined, the terms “vertical” and “normal” refer to directions perpendicular to the horizontal. The term “lateral” refers to a direction within the horizontal plane.

[0047] A feature that is “connected” or “coupled” to or with another feature can be directly connected or coupled to or coupled to another feature; conversely, one or more intermediate features may exist. If no intermediate features exist, a feature can be “indirectly connected” or “indirectly coupled” to or coupled to another feature. If at least one intermediate feature exists, a feature can be “indirectly connected” or “indirectly coupled” to or coupled to another feature. A feature that is “located on” or “in contact with” another feature can be directly located on or in direct contact with another feature; conversely, one or more intermediate features may exist. If no intermediate features exist, a feature can be “directly located on” or “in direct contact with” another feature. If at least one intermediate feature exists, a feature can be “indirectly located on” or “indirectly in contact with” another feature.

[0048] Various embodiments of the present invention have been described for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles of the embodiments, their practical application, or technical improvements to technologies found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A semiconductor structure, comprising: A substrate, comprising a device layer, a processing substrate, and a buried insulating layer located between the processing substrate and the device layer; A first semiconductor layer is located on the device layer in the first device region, and the first semiconductor layer is made of a III-V compound semiconductor material; A second semiconductor layer is located on the device layer in the second device region, and the second semiconductor layer is made of silicon. A first device structure, which includes a gate structure located on the first semiconductor layer; as well as A second device structure includes a doped region located in a second semiconductor layer, the doped region and the second semiconductor layer defining a pn junction. The buried insulating layer is located vertically between the first device structure and the processing substrate, and the buried insulating layer is also located vertically between the second device structure and the processing substrate. The first device structure and the second device structure are formed on the same device layer.

2. The semiconductor structure of claim 1, wherein, The first device structure is a high electron mobility transistor, and the second device structure is a Schottky diode.

3. The semiconductor structure of claim 1, wherein, The first device structure is a high electron mobility transistor, and the second device structure is a bipolar junction transistor.

4. The semiconductor structure of claim 1, wherein, The device layer is composed of having <111> It is composed of single-crystal silicon with crystal orientation, and the silicon of the second semiconductor layer has <111> Single crystals with crystal orientation.

5. The semiconductor structure of claim 1, wherein, The III-V compound semiconductor material includes gallium nitride.

6. The semiconductor structure according to claim 1, wherein, The first semiconductor layer has a first top surface, the second semiconductor layer has a second top surface, and the first top surface and the second top surface are coplanar.

7. The semiconductor structure according to claim 1, wherein, The first semiconductor layer has a first top surface, the second semiconductor layer has a second top surface, and the height difference between the first top surface and the second top surface is 100 nanometers to 500 nanometers.

8. The semiconductor structure according to claim 1, wherein, The processing substrate is made of polycrystalline ceramic material, and the buried insulator layer includes multiple engineered layers.

9. A semiconductor structure, comprising: A substrate comprising a device layer, a processing substrate, and a buried insulating layer located between the processing substrate and the device layer, wherein the device layer is composed of monocrystalline silicon; A semiconductor layer, located on the device layer in the first device region, wherein the semiconductor layer is made of a III-V compound semiconductor material; A first device structure includes a gate structure located on the semiconductor layer; as well as A second device structure includes a doped region in the device layer within a second device region, the doped region and the device layer defining a pn junction. The buried insulating layer is located vertically between the first device structure and the processing substrate, and the buried insulating layer is also located vertically between the second device structure and the processing substrate. The first device structure and the second device structure are formed on the same device layer.

10. The semiconductor structure according to claim 9, wherein, The first device structure is a high electron mobility transistor, and the second device structure is a Schottky diode.

11. The semiconductor structure according to claim 9, wherein, The first device structure is a high electron mobility transistor, and the second device structure is a bipolar junction transistor.

12. The semiconductor structure according to claim 9, wherein, The single-crystal silicon of the device layer has <111> Crystal orientation.

13. The semiconductor structure according to claim 9, wherein, The III-V compound semiconductor material includes gallium nitride.

14. The semiconductor structure according to claim 9, wherein, The semiconductor layer has a first top surface, and the structure further includes: A dielectric layer located on the device layer in the second device region, the dielectric layer having a second top surface, the dielectric layer including trenches extending from the second top surface to the device layer at the location of the doped region in the device layer, and the first top surface being coplanar with the second top surface.

15. The semiconductor structure according to claim 9, wherein, The semiconductor layer has a first top surface, and the structure further includes: A dielectric layer located on the device layer in the second device region, the dielectric layer having a second top surface, the dielectric layer including trenches extending from the second top surface to the device layer at the location of the doped region in the device layer, and the height difference between the first top surface and the second top surface being 100 nanometers to 500 nanometers.

16. A method for manufacturing a semiconductor structure, comprising: A substrate is provided, the substrate including a device layer, a processing substrate, and a buried insulating layer located between the processing substrate and the device layer; A first semiconductor layer is formed on the device layer in the first device region, wherein the first semiconductor layer is made of a III-V compound semiconductor material; A second semiconductor layer is formed on the device layer in the second device region, wherein the second semiconductor layer is made of silicon; Forming a first device structure, the first device structure including a gate structure located on the first semiconductor layer; and A second device structure is formed, the second device structure including a doped region located in a second semiconductor layer, wherein the doped region and the second semiconductor layer define a pn junction. The buried insulating layer is located vertically between the first device structure and the processing substrate, and the buried insulating layer is also located vertically between the second device structure and the processing substrate. The first device structure and the second device structure are formed on the same device layer.

17. The method according to claim 16, wherein, Forming the first semiconductor layer on the first device region of the device layer includes: The first semiconductor layer is epitaxially grown in the first device region and the second device region; and Remove the first semiconductor layer from the second device region.

18. The method according to claim 17, wherein, The first semiconductor layer is removed from the second device region before the second semiconductor layer is formed.

19. The method of claim 16, wherein, The first semiconductor layer has a first top surface, the second semiconductor layer has a second top surface, and the height difference between the first top surface and the second top surface is 100 nanometers to 500 nanometers.

20. The method of claim 16, wherein, The device layer is composed of having <111> It is composed of single-crystal silicon with crystal orientation, and the silicon of the second semiconductor layer has <111> Single crystals with crystal orientation.

Images