Buried oxide layer patterned soi wafer structure, method of making and applications thereof

Abstract

The application discloses a buried oxide layer patterning SOI wafer structure, a manufacturing method and application thereof. The SOI wafer structure comprises a bottom silicon layer, a first insulating oxide layer, a top silicon layer, a trap-rich layer and a protective layer for protecting the trap-rich layer; the first insulating oxide layer has a pattern structure, the pattern structure comprises one or more than one groove formed on the top end surface of the bottom silicon layer and insulating oxide filled in the groove; the trap-rich layer is distributed between the first insulating oxide layer and the bottom silicon layer, the protective layer is distributed between the trap-rich layer and the first insulating oxide layer, and the bottom end surface of the top silicon layer is combined with the top end surface of the bottom silicon layer. The SOI wafer structure provided by the application solves the contradiction between the SOI wafer performance and heat dissipation, and can eliminate the negative influence of the insulating oxide layer on the substrate silicon layer.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor devices, specifically relating to a patterned SOI wafer structure with buried oxide layer, its fabrication method and application. Background Technology

[0002] Existing SOI wafers such as Figure 1 As shown, it includes: a top silicon layer 3, an insulating oxide layer 2 and a low silicon layer 1. The insulating oxide layer 2 is a single layer. Since the thermal conductivity of silicon dioxide constituting the insulating oxide layer 2 is only one-twentieth of that of single-crystal silicon material, heat dissipation is a major problem for existing SOI wafers.

[0003] Currently, SOI wafers are mostly used in low-power applications, while their self-heating effect limits their application in high-power applications. Summary of the Invention

[0004] The main objective of this invention is to provide a patterned SOI wafer structure with a buried oxide layer, its fabrication method, and its application, so as to overcome the shortcomings of the prior art.

[0005] To achieve the aforementioned objectives, the technical solution adopted by this invention includes:

[0006] This invention provides a patterned SOI wafer structure with a buried oxide layer, comprising: a bottom silicon layer, a first insulating oxide layer, a top silicon layer, a trap-rich layer, and a protective layer for protecting the trap-rich layer; the first insulating oxide layer has a patterned structure, the patterned structure including one or more grooves formed on the top surface of the bottom silicon layer and insulating oxide filling the grooves; the trap-rich layer is distributed between the first insulating oxide layer and the bottom silicon layer, the protective layer is distributed between the trap-rich layer and the first insulating oxide layer, and the bottom surface of the top silicon layer is bonded to the top surface of the bottom silicon layer.

[0007] Furthermore, the material of the trap-rich layer includes polycrystalline silicon.

[0008] Furthermore, the protective layer is made of silicon nitride.

[0009] Furthermore, the SOI wafer structure also includes a second insulating oxide layer, which is distributed between the bottom end face of the top silicon layer and the top end face of the bottom silicon layer.

[0010] Furthermore, the second insulating oxide layer is integrated with the first insulating oxide layer.

[0011] This invention also provides a method for fabricating the above-described SOI wafer structure with a buried oxide layer pattern, comprising:

[0012] One or more grooves corresponding to the pattern structure of the first insulating oxide layer are formed on the top surface of the bottom silicon layer;

[0013] A trap-rich layer and a protective layer of the trap-rich layer are sequentially deposited on the top surface of the bottom silicon layer, and then the groove is filled with an insulating oxide to form a first insulating oxide layer.

[0014] Remove the deposited layer on the top surface of the bottom silicon layer, except for the groove, to make the top surface of the bottom silicon layer flat;

[0015] The top surface of the bottom silicon layer is bonded to the bottom surface of the top silicon layer.

[0016] Furthermore, the above-mentioned manufacturing method also includes: after removing the deposited layer on the top surface of the bottom silicon layer in the area other than the groove, making the top surface of the bottom silicon layer flat, forming a second insulating oxide layer on the top surface of the bottom silicon layer, and then bonding the top surface of the bottom silicon layer with the bottom surface of the top silicon layer.

[0017] Furthermore, the above-mentioned manufacturing method also includes: after bonding the top surface of the bottom silicon layer to the bottom surface of the top silicon layer, the top silicon layer needs to be thinned accordingly.

[0018] The present invention also provides an SOI wafer structure with patterned buried oxide layer as described above, or the application of the SOI wafer structure described above in semiconductor device fabrication.

[0019] Compared with the prior art, the SOI wafer structure with buried oxide patterning provided by the present invention, its fabrication method and application have at least the following beneficial effects:

[0020] 1) By patterning the insulating oxide layer of the SOI wafer structure, the performance of the devices or circuits formed on the SOI wafer structure is improved, while also having better heat dissipation performance, thus resolving the contradiction between the performance and heat dissipation of the SOI wafer structure.

[0021] 2) By setting a trap-rich layer between the patterned insulating oxide layer and the substrate silicon layer, the negative impact of the fixed charge in the insulating oxide layer on the substrate is offset. At the same time, by setting a protective layer for the trap-rich layer, the impact of subsequent processes on the trap-rich layer is reduced, so that the trap density of the trap-rich layer is high enough.

[0022] 3) The operating temperature of the radio frequency power device fabricated based on the SOI wafer structure provided by the present invention can be effectively reduced. At the same time, the parasitic capacitance Cds between the drain and source of the device and the parasitic capacitance Cdb between the drain and the substrate are smaller, thereby reducing the output capacitance Coss of the device and improving the high-frequency performance and efficiency of the device.

[0023] 4) Passive devices fabricated based on SOI wafers provided by this invention, such as inductors and capacitors, have smaller parasitic effects, less crosstalk between devices, and higher resonant Q values, thereby significantly reducing high-frequency losses and greatly improving the efficiency of amplifiers or front-end and back-end modules. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a schematic diagram of an SOI wafer structure in existing technology;

[0026] Figure 2 This is a schematic diagram of a SOI wafer structure with a buried oxide layer pattern in an embodiment of the present invention;

[0027] Figures 3a to 3f This is a schematic diagram of a method for fabricating a SOI wafer with a buried oxide layer pattern, according to an embodiment of the present invention.

[0028] Figure 4 This is a schematic diagram of the structure of a radio frequency power device according to an embodiment of the present invention;

[0029] Figure 5 This is a schematic diagram of the structure of a passive device in an embodiment of the present invention;

[0030] Figure 6 This is a schematic diagram of another SOI wafer structure in an embodiment of the present invention.

[0031] Reference numerals: 1. Bottom silicon layer, 2. First insulating oxide layer, 3. Top silicon layer, 4. Trap-rich layer, 5. Protective layer, 6. Groove, 7. Second insulating oxide layer, 8. Back electrode, 9. Source electrode, 10. Drift region, 11. Drain electrode, 12. Polysilicon gate, 121. Polysilicon layer, 122. Gate oxide layer, 13. Shallow trench isolation structure. Detailed Implementation

[0032] In view of the deficiencies of the prior art, the inventors of this invention, through long-term research and extensive practice, have proposed the technical solution of this invention. By proposing an SOI wafer structure with a patterned buried oxide layer layout, the performance of devices or circuits fabricated on this SOI wafer structure is significantly improved, while also possessing better heat dissipation performance. This resolves the contradiction between the performance and heat dissipation characteristics of SOI wafer structures, thereby enabling SOI wafer structures with patterned buried oxide layer layouts to have a wider range of applications, especially meeting the needs of future 5G communications for higher frequencies and higher output power.

[0033] The technical solution of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0034] This invention provides an SOI wafer structure with a buried oxide layer pattern, such as... Figure 2 As shown, it includes: a bottom silicon layer 1, a first insulating oxide layer 2, a top silicon layer 3, a trap-rich layer 4, and a protective layer 5 for protecting the trap-rich layer; wherein, the first insulating oxide layer 2 has a patterned structure, the patterned structure including one or more grooves 6 formed on the top surface of the bottom silicon layer 1 and insulating oxide filling the grooves 6; the trap-rich layer 4 is distributed between the first insulating oxide layer 2 and the bottom silicon layer 1, the protective layer 5 is distributed between the trap-rich layer 4 and the first insulating oxide layer 2, and the bottom surface of the top silicon layer 3 is bonded to the top surface of the bottom silicon layer 1.

[0035] Furthermore, the SOI wafer structure also includes a second insulating oxide layer 7, which is distributed between the bottom surface of the top silicon layer 3 and the top surface of the bottom silicon layer 1.

[0036] Furthermore, the second insulating oxide layer 7 is integrated with the first insulating oxide layer 2.

[0037] Furthermore, the material forming the aforementioned trap-rich layer 4 can be polycrystalline silicon, the material forming the protective layer 5 can be silicon nitride, and the materials forming the first insulating oxide layer 2 and the second insulating oxide layer 7 can be silicon dioxide.

[0038] Specifically, the first insulating oxide layer 2 in the SOI wafer structure carries a fixed charge, which forms a weak mobile charge accumulation region in the shallow region at the interface with silicon. Adding a trap-rich layer 4 formed of polysilicon between the first insulating oxide layer 2 and the bottom silicon layer 3 can effectively counteract the negative impact of the fixed charge in the first insulating oxide layer 2, further improving the performance of the SOI wafer structure. At the same time, covering the trap-rich layer 4 with a protective layer 5 formed of silicon nitride can protect the trap-rich layer 4, reduce the impact of subsequent process steps on the trap-rich layer 4, and ensure that the trap density in the trap-rich layer 4 is high enough.

[0039] In some preferred embodiments, the thickness of the trap-rich layer 4 can be between 0.1 μm and 1 μm, the thickness of the protective layer 5 can be between 5 nm and 50 nm, the thickness of the first insulating oxide layer 2 can be between 0.2 μm and 2 μm, and the thickness of the second insulating oxide layer 7 can be between 1 nm and 50 nm.

[0040] This invention also provides a method for fabricating the above-described SOI wafer structure with a buried oxide pattern. Please refer to [link to relevant documentation]. Figures 3a to 3f It includes:

[0041] First, according to the actual application requirements, one or more grooves 6 corresponding to the pattern structure of the first insulating oxide layer 2 are processed on the top surface of the bottom silicon layer 1. The bottom silicon layer 1 can be in a high-resistivity state or a low-resistivity state.

[0042] Specifically, the method for processing groove 6 can be dry etching, wet etching, or a combination of dry and wet etching, and the depth of groove 6 is determined by the requirements of device or circuit design, usually between 0.2μm and 2μm.

[0043] Furthermore, a trap-rich layer 4 and a protective layer 5 of the trap-rich layer 4 are sequentially deposited on the top surface of the bottom silicon layer 1, and then the above-mentioned groove 6 is filled with insulating oxide to form a first insulating oxide layer 2.

[0044] Specifically, the material forming the trap-rich layer 4 can be polycrystalline silicon. The specific method for forming this polycrystalline silicon layer can be to first deposit an amorphous silicon layer with a thickness of 0.1 μm to 1 μm, and then transform it into a polycrystalline silicon layer through a thermal annealing process. Polycrystalline silicon possesses a large number of interface states, which act as carrier traps, trapping carriers and preventing them from generating substrate crosstalk. The protective layer 5 of the trap-rich layer 4 can be made of silicon nitride, typically with a thickness of 5 nm to 50 nm. It can reduce the impact of subsequent processes on the trap-rich layer 4, ensuring a sufficiently high trap density within it.

[0045] Specifically, the insulating oxide forming the first insulating oxide layer 2 can be silicon dioxide, and its thickness is comparable to the depth of the corresponding groove 200. The thickness is usually between 0.2 μm and 2 μm. The first insulating oxide layer 2 is surrounded by a trap-rich layer 4. The fixed charge in the first insulating oxide layer 2 will attract the charge carriers in the bottom silicon layer 1. These charge carriers are captured by the traps in the trap-rich layer 4 and become fixed charges, which has no negative impact on the performance of the bottom silicon layer 1.

[0046] Furthermore, the deposited layer on the top surface of the bottom silicon layer 1, except for the area of ​​the groove 6, is removed to make the top surface of the bottom silicon layer 1 flat.

[0047] Specifically, methods for removing the deposited layer can be physical or a combination of physical and chemical methods.

[0048] Finally, the top surface of the bottom silicon layer 1 is bonded to the bottom surface of the top silicon layer 3. For example, the top surface of the bottom silicon layer 1 and the bottom surface of the top silicon layer 3 can be bonded together by bonding. The top silicon layer 3 is then thinned according to the actual application requirements.

[0049] In some cases, before bonding the top surface of the bottom silicon layer 1 to the bottom surface of the top silicon layer 3, a first insulating oxide layer 2 can be formed on the top surface of the bottom silicon layer 1 first, and then the top surface of the bottom silicon layer 1 and the bottom surface of the top silicon layer 3 can be bonded together by bonding.

[0050] This invention also proposes the application of the above-described buried oxide patterned SOI wafer structure in semiconductor device fabrication.

[0051] Please see Figure 4 This is a radio frequency (RF) power device formed in the SOI wafer structure. Specifically, the RF power device includes a back electrode 8, a source electrode 9, a drain electrode 11, a drift region 10 formed in the top silicon layer 3 of the SOI wafer structure, and a polysilicon gate 12 formed on the top surface of the top silicon layer 3. The polysilicon gate 12 is composed of a polysilicon layer 121 and a gate oxide layer 122. The lower boundary of the drift region 10 is in contact with the upper boundary of the first insulating oxide layer 2, and the drift region 10 and the drain electrode 11 are disposed in the top silicon layer 3 above the corresponding first insulating oxide layer 2.

[0052] This RF power device can be a high-power device such as an LDMOS. Accordingly, a first insulating oxide layer 2 is disposed below the drift region 10 and drain 11 of the RF power device, with the lower boundary of the drift region 10 contacting the upper boundary of the first insulating oxide layer 2. This reduces the parasitic capacitance Cds between the source 9 and drain 11, and lowers the parasitic capacitance Cdb between the drain 11 and the bottom silicon layer 1, thereby significantly reducing the output capacitance Coss and improving the high-frequency performance and efficiency of the device. Simultaneously, because there is a connection region between the top silicon layer 3 and the bottom silicon layer 1 that is not isolated by the first insulating oxide layer 2, the heat generated by the device in the top silicon layer 3 can be conducted to the bottom silicon layer 1 through this connection region, improving the thermal conductivity of the device. Compared with the traditional SOI wafer structure, this effectively reduces the operating temperature of the device.

[0053] For further details, please refer to Figure 5 This is a passive device formed in the SOI wafer structure, wherein a shallow trench isolation structure 13 is provided on the SOI wafer structure, and the lower boundary of the shallow trench isolation structure 13 is in contact with the upper boundary of the first insulating oxide layer 2 of the SOI wafer structure, and the passive device is disposed in the shallow trench isolation structure 13 (the passive device is not shown in the figure).

[0054] Specifically, the lower boundary of the shallow trench isolation structure 13 is in contact with the upper boundary of the first insulating oxide layer 2 of the SOI wafer, thus forming a thicker insulating oxide layer. Passive devices such as inductors and capacitors fabricated in this thicker insulating oxide layer have less parasitic effects, less crosstalk between devices, and a higher resonant Q value, thereby significantly reducing high-frequency losses and greatly improving the efficiency of amplifiers or front-end and back-end modules.

[0055] It should be understood that radio frequency integrated circuits composed of the above-mentioned radio frequency devices and passive devices can also be fabricated on the SOI substrate with buried oxide patterning in this embodiment, which will not be described in detail here.

[0056] It should be noted that the process method described in this invention can also be applied to traditional SOI wafer structures, such as... Figure 6 As shown, in the traditional SOI wafer structure, a trap-rich layer 4 formed of polysilicon is added, and a protective layer 5 formed of silicon nitride is covered on it. This can also protect the polysilicon trap-rich layer 4, reduce the impact of subsequent process steps on the polysilicon trap-rich layer 4, and maintain the trap density in the polysilicon trap-rich layer 4.

[0057] In summary, the SOI wafer with patterned buried oxide layer distribution, its fabrication method, and its application proposed in this invention not only maintain the performance of SOI wafers but also solve the heat dissipation problem of SOI wafers, greatly expanding the application range of SOI wafers. This allows SOI wafers to be used not only in low-power applications but also in high-power output applications, such as RF power amplifiers, thereby enabling a fully integrated single-chip solution for both front-end and back-end.

[0058] In the description of this invention, it should be noted that the terms "middle", "upper", "lower", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0059] It should be understood that the technical solutions of the present invention are not limited to the specific embodiments described above. Any technical modifications made to the technical solutions of the present invention without departing from the spirit and scope of the claims are within the scope of protection of the present invention.

Claims

1. A patterned SOI wafer structure with a buried oxide layer, comprising a bottom silicon layer, a first insulating oxide layer, and a top silicon layer, characterized in that: The SOI wafer structure further includes a trap-rich layer and a protective layer for protecting the trap-rich layer; the first insulating oxide layer has a patterned structure, the patterned structure including one or more grooves formed on the top surface of the bottom silicon layer and insulating oxide filling the grooves; the trap-rich layer is distributed between the first insulating oxide layer and the bottom silicon layer, the protective layer is distributed between the trap-rich layer and the first insulating oxide layer, the bottom surface of the top silicon layer is bonded to the top surface of the bottom silicon layer, and there is a connection region between the top silicon layer and the bottom silicon layer that is not isolated by the first insulating oxide layer.

2. The SOI wafer structure according to claim 1, characterized in that, The material of the trap-rich layer includes polycrystalline silicon; and / or, the material of the protective layer includes silicon nitride.

3. A method for fabricating an SOI wafer structure with a buried oxide layer pattern according to any one of claims 1-2, characterized in that... include: One or more grooves corresponding to the pattern structure of the first insulating oxide layer are formed on the top surface of the bottom silicon layer; A trap-rich layer and a protective layer of the trap-rich layer are sequentially deposited on the top surface of the bottom silicon layer, and then the groove is filled with an insulating oxide to form a first insulating oxide layer. Remove the deposited layer on the top surface of the bottom silicon layer, except for the groove, to make the top surface of the bottom silicon layer flat; The top surface of the bottom silicon layer is bonded to the bottom surface of the top silicon layer.

4. The manufacturing method according to claim 3, characterized in that... Also includes: After the top surface of the bottom silicon layer is bonded to the bottom surface of the top silicon layer, the top silicon layer is further thinned accordingly.

5. The application of a SOI wafer structure with a buried oxide pattern according to any one of claims 1-2 in the fabrication of semiconductor devices.

Images