A composite termination structure for SiC power devices and a method of manufacturing the same

Abstract

This invention discloses a composite termination structure for SiC power devices and its manufacturing method. The structure includes: an N-drift region formed on an N-type heavily doped substrate, with a device cell region and a device termination region sequentially disposed on the N-drift region; the device cell region includes spaced-apart deep P-well regions and a PN junction formed by the deep P-well regions and the N-drift region to form a main junction; the device termination region includes: a P-type junction termination extension region and a passivation layer; the P-type junction termination extension region has several N+ field-limiting rings spaced-apart on the side near the main junction; a passivation layer is deposited on the surface of the P-type junction termination extension region, and etched trenches are formed on the side of the N+ field-limiting rings away from the N-drift region. This invention can enhance the short-circuit withstand capability of the device. When the device is in reverse blocking state, the PN junction and termination structure of the device cell region simultaneously withstand the withstand voltage, improving the reverse breakdown voltage of the device, thereby making the device more reliable.

Description

Technical Field

[0001] This invention relates to the field of semiconductor power device technology, and in particular to a composite termination structure for SiC power devices and its manufacturing method. Background Technology

[0002] Silicon carbide (SiC) materials, due to their superior wide bandgap, high critical breakdown electric field, and high electron mobility, have attracted much attention for their power devices, which are widely used in inverters, high-voltage switches, and motor drivers. Breakdown voltage is a crucial parameter for evaluating the reliability of power semiconductor devices. However, in practical power semiconductors employing planar diffusion technology, the high-voltage junction must intersect the surface at a finite location. This results in junction curvature compression of the equipotential lines, where the junction bends towards the surface, increasing the maximum electric field. To improve breakdown characteristics and reliability, shifting the maximum electric field point from the surface to the substrate and reducing the peak value are effective methods.

[0003] However, devices requiring high breakdown voltage often face a trade-off between excessive surface electric field near the junction termination and excessive bulk electric field peak. Field limiting rings (N+ field limiting rings), as an effective means of reducing field congestion at the main junction, have been widely used in junction termination technology. N+ field limiting rings are one of the most common structures in low-voltage (1700V) applications. As voltage levels continue to increase, the number of rings in N+ field limiting rings needs to increase, and each injection interval requires high lithographic precision. However, traditional N+ field limiting rings suffer from oxide reliability issues due to the high electric field peak near the silicon-oxide interface. Therefore, existing technologies struggle to simultaneously improve breakdown voltage and reliability. Summary of the Invention

[0004] In view of this, the purpose of this invention is to propose a composite termination structure for SiC power devices and a method for manufacturing the same, which can simultaneously improve breakdown voltage and reliability.

[0005] According to one aspect of the present invention, a composite termination structure for SiC power devices is provided, comprising an N-drift region formed on an N-type heavily doped substrate, wherein a device cell region and a device termination region are sequentially disposed on the N-drift region; the device cell region includes spaced-apart deep P-well regions, and a PN junction formed by the deep P-well regions and the N-drift regions constitutes a main junction;

[0006] The device termination region includes: a P-junction termination extension region and a passivation layer; the P-junction termination extension region is provided with a plurality of N+ field limiting rings at intervals on the side near the main junction; the surface of the P-junction termination extension region is deposited with a passivation layer, and etching trenches are etched in the N+ field limiting rings.

[0007] According to another aspect of the present invention, a method for fabricating a composite termination structure for SiC power devices is provided, the method comprising: S1, depositing a SiO2 oxide layer on a silicon carbide wafer, placing photoresist on the oxide layer and etching a P-well region window, and performing random P-type ion implantation on the silicon carbide wafer, thereby simultaneously forming a P-well region; S2, depositing a SiO2 oxide layer on the silicon carbide wafer, placing photoresist on the oxide layer and etching a deep P-well region and a P-type junction termination extension region opening, and performing P-type ion channel implantation on the silicon carbide wafer, thereby simultaneously forming a deep P-well region and a P-type junction termination extension region; S3, depositing a SiO2 oxide layer on the silicon carbide wafer, placing photoresist on the oxide layer and etching a deep JFET region opening. S4. An N-type ion channel is implanted on the silicon carbide wafer, simultaneously forming a deep JFET region; S5. A SiO2 oxide layer is deposited on the silicon carbide wafer, photoresist is placed on the oxide layer and P+ body region openings are etched, and P-type ion implantation is performed on the silicon carbide wafer, simultaneously forming a P+ body region; S6. A SiO2 oxide layer is deposited on the silicon carbide wafer, photoresist is placed on the oxide layer and N+ source region and N+ field limiting ring openings are etched, and N-type ion implantation is performed on the silicon carbide wafer, simultaneously forming an N+ source region and N+ field limiting ring; S7. A gate dielectric layer and a passivation layer are deposited on the silicon carbide wafer, and trench openings and etched trenches are etched; After filling the etched trenches with SiO2, the gate layer, source metal, and drain metal are deposited.

[0008] It can be observed that, in the above scheme, this invention forms a deep P-well region through two steps: random injection and channel injection. On the one hand, this enhances the device's short-circuit withstand capability; on the other hand, this deep junction structure is more suitable for combining with the composite termination structure proposed in this invention, which embeds a trench N+ field-limiting ring into the P-junction termination extension region. When the device is in reverse blocking mode, the PN junction and termination structure in the device cell region simultaneously withstand the breakdown voltage, improving the reverse breakdown voltage and thus enhancing the device's reliability. The combined design of the device cell region and termination region does not negatively affect the device's on-resistance. Simultaneously, the use of channel injection and low-energy deep junction formation enables the invented MOSFET structure to achieve strong short-circuit withstand capability. This structure, combined with the P-junction termination extension region technology, allows for a more uniform electric field distribution and improves the device's breakdown voltage. The performance of traditional P-junction termination extension region structures depends on the concentration of the P-junction termination extension region; only by controlling the appropriate concentration of the P-junction termination extension region can the depletion layer of the termination region be fully extended. This invention embeds an N+ field limiting ring within the P-type junction termination extension region, and simultaneously adds etched trenches to the N+ field limiting ring. The N-type N+ field limiting ring and trench structure can modulate the charge in the junction termination extension region, thereby reducing the peak surface electric field intensity. This makes the N+ field limiting ring technology more stable, while solving the problem of SiO2 damage caused by excessively high surface electric field intensity and reducing the sensitivity of device breakdown voltage to the concentration in the P-type junction termination extension region. Only one additional trench etching is required, and the trench etching can use the same mask as the N+ field limiting ring implantation. This etched trench N+ field limiting ring embedded in the P-type junction termination extension region is more suitable for deep junction devices. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This is a schematic diagram of the silicon carbide power MOSFET terminal structure provided by the present invention;

[0011] Figure 2 The width w of the N+ field limiting ring in the terminal structure provided by this invention is equal;

[0012] Figure 3 The spacing s of the N+ field limiting rings in the terminal structure provided by this invention are equal;

[0013] Figure 4This is a schematic diagram of the electric field distribution in the horizontal direction of the terminal structure provided by the present invention and a schematic diagram of the depletion region during reverse blocking. The horizontal axis represents the length of the terminal in the horizontal direction, and the vertical axis represents the electric field intensity.

[0014] Figures 5-6 This is a schematic diagram of a structure formed by randomly injecting P-type ions into a P-trap.

[0015] Figures 7-8 This is a schematic diagram of the structure formed by injecting Al ions into the deep P-well and the P-type junction terminal extension region via a 4-channel method.

[0016] Figures 9-10 This is a schematic diagram of a structure formed by P-ion implantation in the deep JFET region channel.

[0017] Figures 11-12 This is a schematic diagram of the structure formed by injecting P-type ions into the P+ body region;

[0018] Figures 13-14 This is a schematic diagram of the structure formed by implanting N-type ions into the N+ source region and the N+ field-confined ring.

[0019] Figure 15 This is a schematic diagram of the structure after the gate dielectric and passivation layer are deposited;

[0020] Figure 16 This is a schematic diagram of the process after etching the grooves;

[0021] Figure 17 This is a schematic diagram of the structure after the trench is filled with SiO2 and the source metal, drain metal, and gate layer are in contact.

[0022] In the figure, 1 is the N-drift region, 2 is the P-well region, 3 is the deep P-well region, 4 is the P-type junction termination extension region, 5 is the P+ body region, 6 is the N+ source region, 7 is the N+ field confinement ring, 8 is the deep JFET region, 9 is the gate dielectric layer, 10 is the passivation layer, 11 is the trench, 12 is the gate layer, 13 is the source metal, 14 is the drain, 15 is the heavily doped N-type substrate, and 16 is the depletion line. Detailed Implementation

[0023] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be particularly noted that the following embodiments are for illustrative purposes only and do not limit the scope of the invention. Similarly, the following embodiments are only some, not all, embodiments of the present invention, and all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0024] This invention provides a composite termination structure for SiC power devices that can simultaneously improve breakdown voltage and reliability.

[0025] Please see Figure 1 The structure includes an N-type heavily doped substrate 15 formed on a drain metal 14 and an N-drift region 1 formed on the N-type heavily doped substrate 15. A device cell region and a device terminal region are sequentially provided on the N-drift region 1. The device cell region includes a deep P-well region 3 arranged at intervals, and a PN junction formed by the deep P-well region 3 and the N-drift region 1 to form a main junction.

[0026] The device cell region includes: a P-well region 2 disposed in a deep P-well region 3; an N+ source region 6 and a P+ body region 5 sequentially disposed within the P-well region 2; the N+ source region 6 and the P+ body region 5 being connected to a source metal 13, and connected through the source metal 13 to the N+ source region 6 and the P+ body region 5 in the next deep P-well region 3; and...

[0027] A deep JFET region 8 is located between two deep P-well regions 3; a gate dielectric layer 9 and a gate layer 13 are sequentially disposed on the upper side of the deep JFET region 8 from bottom to top.

[0028] In this embodiment, the device cell is a double-diffused field-effect transistor with a symmetrical deep P-well structure, including a deep P-well region 3 and a deep JFET region 8 on an N-type drift region 1. The deep P-well region 3 is formed by low-energy channel implantation of Al or B ions. The P-well region 2 in the deep P-well region 3 can be formed by conventional random ion implantation. The P-well 2 contains an N+ source region 6 and a P+ body region 5 formed by ion implantation. The deep JFET region 8 is formed by low-energy channel implantation of P ions. The source region 6 and the body region 5 are connected to the source metal 13. The gate layer 12 and the gate dielectric layer 9 are located on the deep JFET region 8.

[0029] In this embodiment, the gate dielectric material is SiO2, Al2O3, AlN, HfO2, Ga2O3, MgO, or SiN. X One or any combination of Sc2O3 materials. The formation of deep P-well 3 involves two steps: random ion implantation and channel implantation of P-type ions. The formation of deep JFET region 8 mainly relies on low-energy channel implantation of N-type ions, such as N ions.

[0030] The device terminal region includes: a P-junction terminal extension region 4 and a passivation layer 10; the P-junction terminal extension region 4 is provided with a plurality of N+ field confinement rings 7 at intervals on the side close to the main junction; the surface of the P-junction terminal extension region 4 is deposited with a passivation layer 10, and the N+ field confinement rings 7 are provided with etching trenches 11 on the side away from the N- drift region 1.

[0031] The device termination structure is located in the N-drift region 1 on the N-type heavily doped substrate 15, including a P-type junction termination extension region 4. The P-type junction termination extension region 4 contains several N+ field confinement rings 7 and etching trenches 11 formed by N-type ion implantation. The etching trenches 11 are located in the N+ field confinement rings 7. The P-type junction termination extension region 4 is covered by a passivation layer 10. The etching trenches 11 and the N+ field confinement rings 7 connected to them are not covered by the passivation layer 10. The N+ field confinement rings 7 are arranged in the region of the P-type junction termination extension region 4 near the main junction.

[0032] In this embodiment, the depth of the P-junction termination extension region 4 is the same as the depth of the deep P-well region 3. The P-junction termination extension region 4 can be formed simultaneously with the low-energy channel ion implantation of the deep P-well region 3, and its depth is the same as the main junction; or it can be formed in one ion implantation, with an implantation concentration lower than that of the main junction, and the same depth. That is, the formation of the P-junction termination extension region 4 can be selected using the same low-energy channel ion implantation method as the deep P-well region, or it can be formed by a single random ion implantation, different from the deep P-well region. To reduce process steps, the JTE region can preferably be formed simultaneously with the deep P-well region. The depth of the N+ field confinement ring 7 is less than the depth of the P-junction termination extension region 4. The N+ field confinement ring 7 is formed in one ion implantation, and its implantation depth is less than the depth of the P-junction termination extension region 4. In this example, the junction depth of the N+ field confinement ring 7 is between 0.5-1 μm, and the junction depth of the P-junction termination extension region 4 is between 1.5-2.5 μm. The number, spacing, and width of the N+ field limiting rings 7 can be changed and adjusted according to specific needs, but the length of the terminal area must be greater than 3 times the thickness of the drift area.

[0033] In this embodiment, the vertical cross-sectional shape of the etched trench 11 is one or more of the following: rectangular, trapezoidal, V-shaped, stepped, or U-shaped. Preferably, it is rectangular or trapezoidal. The advantage is that it can reduce the peak value of the surface electric field; the specific shape is set according to actual needs, which will not be elaborated here. The etched trench 11 is formed by dry etching, with a uniform etching depth. The number of etched trenches 11 is equal to the number of N+ field-limiting rings 7, which can reduce the peak value of the surface electric field. Their widths can be equal or unequal, and can be set according to the requirements of the electric field peak value; the corresponding reduction in electric field peak value will be different, which will not be elaborated here. The device termination is embedded in the P-type junction termination extension region 4 formed by low-energy channel implantation of Al ions, with a spacing s and a width w equal to (e.g., ...). Figure 2 and Figure 3 The N+ field limiting ring 7 (shown) combined with the etched trench 11 embedded in each N+ field limiting ring 7, thereby achieving a more uniform electric field distribution and a lower surface peak electric field intensity through charge modulation, thus improving the device's withstand voltage and reliability.

[0034] In this embodiment, as Figure 4As shown, the terminal structure in this embodiment, combined with the P-type junction terminal extension region 4, the N+ field limiting ring 7, and the etched trench 11, can extend the depletion region to... Figure 4 The location shown, i.e., 16 in the figure, is the boundary of the depletion region. Figure 4 A schematic diagram of the one-dimensional electric field distribution on the surface of this structure is also provided, with the horizontal axis representing the horizontal distance (μm) of the terminal structure and the vertical axis representing the electric field intensity (MV / cm). Compared to the electric field intensity distribution in the conventional P-junction terminal extension region 4 structure, the embedding of the N+ field limiting ring 7 and the etched trench 11 in this embodiment modulates the reverse electric field laterally to gradually diffuse and separate it away from the active region through space charge modulation, thereby raising the electric field in the P-junction terminal extension region 4 and forming multiple electric field peaks within the P-junction terminal extension region 4, fully expanding the depletion region. At the same time, the upper part of the P-junction terminal extension region 4 can finely modulate the space electric field of the adjacent N+ field limiting ring. The mutual modulation effect between the N+ field limiting ring 7 and the P-junction terminal extension region 4 further disperses the electric field and improves the device's breakdown voltage capability.

[0035] This invention also proposes a method for preparing the above-mentioned composite termination structure for SiC power devices, the method comprising:

[0036] S1. Take a silicon carbide wafer and deposit a SiO2 oxide layer. Arrange photoresist on the oxide layer and etch the P-well region window. Perform random implantation of P-type ions on the silicon carbide wafer to form the P-well region at the same time.

[0037] S2. A SiO2 oxide layer is deposited on a silicon carbide wafer. Photoresist is laid on the oxide layer and deep P-well region openings and P-type junction terminal extension region openings are etched. P-type ion channel implantation is performed on the silicon carbide wafer, and deep P-well region and P-type junction terminal extension region are formed at the same time.

[0038] S3. Deposit a SiO2 oxide layer on the silicon carbide wafer, place photoresist on the oxide layer and etch deep JFET region openings; perform N-type ion channel implantation on the silicon carbide wafer, and simultaneously form deep JFET regions.

[0039] S4. Deposit a SiO2 oxide layer on a silicon carbide wafer, place photoresist on the oxide layer and etch openings in the P+ body region, and perform P-type ion implantation on the silicon carbide wafer to form the P+ body region at the same time.

[0040] S5. Deposit a SiO2 oxide layer on a silicon carbide wafer, arrange photoresist on the oxide layer and etch N+ source region openings and N+ field confinement ring openings, and perform N-type ion implantation on the silicon carbide wafer to simultaneously form N+ source regions and N+ field confinement rings.

[0041] S6. Deposit a gate dielectric layer and a passivation layer on a silicon carbide wafer and etch trench openings and etch etch trenches; fill the etch trenches with SiO2 and then deposit the gate, source metal and drain metal.

[0042] In this embodiment, the specific steps are as follows:

[0043] 1. Please refer to Figure 5 A SiO2 oxide layer is deposited on a silicon carbide wafer, and photoresist is applied to the oxide layer and the P-well region 2 window is etched.

[0044] 2. Please refer to Figure 6 P-type ions are randomly implanted onto a silicon carbide wafer, and a P-well region 2 is formed simultaneously.

[0045] 3. Please refer to Figure 7 A SiO2 oxide layer is deposited on a silicon carbide wafer, and photoresist is laid on the oxide layer and a deep P-well region 3 opening and a P-type junction terminal extension region 4 opening are etched.

[0046] 4. Please refer to Figure 8 P-type ion channel implantation is performed on silicon carbide wafers, while deep P-well region 3 and P-type junction terminal extension region 4 are formed at the same time.

[0047] 5. Please refer to Figure 9 A SiO2 oxide layer is deposited on a silicon carbide wafer, and photoresist is laid on the oxide layer and a deep JFET region 8 opening is etched.

[0048] 6. Please refer to Figure 10 N-type ion channel implantation is performed on the silicon carbide wafer, and a deep JFET region is formed at the same time.

[0049] 7. Please refer to Figure 11 A SiO2 oxide layer is deposited on a silicon carbide wafer, and photoresist is laid on the oxide layer and the P+ body region 5 openings are etched.

[0050] 8. Please refer to Figure 12 P-type ion implantation is performed on a silicon carbide wafer, and a P+ body region is formed simultaneously.

[0051] 9. Please refer to Figure 13 A SiO2 oxide layer is deposited on a silicon carbide wafer, and photoresist is laid on the oxide layer and N+ source region 6 opening and N+ field confinement ring 7 opening are etched.

[0052] 10. Please refer to Figure 14 N-type ion implantation is performed on a silicon carbide wafer, during which N+ source region 6 and N+ field confinement ring 7 are formed simultaneously.

[0053] 11. Please refer to Figure 15 A gate dielectric layer 9 and a passivation layer 10 are deposited on a silicon carbide wafer;

[0054] 12. Please refer to Figure 16 Etching trenches 11 are etched on the silicon carbide wafer;

[0055] 13. Please refer to Figure 17 SiO2 is filled into the etched trench 11 on the silicon carbide wafer; a gate layer 12, a source metal 13, and a drain metal 14 are deposited on the silicon carbide wafer.

[0056] This embodiment forms a deep P-well region through two steps: random implantation and channel implantation. This enhances the device's short-circuit withstand capability and, more importantly, makes the deep junction structure more suitable for the composite termination structure proposed in this invention, which incorporates a trench N+ field-limiting ring embedded in the P-junction termination extension region. When the device is in reverse blocking mode, both the PN junction and the termination structure in the device cell region withstand the breakdown voltage, increasing the reverse breakdown voltage and thus improving the device's reliability. The combined design of the device cell region and termination region does not negatively affect the device's on-resistance. It is important to note that while conventional implantation is random, this invention adds channel implantation to form a deep P-well. This increases the device's short-circuit withstand capability and, more importantly, better matches the trench structure termination proposed in this invention, making it suitable for deep junction devices. The principle mainly involves channel implantation (the previously mentioned angle implantation allows for deeper ion implantation). The N+ field-limiting ring structure is located outside the active region, with the same doping concentration as the main junction, to alleviate electric field concentration at the PN junction bend. As the reverse voltage applied to the electrodes increases, the depletion region of the main junction gradually expands outward. Since the floating FN+ field-limiting rings are not in contact with the main junction or other electrodes, when the depletion region expands to the first FN+ field-limiting ring adjacent to the main junction, the maximum electric field strength of the main junction is shared by the first FN+ field-limiting ring until it passes through. Similarly, as the reverse voltage increases successively, the depletion region also gradually increases and passes through the FN+ field-limiting ring junctions one by one. Because the depletion region of the main junction has already expanded to the last FN+ field-limiting ring junction before avalanche breakdown occurs, the significantly widened depletion region weakens the high electric field at the junction bends, thus increasing the device breakdown voltage.

[0057] Embedding the trench within the field-limiting ring allows for a deeper junction depth compared to a conventional ring, while maintaining the same doping concentration. This reduces junction bend, lowers the surface electric field strength, and thus improves surface withstand voltage. It also solves the problem of SiO2 being easily damaged by excessively high surface electric field strength. Therefore, using an embedded trench structure makes the field-limiting ring technology more stable, requiring only an additional trench etching step, and the trench etching can use the exact same mask as the field-limiting ring implantation.

[0058] As can be seen from the above scheme, this invention forms a deep P-well region through two steps: random injection and channel injection. On the one hand, this enhances the device's short-circuit withstand capability; on the other hand, this deep junction structure is more suitable for combining with the composite termination structure proposed in this invention, which embeds a trench N+ field limiting ring into the P-junction termination extension region. When the device is in reverse blocking state, the PN junction and termination structure of the device cell region simultaneously withstand the withstand voltage, improving the reverse breakdown voltage and thus making the device more reliable. The combined design of the device cell region and termination region does not negatively affect the on-resistance of the device. Simultaneously, the use of channel injection and low-energy deep junction formation enables the invented MOSFET structure to achieve strong short-circuit withstand capability. This structure, combined with the P-junction termination extension region technology, can make the electric field distribution of the device more uniform and improve the device's withstand voltage capability. The performance of traditional P-junction termination extension region structures depends on the concentration of the P-junction termination extension region; only by controlling the appropriate concentration of the P-junction termination extension region can the depletion layer of the termination region be fully extended. This invention embeds an N+ field limiting ring within the P-type junction termination extension region, and simultaneously adds etched trenches to the N+ field limiting ring. The N-type N+ field limiting ring and trench structure can modulate the charge in the junction termination extension region, thereby reducing the peak surface electric field intensity. This makes the N+ field limiting ring technology more stable, while solving the problem of SiO2 damage caused by excessively high surface electric field intensity and reducing the sensitivity of device breakdown voltage to the concentration in the P-type junction termination extension region. Only one additional trench etching is required, and the trench etching can use the same mask as the N+ field limiting ring implantation. This etched trench N+ field limiting ring embedded in the P-type junction termination extension region is more suitable for deep junction devices.

[0059] The above description is only a part of the embodiments of the present invention and does not limit the scope of protection of the present invention. Any equivalent device or equivalent process transformation made based on the content of the present invention specification and drawings, or direct or indirect application in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A method for fabricating a composite termination structure for SiC power devices, characterized in that, The method includes: S1. Take a silicon carbide wafer and deposit a SiO2 oxide layer. Arrange photoresist on the oxide layer and etch the P-well region window. Perform random implantation of P-type ions on the silicon carbide wafer to form the P-well region at the same time. S2. A SiO2 oxide layer is deposited on a silicon carbide wafer. Photoresist is laid on the oxide layer and the openings of the deep P-well region in the cell region and the openings of the P-type junction terminal extension region in the terminal region are etched. P-type ion channel implantation is performed on the silicon carbide wafer, and at the same time, the deep P-well region in the cell region and the P-type junction terminal extension region in the terminal region are formed. S3. Deposit a SiO2 oxide layer on the silicon carbide wafer, place photoresist on the oxide layer and etch deep JFET region openings; perform N-type ion channel implantation on the silicon carbide wafer, and simultaneously form deep JFET regions. S4. Deposit a SiO2 oxide layer on a silicon carbide wafer, place photoresist on the oxide layer and etch openings in the P+ body region, and perform P-type ion implantation on the silicon carbide wafer to form the P+ body region at the same time. S5. Deposit a SiO2 oxide layer on a silicon carbide wafer, place photoresist on the oxide layer and etch N+ source region openings in the deep P-well region and N+ field confinement ring openings in the P-type junction termination extension region, perform N-type ion implantation on the silicon carbide wafer, and simultaneously form N+ source regions in the deep P-well region and N+ field confinement rings in the P-type junction termination extension region. S6. Deposit a gate dielectric layer and a passivation layer on a silicon carbide wafer, etch trench openings and etch trenches; after filling SiO2 into the etched trenches with embedded N+ field limiting rings, deposit a gate layer and a source metal in the cell region, respectively, and form a drain metal on the back side of the substrate.

2. The method for fabricating a composite termination structure for SiC power devices as described in claim 1, characterized in that, In S1-S5, the P-type ions implanted can be Al or B, and the N-type ions implanted can be N, P, or As; in S2 and S3, during channel implantation, the radius of the implanted ions is smaller than the open distance between the atomic rows, and the implantation direction is along the open crystal orientation.

3. The method for fabricating a composite termination structure for SiC power devices as described in claim 1, characterized in that, S1 refers to the doping concentration of implanted ions at 1E18~5E19 cm⁻¹. -3 The implantation energy is between 350 keV and 960 keV, and the depth is between 0.5 and 1 μm; the implanted ion concentration in S4 and S5 is greater than 1E19 cm⁻¹. -3 The depth is between 0.3 and 0.5 μm.

4. The method for fabricating a composite termination structure for SiC power devices as described in claim 1, characterized in that, The gate dielectric layer has a thickness of 200-300 nm, and the passivation layer material is SiN, Si3N4, or SiO. x N y Its thickness is 3-6μm.

5. A composite termination structure for SiC power devices, characterized in that, The structure is prepared according to the method of any one of claims 1 to 4; the structure includes an N-drift region formed on an N-type heavily doped substrate, and a device cell region and a device terminal region are sequentially disposed on the N-drift region; the device cell region includes a deep P-well region formed by random implantation and channel implantation in a two-step process, and a PN junction formed by the deep P-well region and the N-drift region to form a main junction; The device termination region includes: a P-junction termination extension region and a passivation layer; the P-junction termination extension region has several N+ field-limiting rings spaced apart on the side near the main junction, and the depth of the P-junction termination extension region is the same as the depth of the deep P-well region; a passivation layer is deposited on the surface of the P-junction termination extension region, and etching trenches are embedded in the N+ field-limiting rings, the depth of the N+ field-limiting rings being less than the depth of the P-junction termination extension region; wherein, The P-junction terminal extension region is provided with several N+ field limiting rings, each N+ field limiting ring is etched with an etched trench with a thickness smaller than that of the N+ field limiting ring, and the etched trench is filled with a dielectric material.

6. The composite termination structure for SiC power devices as described in claim 5, characterized in that, The cross-sectional shape of the etched groove is one or more of the following: rectangular, trapezoidal, V-shaped, stepped, or U-shaped.

7. A composite termination structure for SiC power devices as described in claim 5, characterized in that, The device cell region includes: A P-well region is formed within a deep P-well region by random implantation of P-type ions; an N+ source region and a P+ bulk region are sequentially arranged within this P-well region; the N+ source region and the P+ bulk region are connected to a source metal, and through this source metal, are connected to the N+ source region and the P+ bulk region in the next deep P-well region; and, The deep JFET region is located between two deep P-well regions and is formed by implantation through an N-type ion channel. The deep JFET region is provided with a gate dielectric layer and a gate layer from bottom to top on the side away from the N-drift region.

8. A composite termination structure for SiC power devices as described in claim 7, characterized in that, The gate dielectric layer is made of SiO2, Al2O3, AlN, HfO2, Ga2O3, MgO, or SiN. X One or any combination of Sc2O3 materials.

Images