A GaN-based high-voltage HEMT device epitaxial structure based on a Si substrate and a manufacturing method thereof

Abstract

The application relates to the chip manufacturing field and discloses a GaN-based high-voltage HEMT device epitaxial structure based on a Si substrate, which comprises a Si substrate layer, a nucleation layer, a bottom buffer layer, a rough polishing passivation layer, a middle buffer layer, a fine polishing slotting layer, a top buffer layer, a low-temperature AIN insertion layer, an ALGaNg barrier functional layer and a GaN cap layer; wherein the thickness of the bottom buffer layer is 30-40 mu m, the rough polishing passivation layer is located on the surface of the bottom buffer layer, the top of the rough polishing passivation layer is provided with the middle buffer layer, the rough polishing passivation layer and the fine polishing slotting layer are connected in the mode of being provided with a triple buffer layer, the scratches and other defects of the Si substrate layer in the original stage are continuously eliminated, the surface defects of the Si substrate layer are not extended and copied in the growth stage, negative effects on the device are avoided, the reverse leakage current of the subsequently deployed diode is prevented from being increased, the energy consumption of the device is reduced, and the operation environment of the device is improved.

Description

Technical Field

[0001] This invention relates to the field of chip manufacturing technology, specifically to an epitaxial structure of a GaN-based high-voltage HEMT device based on a Si substrate and its manufacturing method. Background Technology

[0002] Semiconductor discrete device and integrated circuit manufacturing processes require epitaxial growth technology. Because semiconductors contain N-type and P-type impurities, different combinations of these impurities enable semiconductor devices and integrated circuits to have a wide variety of functions. Epitaxial growth technology can easily achieve this. For silicon epitaxial growth, chemical vapor deposition is currently widely used internationally to meet the requirements of crystal integrity, device structure diversification, mass production, purity, and uniformity. The equipment is controllable and simple, and GaN-based materials have stable physicochemical properties, are corrosion-resistant, and radiation-resistant. Devices fabricated from GaN have high stability and are suitable for working in complex environments. Therefore, GaN-based devices have broad application prospects.

[0003] However, during the epitaxial formation of GaN-based devices, TSD dislocations in the substrate and defects such as scratches carried by the substrate itself can negatively affect the reverse characteristics of PN junction diodes and Schottky diodes. This causes substrate defects to be replicated during growth, making it difficult to buffer and eliminate them, which increases the reverse leakage current of the diode and increases the energy consumption of the device. Summary of the Invention

[0004] (a) Technical problems to be solved

[0005] To address the aforementioned shortcomings of existing technologies, this invention provides an epitaxial structure for a GaN-based high-voltage HEMT device based on a Si substrate and its manufacturing method. This effectively solves the problem that in the epitaxial formation of GaN-based devices, defects such as TSD dislocations in the substrate and scratches inherent in the substrate can negatively impact the reverse characteristics of PN junction diodes and Schottky diodes. These defects are replicated during the growth process, making buffering and elimination difficult, leading to increased reverse leakage current and higher device power consumption.

[0006] (II) Technical Solution

[0007] To achieve the above objectives, the present invention is implemented through the following technical solutions:

[0008] This invention discloses an epitaxial structure for a GaN-based high-voltage HEMT device based on a Si substrate, comprising: a Si substrate layer, a nucleation layer, a bottom buffer layer, a coarsely ground passivation layer, a middle buffer layer, a finely ground trench layer, a top buffer layer, a low-temperature AlN insertion layer, an AlGaNg barrier functional layer, and a GaN cap layer; wherein, the thickness of the bottom buffer layer is 30-40 μm, the coarsely ground passivation layer is located on the surface of the bottom buffer layer, the middle buffer layer is disposed on top of the coarsely ground passivation layer, the depth diameter of the coarsely ground passivation layer inside the bottom buffer layer ranges from 20-25 μm, the longest depth diameter range of the middle buffer layer ranges from 25-35 μm, the shortest depth diameter range of the middle buffer layer ranges from 5-10 μm, and the cross-sectional diameter of the trenches on the surface of the coarsely ground passivation layer ranges from 5-10 μm. The trench spacing is 1-2 μm. The surface of the intermediate buffer layer is provided with a finely ground grooved layer. The diameter of the finely ground grooved layer inside the intermediate buffer layer ranges from 2-5 μm. The cross-sectional diameter of the trenches on the surface of the finely ground grooved layer ranges from 1-3 μm, and the trench spacing is 0.5-1 μm. A top buffer layer is provided at the top of the finely ground grooved layer. The maximum depth diameter of the top buffer layer is 5-8 μm, and the minimum depth diameter of the top buffer layer is 0.5-1.5 μm. The bottom buffer layer, intermediate buffer layer, and top buffer layer are composed of AlGaN material. A low-temperature AlN insertion layer is provided at the top of the top buffer layer. An AlGaNg barrier functional layer is provided at the top of the low-temperature AlN insertion layer. A GaN cap layer is provided at the top of the AlGaNg barrier functional layer.

[0009] Furthermore, the AI ​​content in the bottom buffer layer, middle buffer layer, and top buffer layer gradually decreases along the direction of the nucleation layer and the low-temperature AI insertion layer.

[0010] Furthermore, the nucleation layer is grown on a Si substrate at a temperature of 550-1000℃, with a growth pressure of <50mBar, and exhibits a GaN island structure.

[0011] Furthermore, the Al content in the ALGaNg barrier functional layer is 10%-40%.

[0012] Furthermore, the growth temperature conditions for the bottom buffer layer, the middle buffer layer and the top buffer layer are 1000-1350℃.

[0013] A method for fabricating an epitaxial structure of a GaN-based high-voltage HEMT device on a Si substrate includes the following steps:

[0014] Step 1: Anneal the surface of the Si substrate in the reaction chamber at a constant temperature of 1150℃ for 15 minutes;

[0015] Step 2: epitaxially forming a nucleation layer on a Si substrate, wherein the thickness of the nucleation layer is 5-25 nm;

[0016] Step 3: growing a bottom buffer layer on the surface of the nucleation layer, forming a rough-ground passivation layer by a dry etching method, growing a middle buffer layer on the rough-ground passivation layer, then forming a fine-ground grooved layer by a dry etching method, and growing a top buffer layer on the fine-ground grooved layer;

[0017] Step 4: epitaxially growing a low-temperature AlN insertion layer on the top buffer layer;

[0018] Step 5: growing an AlGaN barrier functional layer on the low-temperature AlN insertion layer, wherein the molar content M of Al element in the AlGaN barrier functional layer satisfies 0.2<M<0.5, and the AlGaN barrier functional layer sequentially generates an N-type doped layer, an undoped layer and a P-type doped layer in a single growth cycle;

[0019] Step 6: growing a GaN cap layer on the AlGaN barrier functional layer.

[0020] Further, the growth stages of the bottom buffer layer, the middle buffer layer and the top buffer layer in Step 3 comprise:

[0021] Step 301: maintaining the reaction chamber pressure at 400-500 torr and the growth temperature at 950°C-1100°C;

[0022] Step 301: maintaining the reaction chamber pressure at 200-300 torr and the growth temperature at 900°C-950°C;

[0023] Step 301: maintaining the reaction chamber pressure at 100-200 torr and the growth temperature at 950°C-1100°C.

[0024] Further, the doping material for the N-type doped layer in Step 5 is any one selected from Si, S and Se.

[0025] Further, the doping material for the P-type doped layer in Step 5 is any one selected from Mg, Be and Zn.

[0026] Further, the growth thickness of the GaN cap layer in Step 6 is 1-2 nm, the growth temperature is 900-1000°C, and the reaction chamber pressure is maintained at 100-250 torr.

[0027] (III) Beneficial Effects

[0028] By adopting the technical scheme provided by the present invention, compared with the known public technology, the present invention has the following beneficial effects:

[0029] 1. This invention uses a triple buffer layer to connect the coarse grinding passivation layer and the fine grinding groove layer, continuously eliminating defects such as scratches on the Si substrate layer in the original stage. This prevents the surface defects of the Si substrate layer from being extended and replicated during the growth stage, thereby avoiding negative impacts on the device, preventing an increase in the reverse leakage current of the subsequently deployed diode, reducing the device's energy consumption, and improving the device's operating environment.

[0030] 2. This invention uses the AlGaN barrier functional layer to perform N-type doping and P-type doping, so that an additional electric field with the same direction as the spontaneous polarization electric field is formed inside the material, thereby enhancing its polarization effect, increasing the surface density of the high-concentration two-dimensional electron gas, improving the binding effect on electrons, and reducing the Coulomb interaction and the influence of impurity scattering between the two.

[0031] 3. The present invention has a simple process, is easy to operate, has low processing difficulty, meets the requirements for batch mass production, has a good market prospect, and has high structural stability, which can adapt to the working needs of complex environments. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0033] Figure 1 This is a schematic diagram of a process for fabricating an epitaxial structure of a GaN-based high-voltage HEMT device on a Si substrate.

[0034] Figure 2 This is a schematic diagram illustrating the architecture of a GaN-based high-voltage HEMT device epitaxial structure on a Si substrate.

[0035] Figure 3 This is a schematic diagram illustrating the growth stages of the bottom buffer layer, middle buffer layer, and top buffer layer in this invention.

[0036] The labels in the figure represent: 1. Si substrate layer; 2. Nucleation layer; 3. Bottom buffer layer; 4. Coarse grinding passivation layer; 5. Middle buffer layer; 6. Fine grinding grooved layer; 7. Top buffer layer; 8. Low-temperature AlN insertion layer; 9. AlGaNg barrier functional layer; 10. GaN cap layer. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0038] The present invention will be further described below with reference to embodiments.

[0039] Example 1

[0040] This embodiment presents an epitaxial structure for a GaN-based high-voltage HEMT device on a Si substrate, such as... Figure 2 As shown, it includes: a Si substrate layer 1, a nucleation layer 2, a bottom buffer layer 3, a coarsely ground passivation layer 4, a middle buffer layer 5, a finely ground trenched layer 6, a top buffer layer 7, a low-temperature AlN insertion layer 8, an AlGaNg barrier functional layer 9, and a GaN cap layer 10; wherein, the bottom buffer layer 3 has a thickness of 30 μm, the coarsely ground passivation layer 4 is located on the surface of the bottom buffer layer 3, and the middle buffer layer 5 is disposed on top of the coarsely ground passivation layer 4. The depth diameter range of the coarsely ground passivation layer 4 inside the bottom buffer layer 3 is 20 μm, the longest depth diameter range of the middle buffer layer 5 is 25 μm, the shortest depth diameter range of the middle buffer layer 5 is 5 μm, the cross-sectional diameter range of the trenches on the surface of the coarsely ground passivation layer 4 is 5 μm, and the trench spacing is 1 μm. The surface of the buffer layer 5 is provided with a finely ground grooved layer 6. The diameter of the finely ground grooved layer 6 located inside the middle buffer layer 5 is 2 micrometers. The cross-sectional diameter of the grooves on the surface of the finely ground grooved layer 6 is 1 micrometer, and the groove spacing is 0.5 micrometers. A top buffer layer 7 is provided at the top of the finely ground grooved layer 6. The maximum depth diameter of the top buffer layer 7 is 5 μm, and the minimum depth diameter of the top buffer layer 7 is 0.5 micrometers. The bottom buffer layer 3, the middle buffer layer 5, and the top buffer layer 7 are composed of AlGaN material. A low-temperature AlN insertion layer 8 is provided at the top of the top buffer layer 7. An AlGaNg barrier functional layer 9 is provided at the top of the low-temperature AlN insertion layer 8. A GaN cap layer 10 is provided at the top of the AlGaNg barrier functional layer 9.

[0041] In this embodiment, the AI ​​content in the bottom buffer layer 3, the middle buffer layer 5 and the top buffer layer 7 gradually decreases along the direction of the nucleation layer 2 and the low-temperature AI insertion layer 8.

[0042] The nucleation layer 2 is grown on a Si substrate at a temperature of 600℃ and a growth pressure of <50mBar, and has a GaN island structure.

[0043] The Al content in the ALGaNg barrier functional layer 9 is 10%-40%.

[0044] The growth temperature conditions for the bottom buffer layer 3, the middle buffer layer 5 and the top buffer layer 7 are 1000-1350℃.

[0045] In Step 5, Si is selected as the doping material for the N-type doped layer.

[0046] In Step 5, Mg is selected as the doping material for the P-type doped layer.

[0047] In Step 6, the GaN cap layer 10 has a growth thickness of 1-2 nm, a growth temperature of 900-1000℃, and a reaction chamber pressure of 100-250 torr.

[0048] In this embodiment, the resulting epitaxial structure, with its specific configuration, exhibits low energy consumption, stable operation, and effectively improves the operating environment, adapting to the needs of complex environments. By growing a triple buffer layer and connecting it with a coarse grinding passivation layer 4 and a fine grinding grooved layer 6, the defects such as scratches exhibited by the Si substrate layer 1 in its initial stage are continuously eliminated. This ensures that surface defects of the Si substrate layer 1 are not extended and replicated during the growth stage, thereby avoiding negative impacts on the device, preventing an increase in the reverse leakage current of the subsequently deployed diodes, reducing device energy consumption, and improving the device's operating environment.

[0049] Example 2

[0050] This embodiment also provides a method for manufacturing an epitaxial structure of a GaN-based high-voltage HEMT device based on a Si substrate, such as... Figure 1 As shown, it includes the following steps:

[0051] Step 1: Anneal the surface of Si substrate layer 1 in the reaction chamber at a constant temperature of 1150℃ for 15 minutes;

[0052] Step 2: Epitaxially form nucleation layer 2 on Si substrate layer 1. The thickness of nucleation layer 2 is 5-25nm.

[0053] Step 3: Grow a bottom buffer layer 3 on the surface of nucleation layer 2, form a coarse grinding passivation layer 4 using dry etching, grow a middle buffer layer 5 on the coarse grinding passivation layer 4, form a fine grinding grooved layer 6 using dry etching, and grow a top buffer layer 7 on the fine grinding grooved layer 6.

[0054] Step 4: Epitaxially grow a low-temperature AIN insertion layer 8 on the top buffer layer 7;

[0055] Step 5: growing an AlGaN barrier functional layer 9 on the low-temperature AlN insertion layer 8, wherein the molar content M of Al element in the AlGaN barrier functional layer 9 satisfies 0.2<M<0.5, and the AlGaN barrier functional layer 9 sequentially forms an N-type doped layer, an undoped layer and a P-type doped layer in a single growth period;

[0056] Step 6: growing a GaN cap layer 10 on the AlGaN barrier functional layer 9.

[0057] In specific implementation of this embodiment, N-type doping and P-type doping are performed through the AlGaN barrier functional layer 9, so that an additional electric field with the same direction as the spontaneous polarization electric field is formed inside the material, thereby enhancing the polarization effect, increasing the surface density of high-concentration two-dimensional electron gas, improving the electron confinement effect, and reducing the influence of Coulomb interaction and impurity scattering between the two.

[0058] Example 3

[0059] In this embodiment, as Figure 3 shown, the growth stages of the bottom buffer layer 3, the middle buffer layer 5 and the top buffer layer 7 in Step 3 comprise:

[0060] Step 301: maintaining the reaction chamber pressure at 400-500 torr and the growth temperature at 950°C-1100°C;

[0061] Step 301: maintaining the reaction chamber pressure at 200-300 torr and the growth temperature at 900°C-950°C;

[0062] Step 301: maintaining the reaction chamber pressure at 100-200 torr and the growth temperature at 950°C-1100°C.

[0063] Example 4

[0064] In this embodiment, an epitaxial structure of GaN-based high-voltage HEMT device based on Si substrate, as Figure 2As shown, it includes: a Si substrate layer 1, a nucleation layer 2, a bottom buffer layer 3, a coarsely ground passivation layer 4, a middle buffer layer 5, a finely ground trenched layer 6, a top buffer layer 7, a low-temperature AlN insertion layer 8, an AlGaNg barrier functional layer 9, and a GaN cap layer 10; wherein, the bottom buffer layer 3 has a thickness of 30 μm, the coarsely ground passivation layer 4 is located on the surface of the bottom buffer layer 3, and the middle buffer layer 5 is disposed on top of the coarsely ground passivation layer 4. The depth diameter range of the coarsely ground passivation layer 4 inside the bottom buffer layer 3 is 20 μm, the longest depth diameter range of the middle buffer layer 5 is 25 μm, the shortest depth diameter range of the middle buffer layer 5 is 5 μm, the cross-sectional diameter range of the trenches on the surface of the coarsely ground passivation layer 4 is 5 μm, and the trench spacing is 1 μm. The surface of the buffer layer 5 is provided with a finely ground grooved layer 6. The diameter of the finely ground grooved layer 6 located inside the middle buffer layer 5 is 2 micrometers. The cross-sectional diameter of the grooves on the surface of the finely ground grooved layer 6 is 1 micrometer, and the groove spacing is 0.5 micrometers. A top buffer layer 7 is provided at the top of the finely ground grooved layer 6. The maximum depth diameter of the top buffer layer 7 is 5 μm, and the minimum depth diameter of the top buffer layer 7 is 0.5 micrometers. The bottom buffer layer 3, the middle buffer layer 5, and the top buffer layer 7 are composed of AlGaN material. A low-temperature AlN insertion layer 8 is provided at the top of the top buffer layer 7. An AlGaNg barrier functional layer 9 is provided at the top of the low-temperature AlN insertion layer 8. A GaN cap layer 10 is provided at the top of the AlGaNg barrier functional layer 9.

[0065] In this embodiment, the AI ​​content in the bottom buffer layer 3, the middle buffer layer 5 and the top buffer layer 7 gradually decreases along the direction of the nucleation layer 2 and the low-temperature AI insertion layer 8.

[0066] The nucleation layer 2 is grown on a Si substrate at a temperature of 1000℃ and a growth pressure of <50mBar, and has a GaN island structure.

[0067] The Al content in the ALGaNg barrier functional layer 9 is 10%-40%.

[0068] The growth temperature conditions for the bottom buffer layer 3, the middle buffer layer 5 and the top buffer layer 7 are 1000-1350℃.

[0069] In Step 5, S is selected as the doping material for the N-type doped layer.

[0070] In Step 5, Be is selected as the doping material for the P-type doped layer.

[0071] In Step 6, the GaN cap layer 10 has a growth thickness of 1-2 nm, a growth temperature of 900-1000℃, and a reaction chamber pressure of 100-250 torr.

[0072] With this design, the resulting epitaxial structure has low energy consumption, stable operation, effectively improves the operating environment, and can adapt to the working needs of complex environments.

[0073] Example 5

[0074] This embodiment presents an epitaxial structure for a GaN-based high-voltage HEMT device on a Si substrate, such as... Figure 2 As shown, the structure includes: a Si substrate layer 1, a nucleation layer 2, a bottom buffer layer 3, a coarsely ground passivation layer 4, a middle buffer layer 5, a finely ground trenched layer 6, a top buffer layer 7, a low-temperature AlN insertion layer 8, an AlGaNg barrier functional layer 9, and a GaN cap layer 10. The bottom buffer layer 3 has a thickness of 45 μm. The coarsely ground passivation layer 4 is located on the surface of the bottom buffer layer 3. The middle buffer layer 5 is disposed on top of the coarsely ground passivation layer 4. The depth diameter of the coarsely ground passivation layer 4 within the bottom buffer layer 3 ranges from 30 μm. The longest depth diameter range of the middle buffer layer 5 is 35 μm, and the shortest depth diameter range of the middle buffer layer 5 is 10 μm. The cross-sectional diameter of the trenches on the surface of the coarsely ground passivation layer 4 ranges from 10 μm, and the trench spacing is 2 μm. The surface of the intermediate buffer layer 5 is provided with a finely ground grooved layer 6. The diameter of the finely ground grooved layer 6 inside the intermediate buffer layer 5 is 5 micrometers. The cross-sectional diameter of the grooves on the surface of the finely ground grooved layer 6 is 3 micrometers, and the groove spacing is 1 micrometer. The top of the finely ground grooved layer 6 is provided with a top buffer layer 7. The maximum depth diameter of the top buffer layer 7 is 8 μm, and the minimum depth diameter of the top buffer layer 7 is 1.5 micrometers. The bottom buffer layer 3, the intermediate buffer layer 5, and the top buffer layer 7 are composed of AlGaN material. The top of the top buffer layer 7 is provided with a low-temperature AlN insertion layer 8. The top of the low-temperature AlN insertion layer 8 is provided with an AlGaNg barrier functional layer 9. The top of the AlGaNg barrier functional layer 9 is provided with a GaN cap layer 10.

[0075] In this embodiment, the AI ​​content in the bottom buffer layer 3, the middle buffer layer 5 and the top buffer layer 7 gradually decreases along the direction of the nucleation layer 2 and the low-temperature AI insertion layer 8.

[0076] The nucleation layer 2 is grown on a Si substrate at a temperature of 1000℃ and a growth pressure of <50mBar, and has a GaN island structure.

[0077] The Al content in the ALGaNg barrier functional layer 9 is 10%-40%.

[0078] The growth temperature conditions for the bottom buffer layer 3, the middle buffer layer 5 and the top buffer layer 7 are 1000-1350℃.

[0079] In Step 5, the doping material for the N-type doped layer is Se.

[0080] In Step 5, Zn is selected as the doping material for the P-type doped layer.

[0081] In Step 6, the GaN cap layer 10 has a growth thickness of 1-2 nm, a growth temperature of 900-1000℃, and a reaction chamber pressure of 100-250 torr.

[0082] With this design, the resulting epitaxial structure has low energy consumption, stable operation, effectively improves the operating environment, and can adapt to the working needs of complex environments.

[0083] In summary, this invention can adapt to the working needs of complex environments by growing a triple buffer layer and connecting it with a coarse grinding passivation layer 4 and a fine grinding groove layer 6. This continuously eliminates defects such as scratches exhibited by the Si substrate layer 1 in the original stage, so that the surface defects of the Si substrate layer 1 will not be extended and replicated during the growth stage, thereby avoiding negative impacts on the device, preventing the increase of reverse leakage current of the subsequently deployed diode, reducing the power consumption of the device, and improving the device operating environment.

[0084] By performing N-type and P-type doping on AlGaN barrier functional layer 9, an additional electric field with the same direction as the spontaneous polarization electric field is formed inside the material, thereby enhancing its polarization effect, increasing the surface density of the high-concentration two-dimensional electron gas, improving the binding effect on electrons, and reducing the influence of Coulomb interaction and impurity scattering. The process is simple, convenient to operate, and easy to process, meeting the requirements for batch mass production. The structure has high stability and can adapt to the working needs of complex environments, showing good market prospects.

[0085] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions will not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An epitaxial structure for a GaN-based high-voltage HEMT device based on a Si substrate, characterized in that, Comprising: a Si substrate layer, a nucleation layer, a bottom buffer layer, a rough-grinding passivation layer, a middle buffer layer, a fine-grinding grooved layer, a top buffer layer, a low-temperature AlN insertion layer, an AlGaN barrier functional layer and a GaN cap layer; wherein the thickness of the bottom buffer layer is 30-40 μm, the rough-grinding passivation layer is located on the surface of the bottom buffer layer, the middle buffer layer is arranged on the top of the rough-grinding passivation layer, the depth diameter of the rough-grinding passivation layer located inside the bottom buffer layer ranges from 20-25 μm, the longest depth diameter of the middle buffer layer ranges from 25-35 μm, the shortest depth diameter of the middle buffer layer ranges from 5-10 μm, the cross-sectional diameter of grooves on the surface of the rough-grinding passivation layer ranges from 5-10 μm, and the groove spacing is 1-2 μm, the fine-grinding grooved layer is arranged on the surface of the middle buffer layer, the diameter of the fine-grinding grooved layer located inside the middle buffer layer ranges from 2-5 μm, the cross-sectional diameter of grooves on the surface of the fine-grinding grooved layer ranges from 1-3 μm, and the groove spacing is 0.5-1 μm, the top buffer layer is arranged on the top of the fine-grinding grooved layer, the maximum depth diameter of the top buffer layer is 5-8 μm, the minimum depth diameter of the top buffer layer is 0.5-1.5 μm, and the bottom buffer layer, the middle buffer layer and the top buffer layer are made of AlGaN material; the low-temperature AlN insertion layer is arranged on the top of the top buffer layer, the AlGaN barrier functional layer is arranged on the top of the low-temperature AlN insertion layer, and the GaN cap layer is arranged on the top of the AlGaN barrier functional layer; the Al content in the bottom buffer layer, the middle buffer layer and the top buffer layer gradually decreases along the direction from the nucleation layer to the low-temperature AlN insertion layer; the nucleation layer is grown on the Si substrate at a temperature of 550-1000°C, the growth pressure is <50mBar, and the nucleation layer has a GaN island structure; the growth temperature of the bottom buffer layer, the middle buffer layer and the top buffer layer is 1000-1350°C.

2. The epitaxial structure of a GaN-based high-voltage HEMT device based on a Si substrate according to claim 1, characterized in that, the content of Al in the AlGaN barrier functional layer is 10%-40%.

3. A method for manufacturing an epitaxial structure of a GaN-based high-voltage HEMT device based on a Si substrate, wherein the method is the method for manufacturing an epitaxial structure of a GaN-based high-voltage HEMT device based on a Si substrate as described in any one of claims 1-2, characterized in that, comprising the following steps: Step 1: annealing the surface of the Si substrate layer in a reaction chamber, keeping the temperature constant at 1150°C for 15 min; Step 2: epitaxially forming the nucleation layer on the Si substrate layer, wherein the thickness of the nucleation layer is 5-25 nm; Step 3: growing the bottom buffer layer on the surface of the nucleation layer, forming the rough-grinding passivation layer by dry etching, growing the middle buffer layer on the rough-grinding passivation layer, then forming the fine-grinding grooved layer by dry etching, and growing the top buffer layer on the fine-grinding grooved layer; Step 4: epitaxially growing the low-temperature AlN insertion layer on the top buffer layer; Step 5: growing the AlGaN barrier functional layer on the low-temperature AlN insertion layer, wherein the molar content M of Al element in the AlGaN barrier functional layer satisfies 0.2<M<0.5, and the AlGaN barrier functional layer sequentially generates an N-type doped layer, an undoped layer and a P-type doped layer in a single growth cycle; Step 6: growing the GaN cap layer on the AlGaN barrier functional layer.

4. The method for manufacturing an epitaxial structure of a GaN-based high-voltage HEMT device based on a Si substrate according to claim 3, characterized in that, The growth stages of the bottom buffer layer, middle buffer layer, and top buffer layer in Step 3 include: Step 301: Maintain the reaction chamber pressure at 400-500 torr and the growth temperature at 950℃-1100℃; Step 301: Maintain the reaction chamber pressure at 200-300 torr and the growth temperature at 900℃-950℃; Step 301: Maintain the reaction chamber pressure at 100-200 torr and the growth temperature at 950℃-1100℃.

5. The method for manufacturing an epitaxial structure of a GaN-based high-voltage HEMT device based on a Si substrate according to claim 3, characterized in that, In Step 5, the doping material for the N-type doped layer is any one of Si, S, or Se.

6. The method for manufacturing an epitaxial structure of a GaN-based high-voltage HEMT device based on a Si substrate according to claim 3, characterized in that, In Step 5, the doping material for the P-type doped layer is selected from Mg, Be, or Zn.

7. The method for manufacturing an epitaxial structure of a GaN-based high-voltage HEMT device based on a Si substrate according to claim 3, characterized in that, In Step 6, the GaN cap layer is grown to a thickness of 1-2 nm, the growth temperature is 900-1000℃, and the reaction chamber pressure is maintained at 100-250 torr.

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