Heterojunction solar cell and method for manufacturing the same

Abstract

The application relates to a heterojunction solar cell and a preparation method thereof. The method comprises the following steps: providing a silicon wafer; the silicon wafer comprises a first surface and a second surface arranged oppositely; depositing a first passivation layer and a first doped layer on the first surface, and depositing a second passivation layer and a second doped layer on the second surface; depositing a buffer layer on the surface of the first doped layer away from the silicon wafer by a PVD deposition mode; depositing a first conductive layer on the surface of the buffer layer away from the silicon wafer, and depositing a second conductive layer on the surface of the second doped layer away from the silicon wafer, to obtain a first sample of the cell; and electroplating copper on the first sample to obtain a first cell. By arranging the buffer layer in contact with the doped layer, the contact resistance value of the cell can be significantly reduced, and the performance of the cell can be improved.

Description

Technical Field

[0001] This application relates to the fields of new energy, photovoltaic and semiconductor technology, and in particular to a heterojunction solar cell and its preparation method. Background Technology

[0002] Due to their higher open-circuit voltage and higher conversion efficiency, crystalline silicon heterojunction solar cells have attracted significant investment from major domestic photovoltaic companies in recent years. Transparent conductive oxide (TCO), as a lateral carrier transport layer, is an essential component of heterojunction solar cells.

[0003] In traditional methods, the contact resistance between boron-doped amorphous silicon and the TCO layer changes significantly after microcrystallization treatment, thereby increasing the contact resistance between microcrystalline silicon and TCO. This leads to an increase in the series resistance of the battery, resulting in a decrease in fill factor and conversion efficiency.

[0004] Therefore, in order to reduce the contact resistance of heterojunction solar cells and improve their performance, it is urgent to find a method for fabricating heterojunction solar cells that can reduce the contact resistance. Summary of the Invention

[0005] Therefore, it is necessary to provide a heterojunction solar cell and its fabrication method to address the aforementioned technical problems.

[0006] In a first aspect, this application provides a method for fabricating a heterojunction solar cell. The method includes:

[0007] A silicon wafer is provided; the silicon wafer includes a first surface and a second surface disposed opposite to each other;

[0008] A first passivation layer and a first doped layer are deposited on the first surface, and a second passivation layer and a second doped layer are deposited on the second surface.

[0009] A buffer layer is deposited on the surface of the first doped layer away from the silicon wafer using PVD deposition.

[0010] A first conductive layer is deposited on the surface of the buffer layer away from the silicon wafer, and a second conductive layer is deposited on the surface of the second doped layer away from the silicon wafer to obtain the first battery sample;

[0011] The first sample was electroplated with copper to obtain the first battery.

[0012] In one embodiment, depositing a first conductive layer on the surface of the buffer layer away from the silicon wafer and depositing a second conductive layer on the surface of the second doped layer away from the silicon wafer includes:

[0013] A first transparent conductive layer is deposited on the surface of the buffer layer away from the silicon wafer, and a second transparent conductive layer is deposited on the surface of the second doped layer away from the silicon wafer to obtain the second battery sample.

[0014] In one embodiment, depositing a first conductive layer on the surface of the buffer layer away from the silicon wafer and depositing a second conductive layer on the surface of the second doped layer away from the silicon wafer includes:

[0015] A third transparent conductive layer is deposited on the surface of the buffer layer away from the silicon wafer, a first transparent conductive layer is deposited on the surface of the third transparent conductive layer away from the silicon wafer, and a first transparent conductive protective layer is deposited on the surface of the first transparent conductive layer away from the silicon wafer.

[0016] A second transparent conductive layer is deposited on the surface of the second doped layer away from the silicon wafer, and a second transparent conductive protective layer is deposited on the surface of the second transparent conductive layer away from the silicon wafer to obtain the third sample of the battery.

[0017] In one embodiment, the method further includes:

[0018] Masking the main grid of the first cell;

[0019] An antireflection layer was deposited on the surface of the first transparent conductive protective layer away from the silicon wafer to obtain the fourth battery sample;

[0020] The fourth sample was surface-treated and encapsulated to obtain the second battery.

[0021] In one embodiment, the first transparent conductive layer and the second transparent conductive layer are formed by RPD deposition.

[0022] In one embodiment, the refractive index of the antireflection layer changes linearly from the side closer to the silicon wafer to the side farther away from the silicon wafer.

[0023] In one embodiment, depositing an antireflection layer on the surface of the first transparent conductive protective layer away from the silicon wafer includes:

[0024] A first silicon oxide film is deposited on the surface of the first transparent conductive protective layer away from the silicon wafer;

[0025] A second silicon oxide film is deposited on the surface of the first silicon oxide film away from the silicon wafer;

[0026] A third silicon oxide film is deposited on the surface of the second silicon oxide film away from the silicon wafer;

[0027] The refractive indices of the first, second, and third silicon oxide films decrease sequentially.

[0028] In one embodiment, the first and second transparent conductive protective layers are made of tin oxide.

[0029] In one embodiment, the third transparent conductive layer material is titanium oxide.

[0030] In one embodiment, masking the main grid of the first battery includes:

[0031] The main grid of the first cell can be masked by encapsulating tape, or by printing photosensitive adhesive on screen to mask the main grid.

[0032] In one embodiment, surface treatment and encapsulation of the fourth sample includes:

[0033] Remove the tape or photosensitive adhesive from the surface of the copper grid lines of the fourth sample.

[0034] Secondly, this application also provides a heterojunction solar cell. The cell includes:

[0035] A silicon wafer, including a first surface and a second surface disposed opposite to each other;

[0036] The first passivation layer is deposited on the first surface;

[0037] A second passivation layer is deposited on the second surface;

[0038] The first doped layer is deposited on the surface of the first passivation layer away from the silicon wafer;

[0039] The second doped layer is deposited on the surface of the second passivation layer away from the silicon wafer;

[0040] A buffer layer is deposited on the surface of the first doped layer away from the silicon wafer;

[0041] The first conductive layer is deposited on the surface of the buffer layer away from the silicon wafer;

[0042] The second conductive layer is deposited on the surface of the second doped layer away from the silicon wafer;

[0043] The first electroplated copper electrode is deposited on the surface of the first conductive layer away from the silicon wafer;

[0044] The second electroplated copper electrode is deposited on the surface of the second conductive layer away from the silicon wafer.

[0045] In one embodiment, a first conductive layer is deposited on the surface of the buffer layer away from the silicon wafer; a second conductive layer is deposited on the surface of the second doped layer away from the silicon wafer, further comprising:

[0046] The first transparent conductive layer is deposited on the surface of the buffer layer away from the silicon wafer;

[0047] A second transparent conductive layer is deposited on the surface of the second doped layer away from the silicon wafer.

[0048] In one embodiment,

[0049] The first conductive layer includes:

[0050] A third transparent conductive layer is deposited on the surface of the buffer layer away from the silicon wafer;

[0051] A first transparent conductive layer is deposited on the surface of the third transparent conductive layer away from the silicon wafer;

[0052] A first transparent conductive protective layer is deposited on the surface of the first transparent conductive layer away from the silicon wafer;

[0053] The second conductive layer includes:

[0054] A second transparent conductive layer is deposited on the surface of the second doped layer away from the silicon wafer;

[0055] A second transparent conductive protective layer is deposited on the surface of the second transparent conductive layer away from the silicon wafer.

[0056] In one embodiment, the battery further includes:

[0057] An antireflection layer is deposited on the surface of the first transparent conductive protective layer away from the silicon wafer.

[0058] The above-described method for fabricating heterojunction solar cells and the heterojunction solar cell involve providing a silicon wafer; the silicon wafer includes a first surface and a second surface disposed opposite to each other; depositing a first passivation layer and a first doped layer on the first surface, and depositing a second passivation layer and a second doped layer on the second surface; depositing a buffer layer on the surface of the first doped layer away from the silicon wafer under low pressure and low oxygen conditions using PVD (Physical Vapor Deposition); depositing a first conductive layer on the surface of the buffer layer away from the silicon wafer using RPD (Reactive Plasma Deposition); and depositing a second conductive layer on the surface of the second doped layer away from the silicon wafer using RPD, thereby obtaining a first sample of the cell; and electroplating copper onto the first sample to obtain a first cell. By setting the buffer layer and the doped layer in contact, the contact resistance of the cell can be significantly reduced, thereby improving the cell performance. Attached Figure Description

[0059] Figure 1 This is a schematic flowchart of a method for fabricating a heterojunction solar cell in one embodiment;

[0060] Figure 2 This is a comparison chart of the permeability of different TCO membranes in one embodiment;

[0061] Figure 3 This is a flowchart illustrating the steps following the electroplating of copper and removal of the copper film from a first sample to obtain a first battery in one embodiment.

[0062] Figure 4 This is a schematic flowchart of a method for fabricating a heterojunction solar cell in another embodiment;

[0063] Figure 5 This is a schematic flowchart of a method for fabricating a heterojunction solar cell in another embodiment;

[0064] Figure 6 This is a schematic diagram of the structure of a heterojunction solar cell in one embodiment;

[0065] Figure 7 This is a schematic diagram of a heterojunction solar cell in one embodiment. Detailed Implementation

[0066] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of the present invention. However, the present invention can be practiced in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0067] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0068] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0069] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0070] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0071] It should be noted that when an element is referred to as being "fixed to" or "set on" another element, it can be directly on the other element or there may be an intervening element. When an element is considered to be "connected to" another element, it can be directly connected to the other element or there may be an intervening element. The terms "vertical," "horizontal," "upper," "lower," "left," "right," and similar expressions used herein are for illustrative purposes only and do not represent the only possible implementation.

[0072] The main processes for heterojunction solar cells include: cleaning and texturing the cells; depositing an intrinsic amorphous silicon passivation layer and doped layer via PECVD (Plasma-enhanced chemical vapor deposition); depositing a TCO layer with a thickness of approximately 80 nm on both sides of the cell; and finally, screen printing silver grid electrodes or electroplating copper electrodes. Currently, TCO film preparation mainly employs techniques such as magnetron sputtering PVD or RPD. PVD preparation of ITO (Indium Tin Oxide) films is currently the mainstream method for heterojunction solar cells, but its relatively low mobility makes it difficult to improve cell conversion efficiency. In contrast, RPD preparation of TCO films offers advantages such as high ionization rate, high film mobility, and minimal interface damage, demonstrating significant development potential.

[0073] Transparent conductive films (TCOs), serving as lateral carrier transport layers, are an essential component of heterojunction solar cells. The low mobility of materials like ITO limits the high-efficiency development of heterojunction solar cells. Employing double or multiple TCO layers to improve the electrical and optical properties of the thin film while reducing the contact resistance between the TCO layer and amorphous silicon is an effective method to enhance solar cell conversion efficiency.

[0074] Currently, the microcrystallization of amorphous silicon in heterojunction solar cells offers superior light transmittance and lower defects, while also improving conductivity and open-circuit voltage. However, this alters the interfacial contact with the TCO film. Therefore, modifying the TCO film fabrication process is crucial for the development of heterojunction solar cells.

[0075] Replacing screen printing with copper electroplating can significantly reduce the amount of silver paste used and lower production costs. The aspect ratio of the front grid electrodes can be greatly improved by copper electroplating, which can improve the conversion efficiency of heterojunction solar cells. However, the existing ITO layer has poor corrosion resistance during electroplating, and there is an urgent need to find a new TCO material as a protective layer.

[0076] In traditional methods, the contact resistance between boron-doped amorphous silicon and the TCO layer changes significantly after microcrystallization treatment, thereby increasing the contact resistance between microcrystalline silicon and TCO. This leads to an increase in the series resistance of the battery, resulting in a decrease in fill factor and conversion efficiency.

[0077] TCO films prepared by RPD exhibit high mobility and optical transmittance. Comparative studies of the contact resistance between TCO prepared by PVD and RPD and the doped layer revealed that on the n-type doped layer side (e.g., the phosphorus doped layer side), the interface between the RPD-deposited TCO and the n-type doped layer has a higher contact resistance, while the interface between the PVD-deposited TCO and the p-type doped layer has a higher contact resistance. Therefore, to obtain better contact performance, it is preferable to deposit the TCO layer by PVD on the n-type doped layer side and by RPD on the p-type doped layer side, thereby improving the overall performance of the battery.

[0078] Reducing the contact resistance with microcrystalline silicon through double-layer or multi-layer TCO film technology can lower the series resistance of heterojunction solar cells and has important reference value for improving the performance of battery devices.

[0079] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0080] See Figure 1 , Figure 1A schematic flowchart of a method for preparing a heterojunction solar cell according to an embodiment of the present invention is shown, including the following steps:

[0081] Step 102, providing a silicon wafer; the silicon wafer includes a first surface and a second surface disposed opposite to each other.

[0082] In one embodiment, the first surface can be the n-side of the silicon wafer, the second surface can be the p-side of the silicon wafer, or a corresponding transformation can be made, without further limitation here.

[0083] In one embodiment, the silicon wafer is an n-type monocrystalline silicon wafer.

[0084] Step 104: Deposit a first passivation layer and a first doped layer on the first surface, and deposit a second passivation layer and a second doped layer on the second surface.

[0085] In one embodiment, a first passivation layer and a first doped layer are deposited on the first surface using chemical vapor deposition, and a second passivation layer and a second doped layer are deposited on the second surface. The materials of the first passivation layer and the second passivation layer can be intrinsic amorphous silicon, intrinsic microcrystalline silicon, etc., or other materials with passivation effects.

[0086] In one embodiment, a first passivation layer and a first doped layer are deposited on the first surface of the silicon wafer, and a second passivation layer and a second doped layer are deposited on the second surface of the silicon wafer. The specific deposition steps may be as follows: depositing a second passivation layer on the second surface of the silicon wafer (the p-type doped surface of the silicon wafer), performing wafer flipping, sequentially depositing the first passivation layer and the first doped layer on the first surface of the silicon wafer (the n-side of the silicon wafer), performing wafer flipping again, and finally depositing a second doped layer on the second passivation layer on the second surface of the silicon wafer.

[0087] In one embodiment, the specific conditions for depositing the first passivation layer and the second passivation layer include: a power supply of 500W, a hydrogen to silane gas flow rate ratio (hydrogen dilution ratio) of 9.5:1, a pressure of 50Pa, and a substrate temperature of 220°C during deposition.

[0088] In one embodiment, the conditions for depositing the first doped layer include: a power supply range of 200W to 500W, a hydrogen to silane gas flow rate ratio (hydrogen dilution ratio) set in the range of 4 to 7, a silane to phosphine gas flow rate ratio (silicon-phosphorus ratio) of 80 to 120, a pressure adjusted in the range of 100 Pa to 130 Pa, and a substrate temperature of 200°C to 230°C during deposition.

[0089] In one embodiment, the conditions for depositing the second doped layer include: a power supply range of 300W to 700W, a hydrogen to silane gas flow rate ratio (hydrogen dilution ratio) of 1 to 4, a silane to phosphine gas flow rate ratio (silicon-phosphorus ratio) of 40 to 70, a pressure range of 45 Pa to 65 Pa, and a substrate temperature range of 200°C to 220°C during deposition.

[0090] Step 106: Deposit a buffer layer on the surface of the first doped layer away from the silicon wafer using PVD deposition.

[0091] In one embodiment, a buffer layer is deposited on the surface of the first doped layer away from the silicon wafer under low pressure and low oxygen conditions using a magnetron sputtering deposition apparatus.

[0092] In one embodiment, the thickness of the buffer layer is 5nm to 10nm. Optionally, the thickness of the buffer layer can be 5nm, 6nm, 7nm, 8nm, 9nm, or 10nm.

[0093] In one embodiment, the buffer layer comprises an ITO (indium tin oxide) film, and optionally, the ratio of indium oxide to tin dioxide in the ITO film can be 90:10 (In2O3:SnO2 = 90:10 wt%).

[0094] In one embodiment, a magnetron sputtering apparatus is used to deposit an ITO film under low-oxygen, low-hydrogen, and low-pressure conditions. The gas flow ratio of argon, oxygen, and hydrogen is adjusted to a specific value, and the chamber pressure is maintained at a specific value. Specifically, the conditions for depositing the buffer layer include: introducing a mixture of argon, hydrogen, and oxygen at room temperature; reducing damage to the interface through low gas pressure; reducing the contact resistance between the buffer layer and the doped layer through low oxygen; and maintaining the chamber pressure between 0.1 Pa and 10 Pa during the deposition process.

[0095] In one embodiment, preferably, the cavity pressure is maintained at 0.1 Pa to 0.6 Pa.

[0096] Step 108: Deposit a first conductive layer on the surface of the buffer layer away from the silicon wafer, and deposit a second conductive layer on the surface of the second doped layer away from the silicon wafer to obtain the first battery sample.

[0097] Step 110: Electroplating copper onto the first sample to obtain the first battery.

[0098] In one embodiment, the first sample is annealed under the following conditions: in an air environment, at a temperature of 150°C-200°C for 20-40 minutes.

[0099] In one embodiment, the first sample is subjected to an electroplating copper process.

[0100] In one embodiment, the copper electroplating process includes the following steps: before the electroplating process, copper seed layers are formed on the surfaces of the first conductive layer and the second conductive layer, respectively; then, photosensitive ink is sprayed on both sides, wherein the thickness of the sprayed ink is 12 μm; the ink on the first surface and the second surface are exposed using an exposure machine, wherein the linewidth after exposure is 15 μm; the first sample is developed to obtain the pattern required by design, wherein the linewidth of the pattern is 15 μm and the depth is 12 μm; the first sample is put into an electroplating device, and copper electrodes are generated according to the designed image, wherein the electroplated linewidth is 15 μm and the height is 10 μm; the first sample is placed in an ink removal solution to remove all residual ink.

[0101] In one embodiment, a first sample is placed in an acidic solution for removing the copper seed layer, wherein the pH value of the acidic solution is 1-2, the reaction time is 20-40 seconds, and the reaction solution temperature is 15℃-35℃, to remove the copper film of the seed layer.

[0102] In one embodiment, due to the protective covering of the copper electrode, the seed layer copper film directly beneath the copper electrode, which has a thickness and width of micrometers, can be preserved, while the seed layer copper film with a thickness of nanometers in the remaining area is removed, exposing the first conductive layer and the second conductive layer.

[0103] In the above method for preparing a heterojunction solar cell, a silicon wafer is provided; the silicon wafer includes a first surface and a second surface disposed opposite to each other; a first passivation layer and a first doped layer are deposited on the first surface, and a second passivation layer and a second doped layer are deposited on the second surface; a buffer layer is deposited on the surface of the first doped layer away from the silicon wafer by PVD deposition; a first conductive layer is deposited on the surface of the buffer layer away from the silicon wafer, and a second conductive layer is deposited on the surface of the second doped layer away from the silicon wafer, to obtain a first cell sample; copper is electroplated onto the first sample to obtain a first cell. By setting the buffer layer and the doped layer in contact, the contact resistance value of the cell can be significantly reduced, and the light transmittance and short-circuit current of the cell can be improved.

[0104] In one embodiment, depositing a first conductive layer on the surface of the buffer layer away from the silicon wafer and depositing a second conductive layer on the surface of the second doped layer away from the silicon wafer includes:

[0105] A first transparent conductive layer is deposited on the surface of the buffer layer away from the silicon wafer, and a second transparent conductive layer is deposited on the surface of the second doped layer away from the silicon wafer to obtain the second battery sample.

[0106] In one embodiment, an RPD device is used to deposit a first transparent conductive layer on the surface of the buffer layer away from the silicon wafer. The conditions for depositing the first transparent conductive layer include: at room temperature, a mixture of argon and hydrogen is introduced, the ratio of argon to hydrogen (Ar:H2) is between 15 and 60, the chamber pressure is controlled between 0.3 Pa and 1 Pa, and the power supply is between 2 kW and 5 kW.

[0107] In one embodiment, preferably, the conditions for depositing the first transparent conductive layer are an argon-to-hydrogen ratio of 30, a chamber pressure of 0.32 Pa, and a power supply of 2.4 KW.

[0108] In one embodiment, the first transparent conductive layer comprises a TCO film. Optionally, the TCO film can be indium cerium oxide (ICO), indium tungsten oxide (IWO), indium titanium oxide (ITiO), indium molybdenum oxide (IMO), indium hafnium oxide (IHfO), or indium zirconium oxide (IZrO). Preferably, it has been verified that indium zirconium oxide (IZrO) as a transparent conductive layer has a high mobility of 126 cm⁻¹. 2 / Vs, and has good contact with the ITO layer, making it suitable as the first transparent conductive layer of the battery.

[0109] In one embodiment, an RPD device is used to deposit a second transparent conductive layer on the surface of the second doped layer away from the silicon wafer.

[0110] In one embodiment, the thickness of the second transparent conductive layer is 70nm to 90nm. Optionally, the thickness of the second transparent conductive layer can be 72nm, 75nm, 78nm, 80nm, 82nm, 85nm, 88nm, or 90nm.

[0111] In one embodiment, the second transparent conductive layer includes a TCO film. Optionally, the TCO film can be indium cerium oxide (ICO), indium tungsten oxide (IWO), indium titanium oxide (ITiO), indium molybdenum oxide (IMO), indium hafnium oxide (IHfO), or indium zirconium oxide (IZrO).

[0112] In one embodiment, ICO is used as the second transparent conductive layer.

[0113] In this embodiment, a buffer layer is provided to reduce the contact resistance between the first doped layer and the TCO layer. Simultaneously, the use of RPD to fabricate the first and second transparent conductive layers offers advantages such as high mobility, high transmittance, and low-temperature processing. Figure 2 As shown, the solid line represents the ITO film, the dashed line represents the ICO film, and the solid line represents the IZrO film. Under the premise of the same wavelength, the transmittance of the ICO film and the IZrO film is higher than that of the ITO film. A second transparent conductive layer is deposited on the second doped layer. Specifically, the ICO film can be prepared by RPD. It is in contact with the second doped layer and can have a low contact resistance value. Under the condition of high transmittance and high mobility, the ICO film can increase the light intake of the cell and improve the short-circuit current of the cell.

[0114] In one embodiment, depositing a first conductive layer on the surface of the buffer layer away from the silicon wafer and depositing a second conductive layer on the surface of the second doped layer away from the silicon wafer includes:

[0115] A third transparent conductive layer is deposited on the surface of the buffer layer away from the silicon wafer, a first transparent conductive layer is deposited on the surface of the third transparent conductive layer away from the silicon wafer, and a first transparent conductive protective layer is deposited on the surface of the first transparent conductive layer away from the silicon wafer.

[0116] A second transparent conductive layer is deposited on the surface of the second doped layer away from the silicon wafer, and a second transparent conductive protective layer is deposited on the surface of the second transparent conductive layer away from the silicon wafer to obtain the third sample of the battery.

[0117] In one embodiment, a third transparent conductive layer is deposited on the surface of the buffer layer away from the silicon wafer using a magnetron sputtering deposition apparatus.

[0118] In one embodiment, the thickness of the third transparent conductive layer is 20nm to 30nm. Optionally, the thickness of the third transparent conductive layer can be 20nm, 22nm, 24nm, 26nm, 28nm, or 30nm.

[0119] In one embodiment, the third transparent conductive layer comprises a titanium dioxide (TiO2) film.

[0120] In one embodiment, an RPD device is used to deposit a first transparent conductive layer on the surface of the third transparent conductive layer away from the silicon wafer.

[0121] In one embodiment, the thickness of the first transparent conductive layer is 25nm to 45nm. Optionally, the thickness of the first transparent conductive layer can be 27nm, 30nm, 32nm, 35nm, 37nm, 40nm, 42nm, or 45nm.

[0122] In one embodiment, the first transparent conductive layer comprises an IZrO film.

[0123] In one embodiment, the conditions for depositing the second transparent conductive layer include: introducing a mixture of argon and hydrogen gas at room temperature, with the argon to hydrogen gas ratio (Ar:H2) between 15 and 60, controlling the chamber pressure between 0.3 Pa and 1 Pa, and the power supply between 2 kW and 5 kW.

[0124] In one embodiment, preferably, the conditions for depositing the second transparent conductive layer are as follows: at room temperature, an argon-hydrogen mixture (hydrogen ratio of 30%) is introduced, the chamber pressure is 0.32 Pa, and the power supply is 2.4 KW.

[0125] In one embodiment, an RPD device is used to deposit a second transparent conductive layer on the surface of the second doped layer away from the silicon wafer.

[0126] In one embodiment, the thickness of the second transparent conductive layer is 70nm to 80nm. Optionally, the thickness of the second transparent conductive layer can be 70nm, 72nm, 74nm, 76nm, 78nm, or 80nm.

[0127] In one embodiment, the second transparent conductive layer comprises an ICO film.

[0128] In one embodiment, a first transparent conductive protective layer is deposited on the surface of the first transparent conductive layer away from the silicon wafer using a magnetron sputtering deposition apparatus, and a second transparent conductive protective layer is deposited on the surface of the second transparent conductive layer away from the silicon wafer.

[0129] In one embodiment, the thickness of the first transparent conductive protective layer and the second transparent conductive protective layer is 10nm to 15nm. Optionally, the thickness of the first transparent conductive protective layer and the second transparent conductive protective layer can be 10nm, 11nm, 12nm, 13nm, 14nm, or 15nm.

[0130] In one embodiment, the first transparent conductive protective layer and the second transparent conductive protective layer comprise tin oxide film.

[0131] In this embodiment, a buffer layer is used to reduce the contact resistance between the TCO layer (refractive index 2) and the doped layer. The third transparent conductive layer is mainly composed of TiO2 film with a refractive index of 2.4-2.7. Air has a refractive index of 1, and silicon has a refractive index of 4. The third transparent conductive layer increases the refractive gradient from air to silicon, further improving light absorption efficiency. The first transparent conductive layer (IZrO) and the second transparent conductive layer (ICO) are prepared by RPD, exhibiting high mobility and high transmittance. This step is a key process for improving the efficiency of heterojunction solar cells. Furthermore, the contact between ICO and the second doped layer is good, eliminating the need for a buffer layer. SnO2 is used as a protective layer on both sides of the battery, improving its corrosion resistance in electroplating and etching solutions, enhancing battery stability. Combined with copper electroplating, this reduces production costs while further improving battery efficiency.

[0132] In one embodiment, such as Figure 3 As shown, after electroplating copper and removing the copper film from the first sample to obtain the first battery, the method further includes:

[0133] Step 302: Mask the main grid of the first cell.

[0134] In one embodiment, the main grid of the first battery is masked by a fully automatic tape machine, or by screen printing technology, photosensitive adhesive is printed to mask the main grid.

[0135] Step 304: Deposit an antireflection layer on the surface of the first transparent conductive protective layer away from the silicon wafer to obtain the fourth battery sample.

[0136] In one embodiment, an antireflection layer is deposited on the surface of the first transparent conductive protective layer away from the silicon wafer using chemical vapor deposition.

[0137] In another embodiment, an antireflection layer is deposited on the surface of the first transparent conductive layer away from the silicon wafer using chemical vapor deposition, thereby increasing photon absorption by adding an antireflection layer.

[0138] In one embodiment, the antireflective layer comprises three silicon oxide films. The first silicon oxide film has a refractive index of 1.8 and a thickness of 20 nm to 30 nm. Optionally, the thickness of the first silicon oxide film is 20 nm, 22 nm, 24 nm, 26 nm, 28 nm, or 30 nm. The second silicon oxide film has a refractive index of 1.7 and a thickness of 30 nm to 50 nm. Optionally, the thickness of the second silicon oxide film is 30 nm, 32 nm, 34 nm, 36 nm, 38 nm, 40 nm, 42 nm, 44 nm, 46 nm, 48 nm, or 50 nm. The third silicon oxide film has a refractive index of 1.6 and a thickness of 40 nm to 70 nm. Optionally, the thickness of the third silicon oxide film is 40 nm, 42 nm, 44 nm, 46 nm, 48 nm, 50 nm, 52 nm, 54 nm, 56 nm, 58 nm, 60 nm, 62 nm, 64 nm, 66 nm, 68 nm, or 50 nm.

[0139] In one embodiment, the thickness of the three-layer silicon oxide film is adjusted according to the total thickness of the first transparent conductive layer, the third transparent conductive layer, and the first transparent conductive protective layer.

[0140] Step 306: The fourth sample is surface treated and encapsulated to obtain the second battery.

[0141] In one embodiment, the adhesive tape or photosensitive adhesive on the surface of the copper grid lines is removed by a process to expose the main grid lines, which are then placed in an ultra-high temperature sintering furnace and finally encapsulated with a POE (Polyolyaltha Olfin) film.

[0142] In this embodiment, a multilayer antireflective film process is used to further improve light absorption, and the encapsulation effect of silicon oxide and POE film is better, which is more conducive to the subsequent assembly of the battery.

[0143] In one embodiment, preferably, the first transparent conductive layer is indium zirconium oxide.

[0144] In this embodiment, when selecting the material for the transparent conductive layer, the mobility of IZrO was taken into account as 126 cm⁻¹. 2 / V·s, ICO mobility is 132cm 2 / V·s, ITO mobility is 71cm 2 / V·s, the mobility of both IZrO and ICO is much higher than that of ITO. It has been verified that the contact between ITO and IZrO is better than that between ITO and ICO. Therefore, in this embodiment, IZrO film is selected as the first transparent conductive layer to be paired with the buffer layer.

[0145] In one embodiment, the first transparent conductive layer and the second transparent conductive layer are formed by RPD deposition.

[0146] In one embodiment, the thickness of the first transparent conductive layer is 70nm-75nm. Optionally, the thickness of the first transparent conductive layer can be 70nm, 71nm, 72nm, 73nm, 74nm, or 75nm.

[0147] In one embodiment, since the total thickness of the TCO is 80nm, and the thickness of the buffer layer deposited under low pressure and low oxygen conditions is 5nm-10nm, the thickness of the first transparent conductive layer is 70nm-75nm.

[0148] In one embodiment, depositing an antireflection layer on the surface of the first transparent conductive protective layer away from the silicon wafer includes:

[0149] A first silicon oxide film is deposited on the surface of the first transparent conductive protective layer away from the silicon wafer;

[0150] A second silicon oxide film is deposited on the surface of the first silicon oxide film away from the silicon wafer;

[0151] A third silicon oxide film is deposited on the surface of the second silicon oxide film away from the silicon wafer;

[0152] The refractive indices of the first, second, and third silicon oxide films decrease sequentially.

[0153] In one embodiment, the conditions for depositing the antireflection layer include: a substrate temperature of 200°C, a radio frequency of 13.56 MHz, the introduction of silane and carbon dioxide for reaction, the gas flow ratio of silane to carbon dioxide being set at 1:10 to 1:20, and the radio frequency power being 30W to 200W. By adjusting different gas pressures and gas flow rates, silicon oxide films with different refractive indices are deposited.

[0154] In one embodiment, the first silicon oxide film in the antireflection layer has a refractive index of 1.8, the second silicon oxide film has a refractive index of 1.7, and the third silicon oxide film has a refractive index of 1.6.

[0155] In this embodiment, a multi-layered TCO layer with different refractive indices and a silicon oxide antireflection layer are used, with the refractive index gradually increasing from air to silicon, which can improve the absorption of sunlight.

[0156] In one embodiment, the refractive index of the antireflection layer changes linearly from the side closer to the silicon wafer to the side farther away from the silicon wafer. Specifically, by adjusting different gas pressures and gas flow rates, a silicon oxide film with a linearly changing refractive index is deposited, thereby causing the refractive index of the antireflection layer to gradually decrease from the side closer to the silicon wafer to the side farther away from the silicon wafer.

[0157] In one embodiment, depositing a first transparent conductive protective layer on the surface of the first transparent conductive layer away from the silicon wafer, and depositing a second transparent conductive protective layer on the surface of the second transparent conductive layer away from the silicon wafer, includes:

[0158] Under specified deposition conditions, a first transparent conductive protective layer and a second transparent conductive protective layer are deposited using a tin oxide-based target and a coating equipment.

[0159] In one embodiment, the conditions for depositing the first transparent conductive protective layer and the second transparent conductive protective layer include: based on a tin oxide-based target, a mixture of argon and oxygen is introduced at room temperature, the ratio of argon to oxygen (Ar:O2) is controlled between 1 and 5, the chamber pressure is maintained between 0.3 Pa and 0.6 Pa, and the power density is between 3 kW / m and 8 kW / m.

[0160] In one embodiment, preferably, the conditions for depositing the first and second transparent conductive protective layers are a gas ratio (Ar:O2) of 2, a pressure of 0.48 Pa, and a power density of 4.2 kW / m. The tin oxide-based target material includes all doped tin oxide-based targets such as pure tin oxide, tantalum-doped tin oxide, gallium-doped tin oxide, magnesium-doped tin oxide, antimony-doped tin oxide, and zirconium-doped tin oxide.

[0161] In one embodiment, the first and second transparent conductive protective layers are made of tin oxide.

[0162] In one embodiment, depositing a third transparent conductive layer on the surface of the buffer layer away from the silicon wafer includes:

[0163] Under specified deposition conditions, a third transparent conductive layer is deposited using a titanium dioxide-based ceramic target and a coating equipment.

[0164] In one embodiment, the conditions for depositing the third transparent conductive layer include: based on a titanium oxide-based ceramic target, a mixture of argon and oxygen is introduced at room temperature, the ratio of argon to oxygen (Ar:O2) is controlled between 1 and 6, the chamber pressure is maintained between 0.4 Pa and 1 Pa, and the power density is between 3 kW / m and 8 kW / m.

[0165] In one embodiment, preferably, the conditions for depositing the third transparent conductive layer are a gas ratio (Ar:O2) of 2, a pressure of 0.75 Pa, and a power density of 4 kW / m. The titanium oxide-based ceramic target includes pure titanium oxide, niobium-doped titanium dioxide, cerium-doped titanium dioxide, and antimony-doped titanium dioxide. Titanium oxide-based ceramic targets are used to deposit the third transparent conductive layer because they have a higher refractive index, reaching 2.4–2.7. Compared to commonly used materials with a refractive index of around 2, such as SnO2, ICO, and ITO, this further enhances the absorption of sunlight.

[0166] In one embodiment, the third transparent conductive layer material is titanium oxide.

[0167] In one embodiment, masking the main grid of the first battery includes:

[0168] The main grid of the first cell can be masked by encapsulating tape, or by printing photosensitive adhesive on screen to mask the main grid.

[0169] In one embodiment, surface treatment and encapsulation of the fourth sample includes:

[0170] Remove the tape or photosensitive adhesive from the surface of the copper grid lines of the fourth sample.

[0171] In another embodiment, such as Figure 4 As shown, a method for preparing a heterojunction solar cell is provided, comprising the following steps:

[0172] Step 402, providing a silicon wafer; the silicon wafer includes a first surface and a second surface disposed opposite to each other.

[0173] Step 404: Deposit a first passivation layer and a first doped layer on the first surface, and deposit a second passivation layer and a second doped layer on the second surface.

[0174] Step 406: Deposit a buffer layer on the surface of the first doped layer away from the silicon wafer using PVD deposition.

[0175] Step 408: Deposit a first transparent conductive layer on the surface of the buffer layer away from the silicon wafer, and deposit a second transparent conductive layer on the surface of the second doped layer away from the silicon wafer to obtain the second battery sample.

[0176] Step 410: Electroplating copper onto the second sample to obtain the first battery.

[0177] The above-described method for fabricating heterojunction solar cells and the heterojunction solar cell involve providing a silicon wafer; the silicon wafer includes a first surface and a second surface disposed opposite to each other; depositing a first passivation layer and a first doped layer on the first surface, and depositing a second passivation layer and a second doped layer on the second surface; depositing a buffer layer on the surface of the first doped layer away from the silicon wafer via PVD deposition; depositing a first transparent conductive layer on the surface of the buffer layer away from the silicon wafer, and depositing a second transparent conductive layer on the surface of the second doped layer away from the silicon wafer, to obtain a second cell sample; and electroplating copper on the second sample to obtain a first cell. By using a buffer layer in contact with the first doped layer, the contact resistance of the cell can be significantly reduced; the RPD fabrication of the first transparent conductive layer (IZrO) and the second transparent conductive layer (ICO) main layers has the characteristics of high mobility and high permeability, which is beneficial for carrier transport.

[0178] In another embodiment, such as Figure 5As shown, a method for preparing a heterojunction solar cell is provided, comprising the following steps:

[0179] Step 502, providing a silicon wafer; the silicon wafer includes a first surface and a second surface disposed opposite to each other.

[0180] Step 504: Deposit a first passivation layer and a first doped layer on the first surface, and deposit a second passivation layer and a second doped layer on the second surface.

[0181] Step 506: Deposit a buffer layer on the surface of the first doped layer away from the silicon wafer using PVD deposition.

[0182] Step 508: Deposit a third transparent conductive layer on the surface of the buffer layer away from the silicon wafer, deposit a first transparent conductive layer on the surface of the third transparent conductive layer away from the silicon wafer, and deposit a first transparent conductive protective layer on the surface of the first transparent conductive layer away from the silicon wafer.

[0183] Step 510: Deposit a second transparent conductive layer on the surface of the second doped layer away from the silicon wafer, and deposit a second transparent conductive protective layer on the surface of the second transparent conductive layer away from the silicon wafer to obtain the third sample of the battery.

[0184] Step 512: Electroplating copper onto the third sample to obtain the first battery.

[0185] Step 514: Mask the main grid of the first cell.

[0186] Step 516: Deposit an antireflection layer on the surface of the first transparent conductive protective layer away from the silicon wafer to obtain the fourth battery sample.

[0187] Step 518: The fourth sample is surface treated and encapsulated to obtain the second battery.

[0188] In the step of electroplating copper on the third sample to obtain the first battery, a copper seed layer can be formed first, and then the electroplating process can be performed. Alternatively, copper grid lines can be electroplated directly on the first transparent conductive protective layer and the second transparent conductive protective layer.

[0189] In the prior art, the transparent conductive layer material is an ITO layer, on which copper grid lines are directly electroplated. The adhesion between the copper grid lines and the ITO layer is poor, and the film is easy to peel off. Therefore, before the copper electroplating process, a copper seed layer needs to be deposited on the ITO layer using a PVD device to improve the adhesion between the subsequent electroplated copper grid lines and the ITO layer.

[0190] In one embodiment, after forming the copper seed layer and performing the copper electroplating process, it is necessary to remove the copper seed layer outside the copper gate lines, which requires an etching process. However, the etching process can damage the transparent conductive layer, increase the process steps, and raise costs. Therefore, in one embodiment, preferably, due to the presence of the first and second transparent conductive protective layers, it is not necessary to prepare a copper seed layer on the first and second transparent conductive protective layers, and the copper electroplating process can be performed directly.

[0191] In this embodiment, the copper grid lines formed by directly performing copper electroplating on the first and second transparent conductive protective layers exhibit better bonding performance with the first and second transparent conductive protective layers. This reduces the need for forming a copper seed layer and subsequent etching processes, simplifying the process and further avoiding damage to the transparent conductive layer caused by the copper seed removal process.

[0192] In this embodiment, a multi-layered TCO layer with different refractive indices and a silicon oxide antireflection layer are used. The refractive index of the silicon oxide antireflection layer gradually increases from air to silicon, which can improve the absorption of sunlight. Tin oxide is used as a protective layer for the TCO, which can improve the corrosion resistance of the battery during the electroplating process. The second transparent conductive layer prepared by RPD is in contact with the second doped layer, which can significantly reduce the contact resistance of the battery.

[0193] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0194] Based on the same inventive concept, this application also provides a heterojunction solar cell that implements the above-described method for preparing heterojunction solar cells. The implementation scheme of this cell is similar to that described in the above method; therefore, the specific limitations of one or more heterojunction solar cell embodiments provided below can be found in the limitations of the method for preparing heterojunction solar cells described above, and will not be repeated here.

[0195] In one embodiment, such as Figure 6As shown, a heterojunction solar cell is provided, comprising: a silicon wafer 602, a first passivation layer 604, a second passivation layer 606, a first doped layer 608, a second doped layer 610, a buffer layer 612, a first conductive layer, a second conductive layer, a first electroplated copper electrode 614, and a second electroplated copper electrode 616, wherein:

[0196] Silicon wafer 602 includes a first surface and a second surface disposed opposite to each other;

[0197] A first passivation layer 604 is deposited on the first surface;

[0198] A second passivation layer 606 is deposited on the second surface;

[0199] The first doped layer 608 is deposited on the surface of the first passivation layer 604 away from the silicon wafer;

[0200] The second doped layer 610 is deposited on the surface of the second passivation layer 606 away from the silicon wafer;

[0201] A buffer layer 612 is deposited on the surface of the first doped layer 608 away from the silicon wafer;

[0202] The first conductive layer is deposited on the surface of the buffer layer 612 away from the silicon wafer;

[0203] The second conductive layer is deposited on the surface of the second doped layer 610 away from the silicon wafer;

[0204] The first electroplated copper electrode 614 is deposited on the surface of the first conductive layer away from the silicon wafer;

[0205] The second electroplated copper electrode 616 is deposited on the surface of the second conductive layer away from the silicon wafer.

[0206] In one embodiment, the first conductive layer is a first transparent conductive layer 618, which is deposited on the surface of the buffer layer away from the silicon wafer; the second conductive layer is a second transparent conductive layer 620, which is deposited on the surface of the second doped layer away from the silicon wafer.

[0207] In one embodiment, a first electroplated copper electrode 614, a first transparent conductive layer 618, a buffer layer 612, a first doped layer 608, and a first passivation layer 604 constitute a first surface of the battery; a second passivation layer 606, a second doped layer 610, a second transparent conductive layer 620, and a second electroplated copper electrode 616 constitute a second surface of the battery.

[0208] In one embodiment, specifically, the first doped layer 608 is an n-type doped layer, the second doped layer 610 is a p-type doped layer, the buffer layer 612 is an ITO layer deposited by PVD, and the first transparent conductive layer 618 and the second transparent conductive layer 620 are both TCO layers deposited by RPD.

[0209] In this embodiment, a 5nm-10nm buffer layer 612 is prepared by PVD, and a 70nm-75nm first transparent conductive layer 618 (ICO, IWO, IZrO, IHfO, IMO, ITiO) is prepared by RPD to form a double-layered TCO layer. This layer contacts the first doped layer 608, i.e., phosphorus-doped microcrystalline silicon. Compared with single-layer ITO and RPD-prepared TCO layers, the double-layered TCO layer can effectively reduce the contact resistance value of the phosphorus-doped microcrystalline silicon interface. The 80nm second transparent conductive layer 620 prepared by RPD has better contact with the second doped layer 610, i.e., boron-doped microcrystalline silicon, than ITO. Furthermore, the electrical and optical properties of the TCO film prepared by RPD are better. Therefore, considering cost, a single-layer TCO film can still achieve the advantages of high transmittance, mobility, and low cross-resistance.

[0210] In one embodiment, such as Figure 7 As shown, the first conductive layer, deposited on the surface of the buffer layer away from the silicon wafer, comprises:

[0211] The third transparent conductive layer 702 is deposited on the surface of the buffer layer 612 away from the silicon wafer;

[0212] A first transparent conductive layer 618 is deposited on the surface of the third transparent conductive layer 702 away from the silicon wafer;

[0213] A first transparent conductive protective layer 704 is deposited on the surface of the first transparent conductive layer 618 away from the silicon wafer;

[0214] The second conductive layer, deposited on the surface of the second doped layer away from the silicon wafer, specifically includes:

[0215] The second transparent conductive layer 620 is deposited on the surface of the second doped layer 610 away from the silicon wafer;

[0216] A second transparent conductive protective layer 706 is deposited on the surface of the second transparent conductive layer 620 away from the silicon wafer.

[0217] Furthermore, the first conductive layer includes a third transparent conductive layer 702, a first transparent conductive layer 618, and a first transparent conductive protective layer 704;

[0218] The second conductive layer includes a second transparent conductive layer 620 and a second transparent conductive protective layer 706;

[0219] Furthermore, both the first transparent conductive protective layer 704 and the second transparent conductive protective layer 706 are made of tin oxide.

[0220] In one embodiment, the heterojunction solar cell further includes:

[0221] An antireflection layer is deposited on the surface of the first transparent conductive protective layer away from the silicon wafer.

[0222] In one embodiment, the antireflective layer includes a first silicon oxide film 708, a second silicon oxide film 710, and a third silicon oxide film 712.

[0223] In one embodiment, a first electroplated copper electrode 614, an antireflection layer (including a first silicon oxide film 708, a second silicon oxide film 710, and a third silicon oxide film 712), a first transparent conductive protective layer 704, a first transparent conductive layer 618, a third transparent conductive layer 702, a buffer layer 612, a first doped layer 608, and a first passivation layer 604 constitute the first surface of the battery; a second passivation layer 606, a second doped layer 610, a second transparent conductive layer 620, a second transparent conductive protective layer 706, and a second electroplated copper electrode 616 constitute the second surface of the battery.

[0224] Furthermore, after depositing a buffer layer 612 via PVD on the front side, a high-refractive-index titanium dioxide transparent conductive layer is deposited to improve light absorption. The first and second transparent conductive layers, fabricated using RPD, exhibit high transmittance and high mobility. Tin oxide transparent conductive films are deposited on both sides of the cell as protective layers to improve corrosion resistance during electroplating. Following the electroplating process, optimization of the multilayer antireflective coating further enhances the solar cell's photon absorption capacity. The multi-layered TCO layer, copper electroplating process, and antireflective layer design are of great significance for improving the photoelectric conversion efficiency of solar cells.

[0225] The modules in the aforementioned heterojunction solar cells can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device, or stored in the memory of a computer device as software, so that the processor can call and execute the operations corresponding to each module.

[0226] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0227] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A method for fabricating a heterojunction solar cell, characterized in that, The method includes: A silicon wafer is provided; the silicon wafer includes a first surface and a second surface disposed opposite to each other; A first passivation layer and a first doped layer are deposited on the first surface, and a second passivation layer and a second doped layer are deposited on the second surface; A buffer layer is deposited on the surface of the first doped layer away from the silicon wafer by PVD deposition; the buffer layer is an ITO layer deposited by PVD. A first conductive layer is deposited on the surface of the buffer layer away from the silicon wafer, and a second conductive layer is deposited on the surface of the second doped layer away from the silicon wafer to obtain a first battery sample; The first sample was electroplated with copper to obtain the first battery. The deposition of a first conductive layer on the surface of the buffer layer away from the silicon wafer, and the deposition of a second conductive layer on the surface of the second doped layer away from the silicon wafer, includes: A first transparent conductive layer is deposited on the surface of the buffer layer away from the silicon wafer; A second transparent conductive layer is deposited on the surface of the second doped layer away from the silicon wafer to obtain a second battery sample; Wherein, the first doped layer is an n-type doped layer, and the second doped layer is a p-type doped layer; the first transparent conductive layer and the second transparent conductive layer are formed by RPD deposition; the first transparent conductive layer and the second transparent conductive layer are any one of indium cerium oxide (ICO), indium tungsten oxide (IWO), indium titanium oxide (ITiO), indium molybdenum oxide (IMO), indium hafnium oxide (IHfO), and indium zirconium oxide (IZrO).

2. The method according to claim 1, characterized in that, The deposition of a first conductive layer on the surface of the buffer layer away from the silicon wafer, and the deposition of a second conductive layer on the surface of the second doped layer away from the silicon wafer, includes: A third transparent conductive layer is deposited on the surface of the buffer layer away from the silicon wafer, a first transparent conductive layer is deposited on the surface of the third transparent conductive layer away from the silicon wafer, and a first transparent conductive protective layer is deposited on the surface of the first transparent conductive layer away from the silicon wafer. A second transparent conductive layer is deposited on the surface of the second doped layer away from the silicon wafer, and a second transparent conductive protective layer is deposited on the surface of the second transparent conductive layer away from the silicon wafer to obtain a third sample of the battery; the materials of the first transparent conductive protective layer and the second transparent conductive protective layer are tin oxide.

3. The method according to claim 2, characterized in that, The method further includes: Masking is applied to the main grid of the first battery; An antireflection layer was deposited on the surface of the first transparent conductive protective layer away from the silicon wafer to obtain the fourth battery sample; The fourth sample is surface-treated and encapsulated to obtain the second battery.

4. The method according to claim 3, characterized in that, The refractive index of the antireflective layer changes linearly from the side closest to the silicon wafer to the side furthest from the silicon wafer.

5. The method according to claim 3, characterized in that, The deposition of an antireflection layer on the surface of the first transparent conductive protective layer away from the silicon wafer includes: A first silicon oxide film is deposited on the surface of the first transparent conductive protective layer away from the silicon wafer; A second silicon oxide film is deposited on the surface of the first silicon oxide film away from the silicon wafer; A third silicon oxide film is deposited on the surface of the second silicon oxide film away from the silicon wafer; The refractive indices of the first silicon oxide film, the second silicon oxide film, and the third silicon oxide film decrease sequentially.

6. The method according to claim 2, characterized in that, The material of the third transparent conductive layer is titanium oxide.

7. The method according to claim 3, characterized in that, The masking of the main grid of the first battery includes: The main grid of the first battery can be masked by encapsulating tape, or by printing photosensitive adhesive on screen to mask the main grid.

8. The method according to claim 3, characterized in that, The surface treatment and encapsulation of the fourth sample includes: Remove the tape or photosensitive adhesive from the surface of the copper grid lines of the fourth sample.

9. A heterojunction solar cell, characterized in that, The battery includes: A silicon wafer, including a first surface and a second surface disposed opposite to each other; A first passivation layer is deposited on the first surface; A second passivation layer is deposited on the second surface; A first doped layer is deposited on the surface of the first passivation layer away from the silicon wafer; A second doped layer is deposited on the surface of the second passivation layer away from the silicon wafer; A buffer layer is deposited on the surface of the first doped layer away from the silicon wafer; The first conductive layer is deposited on the surface of the buffer layer away from the silicon wafer; A second conductive layer is deposited on the surface of the second doped layer away from the silicon wafer; The first electroplated copper electrode is deposited on the surface of the first conductive layer away from the silicon wafer; The second electroplated copper electrode is deposited on the surface of the second conductive layer away from the silicon wafer; The first doped layer is an n-type doped layer, and the second doped layer is a p-type doped layer; The first conductive layer is deposited on the surface of the buffer layer away from the silicon wafer; the second conductive layer is deposited on the surface of the second doped layer away from the silicon wafer and further comprises: a first transparent conductive layer deposited on the surface of the buffer layer away from the silicon wafer; a second transparent conductive layer deposited on the surface of the second doped layer away from the silicon wafer; the buffer layer is an ITO layer deposited by PVD; the first transparent conductive layer and the second transparent conductive layer are both any one of indium cerium oxide (ICO), indium tungsten oxide (IWO), indium titanium oxide (ITiO), indium molybdenum oxide (IMO), indium hafnium oxide (IHfO), and indium zirconium oxide (IZrO); The buffer layer is deposited on the first doped layer by PVD deposition. The first and second transparent conductive layers are formed by RPD deposition.

10. The battery according to claim 9, characterized in that, The first conductive layer also includes: A third transparent conductive layer is deposited between the buffer layer and the first transparent conductive layer; A first transparent conductive protective layer is deposited on the surface of the first transparent conductive layer away from the silicon wafer; The second conductive layer also includes: A second transparent conductive protective layer is deposited on the surface of the second transparent conductive layer away from the silicon wafer; the materials of the first transparent conductive protective layer and the second transparent conductive protective layer are tin oxide.

11. The battery according to claim 10, characterized in that, The battery also includes: An antireflection layer is deposited on the surface of the first transparent conductive protective layer away from the silicon wafer.

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