Array infrared detector chip and preparation method and application thereof

Abstract

The application discloses an array infrared detector chip and a preparation method and application thereof. The array infrared detector chip comprises the following structures: a substrate, an N-type contact layer arranged on the upper surface of the substrate, and a pixel arranged on the upper surface of the N-type contact layer. The number of the pixels is m, and the pixels are separated from each other. The pixel comprises the following structures: a P-type contact layer and a composite distributed Bragg reflector with a number of n. The composite distributed Bragg reflector comprises a distributed Bragg reflector and an i-type absorption layer. The thickness of the i-type absorption layer is 10-500 nm. The number m and the number n are independently selected from positive integers. The array infrared detector chip of the application is a side light structure array infrared detector chip, that is, the light incidence direction is perpendicular to the epitaxial growth direction of the absorption layer material, thereby solving the phenomenon that the response time of the detector is slow and the high-frequency application is not satisfied when the signal-to-noise ratio and the responsivity are improved.

Description

Technical Field

[0001] This invention relates to the field of photoelectric detector technology, and in particular to an array infrared detector chip, its fabrication method, and its application. Background Technology

[0002] Currently, short-wave infrared array detectors are rapidly developing. Array infrared detector components are generally assembled from detector chips and readout circuits using high-precision flip-chip eutectic bonding. However, conventional array infrared detectors have relatively low responsivity. To improve responsivity, conventional array infrared detectors increase the thickness of the i-type absorption layer. However, increasing the thickness of the i-type absorption layer increases the overall device capacitance, lengthening the transit time after electrons and holes separate, thus slowing down the response time. In other words, the responsivity and response time of conventional array infrared detectors are inversely proportional. This means that existing array infrared detectors cannot adequately meet the performance requirements of the current market, and their application in high-performance detectors is severely limited.

[0003] Therefore, there is an urgent need for a new type of array infrared detector chip to solve the above problems. Summary of the Invention

[0004] The first technical problem to be solved by this invention is:

[0005] An array infrared detector chip is provided.

[0006] The second technical problem to be solved by this invention is:

[0007] A method for fabricating the array infrared detector chip is provided.

[0008] The third technical problem to be solved by this invention is:

[0009] Application of the array infrared detector chip.

[0010] To solve the first technical problem, the technical solution adopted by the present invention is as follows:

[0011] An array infrared detector chip includes the following structure:

[0012] Substrate;

[0013] An N-type contact layer is disposed on the upper surface of the substrate;

[0014] Pixel, the pixel being disposed on the upper surface of the N-type contact layer;

[0015] The number of pixels is m, and the pixels are separated from each other;

[0016] The pixel includes the following structure: a P-type contact layer and n composite distributed Bragg reflectors;

[0017] The composite distributed Bragg reflector includes a distributed Bragg reflector and an i-type absorption layer;

[0018] The thickness of the i-type absorption layer is 10-500 nm;

[0019] Where m and n are independently selected from positive integers.

[0020] According to embodiments of the present invention, one of the technical solutions has at least one of the following advantages or beneficial effects:

[0021] 1. The array infrared detector chip of the present invention includes n composite distributed Bragg reflectors, each comprising a distributed Bragg reflector and an i-type absorption layer. Specifically, when n is 1, the structure of the composite distributed Bragg reflector is: a distributed Bragg reflector and an i-type absorption layer; when n is 2, the structure is: a distributed Bragg reflector, an i-type absorption layer, another distributed Bragg reflector, and another i-type absorption layer. This structural arrangement minimizes the thickness of the i-type absorption layer; that is, when the thickness of the i-type absorption layer is 10-500 nm, the array infrared detector chip of the present invention exhibits excellent responsivity.

[0022] 2. The array infrared detector chip of the present invention, due to its structural design, is a side-incident array infrared detector chip, meaning the light incident direction is perpendicular to the epitaxial growth direction of the absorption layer material. This solves the problem of slower detector response time caused by efforts to improve signal-to-noise ratio and responsivity, which fails to meet the requirements of high-frequency applications. Furthermore, since the composite distributed Bragg reflector includes a distributed Bragg reflector and an i-type absorption layer, and the distributed Bragg reflector has a certain light-confining effect, the array infrared detector chip of the present invention requires the light incident direction to be perpendicular to the epitaxial growth direction of the array infrared detector chip to achieve optimal responsivity. In addition, if the light incident direction is not perpendicular to the epitaxial growth direction, the distributed Bragg reflector will inevitably block the light incident to some extent, thereby affecting the absorption of light by the i-type absorption layer.

[0023] According to one embodiment of the present invention, n≥2. When n≥2, in the composite distributed Bragg reflector, the i-type absorption layer and the distributed Bragg reflector will inevitably form a sandwich structure, that is, two distributed Bragg reflectors sandwich an i-type absorption layer. Since the distributed Bragg reflector has a certain light confinement effect, the photoelectric energy can be more concentrated in the i-type absorption layer in this sandwich structure, thereby further improving the responsivity of the array infrared detector chip of the present invention.

[0024] According to one embodiment of the present invention, in use, the light incident direction of the array infrared detector chip is perpendicular to the epitaxial growth direction of the array infrared detector chip. Since the composite distributed Bragg reflector includes a distributed Bragg reflector and an i-type absorption layer, and the distributed Bragg reflector has a certain light confinement effect, the array infrared detector chip of the present invention achieves optimal responsivity only when the light incident direction is perpendicular to the epitaxial growth direction of the array infrared detector chip. Furthermore, if the light incident direction is not perpendicular to the epitaxial growth direction, the distributed Bragg reflector will inevitably block the light incident to a certain extent, thereby affecting the absorption of light by the i-type absorption layer.

[0025] To improve responsivity, existing conventional detectors inevitably require increasing the thickness of the i-type layer, which often exceeds 2000 nm. Such a large thickness inevitably slows down the detector's response time, making it unsuitable for high-frequency applications. Furthermore, existing conventional detectors use a side-spot light-incident method, meaning the light-incident direction is aligned with the epitaxial growth direction, which further delays the detector's response time. Moreover, to improve response, existing conventional detectors typically require thinning or complete removal of the InP substrate, leading to a high probability of fragmentation.

[0026] According to one embodiment of the present invention, the thickness of the type i absorber layer is 10-200 nm.

[0027] According to one embodiment of the present invention, the thickness of the type i absorber layer is 10-150 nm.

[0028] According to one embodiment of the present invention, the thickness of the type i absorber layer is 10-100 nm.

[0029] According to one embodiment of the present invention, the thickness of the type i absorber layer is 50-100 nm.

[0030] According to one embodiment of the present invention, the thickness of the type i absorber layer is 80-100 nm.

[0031] According to one embodiment of the present invention, the values ​​of n and m correspond to the array size of the array infrared detector chip. For example, a 320*256 array is commonly used, in which case n is 256 and m is 320, thus forming a 320*256 array detector.

[0032] According to one embodiment of the present invention, the array size of the array infrared detector chip includes at least: 128*128, 320*256, 640*512, 1280*1024, 2048*2048 and 4096*4096.

[0033] According to one embodiment of the present invention, a passivation film is deposited on the surface of the pixel.

[0034] According to one embodiment of the present invention, the substrate includes an InP substrate.

[0035] According to one embodiment of the present invention, the thickness of the substrate is 200-1000 μm.

[0036] According to one embodiment of the present invention, the thickness of the N-type contact layer is 100-500 nm.

[0037] According to one embodiment of the present invention, the thickness of the P-type contact layer is 100-500 nm.

[0038] According to one embodiment of the present invention, the thickness of the distributed Bragg reflector is 20-100 nm.

[0039] According to one embodiment of the present invention, in the array infrared detector chip, an N-type electrode is provided on the lower surface of the substrate.

[0040] According to one embodiment of the present invention, in the array infrared detector chip, a P-type electrode is provided on the side of the P-type contact layer away from the N-type contact layer.

[0041] According to one embodiment of the present invention, the P-type electrode includes a Ti / Pt / Au electrode, wherein the thicknesses of the Ti layer, the Pt layer and the Au layer are 10-100 nm, 10-100 nm and 100-2000 nm, respectively.

[0042] To solve the second technical problem, the technical solution adopted by the present invention is as follows:

[0043] A method for fabricating the array infrared detector chip includes the following steps:

[0044] An N-type contact layer and an initial pixel are epitaxially grown sequentially on a substrate. The initial pixel is then photolithographically etched and etched to obtain an array infrared detector chip.

[0045] The method for preparing the array infrared detector chip uses a simple packaging method to prepare the infrared detector chip, without the need for additional flip-chip bonding, making the method of the present invention more efficient than conventional methods.

[0046] According to an embodiment of the present invention, a method for fabricating the array infrared detector chip includes the following steps: epitaxially growing an N-type contact layer and an initial pixel on a substrate; performing photolithography and etching on the initial pixel to obtain a number of m pixels; depositing a passivation film on the surface of the pixel to passivate and protect the sidewalls of the pixel; opening holes in the passivation film on the surface of the P-type contact layer; forming P-type electrodes at the opening holes using a photomask lift-off method; and depositing an N-type electrode on the back side of the substrate to obtain the array infrared detector chip.

[0047] Another aspect of the present invention relates to the application of the array infrared detector chip in a photodetector. This includes the array infrared detector chip described in the first aspect embodiment above. Since this application employs all the technical solutions of the above-described array infrared detector chip, it possesses at least all the beneficial effects brought about by the technical solutions of the above embodiments.

[0048] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. Attached Figure Description

[0049] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0050] Figure 1 This is a schematic diagram of the epitaxial layer in Example 1.

[0051] Figure 2 This is a schematic diagram of the structure of an independent pixel in Example 1.

[0052] Figure 3 This is a schematic diagram of the structure of a pixel after the passivation film is deposited in Example 1.

[0053] Figure 4 This is a schematic diagram of the array infrared detector chip structure after depositing P-type electrodes in Example 1.

[0054] Figure 5 This is a schematic diagram of the array infrared detector chip structure after depositing N-type electrodes in Example 1.

[0055] Figure 6 This is a schematic diagram of a comparative infrared detector chip structure. Detailed Implementation

[0056] The embodiments of the present invention are described in detail below. Throughout the embodiments, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions. The embodiments described below are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0057] In the description of this invention, the use of terms such as "first," "second," etc., is for the purpose of distinguishing technical features only and should not be construed as indicating or implying relative importance, or implicitly indicating the number of technical features indicated, or implicitly indicating the order of the technical features indicated.

[0058] In the description of this invention, it should be understood that the orientation descriptions, such as up, down, etc., are based on the orientation or positional relationship shown in the embodiments, and are only for the purpose of facilitating the description of this invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.

[0059] In the description of this invention, it should be noted that, unless otherwise explicitly defined, terms such as "setting," "installation," and "connection" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this invention in conjunction with the specific content of the technical solution.

[0060] The technical solutions of the present invention will be clearly and completely described below with reference to the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of the present invention.

[0061] Unless otherwise specified, the reagents, methods and equipment used in this invention are all conventional reagents, methods and equipment in this technical field.

[0062] Example 1

[0063] An array infrared detector chip includes the following structure:

[0064] N electrode;

[0065] An N-type InP substrate is disposed on the upper surface of the N electrode.

[0066] An N-type InP ohmic contact layer is disposed on the upper surface of the substrate.

[0067] Pixel, the aforementioned pixel is disposed on the upper surface of the aforementioned N-type InP ohmic contact layer;

[0068] The number of pixels mentioned above is 320, and the pixels are separated from each other;

[0069] The aforementioned pixels include the following structure: a P-type InP contact layer and 256 composite distributed Bragg mirrors;

[0070] The aforementioned composite distributed Bragg reflector includes a distributed Bragg reflector (DBR) and an i-type InGaAs absorbing layer;

[0071] The thickness of the i-type InGaAs absorber layer is 100 nm.

[0072] The thickness of the distributed Bragg mirror (DBR) is 50 nm.

[0073] The thickness of the P-type contact layer is 200 nm;

[0074] The InP substrate has a thickness of 350 μm.

[0075] The thickness of the N-type InP ohmic contact layer is 200 nm.

[0076] The fabrication method of the above-mentioned array infrared detector chip includes the following steps:

[0077] 1. For example Figure 1 As shown, a 350μm thick InP substrate is provided, on which a 200nm N-type contact layer, (100nm i-type absorption layer, 50nm DBR)*256 pairs, and a 200nm P-type contact layer are grown sequentially to form an array-type infrared detector epitaxy.

[0078] 2. For example Figure 2 As shown, photolithography is performed on the upper surface of the epitaxial wafer, and the mesa is dry etched to prepare 320 mesa trenches, thereby forming 320*256 independent pixels;

[0079] 3. For example Figure 3 As shown, a 500 nm thick SiNx passivation film is deposited to passivate and protect the sidewalls;

[0080] 4. For example Figure 4 As shown, the passivation film is etched with an open hole using a photomask etching method, and the etching solution is ammonium fluoride solution; a P-type electrode is formed by a photomask stripping method. The P-electrode is Ti / Pt / Au with thicknesses of 50nm / 50nm / 500nm, respectively.

[0081] 5. For example Figure 5 As shown, an N-type electrode is formed on the back side of the substrate. The N-electrode is made of Ti / Pt / Au with thicknesses of 50nm / 50nm / 500nm, respectively, to obtain an array infrared detector chip.

[0082] Example 2

[0083] The difference between Example 2 and Example 1 is that Example 1 has 320*256 independent pixels, while Example 2 has 128*128 independent pixels.

[0084] An array infrared detector chip includes the following structure:

[0085] N electrode;

[0086] An N-type InP substrate is disposed on the upper surface of the N electrode.

[0087] An N-type InP ohmic contact layer is disposed on the upper surface of the substrate.

[0088] Pixel, the aforementioned pixel is disposed on the upper surface of the aforementioned N-type InP ohmic contact layer;

[0089] The number of pixels mentioned above is 128, and the pixels are separated from each other;

[0090] The aforementioned pixel comprises the following structure: a P-type InP contact layer and 128 composite distributed Bragg mirrors;

[0091] The aforementioned composite distributed Bragg reflector includes a distributed Bragg reflector (DBR) and an i-type InGaAs absorbing layer;

[0092] The thickness of the i-type InGaAs absorber layer is 100 nm.

[0093] The thickness of the distributed Bragg mirror (DBR) is 50 nm.

[0094] The thickness of the P-type contact layer is 200 nm;

[0095] The InP substrate has a thickness of 350 μm.

[0096] The thickness of the N-type InP ohmic contact layer is 200 nm.

[0097] The fabrication method of the above-mentioned array infrared detector chip includes the following steps:

[0098] 1. Provide a 350μm thick InP substrate, and grow on it sequentially a 200nm N-type contact layer, (100nm i-type absorption layer, 50nm DBR)*128 pairs, and a 200nm P-type contact layer to form an array-type infrared detector epitaxy.

[0099] 2. Photolithography is performed on the upper surface of the epitaxial wafer, and the mesa is dry etched to prepare 128 mesa trenches, thereby forming 128*128 independent pixels;

[0100] 3. Deposit a 500nm thick SiNx passivation film to passivate and protect the sidewalls;

[0101] 4. The passivation film is etched using a photomask etching method with ammonium fluoride solution; a P-type electrode is formed using a photomask stripping method. The P-electrode is made of Ti / Pt / Au with thicknesses of 50nm / 50nm / 500nm, respectively.

[0102] 5. An N-type electrode is formed on the back side of the substrate. The N-electrode is made of Ti / Pt / Au with thicknesses of 50nm / 50nm / 500nm, respectively, to obtain an array infrared detector chip.

[0103] Example 3

[0104] The difference between Example 3 and Example 1 is that Example 1 has 320*256 independent pixels, while Example 3 has 640*512 independent pixels.

[0105] An array infrared detector chip includes the following structure:

[0106] N electrode;

[0107] An N-type InP substrate is disposed on the upper surface of the N electrode.

[0108] An N-type InP ohmic contact layer is disposed on the upper surface of the substrate.

[0109] Pixel, the aforementioned pixel is disposed on the upper surface of the aforementioned N-type InP ohmic contact layer;

[0110] The number of pixels mentioned above is 640, and the pixels are separated from each other;

[0111] The aforementioned pixels include the following structure: a P-type InP contact layer and 512 composite distributed Bragg reflectors;

[0112] The aforementioned composite distributed Bragg reflector includes a distributed Bragg reflector (DBR) and an i-type InGaAs absorbing layer;

[0113] The thickness of the i-type InGaAs absorber layer is 100 nm.

[0114] The thickness of the distributed Bragg mirror (DBR) is 50 nm.

[0115] The thickness of the P-type contact layer is 200 nm;

[0116] The InP substrate has a thickness of 350 μm.

[0117] The thickness of the N-type InP ohmic contact layer is 200 nm.

[0118] The fabrication method of the above-mentioned array infrared detector chip includes the following steps:

[0119] 1. Provide a 350μm thick InP substrate, and grow a 200nm N-type contact layer, (100nm i-type absorption layer, 50nm DBR)*512 pairs, and a 200nm P-type contact layer on it to form an array-type infrared detector epitaxy.

[0120] 2. Photolithography is performed on the upper surface of the epitaxial wafer, and the mesa is dry etched to prepare 640 mesa trenches, thereby forming 640*512 independent pixels;

[0121] 3. Deposit a 500nm thick SiNx passivation film to passivate and protect the sidewalls;

[0122] 4. The passivation film is etched using a photomask etching method with ammonium fluoride solution; a P-type electrode is formed using a photomask stripping method. The P-electrode is made of Ti / Pt / Au with thicknesses of 50nm / 50nm / 500nm, respectively.

[0123] 5. An N-type electrode is formed on the back side of the substrate. The N-electrode is made of Ti / Pt / Au with thicknesses of 50nm / 50nm / 500nm, respectively, to obtain an array infrared detector chip.

[0124] Example 4

[0125] The difference between Example 4 and Example 1 is that Example 1 has 320*256 independent pixels, while Example 4 has 1280*1024 independent pixels.

[0126] An array infrared detector chip includes the following structure:

[0127] N electrode;

[0128] An N-type InP substrate is disposed on the upper surface of the N electrode.

[0129] An N-type InP ohmic contact layer is disposed on the upper surface of the substrate.

[0130] Pixel, the aforementioned pixel is disposed on the upper surface of the aforementioned N-type InP ohmic contact layer;

[0131] The number of pixels mentioned above is 1280, and the pixels are separated from each other;

[0132] The aforementioned pixel comprises the following structure: a P-type InP contact layer and 1024 composite distributed Bragg reflectors;

[0133] The aforementioned composite distributed Bragg reflector includes a distributed Bragg reflector (DBR) and an i-type InGaAs absorbing layer;

[0134] The thickness of the i-type InGaAs absorber layer is 100 nm.

[0135] The thickness of the distributed Bragg mirror (DBR) is 50 nm.

[0136] The thickness of the P-type contact layer is 200 nm;

[0137] The InP substrate has a thickness of 350 μm.

[0138] The thickness of the N-type InP ohmic contact layer is 200 nm.

[0139] The fabrication method of the above-mentioned array infrared detector chip includes the following steps:

[0140] 1. Provide a 350μm thick InP substrate, and grow on it sequentially a 200nm N-type contact layer, (100nm i-type absorption layer, 50nm DBR)*1024 pairs, and a 200nm P-type contact layer to form an array-type infrared detector epitaxy.

[0141] 2. Photolithography is performed on the upper surface of the epitaxial wafer, and the mesa is dry etched to prepare 1280 mesa trenches, thereby forming 1280*1024 independent pixels;

[0142] 3. Deposit a 500nm thick SiNx passivation film to passivate and protect the sidewalls;

[0143] 4. The passivation film is etched using a photomask etching method with ammonium fluoride solution; a P-type electrode is formed using a photomask stripping method. The P-electrode is made of Ti / Pt / Au with thicknesses of 50nm / 50nm / 500nm, respectively.

[0144] 5. An N-type electrode is formed on the back side of the substrate. The N-electrode is made of Ti / Pt / Au with thicknesses of 50nm / 50nm / 500nm, respectively, to obtain an array infrared detector chip.

[0145] Example 5

[0146] The difference between Example 5 and Example 1 is that Example 1 has 320*256 independent pixels, while Example 5 has 4096*4096 independent pixels.

[0147] An array infrared detector chip includes the following structure:

[0148] N electrode;

[0149] An N-type InP substrate is disposed on the upper surface of the N electrode.

[0150] An N-type InP ohmic contact layer is disposed on the upper surface of the substrate.

[0151] Pixel, the aforementioned pixel is disposed on the upper surface of the aforementioned N-type InP ohmic contact layer;

[0152] The number of pixels mentioned above is 4096, and the pixels are separated from each other;

[0153] The aforementioned pixels include the following structure: a P-type InP contact layer and 4096 composite distributed Bragg reflectors;

[0154] The aforementioned composite distributed Bragg reflector includes a distributed Bragg reflector (DBR) and an i-type InGaAs absorbing layer;

[0155] The thickness of the i-type InGaAs absorber layer is 100 nm.

[0156] The thickness of the distributed Bragg mirror (DBR) is 50 nm.

[0157] The thickness of the P-type contact layer is 200 nm;

[0158] The InP substrate has a thickness of 350 μm.

[0159] The thickness of the N-type InP ohmic contact layer is 200 nm.

[0160] The fabrication method of the above-mentioned array infrared detector chip includes the following steps:

[0161] 1. Provide a 350μm thick InP substrate, and grow on it sequentially a 200nm N-type contact layer, (100nm i-type absorption layer, 50nm DBR)*4096 pairs, and a 200nm P-type contact layer to form an array-type infrared detector epitaxy.

[0162] 2. Photolithography is performed on the upper surface of the epitaxial wafer, and the mesa is dry etched to prepare 4096 mesa trenches, thereby forming 4096*4096 independent pixels;

[0163] 3. Deposit a 500nm thick SiNx passivation film to passivate and protect the sidewalls;

[0164] 4. The passivation film is etched using a photomask etching method with ammonium fluoride solution; a P-type electrode is formed using a photomask stripping method. The P-electrode is made of Ti / Pt / Au with thicknesses of 50nm / 50nm / 500nm, respectively.

[0165] 5. An N-type electrode is formed on the back side of the substrate. The N-electrode is made of Ti / Pt / Au with thicknesses of 50nm / 50nm / 500nm, respectively, to obtain an array infrared detector chip.

[0166] Example 6

[0167] The difference between Example 6 and Example 1 is that the thickness of the i-type InGaAs absorber layer is different. The thickness of the i-type InGaAs absorber layer in Example 1 is 100 nm, while the thickness of the i-type InGaAs absorber layer in Example 6 is 10 nm.

[0168] An array infrared detector chip includes the following structure:

[0169] N electrode;

[0170] An N-type InP substrate is disposed on the upper surface of the N electrode.

[0171] An N-type InP ohmic contact layer is disposed on the upper surface of the substrate.

[0172] Pixel, the aforementioned pixel is disposed on the upper surface of the aforementioned N-type InP ohmic contact layer;

[0173] The number of pixels mentioned above is 320, and the pixels are separated from each other;

[0174] The aforementioned pixels include the following structure: a P-type InP contact layer and 256 composite distributed Bragg mirrors;

[0175] The aforementioned composite distributed Bragg reflector includes a distributed Bragg reflector (DBR) and an i-type InGaAs absorbing layer;

[0176] The thickness of the i-type InGaAs absorber layer is 10 nm.

[0177] The thickness of the distributed Bragg mirror (DBR) is 50 nm.

[0178] The thickness of the P-type contact layer is 200 nm;

[0179] The InP substrate has a thickness of 350 μm.

[0180] The thickness of the N-type InP ohmic contact layer is 200 nm.

[0181] The fabrication method of the above-mentioned array infrared detector chip includes the following steps:

[0182] 1. Provide a 350μm thick InP substrate, and grow a 200nm N-type contact layer, (10nm i-type absorption layer, 50nm DBR)*256 pairs, and a 200nm P-type contact layer on it to form an array-type infrared detector epitaxy.

[0183] 2. Photolithography is performed on the upper surface of the epitaxial wafer, and the mesa is dry etched to prepare 320 mesa trenches, thereby forming 320*256 independent pixels;

[0184] 3. Deposit a 500nm thick SiNx passivation film to passivate and protect the sidewalls;

[0185] 4. The passivation film is etched using a photomask etching method with ammonium fluoride solution; a P-type electrode is formed using a photomask stripping method. The P-electrode is made of Ti / Pt / Au with thicknesses of 50nm / 50nm / 500nm, respectively.

[0186] 5. An N-type electrode is formed on the back side of the substrate. The N-electrode is made of Ti / Pt / Au with thicknesses of 50nm / 50nm / 500nm, respectively, to obtain an array infrared detector chip.

[0187] Example 7

[0188] The difference between Example 7 and Example 1 is that the thickness of the i-type InGaAs absorber layer is different. The thickness of the i-type InGaAs absorber layer in Example 1 is 100 nm, while the thickness of the i-type InGaAs absorber layer in Example 7 is 50 nm.

[0189] An array infrared detector chip includes the following structure:

[0190] N electrode;

[0191] An N-type InP substrate is disposed on the upper surface of the N electrode.

[0192] An N-type InP ohmic contact layer is disposed on the upper surface of the substrate.

[0193] Pixel, the aforementioned pixel is disposed on the upper surface of the aforementioned N-type InP ohmic contact layer;

[0194] The number of pixels mentioned above is 320, and the pixels are separated from each other;

[0195] The aforementioned pixels include the following structure: a P-type InP contact layer and 256 composite distributed Bragg mirrors;

[0196] The aforementioned composite distributed Bragg reflector includes a distributed Bragg reflector (DBR) and an i-type InGaAs absorbing layer;

[0197] The thickness of the i-type InGaAs absorber layer is 50 nm.

[0198] The thickness of the distributed Bragg mirror (DBR) is 50 nm.

[0199] The thickness of the P-type contact layer is 200 nm;

[0200] The InP substrate has a thickness of 350 μm.

[0201] The thickness of the N-type InP ohmic contact layer is 200 nm.

[0202] The fabrication method of the above-mentioned array infrared detector chip includes the following steps:

[0203] 1. Provide a 350μm thick InP substrate, and grow a 200nm N-type contact layer, (50nm i-type absorption layer, 50nm DBR)*256 pairs, and a 200nm P-type contact layer on it to form an array-type infrared detector epitaxy.

[0204] 2. Photolithography is performed on the upper surface of the epitaxial wafer, and the mesa is dry etched to prepare 320 mesa trenches, thereby forming 320*256 independent pixels;

[0205] 3. Deposit a 500nm thick SiNx passivation film to passivate and protect the sidewalls;

[0206] 4. The passivation film is etched using a photomask etching method with ammonium fluoride solution; a P-type electrode is formed using a photomask stripping method. The P-electrode is made of Ti / Pt / Au with thicknesses of 50nm / 50nm / 500nm, respectively.

[0207] 5. An N-type electrode is formed on the back side of the substrate. The N-electrode is made of Ti / Pt / Au with thicknesses of 50nm / 50nm / 500nm, respectively, to obtain an array infrared detector chip.

[0208] Example 8

[0209] The difference between Example 8 and Example 1 is that the thickness of the i-type InGaAs absorber layer is different. The thickness of the i-type InGaAs absorber layer in Example 1 is 100 nm, while the thickness of the i-type InGaAs absorber layer in Example 8 is 200 nm.

[0210] An array infrared detector chip includes the following structure:

[0211] N electrode;

[0212] An N-type InP substrate is disposed on the upper surface of the N electrode.

[0213] An N-type InP ohmic contact layer is disposed on the upper surface of the substrate.

[0214] Pixel, the aforementioned pixel is disposed on the upper surface of the aforementioned N-type InP ohmic contact layer;

[0215] The number of pixels mentioned above is 320, and the pixels are separated from each other;

[0216] The aforementioned pixels include the following structure: a P-type InP contact layer and 256 composite distributed Bragg mirrors;

[0217] The aforementioned composite distributed Bragg reflector includes a distributed Bragg reflector (DBR) and an i-type InGaAs absorbing layer;

[0218] The thickness of the i-type InGaAs absorber layer is 200 nm.

[0219] The thickness of the distributed Bragg mirror (DBR) is 50 nm.

[0220] The thickness of the P-type contact layer is 200 nm;

[0221] The InP substrate has a thickness of 350 μm.

[0222] The thickness of the N-type InP ohmic contact layer is 200 nm.

[0223] The fabrication method of the above-mentioned array infrared detector chip includes the following steps:

[0224] 1. Provide a 350μm thick InP substrate, and grow on it sequentially a 200nm N-type contact layer, (200nm i-type absorption layer, 50nm DBR)*256 pairs, and a 200nm P-type contact layer to form an array-type infrared detector epitaxy.

[0225] 2. Photolithography is performed on the upper surface of the epitaxial wafer, and the mesa is dry etched to prepare 320 mesa trenches, thereby forming 320*256 independent pixels;

[0226] 3. Deposit a 500nm thick SiNx passivation film to passivate and protect the sidewalls;

[0227] 4. The passivation film is etched using a photomask etching method with ammonium fluoride solution; a P-type electrode is formed using a photomask stripping method. The P-electrode is made of Ti / Pt / Au with thicknesses of 50nm / 50nm / 500nm, respectively.

[0228] 5. An N-type electrode is formed on the back side of the substrate. The N-electrode is made of Ti / Pt / Au with thicknesses of 50nm / 50nm / 500nm, respectively, to obtain an array infrared detector chip.

[0229] Example 9

[0230] The difference between Example 9 and Example 1 is that the thickness of the i-type InGaAs absorber layer is different. The thickness of the i-type InGaAs absorber layer in Example 1 is 100 nm, while the thickness of the i-type InGaAs absorber layer in Example 9 is 500 nm.

[0231] An array infrared detector chip includes the following structure:

[0232] N electrode;

[0233] An N-type InP substrate is disposed on the upper surface of the N electrode.

[0234] An N-type InP ohmic contact layer is disposed on the upper surface of the substrate.

[0235] Pixel, the aforementioned pixel is disposed on the upper surface of the aforementioned N-type InP ohmic contact layer;

[0236] The number of pixels mentioned above is 320, and the pixels are separated from each other;

[0237] The aforementioned pixels include the following structure: a P-type InP contact layer and 256 composite distributed Bragg mirrors;

[0238] The aforementioned composite distributed Bragg reflector includes a distributed Bragg reflector (DBR) and an i-type InGaAs absorbing layer;

[0239] The thickness of the i-type InGaAs absorber layer is 500 nm.

[0240] The thickness of the distributed Bragg mirror (DBR) is 50 nm.

[0241] The thickness of the P-type contact layer is 200 nm;

[0242] The InP substrate has a thickness of 350 μm.

[0243] The thickness of the N-type InP ohmic contact layer is 200 nm.

[0244] The fabrication method of the above-mentioned array infrared detector chip includes the following steps:

[0245] 1. Provide a 350μm thick InP substrate, and grow a 200nm N-type contact layer, (500nm i-type absorption layer, 50nm DBR)*256 pairs, and a 200nm P-type contact layer on it in sequence to form an array-type infrared detector epitaxy.

[0246] 2. Photolithography is performed on the upper surface of the epitaxial wafer, and the mesa is dry etched to prepare 320 mesa trenches, thereby forming 320*256 independent pixels;

[0247] 3. Deposit a 500nm thick SiNx passivation film to passivate and protect the sidewalls;

[0248] 4. The passivation film is etched using a photomask etching method with ammonium fluoride solution; a P-type electrode is formed using a photomask stripping method. The P-electrode is made of Ti / Pt / Au with thicknesses of 50nm / 50nm / 500nm, respectively.

[0249] 5. An N-type electrode is formed on the back side of the substrate. The N-electrode is made of Ti / Pt / Au with thicknesses of 50nm / 50nm / 500nm, respectively, to obtain an array infrared detector chip.

[0250] Comparative Example

[0251] An infrared detector chip, such as Figure 6 As shown, it includes the following structure:

[0252] N electrode;

[0253] N-type InP substrate;

[0254] N-type InP ohmic contact layer;

[0255] i-type InGaAs absorber layer;

[0256] P-type InP contact layer;

[0257] P electrode;

[0258] The thickness of the i-type InGaAs absorber layer is 2000 nm.

[0259] The thickness of the DBR is 50nm;

[0260] The thickness of the P-type contact layer is 200 nm;

[0261] The InP substrate has a thickness of 100 μm;

[0262] The thickness of the N-type InP ohmic contact layer is 200 nm.

[0263] The fabrication method of the above-mentioned array infrared detector chip includes the following steps:

[0264] 1. Provide a 350μm thick InP substrate, and sequentially grow a 200nm N-type InP ohmic contact layer, a 2000nm i-type absorption layer, and a 200nm P-type contact layer on it to form an infrared detector epitaxy.

[0265] 2. Photolithography is performed on the upper surface of the epitaxial wafer, and the mesa is dry etched to prepare 320*256 mesa, thereby forming 320*256 independent pixels;

[0266] 3. Deposit a 500nm thick SiNx passivation film to passivate and protect the sidewalls;

[0267] 4. The passivation film is etched with a photomask to create P-type electrode openings using an ammonium fluoride solution; the P-type electrode is formed by photomask stripping, and the P-type electrode is made of Ti / Pt / Au with thicknesses of 50nm / 50nm / 500nm respectively.

[0268] 5. The passivation film is etched with an N-type electrode through a photomask etching method, using an ammonium fluoride solution; the N-type electrode is formed by photomask stripping, and the N-type electrode is made of Ti / Pt / Au with thicknesses of 50nm / 50nm / 500nm respectively.

[0269] 6. The InP substrate is thinned to 100 μm to obtain a comparative infrared detector chip.

[0270] The comparative detector uses a side-light incident method. During use, increasing the I-type layer thickness to improve responsivity slows down the detector's response time, thus failing to meet high-frequency application requirements. Furthermore, to improve response, the InP substrate typically needs to be thinned or completely removed, leading to a high probability of breakage. In this case, Embodiment 1 uses a side-light incident method. Its responsivity improvement is not directly related to the I-type layer thickness. Therefore, high-frequency performance can be improved by reducing the I-type layer thickness. Simultaneously, it features a typical top-P, bottom-N structure, simplifying the packaging and eliminating the need for flip-chip bonding required by conventional area array detectors.

[0271] The above are merely embodiments of the present invention and do not limit the patent scope of the present invention. Any equivalent modifications made based on the content of the present invention specification, or direct or indirect applications in related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. An array infrared detector chip, characterized in that: Includes the following structure: Substrate; An N-type contact layer is disposed on the upper surface of the substrate; Pixel, the pixel being disposed on the upper surface of the N-type contact layer; The number of pixels is m, and the pixels are separated from each other; The pixel includes the following structure: a P-type contact layer and n composite distributed Bragg reflectors; The composite distributed Bragg reflector includes a distributed Bragg reflector and an i-type absorption layer; The thickness of the i-type absorption layer is 10-500 nm; Where m and n are independently selected from positive integers; During use, the light incident direction of the array infrared detector chip is perpendicular to the epitaxial growth direction of the array infrared detector chip.

2. The array infrared detector chip according to claim 1, characterized in that: The surface of the pixel is deposited with a passivation film.

3. The array infrared detector chip according to claim 1, characterized in that: The thickness of the N-type contact layer is 100-500 nm.

4. The array infrared detector chip according to claim 1, characterized in that: The thickness of the P-type contact layer is 100-500 nm.

5. An array infrared detector chip according to claim 1, characterized in that: The thickness of the distributed Bragg reflector is 20-100 nm.

6. The array infrared detector chip according to claim 1, characterized in that: In the array infrared detector chip, a P-type electrode is provided on the side of the P-type contact layer that is away from the N-type contact layer.

7. An array infrared detector chip according to claim 6, characterized in that: The P-type electrode includes a Ti / Pt / Au electrode, wherein the thicknesses of the Ti layer, Pt layer, and Au layer are 10-100 nm, 10-100 nm, and 100-2000 nm, respectively.

8. A method for preparing an array infrared detector chip as described in any one of claims 1 to 7, characterized in that: Includes the following steps: An N-type contact layer and an initial pixel are epitaxially grown sequentially on a substrate. The initial pixel is then photolithographically etched and etched to obtain an array infrared detector chip.

9. The application of an array infrared detector chip as described in any one of claims 1 to 7 in a photodetector.

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