Light emitting diode epitaxial wafer and preparation method thereof, and light emitting diode
By introducing a stress compensation layer into GaN-based light-emitting diodes, the problems of carrier overflow and In segregation caused by lattice mismatch are solved, improving the product yield and internal quantum efficiency of light-emitting diodes and achieving higher luminous brightness.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- JIANGXI ZHAO CHI SEMICON CO LTD
- Filing Date
- 2022-11-21
- Publication Date
- 2026-05-12
Smart Images
Figure CN115911201B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of optoelectronic technology, and in particular to a light-emitting diode epitaxial wafer and its fabrication method, and a light-emitting diode. Background Technology
[0002] GaN-based light-emitting diodes (LEDs) with multiple quantum well structures as the main light-emitting layer have achieved high radiative recombination efficiency, making them a core technology in the semiconductor field in recent years. Their growth primarily involves alternating growth of two materials with different bandgap widths, InGaN and GaN. InGaN has a smaller bandgap than GaN, making it easier for electrons to be confined within the smaller bandgap quantum well layer during electron transport from N-type to P-type semiconductors, leading to radiative recombination with holes. Therefore, the InGaN / GaN multiple quantum well structure effectively confines charge carriers and improves radiative recombination efficiency. However, due to the poor lattice constant matching between InGaN and GaN, a large strain-polarized electric field is generated, resulting in severe band tilt and an inability to effectively confine charge carriers. This leads to more charge carrier overflow and exacerbates luminous efficiency degradation. To reduce the piezoelectric polarization effect caused by lattice mismatch and effectively release the stress in the quantum well region, a low-In composition InGaN / GaN quantum well preparation layer or an InGaN / GaN superlattice preparation layer is typically grown before the quantum well layer.
[0003] Simple InGaN / GaN quantum well preparation layers or InGaN / GaN superlattice preparation layers are prone to severe In segregation due to factors such as the extension of underlying defects or growth temperature mismatch. This results in poor crystal quality, increased stacking faults, and a greater likelihood of smaller V-shaped defects forming between the stress-relief layer or the subsequently grown active layer. These small V-shaped defects are more likely to become leakage channels, affecting the final product yield. At the same time, the uneven stress-relief layer degrades the crystal quality of the subsequently grown quantum well layer, and defects penetrate into the active layer, increasing the probability of nonradiative recombination in the active layer and ultimately leading to a decrease in internal quantum efficiency. Summary of the Invention
[0004] The technical problem to be solved by the present invention is to provide an epitaxial wafer for light-emitting diodes with high yield and effective improvement of chip brightness.
[0005] The technical problem to be solved by the present invention is to provide a method for preparing a light-emitting diode epitaxial wafer, which has a simple process and can stably produce the above-mentioned light-emitting diode epitaxial wafer with good performance.
[0006] To solve the above-mentioned technical problems, the present invention provides a light-emitting diode epitaxial wafer, comprising a substrate and a buffer layer, an N-type GaN layer, a stress compensation layer, a stress relief layer, a multiple quantum well layer, and a P-type GaN layer sequentially stacked on the substrate;
[0007] The stress compensation layer comprises an AlGaN layer, a first GaN layer, an InGaN / GaN superlattice layer, and a second GaN layer, which are sequentially stacked on the N-type GaN layer.
[0008] In one embodiment, the Al component concentration in the AlGaN layer is 0.01-0.1.
[0009] The first GaN layer is a heavily Si-doped GaN layer, and the Si doping concentration of the first GaN layer is 9*10⁻⁶. 18 atoms / cm 3 -9.5*10 18 atoms / cm 3 ;
[0010] The second GaN layer is a lightly Si-doped GaN layer with a Si doping concentration of 1*10⁻⁶. 17 atoms / cm 3 -1*10 18 atoms / cm 3 Furthermore, the stress relief layer gradually increases from low to high from the InGaN / GaN superlattice layer to the stress relief layer.
[0011] In one embodiment, the InGaN / GaN superlattice layer includes overlapping InGaN layers and GaN layers, with an overlap period of 20-30.
[0012] The InGaN / GaN superlattice layer is a low-Si-doped InGaN / GaN superlattice layer with a Si doping concentration of 5*10⁻⁶. 17 atoms / cm 3 -1*10 18 atoms / cm 3 ;
[0013] The In component concentration in the InGaN layer is 0.01-0.1.
[0014] The thickness ratio of the InGaN layer to the GaN layer is <1.5.
[0015] In one embodiment, the thickness of the stress compensation layer is 300nm-500nm;
[0016] The thickness of the AlGaN layer is 20nm-30nm;
[0017] The thickness of the InGaN / GaN superlattice layer is 100nm-150nm;
[0018] The thickness of the first GaN layer is 2.5 to 4 times the thickness of the second GaN layer.
[0019] To address the above problems, this invention provides a method for fabricating a light-emitting diode epitaxial wafer, comprising the following steps:
[0020] Prepare the substrate;
[0021] A buffer layer, an N-type GaN layer, a stress compensation layer, a stress relief layer, a multiple quantum well layer, and a P-type GaN layer are sequentially deposited on the substrate.
[0022] The stress compensation layer comprises an AlGaN layer, a first GaN layer, an InGaN / GaN superlattice layer, and a second GaN layer, which are sequentially stacked on the N-type GaN layer.
[0023] In one embodiment, depositing the AlGaN layer on the N-type GaN layer includes the following steps:
[0024] The temperature of the reaction chamber was controlled at 950℃-1200℃, and N source, Ga source and Al source were introduced to complete the deposition.
[0025] In one embodiment, depositing the first GaN layer on the AlGaN layer includes the following steps:
[0026] First, the temperature of the reaction chamber is controlled at 800℃-980℃, N2 and H2 are introduced as carrier gases, and N source, Ga source and Si source are introduced to complete the deposition;
[0027] The atmosphere ratio of N2 to H2 is (3-4):1.
[0028] In one embodiment, depositing the InGaN / GaN superlattice layer on the first GaN layer includes the following steps:
[0029] The reaction chamber temperature is controlled at 900℃-1050℃. N2 and H2 are introduced as carrier gases. First, Ga source, In source, N source and Si source are introduced to complete the InGaN layer deposition. Then, Ga source, N source and Si source are introduced to complete the GaN layer deposition. The overlapping deposition is carried out for 20-30 cycles.
[0030] The atmosphere ratio of N2 to H2 is (2-3):1.
[0031] In one embodiment, depositing the second GaN layer on the InGaN / GaN superlattice layer includes the following steps:
[0032] The temperature of the reaction chamber is controlled at 900℃-1050℃. N2 and H2 are introduced as carrier gases, and Ga source, N source and Si source are introduced to complete the deposition.
[0033] The atmosphere ratio of N2 to H2 is 1:(1-2).
[0034] Accordingly, the present invention also provides a light-emitting diode, wherein the light-emitting diode includes the light-emitting diode epitaxial wafer described above.
[0035] Implementing this invention has the following beneficial effects:
[0036] This invention grows a stress compensation layer before the multi-quantum-well layer. The stress compensation layer comprises an AlGaN layer, a first GaN layer, an InGaN / GaN superlattice layer, and a second GaN layer sequentially stacked on the N-type GaN layer. The insertion of the stress compensation layer can reduce the crystal quality degradation caused by In segregation in the stress-relieving layer, while also reducing small defects formed in the stress-relieving layer or the active layer, thus improving product yield; it also improves the crystal quality of the stress-relieving layer, thereby improving the crystal quality of the active layer and increasing the internal quantum efficiency. Attached Figure Description
[0037] Figure 1 This is a schematic diagram of the structure of the light-emitting diode epitaxial wafer provided by the present invention.
[0038] Wherein: 1 is the substrate, 2 is the buffer layer, 3 is the N-type GaN layer, 4 is the stress compensation layer, 5 is the stress relief layer, 6 is the multiple quantum well layer, 7 is the P-type GaN layer, 41 is the AlGaN layer, 42 is the first GaN layer, 43 is the InGaN / GaN superlattice layer, and 44 is the second GaN layer. Detailed Implementation
[0039] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be described in further detail below.
[0040] Unless otherwise stated or in case of contradiction, the terms or phrases used herein shall have the following meanings:
[0041] In this invention, the terms "combinations thereof", "any combination thereof", and "any combination thereof" include all suitable combinations of any two or more items listed.
[0042] In this invention, "preferred" is merely a description of a more effective implementation method or embodiment, and should be understood as not constituting a limitation on the scope of protection of this invention.
[0043] In this invention, the technical features described in an open-ended manner include both closed-ended technical solutions composed of the listed features and open-ended technical solutions that include the listed features.
[0044] In this invention, numerical ranges are involved, and unless otherwise specified, they include the two endpoints of the numerical range.
[0045] To address the above problems, the present invention provides a light-emitting diode epitaxial wafer, such as... Figure 1As shown, it includes a substrate 1 and a buffer layer 2, an N-type GaN layer 3, a stress compensation layer 4, a stress relief layer 5, a multiple quantum well layer 6, and a P-type GaN layer 7, which are sequentially stacked on the substrate 1.
[0046] The stress compensation layer 4 includes an AlGaN layer 41, a first GaN layer 42, an InGaN / GaN superlattice layer 43, and a second GaN layer 44, which are sequentially stacked on the N-type GaN layer 3.
[0047] The insertion of the stress compensation layer described in this invention can reduce the crystal quality deterioration caused by In segregation in the stress relief layer, while reducing small defects in the stress relief layer or active layer, thereby improving product yield; improving the crystal quality of the stress relief layer, and thus improving the crystal quality of the active layer, thereby increasing the internal quantum efficiency.
[0048] Specifically, in one embodiment, the Al composition concentration in the AlGaN layer is 0.01-0.1. Due to the high lattice mismatch between the substrate and the N-type GaN layer, the lattice constant of AlGaN is between that of the substrate and GaN, effectively blocking the mismatch stress from the bottom layer and compensating for subsequent stress release. On the other hand, because the InGaN / GaN superlattice layer has a high crystal quality, its electron confinement effect is weakened, increasing the risk of subsequent active layer electron overflow. The AlGaN layer, however, has a relatively higher potential barrier, thus confining electrons.
[0049] In one embodiment, the first GaN layer is a heavily Si-doped GaN layer, and the Si doping concentration of the first GaN layer is 9*10⁻⁶. 18 atoms / cm 3 -9.5*10 18 atoms / cm 3 ;
[0050] The InGaN / GaN superlattice layer is a low-Si-doped InGaN / GaN superlattice layer with a Si doping concentration of 5*10⁻⁶. 17 atoms / cm 3 -1*10 18 atoms / cm 3 ;
[0051] The second GaN layer is a lightly Si-doped GaN layer with a Si doping concentration of 1*10⁻⁶. 17 atoms / cm 3 -1*10 18 atoms / cm 3 Furthermore, the stress relief layer gradually increases from low to high from the InGaN / GaN superlattice layer to the stress relief layer.
[0052] It should be noted that the Si doping concentration of the stress compensation layer gradually decreases from the first GaN layer to the InGaN / GaN superlattice layer, which is more conducive to the lateral spread of current and acts as a decelerator for charge carriers. The doping concentration of the second GaN layer gradually increases from low to high, and the doping concentration range is controlled within 1*10⁻⁶. 17 atoms / cm 3 -1*10 18 atoms / cm 3 The second GaN layer, acting as a space charge layer, has a depletion region size influenced by the Si doping concentration. This depletion region size, in turn, limits the reverse voltage and electrostatic discharge (ESD) immunity. Specifically, a higher Si doping concentration results in a smaller depletion region and consequently a lower reverse cutoff voltage; conversely, a lower Si doping concentration leads to a larger depletion region, smaller capacitance, and consequently, poorer ESD immunity. Therefore, the Si doping concentration within the diode's space charge region must be neither too high nor too low. A gradual increase in doping concentration ensures sufficient reverse voltage while improving the diode's ESD immunity.
[0053] In one embodiment, the InGaN / GaN superlattice layer comprises overlapping InGaN and GaN layers with an overlap period of 20-30; the In concentration in the InGaN layer is 0.01-0.1; and the thickness ratio of the InGaN layer to the GaN layer is <1.5. The thickness of the stress compensation layer is 300nm-500nm; the thickness of the AlGaN layer is 20nm-30nm; the thickness of the InGaN / GaN superlattice layer is 100nm-150nm; and the thickness of the first GaN layer is 2.5-4 times the thickness of the second GaN layer.
[0054] It should be noted that the first GaN layer, as a key layer controlling the starting position of the V-shaped opening, needs sufficient thickness to support the opening distribution, creating larger V-shaped pits that penetrate the entire quantum well, thus increasing the hole injection efficiency from the V-shaped sidewalls. Furthermore, the thickness ratio of the InGaN layer to the GaN layer in the InGaN / GaN superlattice layer is less than 1.5, allowing the InGaN layer to both compensate for stress and control the incorporation efficiency of In, reducing In clustering, decreasing the number of small V-shaped defects, improving the interface quality of the stress relief layer, and consequently improving the quantum well crystal quality and increasing the effective recombination efficiency.
[0055] In addition to the stress compensation layer mentioned above, the other features of the layered structure of the present invention are as follows:
[0056] In one embodiment, the substrate is selected from sapphire substrate, SiO2 sapphire composite substrate, silicon substrate, silicon carbide substrate, gallium nitride substrate, and zinc oxide substrate.
[0057] Preferably, a sapphire substrate is used. Sapphire is currently the most commonly used GaN-based LED substrate material, and most GaN-based LEDs on the market use sapphire as the substrate material. The biggest advantages of sapphire substrates are mature technology, good stability, and low production cost.
[0058] In one embodiment, the buffer layer is an AlGaN buffer layer or an AlN buffer layer. Preferably, the buffer layer is an AlN buffer layer. Using an AlN buffer layer to control crystal defects can improve the quality of subsequent crystal growth and alleviate stress caused by lattice mismatch and thermal mismatch between the substrate and the epitaxial layer. In one embodiment, the thickness of the buffer layer is 10 nm-20 nm.
[0059] In one embodiment, the thickness of the N-type GaN layer is 2μm-3μm, and the N-type GaN layer is Si-doped with a Si doping concentration of 1*10⁻⁶. 19 atoms / cm 3 -1*10 20 atoms / cm 3 .
[0060] In one embodiment, the stress relief layer is a low-doped InGaN / GaN periodically alternating multiple quantum well layer with a Si doping concentration of 1*10⁻⁶. 15 atoms / cm 3 -1*10 17 atoms / cm 3 The number of cycles is between 5 and 8.
[0061] In one embodiment, the multiple quantum well layer is a periodic structure consisting of alternating InGaN quantum well layers and AlGaN quantum barrier layers, with a period number of 5-10; the thickness of the InGaN quantum well layer is 2nm-5nm; and the thickness of the AlGaN quantum barrier is 8nm-10nm. The active region of the multiple quantum wells is the region where electrons and holes recombine. A well-designed structure can significantly increase the overlap of electron and hole wave functions, thereby improving the luminous efficiency of the LED device.
[0062] In one embodiment, the thickness of the P-type GaN layer is 50 nm-80 nm; the N-type GaN layer is Mg-doped, and the Mg doping concentration is 1*10⁻⁶. 19 atoms / cm 3 -1*10 20 atoms / cm 3 .
[0063] Accordingly, the present invention also provides a method for preparing the above-mentioned light-emitting diode epitaxial wafer, comprising the following steps:
[0064] S1. Prepare the substrate;
[0065] In one embodiment, the substrate is selected as a sapphire substrate.
[0066] S2. A buffer layer, an N-type GaN layer, a stress compensation layer, a stress relief layer, a multiple quantum well layer, and a P-type GaN layer are sequentially deposited on the substrate.
[0067] The stress compensation layer comprises an AlGaN layer, a first GaN layer, an InGaN / GaN superlattice layer, and a second GaN layer, which are sequentially stacked on the N-type GaN layer.
[0068] In one implementation, step S2 includes the following steps:
[0069] S21. Deposit the buffer layer on the front side of the substrate:
[0070] In one embodiment, depositing the buffer layer on the front side of the substrate includes the following steps:
[0071] An AlN buffer layer with a thickness of 10 nm-20 nm was deposited in the PVD process of the applied materials.
[0072] S22. Deposit the N-type GaN layer on the buffer layer:
[0073] The reaction chamber temperature was controlled at 1000℃-1200℃, and N source, Ga source and Si source were introduced to complete the deposition.
[0074] S23. Deposit the AlGaN layer on the N-type GaN layer:
[0075] The temperature of the reaction chamber was controlled at 950℃-1200℃, and N source, Ga source and Al source were introduced to complete the deposition.
[0076] S24. Deposit the first GaN layer on the AlGaN layer:
[0077] First, the temperature of the reaction chamber is controlled at 850℃-950℃. N2 and H2 are introduced as carrier gases, and N source, Ga source and Si source are introduced to complete the deposition.
[0078] The atmosphere ratio of N2 to H2 is (3-4):1.
[0079] S25. Deposit the InGaN / GaN superlattice layer on the first GaN layer:
[0080] The reaction chamber temperature is controlled at 900℃-1050℃. N2 and H2 are introduced as carrier gases. First, Ga source, In source, N source and Si source are introduced to complete the InGaN layer deposition. Then, Ga source, N source and Si source are introduced to complete the GaN layer deposition. The overlapping deposition is carried out for 20-30 cycles.
[0081] The atmosphere ratio of N2 to H2 is (2-3):1.
[0082] S26. Deposit the second GaN layer on the InGaN / GaN superlattice layer:
[0083] The temperature of the reaction chamber is controlled at 900℃-1050℃. N2 and H2 are introduced as carrier gases, and Ga source, N source and Si source are introduced to complete the deposition.
[0084] The atmosphere ratio of N2 to H2 is 1:(1-2).
[0085] S27. Deposit the stress relief layer on the second GaN layer:
[0086] The reaction chamber temperature is controlled at 800℃-900℃. Ga, N, In, and Si sources are introduced to complete the InGaN layer deposition. Then, the In source is turned off, and Ga, N, and Si sources are introduced to complete the GaN layer deposition. This process is repeated for 5-8 cycles.
[0087] S28. Deposit the multi-quantum-well layer on the stress-relieving layer:
[0088] The reaction chamber temperature is controlled at 750℃-850℃. Ga, N, In and Si sources are introduced to complete the InGaN layer deposition. Then the In source is turned off, and Ga, N and Si sources are introduced to complete the GaN layer deposition. This process is repeated for 5-10 cycles.
[0089] S29. Deposit the P-type GaN layer on the multi-quantum-well layer:
[0090] The reaction chamber temperature was controlled at 800℃-980℃, and Ga, N and Mg sources were introduced to complete the deposition.
[0091] It should be noted that in the preparation method provided by this invention, the temperature of the AlGaN layer is controlled between 950℃ and 1200℃. The Al atom mobility is relatively low, and the high temperature promotes the incorporation efficiency of Al atoms. The temperature of the first GaN layer is controlled between 850℃ and 950℃. The relatively low temperature slows down the growth rate, which facilitates the opening of V-shaped notches by penetrating dislocations in this layer and inhibits the upward extension of defects in the underlying layer. The temperature of the InGaN / GaN superlattice layer is higher than that of the first GaN layer. This high-temperature growth mode reduces the In content in the InGaN layer, thereby reducing the probability of In cluster formation and ensuring a smoother superlattice crystal quality. The temperature of the second GaN layer is slightly lower than that of the InGaN / GaN superlattice layer. This relatively low temperature acts as an annealing and recrystallization process for the InGaN / GaN superlattice layer, improving the crystal quality of the InGaN / GaN superlattice.
[0092] Furthermore, the N2 / H2 atmosphere ratio gradually decreases from the first GaN layer to the InGaN / GaN superlattice layer to the second GaN layer. The first GaN layer has a relatively high N2 content; the N2 atmosphere reduces the transport effect on surface molecular adsorption, which is more conducive to the formation of V-shaped defects. The increased H2 content in the InGaN / GaN superlattice layer is more conducive to removing In-rich clusters on the InGaN layer surface, reducing the formation of small V-shaped defects, reducing leakage channels, and improving diode yield. The second GaN layer has an even higher H2 content; the increased H2 atmosphere ratio serves as a surface cleaning treatment, resulting in a smoother superlattice stress compensation layer.
[0093] Accordingly, the present invention also provides a light-emitting diode, wherein the light-emitting diode includes the light-emitting diode epitaxial wafer described above.
[0094] The deposition process is completed using MOCVD equipment, CVD equipment or PVD equipment. This invention does not limit the deposition method.
[0095] The present invention is further illustrated below with specific embodiments:
[0096] Example 1
[0097] This embodiment provides a light-emitting diode epitaxial wafer, including a substrate and a buffer layer, an N-type GaN layer, a stress compensation layer, a stress relief layer, a multiple quantum well layer, and a P-type GaN layer sequentially stacked on the substrate.
[0098] The stress compensation layer comprises an AlGaN layer, a first GaN layer, an InGaN / GaN superlattice layer, and a second GaN layer, which are sequentially stacked on the N-type GaN layer.
[0099] The above-mentioned method for fabricating an epitaxial wafer of a light-emitting diode includes the following steps:
[0100] S1. Prepare the substrate;
[0101] S2. A buffer layer, an N-type GaN layer, a stress compensation layer, a stress relief layer, a multiple quantum well layer, and a P-type GaN layer are sequentially deposited on the substrate.
[0102] The stress compensation layer comprises an AlGaN layer, a first GaN layer, an InGaN / GaN superlattice layer, and a second GaN layer, which are sequentially stacked on the N-type GaN layer.
[0103] In one implementation, step S2 includes the following steps:
[0104] S21. Deposit the buffer layer on the front side of the substrate:
[0105] An AlN buffer layer with a thickness of 15 nm was deposited in the applied material PVD.
[0106] S22. Deposit the N-type GaN layer on the buffer layer:
[0107] The reaction chamber temperature was controlled at 1100℃, and N, Ga, and Si sources were introduced to complete the deposition, which achieved a thickness of 2.5 μm and a Si doping concentration of 1.5 × 10⁻⁶. 19 atoms / cm 3 .
[0108] S23. Deposit the AlGaN layer on the N-type GaN layer:
[0109] The reaction chamber temperature was controlled at 940℃, and N source, Ga source and Al source were introduced to complete the deposition, which was 20 nm thick and the Al component concentration was 0.05.
[0110] S24. Deposit the first GaN layer on the AlGaN layer:
[0111] First, the temperature of the reaction chamber is controlled at 940℃, and N2 and H2 are introduced as carrier gases. N source, Ga source and Si source are introduced to complete the deposition.
[0112] The N2:H2 atmosphere ratio is 3:1. The first GaN layer is 180 nm thick, and the Si doping concentration is 9.2 × 10⁻⁶. 18 atoms / cm 3 .
[0113] S25. Deposit the InGaN / GaN superlattice layer on the first GaN layer:
[0114] The reaction chamber temperature was controlled at 990℃, and N2 and H2 were introduced as carrier gases. First, Ga source, In source, N source and Si source were introduced to complete the InGaN layer deposition, and then Ga source, N source and Si source were introduced to complete the GaN layer deposition. 22 overlapping deposition cycles were performed.
[0115] The atmosphere ratio of N2 to H2 is 2:1.
[0116] The thickness ratio of the InGaN layer to the GaN layer is 1.2:1, the thickness of the InGaN / GaN superlattice layer is 120 nm, the In composition concentration is 0.05%, and the Si doping concentration is 5*10⁻⁶. 17 atoms / cm 3 .
[0117] S26. Deposit the second GaN layer on the InGaN / GaN superlattice layer:
[0118] The reaction chamber temperature was controlled at 940℃, and N2 and H2 were introduced as carrier gases. Ga source, N source and Si source were introduced to complete the deposition.
[0119] The atmosphere ratio of N2 to H2 is 1:1.5.
[0120] The second GaN layer is 60 nm thick, and the Si doping concentration is 5*10⁻⁶. 17 atoms / cm 3 Gradient to 9*10 17 atoms / cm 3 .
[0121] S27. Deposit the stress relief layer on the second GaN layer:
[0122] The reaction chamber temperature was controlled at 850℃. Ga, N, In, and Si sources were introduced to complete InGaN layer deposition. Then, the In source was turned off, and Ga, N, and Si sources were introduced to complete GaN layer deposition. This process was repeated for six cycles, with a Si doping concentration of 1*10⁻⁶. 16 atoms / cm 3 .
[0123] S28. Deposit the multi-quantum-well layer on the stress-relieving layer:
[0124] The reaction chamber temperature was controlled at 800℃. Ga, N, In, and Si sources were introduced to complete the InGaN layer deposition. Then, the In source was turned off, and Ga, N, and Si sources were introduced to complete the GaN layer deposition. This process was repeated for eight cycles. The InGaN quantum well layer had a thickness of 3 nm; the AlGaN quantum barrier had a thickness of 9 nm.
[0125] S29. Deposit the P-type GaN layer on the multi-quantum-well layer:
[0126] The reaction chamber temperature was controlled at 900℃, and Ga, N, and Mg sources were introduced to complete the deposition. The thickness of the P-type GaN layer was 70 nm; the N-type GaN layer was Mg-doped, and the Mg doping concentration was 5*10⁻⁶. 19 atoms / cm 3 .
[0127] Example 2
[0128] This embodiment provides a light-emitting diode epitaxial wafer, which differs from Embodiment 1 in that the Al component concentration in the AlGaN layer is 0.1, while the rest is the same as in Embodiment 1.
[0129] Example 3
[0130] This embodiment provides a light-emitting diode epitaxial wafer, which differs from Embodiment 1 in that the Si doping concentration of the first GaN layer is 9.5*10⁻⁶. 18 atoms / cm 3 The Si doping concentration of the second GaN layer from the InGaN / GaN superlattice layer to the stress relief layer is 1*10. 17 atoms / cm 3 Up to 9*10 17 atoms / cm 3 Gradient transition. Everything else is the same as in Example 1.
[0131] Example 4
[0132] This embodiment provides a light-emitting diode epitaxial wafer, which differs from Embodiment 1 in that: the InGaN / GaN superlattice layer includes overlapping InGaN and GaN layers, with an overlap period of 25, and a Si doping concentration of 7*10⁻⁶. 17 atoms / cm 3 Everything else is the same as in Example 1.
[0133] Comparative Example 1
[0134] This comparative example provides a light-emitting diode epitaxial wafer, which differs from Example 1 in that it does not have a stress compensation layer, but is otherwise the same as Example 1.
[0135] The performance of chips fabricated from the epitaxial wafers of light-emitting diodes prepared in Examples 1-4 and Comparative Example 1 was tested. The test method was to prepare 10mil×24mil chips from the above-mentioned epitaxial wafers using the same chip process conditions and conduct luminous brightness tests. Based on the chips prepared in the comparative example, the brightness improvement rate of each example was calculated. The specific test results are shown in Table 1.
[0136] Table 1 shows the performance test results of the LED epitaxial wafers prepared in Examples 1-4.
[0137]
[0138] The results above show that the epitaxial wafers proposed in this invention produce chips with a VR value above 35V, an IR yield of no less than 98%, and a brightness improvement of more than 0.5%. This invention grows a stress compensation layer before the multi-quantum-well layer. The stress compensation layer comprises an AlGaN layer, a first GaN layer, an InGaN / GaN superlattice layer, and a second GaN layer sequentially stacked on the N-type GaN layer. The insertion of the stress compensation layer reduces the crystal quality degradation caused by In segregation in the stress-relieving layer, while also reducing small defects in the stress-relieving layer or the active layer, thus improving product yield; it also improves the crystal quality of the stress-relieving layer, thereby improving the crystal quality of the active layer and increasing internal quantum efficiency.
[0139] The above description is a preferred embodiment of the invention. It should be noted that, for those skilled in the art, several improvements and modifications can be made without departing from the principle of the invention, and these improvements and modifications are also considered to be within the scope of protection of the invention.
Claims
1. A light-emitting diode epitaxial wafer, characterized in that, It includes a substrate and a buffer layer, an N-type GaN layer, a stress compensation layer, a stress relief layer, a multiple quantum well layer, and a P-type GaN layer sequentially stacked on the substrate; The stress compensation layer consists of an AlGaN layer, a first GaN layer, an InGaN / GaN superlattice layer, and a second GaN layer sequentially stacked on the N-type GaN layer. The first GaN layer is a heavily Si-doped GaN layer, and the Si doping concentration of the first GaN layer is 9*10⁻⁶. 18 atoms / cm 3 -9.5*10 18 atoms / cm 3 ; The second GaN layer is a lightly Si-doped GaN layer with a Si doping concentration of 1*10⁻⁶. 17 atoms / cm 3 -1*10 18 atoms / cm 3 Furthermore, from the InGaN / GaN superlattice layer to the stress relief layer, the Si doping concentration of the second GaN layer gradually increases from low to high. The InGaN / GaN superlattice layer comprises overlapping InGaN and GaN layers with an overlap period of 20-30; the thickness ratio of the InGaN layer to the GaN layer is <1.
5. The InGaN / GaN superlattice layer is a low-Si-doped InGaN / GaN superlattice layer with a Si doping concentration of 5*10⁻⁶. 17 atoms / cm 3 -1*10 18 atoms / cm 3 ; The Si doping concentration of the stress compensation layer gradually decreases from the first GaN layer to the InGaN / GaN superlattice layer.
2. The light-emitting diode epitaxial wafer as described in claim 1, characterized in that, The Al component concentration in the AlGaN layer is 0.01-0.
1.
3. The light-emitting diode epitaxial wafer as described in claim 1, characterized in that, The In GaN layer has an In component concentration of 0.01-0.1%.
4. The light-emitting diode epitaxial wafer as described in claim 1, characterized in that, The thickness of the stress compensation layer is 300nm-500nm; The thickness of the AlGaN layer is 20nm-30nm; The thickness of the InGaN / GaN superlattice layer is 100nm-150nm; The thickness of the first GaN layer is 2.5 to 4 times the thickness of the second GaN layer.
5. A method for fabricating a light-emitting diode epitaxial wafer as described in any one of claims 1-4, characterized in that, Includes the following steps: Prepare the substrate; A buffer layer, an N-type GaN layer, a stress compensation layer, a stress relief layer, a multiple quantum well layer, and a P-type GaN layer are sequentially deposited on the substrate. The stress compensation layer comprises an AlGaN layer, a first GaN layer, an InGaN / GaN superlattice layer, and a second GaN layer, which are sequentially stacked on the N-type GaN layer.
6. The method for fabricating a light-emitting diode epitaxial wafer as described in claim 5, characterized in that, Depositing the AlGaN layer on the N-type GaN layer includes the following steps: The temperature of the reaction chamber was controlled at 950℃-1200℃, and N source, Ga source and Al source were introduced to complete the deposition.
7. The method for fabricating a light-emitting diode epitaxial wafer as described in claim 5, characterized in that, Depositing the first GaN layer on the AlGaN layer includes the following steps: First, the temperature of the reaction chamber is controlled at 800℃-980℃, N2 and H2 are introduced as carrier gases, and N source, Ga source and Si source are introduced to complete the deposition; The atmosphere ratio of N2 to H2 is (3-4):
1.
8. The method for fabricating a light-emitting diode epitaxial wafer as described in claim 5, characterized in that, Depositing the InGaN / GaN superlattice layer on the first GaN layer includes the following steps: The reaction chamber temperature is controlled at 900℃-1050℃. N2 and H2 are introduced as carrier gases. First, Ga source, In source, N source and Si source are introduced to complete the InGaN layer deposition. Then, Ga source, N source and Si source are introduced to complete the GaN layer deposition. The overlapping deposition is carried out for 20-30 cycles. The atmosphere ratio of N2 to H2 is (2-3):
1.
9. The method for fabricating a light-emitting diode epitaxial wafer as described in claim 5, characterized in that, Depositing the second GaN layer on the InGaN / GaN superlattice layer includes the following steps: The temperature of the reaction chamber is controlled at 900℃-1050℃. N2 and H2 are introduced as carrier gases, and Ga source, N source and Si source are introduced to complete the deposition. The atmosphere ratio of N2 to H2 is 1:(1-2).
10. A light-emitting diode, characterized in that, The light-emitting diode includes a light-emitting diode epitaxial wafer as described in any one of claims 1-4.