LED

Abstract

This invention discloses a light-emitting diode (LED), comprising: a semiconductor stack including a first semiconductor layer, a second semiconductor layer, and an active layer located between the first semiconductor layer and the second semiconductor layer; a first mesa located at the edge region of the semiconductor stack, exposing a first surface of the first semiconductor layer; and an insulating layer partially formed on the first mesa, the insulating layer comprising a first insulating layer, a fourth insulating layer, and a second insulating layer stacked sequentially, the fourth insulating layer being aluminum oxide, and the insulating layer including a sixth opening to expose the first surface of the first semiconductor layer; wherein the projection of the sixth opening in the growth direction of the semiconductor stack is located within the first mesa, the sixth opening including a first segment and a second segment, the first segment and the second segment being a continuous structure, the first segment extending along a first side of the LED, and the second segment extending along a second side of the LED.

Description

Technical Field

[0001] This invention relates to the field of light-emitting diode manufacturing technology, and in particular to a light-emitting diode. Background Technology

[0002] A light-emitting diode (LED) is a solid-state semiconductor light-emitting diode that contains various light-emitting materials and components. Due to its advantages such as low cost, low power consumption, high luminous efficiency, small size, energy saving, environmental friendliness, and excellent optoelectronic properties, it is widely used in various scenarios including lighting, visible light communication, and light-emitting displays. Summary of the Invention

[0003] To achieve at least one or more advantages of the present invention, one embodiment of the present invention provides a light-emitting diode, comprising: a semiconductor stack including a first semiconductor layer, a second semiconductor layer, and an active layer located between the first semiconductor layer and the second semiconductor layer; a third insulating layer located on the semiconductor stack; the third insulating layer having a fourth opening and a fifth opening; a first pad electrode and a second pad electrode, the first pad electrode being formed in the fourth opening and electrically connected to the first semiconductor layer, the second pad electrode being formed in the fifth opening and electrically connected to the second semiconductor layer, the first pad electrode having an upper edge away from the semiconductor stack and a lower edge close to the semiconductor stack, the second pad electrode having an upper edge away from the semiconductor stack and a lower edge close to the semiconductor stack, a first maximum horizontal distance between the lower edge of the first pad electrode and the fourth opening, and a second maximum horizontal distance between the lower edge of the second pad electrode and the fifth opening, the first maximum horizontal distance being less than 2 μm, and the second maximum horizontal distance being less than 2 μm.

[0004] Other features and beneficial effects of the invention will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other beneficial effects of the invention can be realized and obtained by means of the structures particularly pointed out in the description, claims, and drawings. Attached Figure Description

[0005] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Unless otherwise specified, the positional relationships shown in the drawings in the following description are based on the direction in which the components are drawn in the figure.

[0006] Figure 1 This is a cross-sectional view of the light-emitting diode 1 disclosed in the first embodiment of the present invention;

[0007] Figures 2 to 29 This is a schematic diagram showing the structure of each step in the manufacturing method of the light-emitting diode 2 disclosed in the second embodiment of the present invention.

[0008] Figure 30 This is a top view of the light-emitting diode 3 disclosed in the third embodiment of the present invention;

[0009] Figure 31 for Figure 30 A partially enlarged schematic diagram of the light-emitting diode 3 shown;

[0010] Figure 32 For along Figure 30 A cross-sectional view of the light-emitting diode 3 as shown by line segment I-I';

[0011] Figure 33 for Figure 32 A partially enlarged schematic diagram of the light-emitting diode 3 shown;

[0012] Figure 34 This is a cross-sectional view of the light-emitting diode 4 disclosed in the fourth embodiment of the present invention. Detailed Implementation

[0013] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. The technical features designed in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0014] In the description of this invention, it should be noted that all terms used in this invention (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains, and should not be construed as limiting the invention; it should be further understood that the terms used in this invention should be understood to have the same meaning as those in the context of this specification and in the relevant field, and should not be understood in an idealized or overly formal sense, except as expressly defined in this invention.

[0015] First Embodiment

[0016] Figure 1This is a cross-sectional view of the light-emitting diode 1 disclosed in the first embodiment of the present invention.

[0017] like Figure 1 As shown, the light-emitting diode 1 includes a substrate 110 and a semiconductor stack 120 formed on the substrate 110, wherein the semiconductor stack 120 includes a first semiconductor layer 121, a second semiconductor layer 123, and an active layer 122 located between the first semiconductor layer 121 and the second semiconductor layer 123.

[0018] In one embodiment of the invention, the substrate 110 can be formed using a carrier wafer suitable for semiconductor material growth. Furthermore, the substrate 110 can be formed of a material with excellent thermal conductivity, or it can be a conductive or insulating substrate. Additionally, the substrate 110 can be formed of a light-transmitting material and can have mechanical strength that does not cause bending of the entire semiconductor stack 120 and allows for effective division into separate chips via scribing and breaking processes. For example, the substrate 110 can be a sapphire (Al2O3) substrate, a silicon carbide (SiC) substrate, a silicon (Si) substrate, a zinc oxide (ZnO) substrate, a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, or a gallium phosphide (GaP) substrate, etc., with sapphire (Al2O3) substrates being particularly preferred. In this embodiment, the substrate 110 is a sapphire substrate with a series of protrusions on its surface, including, for example, protrusions without a fixed slope formed by dry etching, or protrusions with a fixed slope formed by wet etching.

[0019] In one embodiment of the present invention, a semiconductor stack 120 with photoelectric properties, such as a light-emitting stack, is formed on a substrate 110 by metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor deposition (HVPE), physical vapor deposition (PVD), or ion plating. The physical vapor deposition method includes sputtering or evaporation. The first semiconductor layer 121, the active layer 122, and the second semiconductor layer 123 may be formed from a group III gallium nitride (GaN) compound semiconductor, such as GaN, AlN, InGaN, AlGaN, InAlGaN, and at least one thereof. The first semiconductor layer 121 is an electron-providing layer and can be formed by implanting an n-type dopant (e.g., Si, Ge, Se, Te, C, etc.). The second semiconductor layer 123 is a hole-providing layer and can be formed by implanting a p-type dopant (e.g., Mg, Zn, Be, Ca, Sr, Ba, etc.). The active layer 122 is a layer in which electrons provided by the first semiconductor layer 121 and holes provided by the second semiconductor layer 123 recombine to output light of a predetermined wavelength. It can be formed from a multilayer semiconductor thin film having a single-layer or multilayer quantum well structure with alternating stacked well and barrier layers. The active layer 122 may be formed with different material compositions or ratios depending on the wavelength of the output light. For example, the emission wavelength of the light-emitting diode 1 in this embodiment is between 420 nm and 580 nm. The active layer 122 may be formed as a pair of well and barrier layers using group III to group V compound semiconductor materials (e.g., InGaN / GaN, InGaN / InGaN, GaN / AlGaN, InAlGaN / GaN, GaAs(InGaAs) / AlGaAs, or GaP(InGaP) / AlGaP), but this disclosure is not limited thereto. The well layer may be formed from a material having a band gap smaller than that of the barrier layer.

[0020] In one embodiment of the present invention, the light-emitting diode 1 includes a transparent conductive layer 130 formed on a semiconductor stack 120 and in contact with a second semiconductor layer 123. The transparent conductive layer 130 can substantially contact almost the entire upper surface of the second semiconductor layer 123. In this structure, when current is supplied to the light-emitting diode, it can be distributed horizontally through the transparent conductive layer 130, and thus can be uniformly supplied to the entire second semiconductor layer 123. In a preferred embodiment, the thickness of the transparent conductive layer 130 is 5-60 nm. When the thickness is less than 5 nm, the forward voltage (Vf) of the light-emitting diode tends to increase, and when it exceeds 60 nm, its light absorption effect will increase significantly. The thickness of the transparent conductive layer 130 is more preferably 10-30 nm, for example, 15 nm or 20 nm. The material of the transparent conductive layer 130 can be ITO, InO, SnO, CTO, ATO, ZnO, GaP, or a combination thereof. The transparent conductive layer 130 can be formed by vapor deposition or sputtering.

[0021] In another embodiment (not shown), the transparent conductive layer 130 has multiple openings that expose a portion of the second semiconductor layer 123. By controlling the size and density of these openings, the area occupied by the transparent conductive layer 130 of the semiconductor stack 120 is greater than 50% and less than 95%. This ensures sufficient ohmic contact between the transparent conductive layer 130 and the second semiconductor layer 123 while reducing the area of ​​the transparent conductive layer 130, thereby improving the brightness of the light-emitting diode. Preferably, the area occupied by the transparent conductive layer 130 of the semiconductor stack 120 is 70-90%. Specifically, the openings are arranged in an array with a diameter of 2-50 μm, and the spacing between adjacent first openings OP1 is 1-20 μm. In this embodiment, the diameter of the openings is selected as 2-10 μm, and the spacing is 5-20 μm.

[0022] In one embodiment of the present invention, the light-emitting diode 1 includes a first insulating layer 140 formed on a semiconductor stack 120. The first insulating layer 140 includes one or more first openings OP1 to expose a portion of the surface of the transparent conductive layer 130. The total cross-sectional area of ​​the first openings OP1 accounts for 3% to 50% of the cross-sectional area of ​​the semiconductor stack 120, preferably 5% to 20%, and more preferably 10%. If the ratio is too low, the contact area between the subsequently formed reflective electrode layer 150 and the transparent conductive layer 130 through the first openings OP1 will be too small, which is not conducive to voltage control. If the ratio is too high, it will affect the reflection effect of the transparent conductive layer 130, the first insulating layer 140 (e.g., low refractive index), and the reflective electrode layer 150 forming an all-around reflective layer structure.

[0023] The first insulating layer 140 may include at least one of SiO2, SiN, SiOxNy, TiO2, Si3N4, Al2O3, TiN, AlN, ZrO2, TiAlN, TiSiN, HfO, TaO2, and MgF2. In an example embodiment, the first insulating layer 140 may have a multilayer film structure in which insulating films with different refractive indices are alternately stacked, and may be configured as a distributed Bragg reflector (DBR). The multilayer film structure may be a structure in which first insulating films and second insulating films having a first refractive index and a second refractive index (as different refractive indices) are alternately stacked.

[0024] In another example embodiment, the first insulating layer 140 may be formed of a material with a refractive index lower than that of the second semiconductor layer 123. The first insulating layer 140 may together with the reflective electrode layer 150 arranged to contact the upper part of the first insulating layer 140 to form an omnidirectional reflector (ODR). In this way, the first insulating layer 140 can be used alone or in combination with the reflective electrode layer 150 as a reflective structure to increase the reflectivity of light emitted by the active layer 122, thereby significantly improving the light extraction efficiency.

[0025] The thickness of the first insulating layer 140 can be in the range of 100 nm to 1500 nm, specifically, it can be in the range of 200 nm to 1000 nm. When the thickness of the first insulating layer 140 is less than 200 nm, the forward voltage is high and the light output is low, which is not ideal. On the other hand, if the thickness of the first insulating layer 140 exceeds 1000 nm, the light output saturates. Therefore, it is preferable that the thickness of the first insulating layer 140 does not exceed 1000 nm, and in particular, it can be 900 nm or less.

[0026] In one embodiment of the present invention, the light-emitting diode 1 includes a reflective electrode layer 150 formed on a semiconductor stack 120. The reflective electrode layer 150 contacts the transparent conductive layer 130 through a first opening OP1. The reflective electrode layer 150 includes a metal reflective layer 151 and a metal protective layer 152. The metal reflective layer 151 is formed on the metal protective layer 152, which can reduce the risk that the metal reflective layer 151 may be oxidized by air or corroded by etching solution during the fabrication process (e.g., during the removal of photoresist).

[0027] The metal reflective layer 151 comprises a reflective metal with high reflectivity to light emitted by the light-emitting diode, such as Ag, Al, Rh, Ru, Ti, Cr, Ni, or alloys or stacks of the above materials.

[0028] The material of the metal protective layer 152 may include nickel (Ni), chromium (Cr), platinum (Pt), titanium (Ti), tungsten (W), zinc (Zn), or alloys or stacks of the above materials. In one embodiment, when the metal protective layer 152 is a metal stack, the metal protective layer 152 is formed by alternating stacks of two or more metals, such as Cr / Pt, Cr / Ti, Cr / TiW, Cr / W, Cr / Zn, Ti / Pt, Ti / W, Ti / TiW, Ti / Zn, Pt / TiW, Pt / W, Pt / Zn, TiW / W, TiW / Zn, W / Zn, Ni / Pt, Ni / Ti, Ni / TiW, Ni / W, or Ni / Zn, etc.

[0029] The light radiated by the semiconductor stack 120 passes through the first insulating layer 140 to the surface of the reflective electrode layer 150 and is reflected back by the reflective electrode layer 150. Therefore, the first insulating layer 140 has a certain degree of light transmittance to the light emitted by the active layer. More preferably, according to the principle of light reflection, the refractive index of the first insulating layer 140 is lower than that of the semiconductor stack 120 material, allowing some of the light radiated by the active layer 122 to be transmitted or refracted at small angles to the surface of its first reflective layer 130, while incident light exceeding the angle of total internal reflection is totally reflected back. Therefore, the light reflection effect of the combination of the first insulating layer 140 and the reflective electrode layer 150 is higher than that of the reflective electrode layer 150 alone.

[0030] Because the metal protective layer 152 formed on the metal reflective layer 151 is relatively thin, it effectively protects against electromigration and thermal diffusion of the metal reflective layer 151. In one embodiment of the present invention, the light-emitting diode 1 includes a metal barrier layer 220, which is formed on the reflective electrode layer 150 and has its edge located on the upper surface of the second insulating layer 161. The metal barrier layer 220 covers the reflective electrode layer 150 to prevent electromigration or thermal diffusion of the metal contained in the reflective electrode layer 150. To effectively protect the reflective electrode layer 150, the metal barrier layer 220 needs to have sufficient thickness, especially at the edge of the reflective electrode layer 150. Therefore, the thickness between the edge of the metal barrier layer 220 and the edge of the reflective electrode layer 150 is greater than 4 μm. To ensure sufficient formation space between the metal barrier layer 220 and the semiconductor stack 120, the spacing between the reflective electrode layer 150 and the semiconductor stack 120 is greater than 8 μm to ensure that no leakage current or ESD abnormalities occur during chip fabrication.

[0031] In one embodiment of the present invention, the thickness of the metal reflective layer 151 is 100~200nm, the thickness of the metal protective layer 152 is 100~500nm, and the thickness of the metal blocking layer 220 is 500nm~1500nm.

[0032] The metal barrier layer 220 may comprise metals such as titanium (Ti), tungsten (W), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt), chromium (Cr), gold (Au), and titanium-tungsten (TiW), or alloys thereof. The metal barrier layer 220 may be a single layer or a multilayer structure, such as titanium (Ti) / aluminum (Al) and / or titanium (Ti) / tungsten (W).

[0033] In one embodiment of the present invention, the light-emitting diode 1 includes a second insulating layer 161 formed on a metal barrier layer 220, and includes a second opening OP2 that partially exposes a first semiconductor layer 121 and a third opening OP3 that partially exposes the metal barrier layer 220.

[0034] The second insulating layer 161 may comprise an insulating material prepared using physical vapor deposition or chemical vapor deposition, such as silicon nitride (SiNx), silicon oxide (SiOx), titanium oxide (TiOx), or magnesium fluoride (MgF2). Furthermore, the second insulating layer 161 may be composed of multiple layers and may include a distributed Bragg reflector in which insulating materials with different refractive indices are alternately stacked. The structure of the second insulating layer 161 including the distributed Bragg reflector reflects light that has passed through the omnidirectional reflector but is not reflected, thereby improving the luminous efficiency of the light-emitting device.

[0035] In one embodiment of the present invention, the light-emitting diode 1 includes a first connecting electrode 171 and a second connecting electrode 172. The first connecting electrode 171 contacts the first semiconductor layer 121 through a second opening OP2 and extends to cover the surface of the second insulating layer 161, wherein the first connecting electrode 171 is insulated from the second semiconductor layer 123 through the second insulating layer 161. The second connecting electrode 172 contacts the metal barrier layer 220 through a third opening OP3 and extends to cover the surface of the second insulating layer 160, wherein the second connecting electrode 172 is electrically connected to the second semiconductor layer 123 through the metal barrier layer 220.

[0036] In one embodiment of the present invention, the light-emitting diode includes a third insulating layer 180, which is formed on a semiconductor stack 120 and covers the first connecting electrode 171 and the second connecting electrode 172. The third insulating layer 180 includes a fourth opening OP4 exposing a portion of the surface of the first connecting electrode 171 and a fifth opening OP5 exposing a portion of the surface of the second connecting electrode 172.

[0037] The third insulating layer 180 may include SiO2, SiN, etc. The third insulating layer 180 may be a multilayer film structure composed of alternating stacked high-refractive-index dielectric films and low-refractive-index dielectric films, such as a Bragg reflector (DBR). The high-refractive-index dielectric film may be made of materials such as TiO2, NB2O5, TA2O5, HfO2, ZrO2, etc.; the low-refractive-index dielectric film may be made of materials such as SiO2, MgF2, SiON, etc. The thickness of the third insulating layer 180 is between 500 nm and 1500 nm. The total area of ​​the plurality of fourth openings OP4 and the plurality of fifth openings OP5 in the third insulating layer 180 is preferably greater than 20% of the total area of ​​the semiconductor stack 120.

[0038] In one embodiment of the present invention, the light-emitting diode 1 includes a first pad electrode 191 and a second pad electrode 192. The first pad electrode 191 is in contact with a first connection electrode 171 through a fourth opening OP4, and is electrically connected to a first semiconductor layer 121 through the first connection electrode 171. The second pad electrode 192 is in contact with a second connection electrode 172 through a fifth opening OP5, and is electrically connected to a second semiconductor layer 123 through the second connection electrode 172.

[0039] In one embodiment of the present invention, each of the first pad electrode 191 and the second pad electrode 192 may comprise a single film of a single material selected from the group consisting of gold (Au), tin (Sn), nickel (Ni), lead (Pb), silver (Ag), indium (In), chromium (Cr), germanium (Ge), silicon (Si), titanium (Ti), tungsten (W), and platinum (Pt), or an alloy comprising at least two of these materials, or a multilayer structure comprising a combination thereof.

[0040] Each of the first pad electrode 191 and the second pad electrode layer 192 can be used as an external terminal of a light-emitting diode, but the inventive concept is not limited thereto.

[0041] Second Embodiment

[0042] Figures 2 to 29 This is a schematic diagram showing the structure of each step in the manufacturing method of the light-emitting diode 2 disclosed in the second embodiment of the present invention.

[0043] LED 2 has a roughly the same structure as LED 1, therefore for Figures 2 to 29 LED 2 and Figure 2 LEDs 1 with the same name, designation, structure, material, or function will be omitted or further described here.

[0044] like Figure 2As shown, the method of manufacturing a light-emitting diode 2 includes the step of forming a semiconductor stack 120, which includes providing a substrate 110; and forming a semiconductor stack 120 on the substrate 110, wherein the semiconductor stack 120 includes a first semiconductor layer 121, a second semiconductor layer 123, and an active layer 122 located between the first semiconductor layer 121 and the second semiconductor layer 123.

[0045] like Figure 3 Top view and Figure 4 For along Figure 3As shown in the cross-sectional view along line segment I-I', after the semiconductor stack 120 is formed on the substrate 110, the method for manufacturing the light-emitting diode 2 includes a mesa formation step. The semiconductor stack 120 is patterned by photolithography and etching to form a first mesa 1201 and a plurality of second mesa 1202. Through photolithography and etching processes, a portion of the interior of the second semiconductor layer 123 and the active layer 122 is removed to form the plurality of second mesa 1202, and the plurality of second mesa 1202 correspondingly expose the second surface 121b of the first semiconductor layer 121. Here, the second mesa 1202 is defined by an inner sidewall 1200c and a second surface 121b. One end of the inner sidewall 1200c is connected to the second surface 121b of the first semiconductor layer 121, while the other end of the inner sidewall 1200c is connected to the surface 123s of the second semiconductor layer 123. In the same or another photolithography and etching process, the second semiconductor layer 123 and the active layer 122 surrounding the semiconductor stack 120 are removed to form a first mesa 1201, and the first mesa 1201 exposes the first surface 121a of the first semiconductor layer 121. In another embodiment, in the photolithography and etching process, a portion of the first semiconductor layer 121 is further etched to a deeper etch depth to expose the first surface 121a. Here, the first mesa 1201 is defined by a first outer sidewall 1200a, a second outer sidewall 1200b, and the first surface 121a, wherein one end of the first outer sidewall 1200a is connected to the first surface 121a of the first mesa 1201, and the other end is connected to the exposed surface 110s of the substrate 110; one end of the second outer sidewall 1200b is connected to the first surface 121a of the first mesa 1201, and the other end is connected to the surface 123s of the second semiconductor layer 123. The first outer sidewall 1200a and the second outer sidewall 1200b may be inclined to the first surface 121a. A first mesa 1201 is formed along a periphery of the semiconductor stack 120, located at and / or surrounding the edge of one or more semiconductor stacks 120. In one embodiment, the first outer sidewall 1200a is inclined to the exposed surface 110s of the substrate 110. An acute angle is formed between the first outer sidewall 1200a and the exposed surface 110s of the substrate 110. In another embodiment, an obtuse angle (not shown) is formed between the first outer sidewall 1200a and the exposed surface 110s of the substrate 110.

[0046] In one embodiment of the present invention, such as Figure 3 As shown, the second mesa 1202 is located inside the semiconductor stack 120, exposing the second surface 121b of the first semiconductor layer 121. The shape of the second mesa 1202 includes elliptical, circular, rectangular, or other arbitrary shapes. The second mesa 1202 can be regularly arranged on the semiconductor stack 120. However, it should be understood that the present invention is not limited thereto, and the configuration and number of the second mesa 1202 can be changed in various ways.

[0047] The steps to form a successor platform, such as Figure 5 Top view Figure 6 for Figure 5 A partially enlarged schematic diagram and Figure 7 For along Figure 5 As shown in the cross-sectional view along line segment I-I', the method for manufacturing a light-emitting diode includes a transparent conductive layer formation step. A transparent conductive layer 130 is formed on a semiconductor stack 120 by means of physical vapor deposition or chemical vapor deposition, and contacts a second semiconductor layer 123. In some embodiments, the horizontal distance between the sidewall 130e of the transparent conductive layer 130 and the second outer sidewall 1200b or inner sidewall 1200c of the semiconductor stack 120 is a third distance D3, which can be less than 10 μm, preferably 2 to 6 μm. In this structure, when current is supplied to the light-emitting diode, it can be distributed horizontally through the transparent conductive layer 130, and thus can be uniformly supplied to the entire second semiconductor layer 123. If the third distance D3 is greater than 10 μm, the contact area between the transparent conductive layer 130 and the second semiconductor layer 123 is too small, the voltage of the light-emitting diode is too high, and the current diffusion effect is poor.

[0048] In one embodiment of the present invention, the step of forming the transparent conductive layer is followed by, for example... Figure 8 Top view Figure 9 for Figure 8 A partially enlarged schematic diagram Figure 10 For along Figure 8 Cross-sectional view of line segment I-I' and Figure 11 for Figure 10 As shown in the partially enlarged schematic diagram, the manufacturing method of the light-emitting diode 2 includes a step of forming a first insulating layer 140. The first insulating layer 140 is formed on the semiconductor stack 120 by means of physical vapor deposition or chemical vapor deposition, and then patterned by photolithography and etching. The first insulating layer 140 may include one or more first openings OP1 to expose a portion of the surface of the transparent conductive layer 130. The first insulating layer 140 is formed on the transparent conductive layer 130 and covers the sidewalls 130e of the transparent conductive layer 130 and the sidewalls of the semiconductor stack 120. Specifically, the first insulating layer 140 may cover a portion of the surface of the transparent conductive layer 130, the second outer sidewall 1200b of the semiconductor stack 120, the first surface 121a of the first semiconductor layer 121, the first outer sidewall 1200a, the inner sidewall 1200c, and the second surface 121b of the first semiconductor layer 121. When the mesa has inclined sidewalls, the first insulating layer 140 disposed on the sidewalls of the mesa can be formed more stably.

[0049] In one embodiment, such as Figure 11As shown, the first insulating layer 140 has an upper surface 140S1 away from the semiconductor stack 120 and a lower surface 140S2 opposite to the upper surface 140S1. The upper surface 140S1 has a first surface 140S1a, a second surface 140S1b, and a third surface 140S1c connecting the first surface 140S1a and the second surface 140S1b. The thickness between the first surface 140S1a and the lower surface 140S2 is less than the thickness between the second surface 140S1b and the lower surface 140S2, that is, the first surface 140S1a is closer to the semiconductor stack 120 than the second surface 140S1b. The third surface 140S1c is an inclined surface relative to the first surface 140S1a and the second surface 140S1b, and the included angle between the third surface 140S1c and the first surface 140S1a is an obtuse angle.

[0050] Following the formation of the first insulating layer 140, as follows: Figure 12 Top view Figure 13 for Figure 12 A magnified view of part A Figure 14 for Figure 12 A magnified view of part B. Figure 15 For along Figure 12 The sectional view of line segment I-I' and Figure 16 for Figure 15 As shown in the partially enlarged schematic diagram, the manufacturing method of the light-emitting diode includes a step of forming a reflective electrode layer 150. The reflective electrode layer 150 is directly formed on the semiconductor stack 120 by means of physical vapor deposition or magnetron sputtering. The reflective electrode layer 150 is disposed on the first surface 140S1a and the third surface 140S1c of the first insulating layer 140, and contacts the transparent conductive layer 130 through a first opening OP1. The edge 150e of the reflective electrode layer 150 is formed on the third surface 140S1c of the first insulating layer 140.

[0051] In one embodiment, such as Figure 16 As shown, the reflective electrode layer 150 includes a metal reflective layer 151 and a metal protective layer 152. The metal reflective layer 151 is formed on a first surface 140S1a of the first insulating layer 140, and the edge of the metal reflective layer 151 is located on a third surface 140S1c. By controlling the edge of the metal reflective layer 151 to be formed on the third surface 140S1c, it is beneficial to deposit the metal protective layer 152 above the edge of the metal reflective layer 151.

[0052] The metal protective layer 152 can cover the upper and side surfaces of the metal reflective layer 151 to protect the metal reflective layer 151 from oxidation or corrosion during the manufacturing process (e.g., adhesive removal) and to inhibit the migration of metal elements contained in the metal reflective layer 151. The metal protective layer 152 may include an upper portion R1 covering the upper surface of the metal reflective layer 151 and a side portion R2 covering the side surfaces of the metal reflective layer 151. The side portion R2 is formed on the third surface 140S1c of the first insulating layer 140, and the thickness of the side portion R2 gradually decreases. For example, the upper portion R1 and the side portion R2 may be in contact with each other and continuous.

[0053] In one embodiment, the thickness of the metal reflective layer 151 is 100~200nm, and the thickness of the upper part R1 of the metal protective layer 152 is 100~500nm.

[0054] In one embodiment, such as Figure 16 As shown, the thickness between the surface 150s of the reflective electrode layer 150 away from the semiconductor stack and the lower surface 140S2 of the first insulating layer 140 is less than the thickness between the second surface 140S1b and the lower surface 140S2 of the first insulating layer 140. This ensures that the reflective electrode layer 150 has sufficient reflectivity and also ensures the adhesion between the reflective electrode layer 150 and the first insulating layer 140.

[0055] In one embodiment of the present invention, the horizontal distance between the edge 150e of the reflective electrode layer 150 and the second outer sidewall 1200b or inner sidewall 1200c of the semiconductor stack 120 is a fourth distance D4 (i.e., the horizontal distance between the edge 150e of the reflective electrode layer 150 and the upper edge of the second semiconductor layer 123). The fourth distance D4 is 1~5μm, for example 2μm, 3μm or 4μm. Since the fourth distance D4 is small, designing a metal barrier layer 220 as in the light-emitting diode 1 may lead to leakage and ESD abnormalities. Therefore, in one embodiment of the present invention, the metal barrier layer 220 structure is omitted on the reflective electrode layer 150 to maximize the area of ​​the reflective electrode layer 150 and improve the brightness of the light-emitting diode. If the fourth distance D4 is less than 1μm, the spacing between the reflective electrode layer 150 and the semiconductor stack 120 is too small, which may cause leakage and ESD abnormalities in the light-emitting diode. If the fourth distance D4 is greater than 5μm, it will affect the area of ​​the reflective electrode layer 150, thereby reducing the brightness of the light-emitting diode.

[0056] In one embodiment of the present invention, since the light-emitting diode 2 eliminates the metal blocking layer 220, the projection of the transparent conductive layer 130 in the growth direction of the semiconductor stack 120 is located within the projection of the reflective electrode layer 150 in the growth direction of the semiconductor stack 120, so as to maximize the area of ​​the reflective electrode layer 150, thereby making the third distance D3 greater than the fourth distance D4.

[0057] In one embodiment of the present invention, such as Figure 15 and Figure 16 As shown, the projection of the transparent conductive layer 130 in the growth direction of the semiconductor stack 120 is located within the projection of the third surface 140S1c and the first surface 140S1a of the first insulating layer 160 in the growth direction of the semiconductor stack 120.

[0058] The steps for forming the continuation reflective electrode layer 150 are as follows: Figure 17 Top view Figure 18 for Figure 17 A magnified view of part A Figure 19 for Figure 17 A magnified view of part B. Figure 20 For along Figure 17 The sectional view of line segment I-I' is shown below. Figure 21 for Figure 20 A magnified diagram of part A and Figure 22 for Figure 20 The enlarged schematic diagram of part B shows that the manufacturing method of the light-emitting diode includes the steps of forming a fourth insulating layer 162 and a second insulating layer 161. The fourth insulating layer 162 is formed on the semiconductor stack 120 by atomic layer deposition. The fourth insulating layer 162 is formed on the reflective electrode layer 150 and extends to the second surface 140S1b of the first insulating layer 140. The fourth insulating layer 162 can be aluminum oxide or silicon oxide, preferably aluminum oxide. The fourth insulating layer 162 prepared by atomic layer deposition has good density, which can strengthen the protection of the reflective electrode layer 150 and further prevent the electromigration or thermal diffusion of the metal elements contained in the reflective electrode layer 150. This increases the area of ​​the reflective electrode layer 150 to increase the brightness of the light-emitting diode and prevents migration, thus improving the reliability of the light-emitting diode. In one embodiment, the second insulating layer 161 is formed on the fourth insulating layer 162 by physical vapor deposition or chemical vapor deposition. The second insulating layer 161 can be one or more of silicon oxide, silicon nitride, silicon oxynitride, or titanium oxide.

[0059] In one embodiment, the thickness of the fourth insulating layer 162 is 20-150 nm. If the thickness of the fourth insulating layer 162 is less than 20 nm, the protection effect on the reflective electrode layer 150 is limited, and it cannot effectively prevent the electromigration or thermal diffusion of the metal elements contained in the reflective electrode layer 150; if the thickness of the fourth insulating layer 162 is greater than 150 nm, the process preparation time is too long, resulting in reduced efficiency and increased cost. The thickness of the second insulating layer 161 is 20-150 nm. In a preferred embodiment, the thickness of the second insulating layer 161 is greater than the thickness of the fourth insulating layer 162, which can utilize the strong coverage and strong barrier properties of the film formed by atomic layer deposition, while also taking into account production efficiency.

[0060] The fourth insulating layer 162 and the second insulating layer 161 are patterned by photolithography or etching to form a second opening OP2 to expose the second surface 121b of the first semiconductor layer 121, and a third opening OP3 to expose a portion of the surface of the reflective electrode layer 150. During the patterning of the fourth insulating layer 162 and the second insulating layer 161, the first insulating layer 140, which was covered within the mesa during the aforementioned first insulating layer 140 formation step, is partially etched away to expose the second surface 121b of the first semiconductor layer 121.

[0061] In one embodiment of the present invention, in order to increase the contact area between the first connecting electrode 171 and the first semiconductor layer 121 through the second opening OP2 to reduce the voltage of the light-emitting diode, the second opening OP2 can be formed by ICP dry etching. Since the metal protective layer 152 in the reflective electrode layer 150 is relatively thin, if the third opening OP3 is formed by ICP dry etching, the gas used in the ICP dry etching may corrode the metal protective layer 152, causing electromigration or thermal diffusion of Ag or Al in the metal reflective layer 151. Therefore, in one embodiment of the present invention, the third opening OP3 is formed by wet etching.

[0062] like Figure 21 As shown, the sidewall of the second opening OP2 can form a first angle α1 with the second surface 120b of the first semiconductor layer 121. For example... Figure 22 As shown, the sidewall of the third opening OP3 can form a second angle α2 with the surface of the reflective electrode layer 150.

[0063] In one embodiment of the present invention, the second opening OP2 is formed by ICP dry etching, and the third opening OP3 is formed by BOE wet etching. Therefore, the first included angle α1 can be greater than the second included angle α2.

[0064] In another embodiment of the invention, since the metal layer 210 is formed on the reflective electrode layer 150, it can prevent the gas used in ICP dry etching from corroding the reflective electrode layer 150, and the third opening OP3 can be obtained by ICP dry etching. Therefore, the first included angle α1 can be equal to the second included angle α2.

[0065] Following the steps of forming the fourth insulating layer 162 and the second insulating layer 161, as follows: Figure 23 Top view Figure 24 For along Figure 23 The sectional view of line segment I-I' and Figure 25 for Figure 24As shown in the enlarged schematic diagram of part A, the manufacturing method of the light-emitting diode includes the step of forming a connection electrode 170. The connection electrode 170 is formed on the semiconductor stack 120 by means of physical vapor deposition or magnetron sputtering. Then, the connection electrode 170 is patterned by photolithography and etching to form a first connection electrode 171 and a second connection electrode 172.

[0066] The first connecting electrode 171 contacts the second surface 121b of the first semiconductor layer 121 through the second opening OP2 and extends to cover the surface of the second insulating layer 161, wherein the first connecting electrode 171 is insulated from the second semiconductor layer 123 through the second insulating layer 161. The second connecting electrode 172 contacts the reflective electrode layer 150 through the third opening OP3 and extends to cover the surface of the second insulating layer 160, wherein the second connecting electrode 172 is electrically connected to the second semiconductor layer 123 through the reflective electrode layer 150.

[0067] In one embodiment of the present invention, the first connecting electrode 171 and the second connecting electrode 172 are spaced apart from each other, such that the first connecting electrode 171 is not in contact with the second connecting electrode 172. In a top view of the light-emitting diode, the first connecting electrode 171 surrounds multiple sidewalls of the second connecting electrode 172. To allow for better current diffusion, the area of ​​the first connecting electrode 171 is larger than the area of ​​the second connecting electrode 172.

[0068] The steps for forming the connecting electrode 170 are as follows: Figure 26 Top view and Figure 27 along Figure 26 As shown in the cross-sectional view along line segment I-I', the manufacturing method of a light-emitting diode includes a step of forming a third insulating layer 180. A third insulating layer 180 is formed on a semiconductor stack 120 by means of physical vapor deposition or chemical vapor deposition, and then the third insulating layer 180 is patterned by photolithography and etching to form a fourth opening OP4 and a fifth opening OP5 to expose the first connecting electrode 171 and the second connecting electrode 172, respectively.

[0069] Following the third insulating layer formation step, the method for manufacturing a light-emitting diode includes a pad electrode 190 formation step. For example... Figure 28 Top view and Figure 29 along Figure 28 As shown in the cross-sectional view of line segment I-I', a first pad electrode 191 and a second pad electrode 192 are formed on one or more semiconductor stacks 120 by means of electroplating, physical vapor deposition or chemical vapor deposition.

[0070] The first pad electrode 191 contacts the first connecting electrode 171 through the fourth opening OP4, and forms an electrical connection with the first semiconductor layer 121 through the first connecting electrode 171. The second pad electrode 192 contacts the second connecting electrode 172 through the fifth opening OP5, and forms an electrical connection with the second semiconductor layer 123 through the second connecting electrode 172. The projection of the first pad electrode 191 in the growth direction of the semiconductor stack 120 is located within the first connecting electrode 171, and the projection of the second pad electrode 192 in the growth direction of the semiconductor stack 120 is located within the second connecting electrode 172. The area of ​​the fourth opening OP4 is larger than the area of ​​the first pad electrode 191, and the area of ​​the fifth opening OP5 is larger than the area of ​​the second pad electrode 192. This structural arrangement allows the first pad electrode 191 and the second pad electrode 192 to be on the same horizontal plane, reducing the die-bonding void ratio at the LED package end and enhancing heat dissipation performance.

[0071] In another embodiment of the invention, such as Figure 3 and Figure 28 As shown, the light-emitting diode 2 includes multiple corners and multiple edges, where any corner is formed by two adjacent edges. The multiple corners include a first corner C1, a second corner C2, a third corner C3, and a fourth corner C4. The multiple edges include a first edge E1, a second edge E2, a third edge E3, and a fourth edge E4. The first edge E1 and the third edge E3 can face each other, and the second edge E2 and the fourth edge E4 can face each other. The first corner C1 is adjacent to the first edge E1 and the second edge E2; the second corner C2 is adjacent to the second edge E2 and the third edge E3; the third corner C3 is adjacent to the third edge E3 and the fourth edge E4; and the fourth corner C4 is adjacent to the fourth edge E4 and the first edge E1. Specifically, the first corner C1 and the second corner C4 are relatively close to the first pad electrode 191, and the second corner C2 and the third corner C3 are relatively close to the second pad electrode 192.

[0072] In one embodiment of the present invention, such as Figure 3 and Figure 28 As shown, the first mesa 1201 is located at the edge of the semiconductor stack 120, wherein the first mesa 1201 continuously surrounds the second semiconductor layer 123 and the active layer 122 of the semiconductor stack 120 by continuously exposing the first surface 121a of the outermost first semiconductor layer 121 of the semiconductor stack 120.

[0073] In another embodiment of the invention, the first mesa 1201 is located at the edge of the semiconductor stack 120, wherein the first mesa 1201 discontinuously exposes (i.e., at least part of the area is exposed and at least part of the area is not exposed) the first surface 121a of the outermost first semiconductor layer 121 of the semiconductor stack 120 to discontinuously surround the second semiconductor layer 123 and the active layer 122 of the semiconductor stack 120.

[0074] like Figure 3 , Figure 4 and Figure 28 As shown, the first mesa 1201 may include a first platform 1201a and a second platform 1201b continuously surrounding the semiconductor stack 120. The horizontal distance between the upper edge of the second outer wall 1200b of the first platform 1201a and the edge of the light-emitting diode (e.g., the first edge E1) is a first distance D1, and the horizontal distance between the upper edge of the second outer wall 1200b of the second platform 1201b and the edge of the light-emitting diode (e.g., the first edge E1) is a second distance D2. In one embodiment, the first distance D1 is smaller than the second distance D2, which can increase the light-emitting area of ​​the light-emitting diode and improve its brightness. The first distance D1 is 10~30μm, and the second distance is 20~40μm.

[0075] In another embodiment of the invention, the first mesa 1201 may include only the second platform 1201b to continuously surround the semiconductor stack 120, and the distance between the second platform 1201b and the edge of the light-emitting diode (e.g., the first edge E1) is the second distance D2.

[0076] In another embodiment of the invention, the first mesa 1201 may include only the second platform 1201b to discontinuously surround the semiconductor stack 120, and the distance between the second platform 1201b and the edge of the light-emitting diode (e.g., the first edge E1) is the second distance D2.

[0077] In one embodiment of the present invention, the second platform 1201b is located at the four corners of the light-emitting diode 2, such as... Figure 3 As shown, the second platform 1201b is L-shaped, comprising a first segment and a second segment. The second platform 1201b is located at the corner of the first platform 1201 closest to the light-emitting diode 2.

[0078] like Figure 17 , Figure 20 and Figure 28As shown, the fourth insulating layer 162 and the second insulating layer 161 contact and cover the first insulating layer 140, such that the first outer sidewall 1200a, the second outer sidewall 1200b, and the first surface 121a of the first mesa 1201 covered by the first insulating layer 140 are also covered by the fourth insulating layer 162 and the second insulating layer 161. The fourth insulating layer 162 and the second insulating layer 161 can protect the sidewalls of the semiconductor stack 120 and prevent the active layer 122 from being damaged by subsequent fabrication processes. The fourth insulating layer 162 and the second insulating layer 161 also include a sixth opening OP6, which is located on the first mesa 1201 of the semiconductor stack 120, exposing the first surface 121a of the first semiconductor layer. Specifically, the projection of the sixth opening OP6 in the semiconductor stack growth direction is located within the second platform 1201b, and the first connecting electrode 171 can make discontinuous contact with the first semiconductor layer 121 of the first mesa 1201 through the sixth opening OP6, thereby enhancing the current diffusion of the light-emitting diode.

[0079] In one embodiment of the present invention, such as Figure 23 , 24 As shown in Figures 2 and 25, the sidewall 171e of the first connecting electrode 171 near the edge of the light-emitting diode is located on the first mesa 1201 or the second mesa 1202. That is, the projection of the first connecting electrode 171 in the growth direction of the semiconductor stack 120 is located within the first mesa 1201 or the second mesa 1202, which can effectively reduce the risk of short circuit.

[0080] In one embodiment of the present invention, the sixth opening OP6 can also be L-shaped, comprising a first segment OP61 and a second segment OP62, wherein the first segment OP61 and the second segment OP62 are continuous structures. Since the fourth insulating layer 162 is alumina prepared by atomic layer deposition, the stress of the alumina is relatively high, and there is a risk that the alumina may detach from the first insulating layer 140 during the dicing process of the light-emitting diode, especially at the four corner edges of the light-emitting diode. Therefore, providing the sixth opening OP6 at the four corners of the light-emitting diode can release the alumina stress, thereby reducing the risk of the alumina detaching from the first insulating layer 140. Furthermore, since the sixth opening OP6 is present at the four corner edges of the light-emitting diode 2, only the third insulating layer 180 is present at the four corners of the light-emitting diode, which can reduce the silicon avalanche anomaly that occurs during the hidden dicing process of the light-emitting diode. The sixth opening OP6 located at the first corner C1 has a first segment extending along the first side E1 of the light-emitting diode and a second segment extending along the second side E2 of the light-emitting diode. The sixth opening OP6 located at the second corner C2 has its first segment extending along the second side E2 of the LED and its second segment extending along the third side E3 of the LED. The sixth opening OP6 located at the third corner C3 has its first segment extending along the third side E3 of the LED and its second segment extending along the fourth side E4 of the LED. The sixth opening OP6 located at the fourth corner C4 has its first segment extending along the fourth side E4 of the LED and its second segment extending along the first side E1 of the LED.

[0081] In one embodiment of the present invention, the area of ​​the first surface 121a of the first semiconductor layer 121 exposed by the sixth opening OP6 located at the first corner C1 or the fourth corner C4 is greater than the area of ​​the first surface 121a of the first semiconductor layer 121 exposed by the sixth opening OP6 located at the second corner C2 or the third corner C3.

[0082] In one embodiment of the present invention, such as Figure 17 As shown, the first and second segments of the sixth opening OP6 located at the second corner C2 or the third corner C3 can be equal. By increasing the length of the second segment, the contact area between the first connecting electrode 171 and the first semiconductor layer 121 can be increased, thereby enhancing current diffusion.

[0083] In one embodiment of the present invention, such as Figure 17 As shown, the first segment and the second segment of the sixth opening located at the first corner C1 or the fourth corner C4 can be unequal. By reducing the length of the second segment, the light-emitting area of ​​the LED 2 can be increased, thereby improving the brightness of the LED 2.

[0084] In one embodiment of the present invention, the sixth opening OP6 can be formed by ICP dry etching. The angle between the sidewall of the sixth opening OP6 and the first surface 120b of the first semiconductor layer 121 is a third angle. The third angle is greater than the second angle α2.

[0085] Third Embodiment

[0086] Figure 30 This is a top view of the light-emitting diode 3 disclosed in the third embodiment of the present invention. Figure 31 for Figure 30 A partially enlarged schematic diagram Figure 32 For along Figure 30 A cross-sectional view of LED 3 along line segment I-I' and Figure 33 for Figure 32 A magnified view of a portion of the image.

[0087] LED 3 has a roughly the same structure as LED 1 or LED 2, therefore for Figure 30 and Figure 31 LED 3 and Figures 1-29 LEDs 1 or 2 with the same name, designation, structure, material, or function will be omitted or further described here.

[0088] In the fabrication of LED 1 or LED 2, the third insulating layer 180 and the pad electrode undergo a two-stage photolithography process. Due to process issues such as exposure offset, the spacing between the pad electrode and the adjacent opening of the insulating layer varies, and the pad electrode may even cover the third insulating layer 180. This results in an uneven morphology for the pad electrode 190, increasing the risk of high void ratio during the LED packaging process. Furthermore, due to the two photolithography processes, factors such as the linewidth of the photomask and the lateral etching of the insulating layer mean that the spacing between the third insulating layer 180 and the pad electrode 190 is generally greater than 5 μm, thus reducing the area of ​​the pad electrode 190.

[0089] Therefore, such as Figures 30 to 33As shown, the third insulating layer 180 and the pad electrodes are fabricated using the same photolithography process to achieve self-aligned evaporation of the pad electrodes. The first pad electrode 191 has the same spacing as the adjacent fourth opening OP4, and the second pad electrode 192 has the same spacing as the adjacent fifth opening. Specifically, the first pad electrode 191 has an upper edge 191a away from the semiconductor stack 120 and a lower edge 191b close to the semiconductor stack 120, and the second pad electrode 192 has an upper edge away from the semiconductor stack 120 and a lower edge close to the semiconductor stack 120. The lower edge 191b of the first pad electrode 191 has a first maximum horizontal distance D5 with the edge of the fourth opening OP4, which is less than 5 μm. Due to errors from measuring tools, the edge of the first pad electrode 191 has a first minimum horizontal distance D6 with the edge of the fourth opening OP4, which is 50% to 150% of the first maximum horizontal distance D5. The lower edge 192b of the second pad electrode 192 and the edge of the fifth opening OP5 have a second maximum horizontal distance, which is less than 5 μm. The edge of the second pad electrode 192 and the edge of the fifth opening OP5 have a second minimum horizontal distance, which is 50% to 150% of the second maximum horizontal distance.

[0090] In one embodiment of the present invention, such as Figures 30 to 33 As shown, the surfaces of the first pad electrode 191 and the second pad electrode 192 that are away from the semiconductor stack 120 are higher than the surfaces of the third insulating layer 180 that are away from the semiconductor stack 120.

[0091] In one embodiment of the present invention, such as Figures 30 to 33 As shown, the first side E1 is relative to the first pad electrode 191, and the third side E2 is relative to the side farther from the first pad electrode 192. The first side E1 and the third side E2 are parallel. A virtual line E5 parallel to the first side E1 and the third side E3 is drawn through the midpoint between the first side E1 and the third side E3. The number of second mesa 1202 adjacent to the first side E1 is greater than the number of second mesa 1202 adjacent to the third side E3. In this way, while maximizing current extension, the area of ​​the second pad electrode 192 can be enlarged as much as possible, ensuring that the areas of the first pad electrode and the second pad electrode are equal in size and symmetrical.

[0092] In another embodiment of the present invention (not shown), the area of ​​the second surface 121b of the first semiconductor layer 121 exposed on the second mesa 1202 adjacent to the first side E1 is greater than the area of ​​the second surface 121b of the first semiconductor layer 121 exposed on the second mesa 1202 adjacent to the third side E3. The number of second mesa 1202 adjacent to the first side E1 and the number of second mesa 1202 adjacent to the third side E3 may be the same or different.

[0093] Fourth embodiment

[0094] Figure 34 This is a cross-sectional view of the light-emitting diode 4 disclosed in the fourth embodiment of the present invention.

[0095] LED 4 has a roughly the same structure as LEDs 1, 2, or 3, therefore for Figure 34 LED 4 and Figures 1-33 LEDs 1, 2, or 3 have the same name, designation, construction, structure, material, or function, which will be omitted or further described here.

[0096] like Figure 34 As shown, to increase the current spreading effect of the light-emitting diode, especially in high-current product components, a metal layer 210 is provided between the reflective electrode layer 150 and the fourth insulating layer 162. This metal layer 210 is formed on the reflective electrode layer 140, i.e., on the upper part R1 of the metal protective layer 152; and the projection of the metal layer 210 in the growth direction of the semiconductor stack 120 lies within the projection of the reflective electrode layer 140. The horizontal distance between the sidewall of the metal layer 210 and the second outer sidewall 1200b or inner sidewall 1200c of the semiconductor stack 120 is a seventh distance D7, which is greater than the fourth distance D4. The metal layer 210 can be composed of one or more highly conductive metals selected from titanium, platinum, nickel, or gold.

Claims

1. A light-emitting diode, comprising: A semiconductor stack includes a first semiconductor layer, a second semiconductor layer, and an active layer located between the first semiconductor layer and the second semiconductor layer; The first mesa is located at the edge region of the semiconductor stack, exposing the first surface of the first semiconductor layer; An insulating layer, including a portion formed on the first mesa, the insulating layer comprising a first insulating layer, a fourth insulating layer and a second insulating layer stacked sequentially, the fourth insulating layer being aluminum oxide, and the insulating layer including a sixth opening to expose the first surface of the first semiconductor layer; The projection of the sixth opening in the semiconductor stack growth direction is located at the corner of the light-emitting diode; The projection of the sixth opening in the semiconductor stack growth direction is located within the first mesa. The sixth opening includes a first segment and a second segment, which are continuous structures. The first segment extends along the first side of the light-emitting diode, and the second segment extends along the second side of the light-emitting diode. The corners include a first corner, a second corner, a third corner, and a fourth corner; the first segment and the second segment of the sixth opening located at the first corner or the fourth corner are of unequal length; the first segment and the second segment of the sixth opening located at the second corner or the third corner are of equal length.

2. The light-emitting diode according to claim 1, wherein the first insulating layer and the second insulating layer are silicon oxide, and the fourth insulating layer is aluminum oxide.

3. The light-emitting diode according to claim 1, wherein the thickness of the fourth insulating layer is 20~150nm, and the thickness of the second insulating layer is greater than that of the fourth insulating layer.

4. The light-emitting diode according to claim 1 further includes a first pad electrode and a second pad electrode, wherein the first pad electrode is electrically connected to the first semiconductor layer, the second pad electrode is electrically connected to the second semiconductor layer, and the light-emitting diode has four corners, wherein the corners relatively close to the first pad electrode are the first corner and the fourth corner, and the corners relatively far from the first pad electrode are the second corner and the third corner.

5. The light-emitting diode according to claim 4, wherein the area of ​​the first semiconductor layer exposed by the sixth opening located at the first corner or the fourth corner is smaller than the area of ​​the first semiconductor layer exposed by the sixth opening located at the second corner or the third corner.

6. The light-emitting diode according to claim 1, wherein the first platform includes a first platform and a second platform, the horizontal distance between the inner edge of the first platform and the edge of the light-emitting diode is a first distance, the horizontal distance between the inner edge of the second platform and the edge of the light-emitting diode is a second distance, and the first distance is less than the second distance.

7. The light-emitting diode according to claim 6, wherein the first distance is 10~30μm and the second distance is 20~40μm.

8. The light-emitting diode according to claim 6, wherein the second platform is L-shaped.

9. The light-emitting diode according to claim 6, wherein the projection of the sixth opening in the semiconductor stack growth direction is located within the second platform.

10. The light-emitting diode according to claim 6, wherein the light-emitting diode has four corners, and the second platform is located at least at one corner of the light-emitting diode.

11. The light-emitting diode according to claim 1, further comprising a reflective electrode layer formed on the semiconductor stack, the first insulating layer located between the semiconductor stack and the reflective electrode layer, the fourth insulating layer formed on the reflective electrode layer, and the second insulating layer formed on the fourth insulating layer.

12. The light-emitting diode according to claim 11, wherein the horizontal distance between the edge of the reflective electrode layer and the edge of the second semiconductor layer is less than 1~5μm.

13. The light-emitting diode according to claim 11, further comprising a transparent conductive layer formed on the semiconductor stack, the transparent conductive layer being located between the second semiconductor layer and the first insulating layer, and the projection of the transparent conductive layer in the growth direction of the semiconductor stack being located within the projection of the reflective electrode layer in the growth direction of the semiconductor stack.

14. The light-emitting diode of claim 11, further comprising a second mesa located inside the semiconductor stack and exposing a second surface of the first semiconductor layer, the insulating layer including a portion formed on the second mesa, the insulating layer including a second opening exposing a second surface of the first semiconductor layer, and the fourth insulating layer and the second insulating layer located on the reflective electrode layer having a third opening exposing a portion of the surface of the reflective electrode layer.

15. The light-emitting diode according to claim 14, further comprising a first connection electrode and a second connection electrode formed on the second insulating layer, wherein the first connection electrode is electrically connected to the first semiconductor layer through the second opening, and the second connection electrode is electrically connected to the first semiconductor layer through the third opening.

16. The light-emitting diode according to claim 14, wherein a third angle is formed between the sixth opening and the first surface of the first semiconductor layer, and a second angle is formed between the third opening and the surface of the reflective electrode layer, wherein the third angle is greater than the second angle.

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