An inductance current detection circuit applied to a buck converter

Abstract

The application relates to an inductance current detection circuit applied to a buck converter, which comprises a right-side NMOS sampling tube circuit arranged at a power ground node PGND connected with the source of an LS lower NMOS power tube in the buck converter, a left-side NMOS sampling tube circuit arranged at a drain node sw of the LS lower NMOS power tube, a balance voltage circuit established between a left-side NMOS sampling tube source node VA and a right-side NMOS sampling tube source node VB, and a detection current circuit for making the detection current flow into the node VA, so that a linear relationship between the detection current and the inductance current can be established, the inductance current flowing through the lower tube in the on stage can be detected in real time, and various complex functions and application requirements of the buck converter, such as current limiting, can be met.

Description

Technical Field

[0001] This invention relates to inductor current detection technology in Buck converters, and in particular to an inductor current detection circuit applied in Buck converters. It utilizes a right-side NMOS sampling transistor circuit connected to the power ground node PGND of the lower NMOS power transistor (LS) in the Buck converter, and a left-side NMOS sampling transistor circuit connected to the drain node sw of the lower NMOS power transistor (LS). A balanced voltage circuit is established between the source nodes VA and VB of the left and right NMOS sampling transistors, ensuring VA = VB. This balanced voltage circuit includes a detection current circuit that allows the detection current to flow into node VA. This establishes a linear relationship between the detection current and the inductor current, facilitating real-time detection of the inductor current flowing during the conduction phase of the lower transistor, thereby meeting the complex functional and application requirements of Buck converters, such as current limiting. Background Technology

[0002] Buck converters are ubiquitous in daily life, widely used in smartphones, home appliances, automotive electronics, and industrial equipment. With societal and technological advancements, the demand for buck converters has increased significantly, directly driving their rapid development. Early buck converters could achieve maximum output currents of several hundred milliamperes, gradually progressing to several amperes, tens of amperes, and even hundreds or thousands of amperes in multiphase power supplies. As the maximum output current increases dramatically, buck converters need to monitor inductor current in real time to achieve various complex functions and application requirements, such as current limiting. Figure 2 and Figure 3 The basic topology and basic operating waveforms of the buck converter are shown respectively. When the HS signal is high, the upper power transistor is turned on, and the inductor current I... L Ramp-up; when the LS signal is high, the lower power transistor is turned on, and the inductor current I... L A downward slope. For example... Figure 2 As shown, the buck converter includes an NMOS power transistor on the HS and an NMOS power transistor on the LS. The drain of the NMOS power transistor on the HS is connected to the input voltage terminal Vin, and the gate is connected to the upper control signal HS (see...). Figure 3 The source and drain of the NMOS power transistor under LS are interconnected to form node sw. Node sw is connected to the output voltage terminal Vout through inductor L. Vout is connected to power ground PGND through an output capacitor and another through a load. The source of the NMOS power transistor under LS is connected to power ground PGND, and the gate is connected to the control signal LS (see the HS waveform). Figure 3 (LS waveform in the image), the inductor current IL flows to Vout (see...) Figure 3In the IL waveform, when the LS signal is high, the NMOS power transistor below LS is turned on, and the NMOS power transistor above HS is turned off. The sloping IL is the on-state current of the NMOS power transistor below LS, and IL flows from PGND to sw. Summary of the Invention

[0003] This invention addresses the deficiencies or shortcomings of existing technologies by providing an inductor current detection circuit for Buck converters. It utilizes a right-side NMOS sampling transistor circuit connected to the power ground node PGND of the lower NMOS power transistor (LS) in the Buck converter, and a left-side NMOS sampling transistor circuit connected to the drain node sw of the lower NMOS power transistor (LS). A balanced voltage circuit is established between the source nodes VA and VB of the left and right NMOS sampling transistors, ensuring VA = VB. This balanced voltage circuit includes a current detection circuit that allows the detection current to flow into node VA. This establishes a linear relationship between the detection current and the inductor current, facilitating real-time detection of the inductor current flowing during the lower transistor's conduction phase. This satisfies the complex functional and application requirements of Buck converters, such as current limiting.

[0004] The technical solution of the present invention is as follows:

[0005] An inductor current detection circuit applied in a buck converter is characterized by comprising a right-side NMOS sampling transistor circuit connected to the power ground node PGND of the NMOS power transistor at the lower LS in the buck converter, and a left-side NMOS sampling transistor circuit connected to the drain node sw of the NMOS power transistor at the lower LS. A balancing voltage circuit is established between the source node VA of the left-side NMOS sampling transistor and the source node VB of the right-side NMOS sampling transistor to ensure that VA = VB. The balancing voltage circuit includes a detection current circuit that allows the detection current to flow into node VA. Let the detection current be I. sense The inductor current flowing through the NMOS power transistor under LS is IL, and the on-resistance of the NMOS power transistor under LS is R. dsonL The on-resistance of both the left and right NMOS sampling transistors is R. sense , then I sense =(R dsonL / R sense )*IL.

[0006] The right-side NMOS sampling transistor circuit includes a right-side NMOS sampling transistor and a second NMOS transistor M2. The drain of M2 is connected to the source of the right-side NMOS sampling transistor, and the source of M2 is grounded. The gate of M2 is connected to the lower control signal LS through an inverter. The drain of the right-side NMOS sampling transistor is connected to the power ground node PGND. The left-side NMOS sampling transistor circuit includes a left-side NMOS sampling transistor and a first NMOS transistor M1. The drain of M1 is connected to the source of the left-side NMOS sampling transistor, and the source of M1 is grounded. The gate of M1 is connected to the lower control signal LS through an inverter. The drain of the left-side NMOS sampling transistor is connected to the drain node sw of the NMOS power transistor under LS. The gates of the NMOS power transistor under LS, the left-side NMOS sampling transistor, and the right-side NMOS sampling transistor are all connected to the lower control signal LS.

[0007] The balanced voltage circuit includes a third NPN transistor Q3 and a fourth NPN transistor Q4. The emitter of Q3 is connected to node VA and the emitter of the first NPN transistor Q1, respectively. The emitter of Q4 is connected to node VB and the emitter of the second NPN transistor Q2, respectively. The collectors of Q1 and Q2, as well as the bases of Q1, Q2, Q3, and Q4, are all connected to the power supply voltage terminal VDD through a current source. The collector of Q3 is connected to the source of the seventh NMOS transistor, and the collector of Q4 is connected to the source of the eighth NMOS transistor. The gates of the seventh and eighth NMOS transistors are both connected to a bias voltage Vb. The drain of the seventh NMOS transistor is interconnected with the drain of the third PMOS transistor M3, and the drain of the eighth NMOS transistor is interconnected with the drain of the fourth PMOS transistor M4. The gate-drain interconnection of M4 is then connected to the gate of M3. The sources of both M3 and M4 are connected to the power supply voltage terminal VDD.

[0008] Q1, Q2, Q3 and Q4 are all BJT bipolar junction transistors.

[0009] The current detection circuit includes a fifth PMOS transistor M5 and a sixth PMOS transistor M6. The drain of M5 is connected to node VA via a resistor. The gates of M5 and M6 are interconnected and then connected to the drain of M3. The sources of both M5 and M6 are connected to the power supply voltage terminal VDD. The drain of M6 is M*I. sense Outflow terminal, M is a positive integer, and the drain of M5 is I. sense outflow end.

[0010] Assuming the current source current is 2*Ib, when there is a difference between the currents flowing through Q1 and Q2, this current difference, after being amplified by X times by the Q1-Q3 pair and the Q2-Q4 pair, manifests as the drain voltage V at transistor M3. G The voltage drops rapidly, where X is an integer greater than or equal to 1, thus causing the source-gate voltage V of transistor M5 to decrease rapidly. SG5 Greater than its threshold voltage V TH5 The absolute value of the detected current I senseIt begins to build up and flow into node VA, thereby raising the voltage V. A With voltage V A As the voltage rises, the base-emitter voltages of Q1 and Q2 will gradually reach equilibrium, and the current flowing through both Q1 and Q2 will be equal to Ib. At equilibrium, the voltage V... A Equal to voltage V B .

[0011] V A =[(1+X)*Ib+I sense ]*R sense +sw

[0012] V B = (1+X)*Ib*R sense +PGND

[0013] sw = PGND - IL * R dsonL

[0014] V A =V B

[0015] I can be obtained by solving the above formula. sense =(R dsonL / R sense )*IL.

[0016] The buck converter includes an NMOS power transistor on HS and an NMOS power transistor on LS. The drain of the NMOS power transistor on HS is connected to the input voltage terminal Vin, and the gate is connected to the upper control signal HS. The source is interconnected with the drain of the NMOS power transistor on LS to form a node sw. The node sw is connected to the output voltage terminal Vout through an inductor L. Vout is connected to power ground PGND through an output capacitor and to power ground PGND through a load. The source of the NMOS power transistor on LS is connected to power ground PGND, and the gate is connected to the lower control signal LS. The inductor current IL flows to Vout.

[0017] The technical effects of this invention are as follows: This invention provides an inductor current detection circuit applied in a buck converter. Utilizing a negative feedback mechanism, it can accurately detect the inductor current flowing through the lower transistor during its conduction phase, and can detect the inductor current I when the LS signal is high. L Real-time detection. Detection current I sense and inductor current I L Proportional, with a proportionality constant of R dsonL / R sense This is a fixed value. By selecting the same type of sampling transistor and low-power transistor, the proportionality coefficient can be made less sensitive to process drift and temperature changes, thus achieving high-precision inductor current detection. The obtained detection current I senseAfter linear copying using the current mirror formed by transistors M5 and M6, complex functions such as current limiting can be implemented. When the LS signal is low, the lower transistor is turned off, and the inductor current is not detected. Switching transistors M1 and M2 are turned on, maintaining V... A and V B The voltages are equal, therefore the current I is detected. sense It is zero. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of an inductor current detection circuit applied in a buck converter, which embodies the present invention. A buck converter is a step-down converter.

[0019] Figure 2 This is a basic topology diagram of a Buck converter.

[0020] Figure 3 This is a schematic diagram of the basic operating waveforms of a Buck converter.

[0021] The reference numerals in the attached diagram are listed below: VDD - Power supply terminal; PGND - Power ground terminal; Vin - Input voltage terminal; Vout - Output voltage terminal; Cout - Output capacitor; L - Inductor; I - Inductor; L - Inductor current; HS - Upper power transistor or upper control signal; LS - Lower power transistor or lower control signal; sw, VA, VB, VG - Node or node voltage (lower transistor drain voltage sw, left sampling transistor source voltage VA, right sampling transistor source voltage VB, lower transistor drain voltage VG); Vb - Bias voltage; R dsonL - The on-resistance of the lower transistor; R sense - Sampling tube on-resistance; 1:M- Amplification ratio (M is a positive integer, M*I) sense (Amplifying the detection current by M times); 1:X - Amplification ratio (X is an integer greater than or equal to 1, amplifying the current difference by X times); 2*Ib - Current source; I sense - Detect current; M1~M2-First NMOS transistor to second NMOS transistor; M3~M6-Third PMOS transistor to sixth PMOS transistor; Q1~Q4-First NPN transistor to fourth NPN transistor (can be BJT transistor or MOSFET transistor, BJT, Bipolar Junction Transistor, MOSFET, Metal Oxide Semiconductor Field Effect Transistor). Detailed Implementation

[0022] The following is in conjunction with the attached diagram ( Figures 1-3 The invention will be described in the following sections and examples.

[0023] Figure 1 This is a schematic diagram of an inductor current detection circuit applied in a buck converter, which embodies the present invention. A buck converter is a step-down converter. Figure 2 This is a basic topology diagram of a Buck converter. Figure 3 This is a schematic diagram of the basic operating waveforms of a Buck converter. (Reference) Figures 1 to 3 As shown, an inductor current detection circuit applied in a buck converter is characterized by including a right-side NMOS sampling transistor circuit connected to the power ground node PGND of the NMOS power transistor under the LS in the buck converter, and a left-side NMOS sampling transistor circuit connected to the drain node sw of the NMOS power transistor under the LS. A balancing voltage circuit is established between the source node VA of the left-side NMOS sampling transistor and the source node VB of the right-side NMOS sampling transistor to make VA = VB. The balancing voltage circuit includes a detection current circuit that allows the detection current to flow into node VA. Let the detection current be I. sense The inductor current flowing through the NMOS power transistor under LS is IL, and the on-resistance of the NMOS power transistor under LS is R. dsonL The on-resistance of both the left and right NMOS sampling transistors is R. sense , then I sense =(R dsonL / R sense )*IL.

[0024] The right-side NMOS sampling transistor circuit includes a right-side NMOS sampling transistor and a second NMOS transistor M2. The drain of M2 is connected to the source of the right-side NMOS sampling transistor, and the source of M2 is grounded. The gate of M2 is connected to the lower control signal LS through an inverter. The drain of the right-side NMOS sampling transistor is connected to the power ground node PGND. The left-side NMOS sampling transistor circuit includes a left-side NMOS sampling transistor and a first NMOS transistor M1. The drain of M1 is connected to the source of the left-side NMOS sampling transistor, and the source of M1 is grounded. The gate of M1 is connected to the lower control signal LS through an inverter. The drain of the left-side NMOS sampling transistor is connected to the drain node sw of the NMOS power transistor under LS. The gates of the NMOS power transistor under LS, the left-side NMOS sampling transistor, and the right-side NMOS sampling transistor are all connected to the lower control signal LS. The balanced voltage circuit includes a third NPN transistor Q3 and a fourth NPN transistor Q4. The emitter of Q3 is connected to node VA and the emitter of the first NPN transistor Q1, respectively. The emitter of Q4 is connected to node VB and the emitter of the second NPN transistor Q2, respectively. The collectors of Q1 and Q2, as well as the bases of Q1, Q2, Q3, and Q4, are all connected to the power supply voltage VDD through current sources. The collector of Q3 is connected to the source of the seventh NMOS transistor, and the collector of Q4 is connected to the source of the eighth NMOS transistor. The gates of both the seventh and eighth NMOS transistors are biased by a voltage Vb. The seventh NMOS transistor is interconnected with the drain of the third PMOS transistor M3, and the eighth NMOS transistor is interconnected with the drain of the fourth PMOS transistor M4. The gate-drain interconnect of M4 is then connected to the gate of M3. The sources of both M3 and M4 are connected to the power supply voltage VDD. Q1, Q2, Q3, and Q4 are all BJT (bipolar junction transistors).

[0025] The current detection circuit includes a fifth PMOS transistor M5 and a sixth PMOS transistor M6. The drain of M5 is connected to node VA through a resistor. The gates of M5 and M6 are interconnected and then connected to the drain of M3. The sources of both M5 and M6 are connected to the power supply voltage terminal VDD. The drain of M6 is M*I. sense Outflow terminal, M is a positive integer, and the drain of M5 is I. sense Outflow terminal. Assume the current source current is 2*Ib. When there is a difference in the current flowing through Q1 and Q2, this current difference, after being amplified by X times by the Q1-Q3 pair and the Q2-Q4 pair, manifests as the voltage V at the drain of transistor M3. G The voltage drops rapidly, where X is an integer greater than or equal to 1, thus causing the source-gate voltage V of transistor M5 to decrease rapidly. SG5 Greater than its threshold voltage V TH5 The absolute value of the detected current I sense It begins to build up and flow into node VA, thereby raising the voltage V. A With voltage V AAs the voltage rises, the base-emitter voltages of Q1 and Q2 will gradually reach equilibrium, and the current flowing through both Q1 and Q2 will be equal to Ib. At equilibrium, the voltage V... A Equal to voltage V B .

[0026] V A =[(1+X)*Ib+I sense ]*R sense +sw;V B = (1+X)*Ib*R sense +PGND; sw = PGND - IL*R dsonL V A =V B Solving for I using the above formula yields... sense =(R dsonL / R sense )*IL.

[0027] The buck converter includes an NMOS power transistor on the upper HS and an NMOS power transistor on the lower LS. The drain of the NMOS power transistor on the upper HS is connected to the input voltage terminal Vin, and the gate is connected to the upper control signal HS (see above). Figure 3 The source of the NMOS power transistor under LS is interconnected with the drain of the transistor to form a node sw. The node sw is connected to the output voltage terminal Vout through an inductor L. One path of Vout is connected to the power ground PGND through the output capacitor, and the other path is connected to the power ground PGND through the load. The source of the NMOS power transistor under LS is connected to the power ground PGND, and the gate is connected to the control signal LS (see the HS waveform). Figure 3 (LS waveform in the image), the inductor current IL flows to Vout.

[0028] This invention proposes an inductor current detection circuit for use in buck converters. Utilizing a negative feedback mechanism, it can accurately detect the inductor current flowing through the lower transistor during its conduction phase. The schematic diagram is shown below. Figure 1 As shown. Figure 2 and Figure 3 The basic topology and basic operating waveforms of the buck converter are shown respectively. When the HS signal is high, the upper power transistor is turned on, and the inductor current I... L Ramp-up; when the LS signal is high, the lower power transistor is turned on, and the inductor current I... L The slope is sloping down. The inductor current detection circuit proposed in this patent can detect the inductor current I when the LS signal is high. L Real-time detection. The specific working principle of the inductor current detection circuit is as follows:

[0029] During the conduction phase of the lower transistor, the inductor current I LThe current flows from the source of the lower transistor (i.e., the PGND node) to the drain of the lower transistor (i.e., the SW node). Due to the on-resistance R of the lower transistor... dsonL Inductor current I L Flow through resistor R dsonL This results in a forward voltage drop, therefore the voltage at node SW is...

[0030] SW = PGND - I L *B daonL

[0031] The two sampling transistors used for sampling at the SW node and PGND node are of the same size and have good matching on the layout. This ensures that the on-resistance of the two sampling transistors is equal, both being R. sense At the moment the lower transistor just turns on, both sampling transistors also turn on simultaneously. Because the voltage at the sw node is lower than the voltage at the PGND node, the source voltage V of the left sampling transistor... A It will be less than the source voltage V of the sampling transistor on the right. B This causes the base-emitter voltage V of the BJT transistor Q1 to... BE1 The base-emitter voltage V of the BJT transistor Q2 is greater than BE2 Therefore, a current greater than Ib will flow through transistor Q1, and a current less than Ib will flow through transistor Q2. This means there is a difference in the current flowing through transistors Q1 and Q2. This current difference, amplified by X times by the transistor pair of Q1 and Q3 and the transistor pair of Q2 and Q4, manifests as the drain voltage V of transistor M3. G The voltage drops rapidly, causing the source-gate voltage V of transistor M5 to decrease rapidly. SG5 Greater than its threshold voltage V TH5 The absolute value of the detected current I sense It begins to build up and flow into the source node of the left sampling tube, thereby raising the voltage V. A With voltage V A As the voltage rises, the base-emitter voltages of transistors Q1 and Q2 will gradually reach equilibrium. The current flowing through both transistors Q1 and Q2 will be equal to Ib (ignoring the base current of the BJT). At equilibrium, the voltage V... A Equal to voltage V B According to voltage V A Equal to voltage V B The detection current I can be calculated. sense .

[0032] Write down the voltage V A and voltage V B The formula is:

[0033] V A =[(1+X)*I b +I sense ]*B sense +sw

[0034] V B = (1+X)*I b *B sense +PGND

[0035] By making the two equations equal and combining them with the voltage formula at node sw, the detection current I can be derived. sense for

[0036]

[0037] From the above formula, it can be seen that the detection current I sense and inductor current I L Proportional, with a proportionality constant of R dsonL / R sebse This is a fixed value. By selecting the same type of sampling transistor and low-power transistor, the proportionality coefficient can be made less sensitive to process drift and temperature changes, thus achieving high-precision inductor current detection. The obtained detection current I sense After linear copying using a current mirror composed of M5 and M6 transistors, complex functions such as current limiting can be implemented.

[0038] When the LS signal is low, the lower transistor is turned off, and the inductor current is not detected. Switches M1 and M2 are turned on, maintaining V. A and V B The voltages are equal, therefore the current I is detected. sense It is zero. It is worth noting that... Figure 1 The design employs a pair of Q1 and Q3 BJT transistors and a pair of Q2 and Q4 BJT transistors. Similarly, a pair of MOS transistors can be used to achieve the same effect.

[0039] Contents not described in detail in this specification are prior art known to those skilled in the art. It is hereby indicated that the above description is intended to help those skilled in the art understand this invention, but does not limit the scope of protection of this invention. Any equivalent substitutions, modifications, improvements, and / or simplifications of the above descriptions that do not depart from the essential content of this invention fall within the scope of protection of this invention.

Claims

1. An inductor current detection circuit applied in a buck converter, characterized in that, The circuit includes a right-side NMOS sampling transistor circuit connected to the power ground node PGND, which is connected to the source of the NMOS power transistor in the LS converter, and a left-side NMOS sampling transistor circuit connected to the drain node sw of the NMOS power transistor in the LS converter. A balancing voltage circuit is established between the source node VA of the left-side NMOS sampling transistor and the source node VB of the right-side NMOS sampling transistor, ensuring that VA = VB. This balancing voltage circuit includes a current detection circuit that allows a detection current to flow into node VA. Let the detection current be I. sense The inductor current flowing through the NMOS power transistor under LS is IL, and the on-resistance of the NMOS power transistor under LS is R. dsonL The on-resistance of both the left and right NMOS sampling transistors is R. sense , then I sense =(R dsonL / R sense ) IL; The right-side NMOS sampling transistor circuit includes a right-side NMOS sampling transistor and a second NMOS transistor M2. The drain of M2 is connected to the source of the right-side NMOS sampling transistor, and the source of M2 is grounded. The gate of M2 is connected to the lower control signal LS through an inverter. The drain of the right-side NMOS sampling transistor is connected to the power ground node PGND. The left-side NMOS sampling transistor circuit includes a left-side NMOS sampling transistor and a first NMOS transistor M1. The drain of M1 is connected to the source of the left-side NMOS sampling transistor, and the source of M1 is grounded. The gate of M1 is connected to the lower control signal LS through an inverter. The drain of the left-side NMOS sampling transistor is connected to the drain node sw of the NMOS power transistor below LS. The gates of the NMOS power transistor below LS, the left-side NMOS sampling transistor, and the right-side NMOS sampling transistor are all connected to the lower control signal LS. The balanced voltage circuit includes a third NPN transistor Q3 and a fourth NPN transistor Q4. The emitter of Q3 is connected to node VA and the emitter of the first NPN transistor Q1, respectively. The emitter of Q4 is connected to node VB and the emitter of the second NPN transistor Q2, respectively. The collectors of Q1 and Q2, as well as the bases of Q1, Q2, Q3, and Q4, are all connected to the power supply voltage terminal VDD through a current source. The collector of Q3 is connected to the source of the seventh NMOS transistor, and the collector of Q4 is connected to the source of the eighth NMOS transistor. The gates of the seventh and eighth NMOS transistors are both connected to a bias voltage Vb. The drain of the seventh NMOS transistor is interconnected with the drain of the third PMOS transistor M3, and the drain of the eighth NMOS transistor is interconnected with the drain of the fourth PMOS transistor M4. The gate-drain interconnection of M4 is then connected to the gate of M3. The sources of M3 and M4 are both connected to the power supply voltage terminal VDD. Let the current of the current source be 2. Ib, when there is a difference in the current flowing through Q1 and Q2, this difference, after being amplified by X times by the Q1-Q3 pair and the Q2-Q4 pair, manifests as the drain voltage V at transistor M3. G The voltage drops rapidly, where X is an integer greater than or equal to 1, thus causing the source-gate voltage V of transistor M5 to decrease rapidly. SG5 Greater than its threshold voltage V TH5 The absolute value of the detected current I sense It begins to build up and flow into node VA, thereby raising the voltage V. A With voltage V A As the voltage rises, the base-emitter voltages of Q1 and Q2 will gradually reach equilibrium, and the current flowing through both Q1 and Q2 will be equal to Ib. At equilibrium, the voltage V... A Equal to voltage V B .

2. The inductor current detection circuit applied in a Buck converter according to claim 1, characterized in that, Q1, Q2, Q3 and Q4 are all BJT bipolar junction transistors.

3. The inductor current detection circuit applied in a Buck converter according to claim 1, characterized in that, The current detection circuit includes a fifth PMOS transistor M5 and a sixth PMOS transistor M6. The drain of M5 is connected to node VA via a resistor. The gates of M5 and M6 are interconnected and then connected to the drain of M3. The sources of both M5 and M6 are connected to the power supply voltage terminal VDD. The drain of M6 is M3. I sense Outflow terminal, M is a positive integer, and the drain of M5 is I. sense outflow end.

4. The inductor current detection circuit applied in a Buck converter according to claim 1, characterized in that, V A =[(1+X) Ib+I sense ] R sense +Vsw V B =(1+X) Ib R sense +VPGND Vsw= VPGND-IL R dsonL V A = V B Where Vsw is the voltage at node sw, and VPGND is the voltage at node PGND, I can be obtained by solving the above formula. sense =(R dsonL / R sense ) IL.

5. The inductor current detection circuit applied in a Buck converter according to claim 1, characterized in that, The buck converter includes an NMOS power transistor on HS and an NMOS power transistor on LS. The drain of the NMOS power transistor on HS is connected to the input voltage terminal Vin, and the gate is connected to the upper control signal HS. The source is interconnected with the drain of the NMOS power transistor on LS to form a node sw. The node sw is connected to the output voltage terminal Vout through an inductor L. Vout is connected to power ground PGND through an output capacitor and to power ground PGND through a load. The source of the NMOS power transistor on LS is connected to power ground PGND, and the gate is connected to the lower control signal LS. The inductor current IL flows to Vout.

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