A two and a half decimal divider

Abstract

The application provides a two-point-five fractional divider, comprising a frequency division module; the frequency division module comprises a first CML latch, a second CML latch, a third CML latch, a fourth CML latch, a fifth CML latch, a sixth CML latch and a logic gate; the logic gate is an AND gate, or the logic gate is an OR gate. The two-point-five fractional divider provided by the embodiment of the application does not need to set a delay unit and a digital calibration circuit, can effectively reduce the influence of power supply voltage and temperature change, has strong robustness to power supply voltage and temperature change, and has high stability; the frequency division module is mainly constructed by a CML circuit, has simple structure, low cost, and can work at a high frequency.

Description

Technical Field

[0001] This invention relates to the field of frequency divider technology, and more specifically, to a 2.5 fractional frequency divider. Background Technology

[0002] A fractional frequency divider is a circuit that divides a clock signal by a fractional factor. By dividing a higher-frequency signal, the desired lower-frequency signal can be obtained. Current fractional frequency dividers generally require delay units, but due to the mismatch between delay units in digital fractional frequency dividers, many inherent spurious signals are generated. Therefore, digital fractional frequency dividers also require additional digital calibration circuitry to eliminate these spurious signals.

[0003] The delay unit used in digital fractional frequency dividers is easily affected by variations in process technology, power supply voltage, and temperature (PVT), resulting in poor stability during operation. Adding calibration circuitry cannot effectively solve this problem and will also increase costs. Summary of the Invention

[0004] To address the aforementioned problems, the objective of this invention is to provide a 2.5 fractional frequency divider that does not require a delay unit.

[0005] This invention provides a 2.5 fractional frequency divider, comprising: a frequency divider module; the frequency divider module includes: a first CML latch, a second CML latch, a third CML latch, a fourth CML latch, a fifth CML latch, a sixth CML latch, and logic gates; the logic gates are AND gates, or OR gates.

[0006] The positive and negative output terminals of the first CML latch are respectively connected to the positive and negative input terminals of the second CML latch; the positive and negative output terminals of the second CML latch are respectively connected to the positive and negative input terminals of the third CML latch.

[0007] The positive and negative output terminals of the fourth CML latch are respectively connected to the positive and negative input terminals of the fifth CML latch; the positive and negative output terminals of the fifth CML latch are respectively connected to the positive and negative input terminals of the sixth CML latch.

[0008] The positive and negative output terminals of the third CML latch are respectively connected to the first negative and first positive input terminals of the logic gate; the positive and negative output terminals of the sixth CML latch are respectively connected to the second negative and second positive input terminals of the logic gate.

[0009] The positive output terminal of the logic gate is connected to the positive input terminal of the first CML latch and the positive input terminal of the fourth CML latch, and the negative output terminal of the logic gate is connected to the negative input terminal of the first CML latch and the negative input terminal of the fourth CML latch.

[0010] The positive clock signal terminals of the first CML latch, the third CML latch, and the fifth CML latch are all used to receive positive clock signals, and the negative clock signal terminals are all used to receive negative clock signals.

[0011] The positive clock signal terminals of the second, fourth, and sixth CML latches are all used to connect to the negative clock signal, and the negative clock signal terminals are all used to connect to the positive clock signal; the positive clock signal and the negative clock signal are at the same frequency as the differential signal to be divided.

[0012] The positive output terminal of the logic gate has a corresponding logical relationship with the first positive input terminal and the second positive input terminal of the logic gate. The positive output terminal and the negative output terminal of the logic gate are used to output the differential signal after frequency division.

[0013] In one possible implementation, the frequency division module further includes: a first CML buffer;

[0014] The positive and negative output terminals of the logic gate are also connected to the positive and negative input terminals of the first CML buffer, respectively; the positive and negative output terminals of the first CML buffer are used to output the frequency-divided differential signal.

[0015] In one possible implementation, the frequency division module further includes: a second CML buffer;

[0016] The positive and negative output terminals of the second CML buffer are used to connect the differential signal to be divided.

[0017] The positive output terminal of the second CML buffer is used to output the positive clock signal, and the negative output terminal of the second CML buffer is used to output the negative clock signal.

[0018] In one possible implementation, the 2.5 fractional frequency divider also includes a correction module;

[0019] The correction module is connected to the output of the frequency divider module and is used to correct the duty cycle of the frequency-divided differential signal output by the frequency divider module to 50%.

[0020] In one possible implementation, the correction module includes: a duty cycle detection circuit and a duty cycle adjustment circuit;

[0021] The input terminal of the duty cycle detection circuit is connected to the output terminal of the correction module, and the output terminal of the duty cycle detection circuit is connected to the duty cycle adjustment circuit. The duty cycle detection circuit is used to generate a corresponding control signal based on the duty cycle of the input signal and transmit the control signal to the duty cycle adjustment circuit. The control signal has a monotonic relationship with the degree of deviation of the duty cycle of the input signal from 50% duty cycle.

[0022] The input terminal of the duty cycle adjustment circuit is connected to the output terminal of the frequency divider module, and the output terminal of the duty cycle adjustment circuit is connected to the output terminal of the correction module. The duty cycle adjustment circuit is used to adjust the frequency-divided differential signal output by the frequency divider module according to the control signal, and adjust the duty cycle of the frequency-divided differential signal to 50%.

[0023] In one possible implementation, the output terminal of the duty cycle detection circuit includes a positive output terminal and a negative output terminal. The positive output terminal of the duty cycle detection circuit is used to output a positive control signal, and the negative output terminal of the duty cycle detection circuit is used to output a negative control signal. Both the positive control signal and the negative control signal are voltage signals, and the difference between the positive control signal and the negative control signal has a monotonic relationship with the degree of deviation of the duty cycle of the input signal from 50%.

[0024] The duty cycle adjustment circuit includes a first MOSFET, a second MOSFET, and a CML buffer body circuit; one of the CML buffer body circuits for outputting a positive signal has a first pull-up resistor, and the other of the CML buffer body circuits for outputting a negative signal has a second pull-up resistor.

[0025] The source and drain of the first MOSFET are respectively connected to the two ends of the first pull-up resistor, and the source and drain of the second MOSFET are respectively connected to the two ends of the second pull-up resistor.

[0026] The gate of the first MOS transistor is connected to the positive output terminal of the duty cycle detection circuit, and the gate of the second MOS transistor is connected to the negative output terminal of the duty cycle detection circuit; the first MOS transistor and the second MOS transistor operate in the linear region.

[0027] In one possible implementation, the correction module further includes: a third CML buffer;

[0028] The positive input terminal of the third CML buffer is connected to the positive output terminal of the CML buffer body circuit used for outputting positive signals; the negative input terminal of the third CML buffer is connected to the negative output terminal of the CML buffer body circuit used for outputting negative signals.

[0029] The output of the third CML buffer is the output of the correction module.

[0030] In one possible implementation, the 2.5 fractional frequency divider also includes: an orthogonal module;

[0031] The input terminal of the quadrature module is connected to the output terminal of the correction module, and is used to convert the differential signal output by the correction module into two quadrature signals.

[0032] In one possible implementation, the orthogonal module includes a two-stage resistor-capacitor multiphase filter.

[0033] In one possible implementation, the 2.5 fractional divider further includes: a CML buffer group, which includes one CML buffer or multiple CML buffers connected in series.

[0034] The input of the CML buffer group is connected to the output of the quadrature module, and is used to adjust the swing of the two quadrature signals to be the same.

[0035] In the solution provided by this invention, six CML latches and one logic gate are used to divide the original clock signal by a division factor of 2.5. The output of the logic gate can output the divided signal, thus achieving a 2.5 division. This 2.5 fractional divider does not require a delay unit or digital calibration circuit, effectively reducing the impact of power supply voltage and temperature changes. It has strong robustness to power supply voltage and temperature changes and high stability. This divider module is mainly constructed from CML circuits, has a simple structure, low cost, and can operate at relatively high frequencies.

[0036] The correction module can correct the signal's duty cycle to 50%. Using this signal as a carrier input to the mixer increases the mixer's output gain, thus improving the transmitter's transmission efficiency when applied to a transmitter. Duty cycle adjustment can be easily achieved by using a MOSFET operating in the linear region as a voltage-controlled resistor and adjusting the values ​​of the two pull-up resistors in the CML buffer circuit. Furthermore, with the help of the quadrature module, this 2.5 fractional divider can output two quadrature signals with equal swing and a 90-degree phase difference. These two quadrature signals can be directly used by the RF transmitter for modulation of the transmitted signal.

[0037] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This shows a first structural schematic diagram of the 2.5 fractional frequency divider provided in an embodiment of the present invention;

[0040] Figure 2 A timing diagram of a 2.5 fractional frequency divider provided in an embodiment of the present invention is shown;

[0041] Figure 3 Another timing diagram of the 2.5 fractional frequency divider provided in an embodiment of the present invention is shown;

[0042] Figure 4 This diagram illustrates a structural schematic of the frequency division module in the 2.5 fractional frequency divider provided in an embodiment of the present invention.

[0043] Figure 5 This shows a second structural schematic diagram of the 2.5 fractional frequency divider provided in an embodiment of the present invention;

[0044] Figure 6 This invention provides a schematic diagram of the duty cycle adjustment circuit in a 2.5 fractional frequency divider.

[0045] Figure 7 This diagram shows a third structural schematic of the 2.5 fractional frequency divider provided in an embodiment of the present invention;

[0046] Figure 8 This diagram illustrates a structural schematic of the orthogonal module in the 2.5 fractional frequency divider provided in an embodiment of the present invention.

[0047] Explanation of reference numerals in the attached figures:

[0048] 10. Frequency divider module; 101. First CML latch; 102. Second CML latch; 103. Third CML latch; 104. Fourth CML latch; 105. Fifth CML latch; 106. Sixth CML latch; 107. Logic gate; 108. First CML buffer; 109. Second CML buffer; 20. Correction module; 201. Duty cycle detection circuit; 202. Duty cycle adjustment circuit; Q1. First MOSFET; Q2. Second MOSFET; R1. First pull-up resistor; R2. Second pull-up resistor; 203. Third CML buffer; 30. Quadrature module. Detailed Implementation

[0049] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0050] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0051] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0052] This invention provides a 2.5 fractional-time divider, capable of performing 2.5 fractional-time division; for example, dividing a 50MHz input signal into a 20MHz signal. See also... Figure 1 As shown, the 2.5 fractional frequency divider includes a frequency divider module 10; the frequency divider module 10 includes a first CML latch 101, a second CML latch 102, a third CML latch 103, a fourth CML latch 104, a fifth CML latch 105, a sixth CML latch 106, and a logic gate 107. In this embodiment of the invention, six CML (Current Mode Logic) latches and one logic gate (AND gate, OR gate, OR gate) are used to achieve a 2.5 frequency divider; and the frequency divider module 10 is mainly composed of current-mode logic circuits, and its operating frequency can reach up to 8GHz. The CML latch itself is prior art; for ease of description, this embodiment of the invention will first provide a brief description of the CML latch.

[0053] like Figure 1As shown, the CML latch has clock signal terminals for inputting differential clock signals, namely the positive clock signal terminal CKP and the negative clock signal terminal CKN. Under the action of different differential clock signals, the CML latch performs different functions. Furthermore, the CML latch also has two input terminals for inputting differential signals, namely the positive input terminal DP and the negative input terminal DN, and two output terminals that can output corresponding differential signals, namely the positive output terminal QP and the negative output terminal QN. Specifically, if the signal at the positive clock signal terminal CKP is positive (correspondingly, the signal at the negative clock signal terminal CKN is negative), the input and output of the CML latch are the same, i.e., QP = DP; if the signal at the positive clock signal terminal CKP is negative, the CML latch is in a latched state, and its output remains unchanged, i.e., regardless of what signal DP is, QP always remains unchanged. The negative input terminal DN of the CML latch has the opposite signal to the positive input terminal DP (one positive and one negative, or one high and one low), and the negative output terminal QN has the opposite signal to the negative output terminal QP. The following embodiments of the present invention mainly describe the specific situation of the positive input terminal and the positive output terminal. In particular, to facilitate the differentiation of the various ports of the six CML latches, the present invention adds different serial numbers to the various ports of the six CML latches. For example, the positive input terminal of the first CML latch 101 is DP1.

[0054] like Figure 1 As shown, the positive output terminal QP1 and the negative output terminal QN1 of the first CML latch 101 are connected to the positive input terminal DP2 and the negative input terminal DN2 of the second CML latch 102, respectively; the positive output terminal QP2 and the negative output terminal QN2 of the second CML latch 102 are connected to the positive input terminal DP3 and the negative input terminal DN3 of the third CML latch 103, respectively.

[0055] The positive output terminal QP4 and the negative output terminal QN4 of the fourth CML latch 104 are connected to the positive input terminal DP5 and the negative input terminal DN5 of the fifth CML latch 105, respectively; the positive output terminal QP5 and the negative output terminal QN5 of the fifth CML latch 105 are connected to the positive input terminal DP6 and the negative input terminal DN6 of the sixth CML latch 106, respectively.

[0056] The positive output terminal QP3 and the negative output terminal QN3 of the third CML latch 103 are respectively connected to the first negative input terminal AN and the first positive input terminal AP of the logic gate 107; the positive output terminal QP6 and the negative output terminal QN6 of the sixth CML latch 106 are respectively connected to the second negative input terminal BN and the second positive input terminal BP of the logic gate 107.

[0057] The positive output terminal QP of logic gate 107 is connected to the positive input terminal DP1 of the first CML latch 101 and the positive input terminal DP4 of the fourth CML latch 104. The negative output terminal QN of logic gate 107 is connected to the negative input terminal DN1 of the first CML latch 101 and the negative input terminal DN4 of the fourth CML latch 104.

[0058] The positive clock signal terminals (CKP1, CKP3, CKP5) of the first CML latch 101, the third CML latch 103, and the fifth CML latch 105 are all used to connect to the positive clock signal CK+, and the negative clock signal terminals (CKN1, CKN3, CKN5) are all used to connect to the negative clock signal CK-. Conversely, the positive clock signal terminals (CKP2, CKP4, CKP6) of the second CML latch 102, the fourth CML latch 104, and the sixth CML latch 106 are all used to connect to the negative clock signal CK-, and the negative clock signal terminals (CKN2, CKN4, CKN6) are all used to connect to the positive clock signal CK+; these positive clock signals CK+ and CK- are at the same frequency as the differential signal to be divided. All six CML latches are connected to the same clock signal, only the connection method of the positive and negative terminals is different.

[0059] The positive output terminal QP of logic gate 107 has a corresponding logical relationship with the first positive input terminal AP and the second positive input terminal BP of logic gate 107. The positive output terminal QP and the negative output terminal QN of logic gate 107 are used to output the frequency-divided differential signal. That is, if logic gate 107 is an AND gate, then its positive output terminal QP has an AND logical relationship with AP and BP; if logic gate 107 is an OR gate, then its positive output terminal QP has an OR logical relationship with AP and BP.

[0060] In this embodiment of the invention, the first CML latch 101, the second CML latch 102, and the third CML latch 103 are connected in sequence and connected to one input terminal of the logic gate 107 (first negative input terminal AN, first positive input terminal AP); the fourth CML latch 104, the fifth CML latch 105, and the sixth CML latch 106 are connected in sequence and connected to the other input terminal of the logic gate 107 (second negative input terminal BN, second positive input terminal BP). The differential signal to be divided can be used as the clock signal for the six CML latches. The positive and negative signals connected to the clock signal terminals of different CML latches are different, and, as shown... Figure 1 As shown, the positive and negative signals connected to the three upper CML latches are exactly opposite to those connected to the three lower CML latches. The differential signal to be divided is used as a clock signal and sent to the six CML latches respectively, so that the time delays of the CML latches are different and no other delay unit is needed.

[0061] Based on the frequency division module 10 provided in this embodiment of the invention, after the logic gate 107 performs a logic judgment, the frequency of the differential signal (i.e. the frequency-divided differential signal) output by it is 1 / 2.5 of the frequency of the differential signal to be divided, thereby realizing the 2.5-point frequency division of the differential signal to be divided.

[0062] Specifically, the differential signal to be divided is represented by a square wave signal. When logic gate 107 is an AND gate, a timing diagram of the frequency divider module 10 can be found here. Figure 2 As shown, Figure 2 In the second row, QP represents the positive output terminal QP of the AND gate. The working principle of this frequency divider module 10 is as follows:

[0063] When the positive clock signal CK+ is low, the first CML latch 101, the third CML latch 103, and the fifth CML latch 105 are in "latch state", and their outputs QP1, QP3, and QP5 remain unchanged.

[0064] When the positive clock signal CK+ is high, the second CML latch 102, the fourth CML latch 104, and the sixth CML latch 106 are in "latch state", and their outputs QP2, QP4, and QP6 remain unchanged.

[0065] Furthermore, the output QP of the AND gate (i.e., logic gate 107) = AP & BP; QP is only high when both AP and BP are high. For example... Figure 1 As shown, since AP = QN3 and BP = QN6, QP is high when both QP3 and QP6 are low. For example, this AND gate can be a CML AND gate, which is an existing mature technology that can achieve the function required by logic gate 107 in this embodiment of the invention. The specific structure of the CML AND gate will not be described in detail here.

[0066] Initially, the output of the CML latch in the frequency divider module 10, which is in a latched state, is unknown. In this embodiment of the invention, it is assumed that the positive clock signal CK+ is low at the initial moment, meaning that QP1, QP3, and QP5 may be in various states. This embodiment of the invention will be illustrated using the example where QP1, QP3, and QP5 are all low. Figure 2 As shown, each cycle of the positive clock signal CK+ is divided into two time periods, forming time periods T1, T2, T3, etc.

[0067] In T1: Assume that QP1, QP3, and QP5 are all low level; QP2 = QP1, which is low level; QP6 = QP5, which is low level; AP is high level, BP is high level, so the positive output terminal QP (hereinafter referred to as QP in this embodiment) of the AND gate (i.e., logic gate 107) is high level; QP4 = QP, which is high level.

[0068] At T2: the second CML latch 102, the fourth CML latch 104, and the sixth CML latch 106 are in "latch state", QP2 is still low, QP4 is still high, and QP6 is still low; QP3 = QP2, which is low; QP5 = QP4, which is high; AP is high, BP is high, and QP is high; QP1 = QP, which is high.

[0069] At T3: QP1 remains high, QP3 remains low, and QP5 remains high; QP2 = QP1, which is high; QP6 = QP5, which is high; AP is high, BP is low, so QP is low; QP4 = QP, which is low.

[0070] At T4: QP2 remains high, QP4 remains low, and QP6 remains high; QP3 = QP2, which is high; QP5 = QP4, which is low; AP is low, BP is low, and QP is low; QP1 = QP, which is low.

[0071] At T5: QP1 remains low, QP3 remains high, and QP5 remains low; QP2 = QP1, which is low; QP6 = QP5, which is low; AP is low, BP is high, so QP is low; QP4 = QP, which is low.

[0072] At T6: QP2 remains low, QP4 remains low, and QP6 remains low; QP3 = QP2, which is low; QP5 = QP4, which is low; AP is high, BP is high, and QP is high; QP1 = QP, which is high.

[0073] At T7: QP1 remains high, QP3 remains low, and QP5 remains low; QP2 = QP1, which is high; QP6 = QP5, which is low; AP is high, BP is high, so QP is high; QP4 = QP, which is high.

[0074] At T8: QP2 remains high, QP4 remains high, and QP6 remains low; QP3 = QP2, which is high; QP5 = QP4, which is high; AP is low, BP is high, and QP is low; QP1 = QP, which is low.

[0075] At T9: QP1 remains low, QP3 remains high, and QP5 remains high; QP2 = QP1, which is low; QP6 = QP5, which is high; AP is low, BP is low, therefore QP is low; QP4 = QP, which is low.

[0076] At T10: QP2 remains low, QP4 remains low, and QP6 remains high; QP3 = QP2, which is low; QP5 = QP4, which is low; AP is high, BP is low, and QP is low; QP1 = QP, which is low.

[0077] At time T11: QP1 is still low, QP3 is still low, and QP5 is still low. At this time, the same as in time period T1, QP2 = QP1, which is low; QP6 = QP5, which is low; AP is high, BP is high, so QP is high; QP4 = QP, which is high.

[0078] Therefore, the frequency divider module 10 can be configured according to... Figure 2 The methods corresponding to T1-T10 work cyclically; and, as Figure 2 As shown, compared with the original positive clock signal CK+, the period of the signal output by the positive output terminal QP of the AND gate is 2.5 times that of CK+, and correspondingly, its frequency is 1 / 2.5 of the original signal, thus achieving a 2.5 frequency division.

[0079] Furthermore, assuming that at the initial moment, QP1, QP3, and QP5 are in other states than those involved in T1-T10 above, such as QP1, QP3, and QP5 being low level, low level, and high level respectively, the frequency divider module 10 can also enter the above-mentioned cyclic operation process after a period of time.

[0080] For example, at the initial moment, CK+ is low (simply referred to as "low"; correspondingly, high level can be simply referred to as "high"). If the initial values ​​of QP1, QP3, and QP5 are low, low, and high respectively; QP2 = QP1, low; QP6 = QP5, high; and QP4 = QP, low. In the next time interval, QP2, QP4, and QP6 remain low, low, and high respectively; QP3 = QP2, low; QP5 = QP4, low; and QP1 = QP, low. In the next time interval, QP1, QP3, and QP5 are low, low, and low respectively, the same as the T1 time interval mentioned above, and the cycle continues as described above.

[0081] In addition, if CK+ is high at the initial moment, the second CML latch 102, the fourth CML latch 104, and the sixth CML latch 106 are in "latch state". Setting different initial values ​​for QP2, QP4, and QP6 can also enter the above loop, which will not be described in detail here.

[0082] Alternatively, if logic gate 107 is an OR gate, then the output QP of the OR gate (i.e., logic gate 107) = AP||BP. As long as either AP or BP is high, then QP is high. For example... Figure 1As shown, since AP = QN3 and BP = QN6, QP is high if either QP3 or QP6 is low. For example, the OR gate can be a CML OR gate, which is an existing mature technology that can achieve the function required by logic gate 107 in this embodiment of the invention. The specific structure of the CML OR gate will not be described in detail here.

[0083] When logic gate 107 is an OR gate, a timing diagram of the frequency divider module 10 can be found here. Figure 3 As shown, Figure 3 In the second row, QP represents the positive output terminal QP of the OR gate. The working principle of this frequency divider module 10 is as follows:

[0084] In T1: Assume that QP1, QP3, and QP5 are all low level; QP2 = QP1, which is low level; QP6 = QP5, which is low level; AP is high level, BP is high level, so the positive output terminal QP (hereinafter referred to as QP in this embodiment) of the OR gate (logic gate 107) is high level; QP4 = QP, which is high level.

[0085] At T2: the second CML latch 102, the fourth CML latch 104, and the sixth CML latch 106 are in "latch state", QP2 is still low, QP4 is still high, and QP6 is still low; QP3 = QP2, which is low; QP5 = QP4, which is high; AP is high, BP is high, and QP is high; QP1 = QP, which is high.

[0086] At T3: QP1 remains high, QP3 remains low, and QP5 remains high; QP2 = QP1, which is high; QP6 = QP5, which is high; AP is high, BP is low, so QP is high; QP4 = QP, which is high.

[0087] At T4: QP2 remains high, QP4 remains high, and QP6 remains high; QP3 = QP2, which is high; QP5 = QP4, which is high; AP is low, BP is low, and QP is low; QP1 = QP, which is low.

[0088] At T5: QP1 remains low, QP3 remains high, and QP5 remains high; QP2 = QP1, which is low; QP6 = QP5, which is high; AP is low, BP is low, therefore QP is low; QP4 = QP, which is low.

[0089] At T6: QP2 remains low, QP4 remains low, and QP6 remains high; QP3 = QP2, which is low; QP5 = QP4, which is low; AP is high, BP is low, and QP is high; QP1 = QP, which is high.

[0090] At T7: QP1 remains high, QP3 remains low, and QP5 remains low; QP2 = QP1, which is high; QP6 = QP5, which is low; AP is high, BP is high, so QP is high; QP4 = QP, which is high.

[0091] At T8: QP2 remains high, QP4 remains high, and QP6 remains low; QP3 = QP2, which is high; QP5 = QP4, which is high; AP is low, BP is high, and QP is high; QP1 = QP, which is high.

[0092] At T9: QP1 remains high, QP3 remains high, and QP5 remains high; QP2 = QP1, which is high; QP6 = QP5, which is high; AP is low, BP is low, therefore QP is low; QP4 = QP, which is low.

[0093] At T10: QP2 remains high, QP4 remains low, and QP6 remains high; QP3 = QP2, which is high; QP5 = QP4, which is low; AP is low, BP is low, and QP is low; QP1 = QP, which is low.

[0094] At T11: QP1 remains low, QP3 remains high, and QP5 remains low; QP2 = QP1, which is low; QP6 = QP5, which is low; AP is low, BP is high, so QP is high; QP4 = QP, which is high.

[0095] At T12: QP2 remains low, QP4 remains high, and QP6 remains low; QP3 = QP2, which is low; QP5 = QP4, which is high; AP is high, BP is high, and QP is high; QP1 = QP, which is high.

[0096] In time T13: QP1 remains high, QP3 remains low, and QP5 remains high; similar to time T3, QP2 = QP1, which is high; QP6 = QP5, which is high; AP is high, BP is low, so QP is high; QP4 = QP, which is high.

[0097] Therefore, the frequency divider module 10 can be configured according to... Figure 3 The methods corresponding to T3-T12 work in a cyclical manner; and, as Figure 3 As shown, compared with the original positive clock signal CK+, the period of the signal output by the positive output terminal QP of the AND gate is 2.5 times that of CK+, and correspondingly, its frequency is 1 / 2.5 of the original signal, thus achieving a 2.5 frequency division.

[0098] Other initial conditions can also enter the loops corresponding to T3-T12 mentioned above, which will not be described in detail in this embodiment.

[0099] This invention provides a 2.5 fractional frequency divider that utilizes six CML latches and one logic gate to divide the original clock signal by a 2.5 division factor. The output of the logic gate can output the divided signal, thus achieving 2.5 frequency division. This 2.5 fractional frequency divider does not require a delay unit or digital calibration circuit, effectively reducing the impact of power supply voltage and temperature changes. It exhibits strong robustness to power supply voltage and temperature variations and high stability. Furthermore, the frequency divider module 10 is mainly constructed from CML circuits, resulting in a simple structure, low cost, and the ability to operate at relatively high frequencies.

[0100] Optionally, see Figure 4 As shown, the frequency divider module 10 further includes: a first CML buffer 108; the positive output terminal QP and the negative output terminal QN of the logic gate 107 are also connected to the positive input terminal IP and the negative input terminal IN of the first CML buffer 108, respectively; the positive output terminal OP and the negative output terminal ON of the first CML buffer 108 are used to output the frequency-divided differential signal. In this embodiment of the invention, the signal output by the logic gate 107 is buffered after passing through the first CML buffer 108 before being output, which can achieve buffering and has better load capacity.

[0101] Optionally, the clock signal terminals (CKP, CKN) of the CML latch can be directly connected to the differential signal to be divided; or, as... Figure 4 As shown, the frequency divider module 10 further includes: a second CML buffer 109; the positive output terminal IP and the negative output terminal IN of the second CML buffer 109 are used to input the differential signal to be divided; the positive output terminal OP of the second CML buffer 109 is used to output a positive clock signal, and the negative output terminal ON of the second CML buffer 109 is used to output a negative clock signal.

[0102] In this embodiment of the invention, the differential signal to be divided is buffered by the second CML buffer 109 and then connected to the six CML latches, which can provide a more stable clock signal for the six CML latches.

[0103] Among them, the CML buffer (such as the first CML buffer 108 and the second CML buffer 109 mentioned above) is an existing mature technology, and its structure and working principle will not be described in detail here.

[0104] Optionally, such as Figure 2 and Figure 3 As shown, the differential signal output by the frequency divider module 10 has a duty cycle that is not 50%; for example, as Figure 2 As shown, if logic gate 107 is an AND gate, the duty cycle of the differential signal output by frequency divider module 10 is 40%; if logic gate 107 is an OR gate, the duty cycle of the differential signal output by frequency divider module 10 is 60%. In scenarios where the duty cycle requirement is not high (such as phase-locked loops), the differential signal output by frequency divider module 10 can be used directly. In some scenarios, a differential signal with a 50% duty cycle is required. In this case, see [reference needed]. Figure 5 As shown, the 2.5 fractional frequency divider also includes: a correction module 20; as Figure 5 As shown, the correction module 20 is connected to the output terminal of the frequency divider module 10 and is used to correct the duty cycle of the frequency-divided differential signal output by the frequency divider module 10 to 50%.

[0105] In this embodiment of the invention, the correction module 20 can correct the duty cycle of the input signal (i.e., the differential signal after frequency division output by the frequency division module 10). The correction module 20 outputs a differential signal with a duty cycle of 50 without changing the signal frequency.

[0106] Optionally, such as Figure 5 As shown, the correction module 20 includes a duty cycle detection circuit 201 and a duty cycle adjustment circuit 202. The input terminal of the duty cycle detection circuit 201 is connected to the output terminal of the correction module 20, and the output terminal of the duty cycle detection circuit 201 is connected to the duty cycle adjustment circuit 202. The duty cycle detection circuit 201 generates a corresponding control signal based on the duty cycle of the input signal (i.e., the signal output by the output terminal of the correction module 20) and transmits the control signal to the duty cycle adjustment circuit 202. The control signal has a monotonic relationship with the degree of deviation of the duty cycle of the input signal from a 50% duty cycle.

[0107] The input terminal of the duty cycle adjustment circuit 202 is connected to the output terminal of the frequency divider module, and the output terminal of the duty cycle adjustment circuit 202 is connected to the output terminal of the correction module 20 (that is, the output terminal of the duty cycle adjustment circuit 202 can be used as the output terminal of the correction module 20); the duty cycle adjustment circuit 202 is used to adjust the frequency-divided differential signal output by the frequency divider module according to the control signal, and adjust the duty cycle of the frequency-divided differential signal to 50%.

[0108] In this embodiment of the invention, the correction module 20 is a feedback circuit. The duty cycle detection circuit 201 detects the duty cycle of the signal output by the output terminal of the correction module 20. Based on the degree of deviation of the duty cycle from 50% (for example, the difference between the duty cycle and 50%), it generates a corresponding control signal and sends the control signal to the duty cycle adjustment circuit 202. The signal input to the duty cycle adjustment circuit 202 is the differential signal after frequency division output by the frequency division module 10. It adjusts the duty cycle of the differential signal after frequency division according to the control signal, adjusts the duty cycle of the differential signal after frequency division to 50%, and outputs it. Finally, the correction module 20 can correct the duty cycle of the differential signal and output a differential signal with a duty cycle of 50%. The corrected differential signal is also a 2.5 frequency division signal.

[0109] The control signal and the input signal have a monotonic relationship regarding the degree of deviation of the duty cycle from 50%, which can be linear or non-linear. Generally, the greater the difference between the duty cycle of the input signal and 50%, the larger the control signal output by the duty cycle detection circuit 201; for example, if the control signal is a voltage signal, the larger its voltage value.

[0110] Optionally, such as Figure 5 As shown, the output terminals of the duty cycle detection circuit 201 include a positive output terminal OP and a negative output terminal ON. The positive output terminal OP of the duty cycle detection circuit 201 is used to output a positive control signal Ctrl. P The negative output terminal ON of the duty cycle detection circuit 201 is used to output the negative control signal Ctrl. N Positive control signal Ctrl P With negative control signal Ctrl N Both are voltage signals, and the positive control signal Ctrl is... P With negative control signal Ctrl N The difference between the two values ​​has a monotonic relationship with the degree of deviation of the input signal's duty cycle from 50% duty cycle.

[0111] And see also Figure 6 As shown, the duty cycle adjustment circuit 202 includes a first MOSFET Q1, a second MOSFET Q2, and a CML buffer body circuit. One path of the CML buffer body circuit for outputting a positive signal has a first pull-up resistor R1, and the other path for outputting a negative signal has a second pull-up resistor R2. The source and drain of the first MOSFET Q1 are connected to the two ends of the first pull-up resistor R1, and the source and drain of the second MOSFET Q2 are connected to the two ends of the second pull-up resistor R2. The gate of the first MOSFET Q1 is connected to the positive output terminal OP of the duty cycle detection circuit 201 to receive the positive control signal Ctrl. PThe gate of the second MOSFET Q2 is connected to the negative output terminal ON of the duty cycle detection circuit 201 to receive the negative control signal Ctrl. N Furthermore, both the first MOSFET Q1 and the second MOSFET Q2 operate in the linear region.

[0112] In this embodiment of the invention, the duty cycle detection circuit 201 is used to output a differential control signal, namely, a positive control signal Ctrl. P and negative control signal Ctrl N Furthermore, the control signal is a voltage signal. In addition, the duty cycle adjustment circuit 202 is an improved CML buffer. The duty cycle adjustment circuit 202 is equipped with a MOSFET (field-effect transistor) operating in the linear region (also known as the variable resistance region). The resistance value of the MOSFET is controlled by a voltage-type control signal, thereby changing the duty cycle of the output signal.

[0113] The duty cycle adjustment circuit 202 is a CML buffer that includes a variable resistive load. Compared to a regular CML buffer, the duty cycle adjustment circuit 202, in addition to the differential input IP / IN signal and the differential output OP / ON signal, also includes a differential input control signal Ctrl. P / Ctrl N It is used to control the resistance value of the voltage-controlled resistor (i.e., MOSFET), so that the size of the pull-up resistor of the CML buffer can be directly adjusted by the voltage, thereby controlling the settling time of the rise and fall of the CML buffer output, and thus changing the duty cycle.

[0114] For example, Figure 6 The circuitry excluding the first and second MOSFETs constitutes the CML buffer body circuit. Figure 6 The CML buffer body circuit is the basic circuit of the CML buffer. The input terminals (positive input terminal IP, negative input terminal IN) of the CML buffer receive differential signals, and the output terminals (positive output terminal OP, negative output terminal ON) output differential signals of the same frequency; and, as... Figure 6 As shown, the path for outputting a positive signal (i.e., the path where the positive output terminal OP is located) has a pull-up resistor, which is referred to as the first pull-up resistor R1 in this embodiment; the path for outputting a negative signal (i.e., the path where the negative output terminal ON is located) also has a pull-up resistor, which is referred to as the second pull-up resistor R2 in this embodiment. Based on the main circuit of this CML buffer, a MOSFET is connected in parallel with each of the two pull-up resistors, that is, the source and drain of the first MOSFET Q1 are connected to the two ends of the first pull-up resistor R1, and the source and drain of the second MOSFET Q2 are connected to the two ends of the second pull-up resistor R2. Both the first MOSFET Q1 and the second MOSFET Q2 operate in the linear region, utilizing the control signal (i.e., the positive control signal Ctrl) input to the gate. Pand negative control signal Ctrl N This allows the voltage to change the resistance value of the entire pull-up resistor.

[0115] Specifically, with Figure 6 Taking the structure shown as an example, both the first MOSFET Q1 and the second MOSFET Q2 are PMOS transistors, with their sources connected to VDD and their drains connected to the other end of the pull-up resistor. The gate voltage of this PMOS transistor is a suitable value, allowing it to operate in the linear region. The higher the gate voltage of the PMOS transistor, the lower its gate-source voltage Vgs, and the greater the monotonic resistance of the PMOS transistor operating in the linear region. Therefore, the positive control signal Ctrl... P The larger the value, the larger the resistance of the first MOSFET Q1, which increases the rise and fall setup time of the positive output terminal OP of the CML buffer circuit used to output positive signals, thereby changing the duty cycle.

[0116] Among them, the positive control signal Ctrl P With negative control signal Ctrl N The difference between the two values ​​has a monotonic relationship with the degree to which the duty cycle of the input signal deviates from 50%. For example, increasing Ctrl... P -Ctrl N When this occurs, the load on the pull-up resistors (including the first pull-up resistor R1 and the first MOSFET Q1) at the OP terminal of the CML buffer body circuit increases, while the load on the pull-up resistors (including the second pull-up resistor R2 and the second MOSFET Q2) at the ON terminal decreases. This slows down the setup time at the OP terminal and speeds up the setup time at the ON terminal, ultimately reducing the duty cycle of the signal output by the duty cycle adjustment circuit 202, for example, from 60% to 50%.

[0117] In this embodiment of the invention, the duty cycle detection circuit 201 can be an integrating circuit, such as an integrator with a gm-C structure, which gradually adjusts the output differential control signal Ctrl by integration. P Ctrl N Ultimately, this results in the two control signals Ctrl being... P Ctrl N Under its influence, the pull-up resistors at the OP and ON terminals of the CML buffer circuit meet the requirements, enabling it to output a differential signal with a 50% duty cycle.

[0118] Optionally, see Figure 5As shown, the correction module 20 further includes: a third CML buffer 203; the positive input terminal IP of the third CML buffer 203 is connected to the positive output terminal of the CML buffer body circuit used for outputting positive signals; the negative input terminal IN of the third CML buffer 203 is connected to the negative output terminal of the CML buffer body circuit used for outputting negative signals; the output terminal of the third CML buffer 203 is the output terminal of the correction module 20.

[0119] As described above, the duty cycle adjustment circuit 202 in the correction module 20 is essentially a CML buffer, due to the control signal Ctrl. P Ctrl N Changing the pull-up resistor of the CML buffer causes a change in its output DC operating point. In this embodiment of the invention, a third CML buffer 203 is added to the correction module 20. The input of the third CML buffer 203 is connected to the output of the CML buffer main circuit, and it is equivalent to the next-level buffer in the CML buffer main circuit. The DC operating point can be restored using the third CML buffer 203. In this case, the correction module 20 can output a differential signal with a duty cycle of 50% and a normal DC operating point.

[0120] In IoT RF transmitters, both power amplifiers (PAs) and frequency synthesizers are integrated. However, this integration severely degrades the performance of voltage-controlled oscillators (VCOs). Several methods have been proposed to address the frequency pulling and spurious emissions caused by the PA affecting the VCO. Using a digital fractional divider to divide the frequency synthesizer output by a fractional number ensures that the PA's fundamental frequency and its harmonics are not integer multiples of the VCO's operating frequency, thus significantly mitigating the frequency pulling problem caused by the PA. The 2.5 fractional divider provided in this invention can be applied to RF transmitters to effectively suppress the frequency pulling problem caused by the PA on the VCO.

[0121] Furthermore, the mixer can achieve its maximum gain when the input carrier duty cycle is 50%. The 2.5 fractional divider provided in this embodiment of the invention has a 50% duty cycle for the signal output by the correction module 20. By using this signal as a carrier input to the mixer, the data to be transmitted by the radio frequency transmitter can be modulated, thereby increasing the output gain of the mixer and improving the transmission efficiency of the transmitter.

[0122] Optionally, to facilitate coherent modulation and data transmission by the transmitter, see [reference needed]. Figure 7 As shown, the 2.5 fractional frequency divider also includes: an orthogonal module 30; the input of the orthogonal module 30 is connected to the output of the correction module 20, and is used to convert the differential signal output by the correction module 20 into two orthogonal signals.

[0123] In embodiments of the present invention, such as Figure 7 As shown, the differential signal to be divided is input to the frequency divider module 10. The frequency divider module 10 can output the divided differential signal, and the frequency of the divided differential signal is one-two-fifth of the frequency of the differential signal to be divided. Furthermore, the duty cycle of the divided differential signal is 40% or 60%. After the duty cycle is corrected by the correction module 20, a differential signal with a 50% duty cycle can be output, and this differential signal is input to the quadrature module 30. The quadrature module 30 can generate and output two quadrature signals with the same frequency as the input signal based on the input signal. These two quadrature signals can be directly used by the RF transmitter for coherent modulation of the transmitted signal.

[0124] Optionally, see Figure 8 As shown, the quadrature module 30 includes a two-stage resistor-capacitor multiphase filter. In this embodiment of the invention, the two-stage resistor-capacitor multiphase filter (RC polyphase filter) can generate two quadrature signals with a 90-degree phase difference and the same output frequency as the input signal, based on the input signal. The duty cycle of the signal output by the correction module 20 is 50%, therefore the phase orthogonality of the output by the quadrature module 30 will not deteriorate due to a duty cycle other than 50%, thus ensuring the orthogonality quality of the quadrature signals.

[0125] Specifically, such as Figure 8 As shown, VP and VN are the inputs of the quadrature module 30, IP and IN are the I-channel differential outputs of the quadrature signal, and QP and QN are the Q-channel differential outputs of the quadrature signal. The phase difference between the two signals is 90 degrees, and they are orthogonal, so two quadrature signals can be output. These quadrature signals are voltage signals.

[0126] Alternatively, due to Figure 8 Due to the characteristics of the circuit structure shown, the swings of the two quadrature signals are not equal. This embodiment of the invention utilizes the swing adjustment feature of the CML buffer to adjust the swings of the two quadrature signals (i.e., the I-path and the Q-path) to be the same. Specifically, the 2.5 fractional divider further includes a CML buffer group, which may include one CML buffer or multiple CML buffers connected in series. The input of the CML buffer group is connected to the output of the quadrature module 30 to adjust the swings of the two quadrature signals to be the same. For example, the CML buffer group is a three-stage series CML buffer structure.

[0127] The quadrature module 30 has two outputs, allowing the swing of one output to be adjusted to match that of the other. Alternatively, the swings of both outputs can be adjusted. In this case, a CML buffer group can be set for each output, with one CML buffer group adjusting the swing of the I-channel and the other adjusting the swing of the Q-channel. Ultimately, the output swings of the I-channel and Q-channel signals are made the same (restoring to full swing). After adjustment by the CML buffer group, two quadrature signals with equal swings and a 90-degree phase difference can be output. This 2.5 fractional frequency divider is a 2.5 fractional frequency divider with quadrature output function.

[0128] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A 2.5 fractional frequency divider, characterized in that, include: Frequency divider module (10); The frequency division module (10) includes: a first CML latch (101), a second CML latch (102), a third CML latch (103), a fourth CML latch (104), a fifth CML latch (105), a sixth CML latch (106), and a logic gate (107); the logic gate (107) is an AND gate, or the logic gate (107) is an OR gate; The positive and negative output terminals of the first CML latch (101) are respectively connected to the positive and negative input terminals of the second CML latch (102); the positive and negative output terminals of the second CML latch (102) are respectively connected to the positive and negative input terminals of the third CML latch (103). The positive and negative output terminals of the fourth CML latch (104) are respectively connected to the positive and negative input terminals of the fifth CML latch (105); the positive and negative output terminals of the fifth CML latch (105) are respectively connected to the positive and negative input terminals of the sixth CML latch (106). The positive and negative output terminals of the third CML latch (103) are respectively connected to the first negative input terminal and the first positive input terminal of the logic gate (107); the positive and negative output terminals of the sixth CML latch (106) are respectively connected to the second negative input terminal and the second positive input terminal of the logic gate (107); The positive output terminal of the logic gate (107) is connected to the positive input terminal of the first CML latch (101) and the positive input terminal of the fourth CML latch (104), and the negative output terminal of the logic gate (107) is connected to the negative input terminal of the first CML latch (101) and the negative input terminal of the fourth CML latch (104). The positive clock signal terminals of the first CML latch (101), the third CML latch (103), and the fifth CML latch (105) are all used to receive positive clock signals, and the negative clock signal terminals are all used to receive negative clock signals. The positive clock signal terminals of the second CML latch (102), the fourth CML latch (104), and the sixth CML latch (106) are all used to connect to the negative clock signal, and the negative clock signal terminals are all used to connect to the positive clock signal; the positive clock signal and the negative clock signal are at the same frequency as the differential signal to be divided. The positive output terminal of the logic gate (107) has a corresponding logical relationship with the first positive input terminal and the second positive input terminal of the logic gate (107). The positive output terminal and the negative output terminal of the logic gate (107) are used to output the differential signal after frequency division.

2. The 2.5 fractional frequency divider according to claim 1, characterized in that, The frequency division module (10) further includes: a first CML buffer (108); The positive and negative output terminals of the logic gate (107) are also connected to the positive and negative input terminals of the first CML buffer (108), respectively; the positive and negative output terminals of the first CML buffer (108) are used to output the frequency-divided differential signal.

3. The 2.5 fractional frequency divider according to claim 1, characterized in that, The frequency division module (10) further includes: a second CML buffer (109); The positive and negative output terminals of the second CML buffer (109) are used to connect the differential signal to be divided. The positive output terminal of the second CML buffer (109) is used to output the positive clock signal, and the negative output terminal of the second CML buffer (109) is used to output the negative clock signal.

4. The 2.5 fractional frequency divider according to claim 1, characterized in that, Also includes: Correction module (20); The correction module (20) is connected to the output terminal of the frequency divider module (10) and is used to correct the duty cycle of the frequency-divided differential signal output by the frequency divider module (10) to 50%.

5. The 2.5 fractional frequency divider according to claim 4, characterized in that, The correction module (20) includes: a duty cycle detection circuit (201) and a duty cycle adjustment circuit (202); The input terminal of the duty cycle detection circuit (201) is connected to the output terminal of the correction module (20), and the output terminal of the duty cycle detection circuit (201) is connected to the duty cycle adjustment circuit (202). The duty cycle detection circuit (201) is used to generate a corresponding control signal according to the duty cycle of the input signal and transmit the control signal to the duty cycle adjustment circuit (202). The control signal has a monotonic relationship with the degree of deviation of the duty cycle of the input signal from 50% duty cycle. The input terminal of the duty cycle adjustment circuit (202) is connected to the output terminal of the frequency divider module, and the output terminal of the duty cycle adjustment circuit (202) is connected to the output terminal of the correction module (20). The duty cycle adjustment circuit (202) is used to adjust the frequency-divided differential signal output by the frequency divider module according to the control signal, and adjust the duty cycle of the frequency-divided differential signal to 50%.

6. The 2.5 fractional frequency divider according to claim 5, characterized in that, The output terminals of the duty cycle detection circuit (201) include a positive output terminal and a negative output terminal. The positive output terminal of the duty cycle detection circuit (201) is used to output a positive control signal, and the negative output terminal of the duty cycle detection circuit (201) is used to output a negative control signal. Both the positive control signal and the negative control signal are voltage signals, and the difference between the positive control signal and the negative control signal has a monotonic relationship with the degree of deviation of the duty cycle of the input signal from 50% duty cycle. The duty cycle adjustment circuit (202) includes a first MOS transistor (Q1), a second MOS transistor (Q2), and a CML buffer body circuit; one of the CML buffer body circuits for outputting a positive signal has a first pull-up resistor (R1), and one of the CML buffer body circuits for outputting a negative signal has a second pull-up resistor (R2). The source and drain of the first MOSFET (Q1) are connected to the two ends of the first pull-up resistor (R1), and the source and drain of the second MOSFET (Q2) are connected to the two ends of the second pull-up resistor (R2). The gate of the first MOS transistor (Q1) is connected to the positive output terminal of the duty cycle detection circuit (201), and the gate of the second MOS transistor (Q2) is connected to the negative output terminal of the duty cycle detection circuit (201); the first MOS transistor (Q1) and the second MOS transistor (Q2) operate in the linear region.

7. The 2.5 fractional frequency divider according to claim 6, characterized in that, The correction module (20) further includes: a third CML buffer (203); The positive input terminal of the third CML buffer (203) is connected to the positive output terminal of the CML buffer body circuit used for outputting positive signals; the negative input terminal of the third CML buffer (203) is connected to the negative output terminal of the CML buffer body circuit used for outputting negative signals. The output of the third CML buffer (203) is the output of the correction module (20).

8. The 2.5 fractional frequency divider according to claim 4, characterized in that, Also includes: Orthogonal module (30); The input terminal of the orthogonal module (30) is connected to the output terminal of the correction module (20) to convert the differential signal output by the correction module (20) into two orthogonal signals.

9. The 2.5 fractional frequency divider according to claim 8, characterized in that, The orthogonal module (30) includes: a two-stage resistor-capacitor multiphase filter.

10. The 2.5 fractional frequency divider according to claim 8, characterized in that, Also includes: CML buffer group, the CML buffer group includes one CML buffer, or includes multiple CML buffers connected in series; The input terminal of the CML buffer group is connected to the output terminal of the quadrature module (30) to adjust the swing of the two quadrature signals to be the same.

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