Voltage-modulated column-level single-slope analog-to-digital converter

Abstract

The application discloses a voltage modulation column-level single-ramp analog-to-digital converter and relates to the technical field of analog-to-digital converters, comprising a bias power supply, a slope generator, a first capacitor circuit, a second capacitor circuit, a first inverter, a reset switch, an N-bit counter and an N-bit register, wherein N is a positive integer. The application realizes the comparator in the column-level single-ramp analog-to-digital converter through the inverter structure. When the comparator flips, the current consumption is no longer continued, the power consumption of each column circuit is low, compared with the traditional operational amplifier type comparator, the power consumption of each column circuit is reduced, and the structure is simple. With the increase of the pixel array, the power consumption reduction effect will be more significant.

Description

Technical Field

[0001] This invention relates to the field of analog-to-digital converter technology, and more particularly to a voltage-modulated column-level single-slope analog-to-digital converter. Background Technology

[0002] Low-power CMOS image sensors are a core technology for acquiring and transmitting visual information that requires battery power in fields such as the Internet of Things (IoT), 5G mobile terminal devices, and artificial intelligence. Currently, CMOS image sensors primarily employ a column-parallel architecture, with the main power consumption source being the core module, the column-level analog-to-digital converter (ADC). There are four commonly used column-level ADCs: single-slope ADC, cyclic ADC, successive approximation ADC, and delta modulation ADC. Among these, the single-slope ADC, containing only one comparator and one counter per column, consumes the least power; therefore, low-power CMOS image sensors widely adopt the column-level single-slope ADC architecture.

[0003] The comparators in a column-level single-slope ADC are typically implemented using operational amplifier structures; however, quantizing an N-bit code value requires 2... N The op-amp comparator completes in one clock cycle, and the entire 2 clock cycles are completed. N During the quantization process of each clock cycle, static current is continuously consumed, resulting in high power consumption. Summary of the Invention

[0004] This invention provides a voltage-modulated column-level single-slope analog-to-digital converter, which solves the technical problem of high power consumption in existing column-level single-slope ADCs using operational amplifier comparators. It reduces the power consumption of each column circuit, and the power reduction effect becomes more significant as the pixel array increases.

[0005] The present invention provides the following technical solution through an embodiment of the present invention:

[0006] A voltage-modulated column-level single-slope analog-to-digital converter includes a bias power supply, a ramp generator, a first capacitor circuit, a second capacitor circuit, a first inverter, a reset switch, an N-bit counter, and an N-bit register, where N is a positive integer.

[0007] An external analog signal is input to the input terminal of the first inverter via the first capacitor circuit. The output terminal of the ramp generator is connected to the input terminal of the first inverter via the second capacitor circuit. The two ends of the reset switch are respectively connected to the input terminal and the output terminal of the first inverter. The output terminal of the bias power supply is connected to the power supply terminal of the first inverter. The output terminal of the first inverter is connected to the input terminal of the N-bit counter. The output terminal of the N-bit counter is connected to the N-bit register.

[0008] Preferably, the first capacitor circuit includes a capacitor C1.

[0009] Preferably, the second capacitor circuit includes capacitor C2.

[0010] Preferably, the first inverter includes a pull-up circuit and a pull-down circuit, wherein the pull-up circuit is turned on at a low level and the pull-down circuit is turned on at a high level;

[0011] The analog signals are input to the input terminals of the pull-up circuit and the pull-down circuit respectively via the first capacitor circuit. The output terminal of the ramp generator is connected to the input terminals of the pull-up circuit and the pull-down circuit respectively via the second capacitor circuit. The output terminal of the bias power supply is grounded via the series-connected pull-up circuit and pull-down circuit. The common terminal of the pull-up circuit and the pull-down circuit is connected to the first terminal of the reset switch and the input terminal of the N-bit counter respectively. The second terminal of the reset switch is connected to the input terminals of the pull-up circuit and the pull-down circuit respectively.

[0012] Preferably, the pull-up circuit includes a first MOS transistor, which is a PMOS transistor.

[0013] Preferably, the pull-down circuit includes a second MOS transistor, which is an NMOS transistor.

[0014] Preferably, the bias power supply is used to decrease the voltage input to the power supply terminal of the first inverter after the static operating current of the first inverter increases, and to increase the voltage input to the power supply terminal of the first inverter after the static operating current of the first inverter decreases.

[0015] Preferably, the bias power supply includes an operational amplifier and a second inverter, wherein the second inverter is identical to the first inverter;

[0016] The non-inverting input of the operational amplifier is connected to a reference voltage. The output of the operational amplifier is connected to the power supply terminals of the first inverter and the second inverter, respectively. The input and output terminals of the second inverter are both connected to the inverting input of the operational amplifier.

[0017] Preferably, the operational amplifier is powered by a single power supply.

[0018] Preferably, the operational amplifier is an error amplifier.

[0019] One or more technical solutions provided in the embodiments of the present invention have at least the following technical effects or advantages:

[0020] The comparator in the column-level single-slope analog-to-digital converter is implemented by using an inverter structure. After the comparator flips, it no longer consumes current. The power consumption of each column circuit is low. Compared with the traditional op-amp type comparator, the power consumption of each column circuit is reduced and the structure is simple. As the pixel array increases, the power consumption reduction effect will be more significant. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of the column circuit of the present invention;

[0023] Figure 2 This is a schematic diagram of the structure of the first inverter of the present invention;

[0024] Figure 3 The circuit diagram of the column circuit of the present invention is shown below;

[0025] Figure 4 This is a schematic diagram of the bias power supply of the present invention;

[0026] Figure 5 This is a circuit diagram of the bias power supply of the present invention. Detailed Implementation

[0027] This invention provides a voltage-modulated column-level single-slope analog-to-digital converter, which solves the technical problem of high power consumption in existing column-level single-slope ADCs using operational amplifier comparators.

[0028] The technical solution of this invention is to solve the above-mentioned technical problems, and the overall idea is as follows:

[0029] A voltage-modulated column-level single-slope analog-to-digital converter, such as Figure 1 As shown, it includes a bias power supply, a ramp generator, a first capacitor circuit, a second capacitor circuit, a first inverter, a reset switch, an N-bit counter, and an N-bit register, where N is a positive integer;

[0030] An external analog signal is input to the input terminal of the first inverter via a first capacitor circuit. The output terminal of the ramp generator is connected to the input terminal of the first inverter via a second capacitor circuit. The two ends of the reset switch are connected to the input terminal and the output terminal of the first inverter, respectively. The output terminal of the bias power supply is connected to the power supply terminal of the first inverter. The output terminal of the first inverter is connected to the input terminal of an N-bit counter. The output terminal of the N-bit counter is connected to an N-bit register.

[0031] To better understand the above technical solutions, the following will provide a detailed explanation of the technical solutions in conjunction with the accompanying drawings and specific implementation methods.

[0032] First, it should be clarified that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0033] In this embodiment, the first capacitor circuit, the second capacitor circuit, the first inverter, the reset switch, the N-bit counter, and the N-bit register constitute one column circuit in the column-level single-ramp analog-to-digital converter. The column-level single-ramp analog-to-digital converter includes multiple column circuits, each of which receives one column of analog signals from each column, converts it into digital code values, and outputs them. The first capacitor circuit and the second capacitor circuit are circuits composed of capacitors for charging and discharging. The first capacitor circuit or the second capacitor circuit may include one capacitor or multiple capacitors connected in series or parallel. The bias power supply is used to provide the power supply voltage Vdd_inv for the first inverter in all column circuits, the ramp generator is used to provide the ramp signal Vramp required for the analog-to-digital conversion of all column circuits, and the first inverter is used to compare the power supply voltage Vdd_inv with the ramp signal Vramp.

[0034] Among them, such as Figure 2 As shown, the first inverter includes a pull-up circuit and a pull-down circuit. The pull-up circuit is turned on at a low level, and the pull-down circuit is turned on at a high level. The analog signal is input to the input terminals of the pull-up circuit and the pull-down circuit respectively through the first capacitor circuit. The output terminal of the ramp generator is connected to the input terminals of the pull-up circuit and the pull-down circuit respectively through the second capacitor circuit. The output terminal of the bias power supply is grounded through the series-connected pull-up circuit and pull-down circuit. The common terminal of the pull-up circuit and the pull-down circuit is connected to the first terminal of the reset switch and the input terminal of the N-bit counter respectively. The second terminal of the reset switch is connected to the input terminals of the pull-up circuit and the pull-down circuit respectively.

[0035] The port connected to the output of the bias power supply via the pull-up circuit is the power supply terminal of the first inverter. The input terminals of the pull-up and pull-down circuits are the input terminals of the first inverter, and the common terminal of the pull-up and pull-down circuits is the output terminal of the first inverter. When the input of the first inverter is high, the pull-down circuit is on, the input terminal of the N-bit counter is grounded, and the first inverter outputs a low level. When the input of the first inverter is low, the pull-up circuit is on, the input terminal of the N-bit counter is connected to the output terminal of the bias power supply, and the first inverter outputs a high level. The pull-up circuit may include a single low-level on switch or multiple series-connected low-level on switches, such as MOSFETs; the pull-down circuit may also include a single high-level on switch or multiple series-connected high-level on switches, such as MOSFETs.

[0036] Specifically, such as Figure 3 As shown, RST is the reset switch; the first capacitor circuit may only include capacitor C1, and the second capacitor circuit may only include capacitor C2; the pull-up circuit may include a first MOSFET M1, which is a PMOS; the pull-down circuit may include a second MOSFET M2, which is an NMOS. The externally input column analog signal Vpixel is connected to the gates of the first MOSFET M1 and the second MOSFET M2 via capacitor C1. The output of the ramp generator is connected to the gates of the first MOSFET M1 and the second MOSFET M2 via capacitor C2. The output of the bias power supply is grounded via the first MOSFET M1 and the second MOSFET M2 connected in series. The common terminal of the first MOSFET M1 and the second MOSFET M2 is connected to the first terminal of the reset switch RST and the input terminal of the N-bit counter, respectively. The second terminal of the reset switch RST is connected to the gates of the first MOSFET M1 and the second MOSFET M2.

[0037] In this circuit, the drain of the first MOSFET M1 is connected to the drain of the second MOSFET M2, the source of the second MOSFET M2 is grounded, the gate of the first MOSFET M1 is the input terminal of the pull-up circuit, the gate of the second MOSFET M2 is the input terminal of the pull-down circuit, the common terminal of the drains of the first MOSFET M1 and the second MOSFET M2 is the output terminal of the first inverter, and the source of the first MOSFET M1 is the power supply terminal of the first inverter.

[0038] The working principle of one of the circuits in this embodiment is as follows: First, during the pixel reset voltage output stage, the Vpixel voltage is the pixel reset voltage Vrst. The reset switch RST is closed, and the first inverter is reset. Figure 2The voltage at point Vi is the reset voltage Vcm of the first inverter, and the voltage Vramp is the ramp reset voltage Vramp0. Next, in the pixel signal voltage output stage, the voltage Vpixel is the pixel signal voltage Vsig, the reset switch RST is open, and the voltage Vramp rises on a ramp. Since point Vi is floating, according to the principle of charge conservation...

[0039] (Vcm-Vrst)C1+(Vcm-Vramp0)C2=(Vi-Vsig)C1+(Vi-Vramp)C2;

[0040] achievable

[0041] when When the driving input voltage Vi of the two MOSFETs is greater than the reset voltage Vcm of the first inverter, the second MOSFET M2 is turned on, the output Vo is grounded and the voltage is zero, the first inverter flips, the N-bit counter stops counting, and the count value at this time is saved into the N-bit register, which is the N-bit quantization code value of the pixel signal in that column.

[0042] In this embodiment, the comparator in the column-level single-slope analog-to-digital converter is implemented through an inverter structure. After the comparator flips, it no longer consumes current. The power consumption of each column circuit is low. Compared with the traditional op-amp type comparator, the power consumption of each column circuit is reduced and the structure is simple. As the pixel array increases, the power consumption reduction effect will be more significant.

[0043] As can be seen from the working principle of the column circuit, when the flip point of the first inverter deviates, the N-bit counter will overcount or undercount, resulting in a deviation in the quantization code value. Since the quiescent operating point of the first inverter is easily affected by process technology, power supply voltage, and temperature, this can also lead to a deviation in the flip point of the first inverter. Therefore, in this embodiment, the bias power supply is preferably used to decrease the voltage input to the power supply terminal of the first inverter after the quiescent operating current increases, and to increase the voltage input to the power supply terminal of the first inverter after the quiescent operating current decreases. In this way, when the quiescent operating current of the first inverter increases, the bias power supply can decrease the first inverter current, thereby stabilizing the first inverter current; when the quiescent operating current of the first inverter decreases, the bias power supply can increase the first inverter current, similarly stabilizing the first inverter current. In this way, when the quiescent operating current of the first inverter in the column circuit fluctuates due to process conditions, power supply voltage, and temperature, the bias power supply can stabilize the current of the first inverter, thereby stabilizing the operating point of the array inverters. The first inverter is less affected by process conditions, power supply voltage, and temperature, resulting in a more stable quiescent operating point, thus enabling applications in high-precision environments. Furthermore, since the bias power supply provides the power supply voltage Vdd_inv for the first inverters in all column circuits, all column circuits share a single bias power supply. Therefore, the power consumption of the bias power supply is negligible compared to the total power consumption of the column circuits, essentially adding no power consumption.

[0044] like Figure 4 As shown, the bias power supply includes operational amplifier U1 and a second inverter, which is identical to the first inverter. The non-inverting input of operational amplifier U1 is connected to a reference voltage Vref. The output of operational amplifier U1 is connected to the power supply terminals of both the first and second inverters. The input and output of the second inverter are both connected to the inverting input of operational amplifier U1. The output of operational amplifier U1 is the output of the bias power supply. Operational amplifier U1 can be an error amplifier and can be powered by a single or dual power supply. Because the second inverter is identical to the first inverter, fluctuations in the quiescent current of the first inverter will cause fluctuations in the second inverter; an increase in the quiescent current of the first inverter will also increase the quiescent current of the second inverter. Figure 4 As the intermediate voltage Vn increases while the reference voltage Vref remains constant, the output voltage of operational amplifier U1 decreases, meaning the power supply voltage Vdd_inv of the first inverter decreases, creating negative feedback. This reduces and stabilizes the current of the first inverter. Similarly, when the quiescent operating currents of the first MOSFET M1 and the second MOSFET M2 decrease, the quiescent operating current of the second inverter also decreases. Figure 4When the intermediate voltage Vn decreases and the reference voltage Vref remains constant, the output voltage of the operational amplifier U1 increases, which means that the power supply voltage Vdd_inv of the first inverter increases, forming negative feedback, thereby increasing the current of the first inverter and stabilizing the current of the first inverter.

[0045] In this embodiment, if the first inverter includes a first MOSFET M1 and a second MOSFET M2, then the second inverter includes a third MOSFET M3 and a fourth MOSFET M4. The third MOSFET M3 is a PMOS, and the fourth MOSFET M4 is an NMOS. The third MOSFET M3 has the same dimensions as the first MOSFET M1, and the fourth MOSFET M4 has the same dimensions as the second MOSFET M2. Figure 5 As shown, the output of operational amplifier U1 is connected to the source of the third MOSFET M3, the drain of the third MOSFET M3 is connected to the drain of the fourth MOSFET M4, and the common terminal of the drains of the third MOSFET M3 and the fourth MOSFET M4 is connected to the inverting input of operational amplifier U1. The inverting input of operational amplifier U1 is also connected to the gates of the third MOSFET M3 and the fourth MOSFET M4, respectively. The source of the fourth MOSFET M4 is grounded. The source of the third MOSFET M3 is the power supply terminal of the second inverter, the gates of the third MOSFET M3 and the fourth MOSFET M4 are the input terminals of the second inverter, and the common terminal of the drains of the third MOSFET M3 and the fourth MOSFET M4 is the output terminal of the second inverter.

[0046] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0047] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A voltage-modulated column-level single-skew analog-to-digital converter, characterized in that, It includes a bias power supply, a ramp generator, a first capacitor circuit, a second capacitor circuit, a first inverter, a reset switch, an N-bit counter, and an N-bit register, where N is a positive integer; An external analog signal is input to the input terminal of the first inverter via the first capacitor circuit. The output terminal of the ramp generator is connected to the input terminal of the first inverter via the second capacitor circuit. The two ends of the reset switch are respectively connected to the input terminal and the output terminal of the first inverter. The output terminal of the bias power supply is connected to the power supply terminal of the first inverter. The output terminal of the first inverter is connected to the input terminal of the N-bit counter. The output terminal of the N-bit counter is connected to the N-bit register. The bias power supply includes an operational amplifier and a second inverter, the second inverter being identical to the first inverter; The non-inverting input of the operational amplifier is connected to a reference voltage. The output of the operational amplifier is connected to the power supply terminals of the first inverter and the second inverter, respectively. The input and output terminals of the second inverter are both connected to the inverting input of the operational amplifier.

2. The voltage-modulated column-stage single-skew analog-to-digital converter as described in claim 1, characterized in that, The first capacitor circuit includes capacitor C1.

3. The voltage-modulated column-stage single-skew analog-to-digital converter as described in claim 1, characterized in that, The second capacitor circuit includes capacitor C2.

4. The voltage-modulated column-stage single-skew analog-to-digital converter as described in claim 1, characterized in that, The first inverter includes a pull-up circuit and a pull-down circuit, wherein the pull-up circuit is turned on at a low level and the pull-down circuit is turned on at a high level; The analog signals are input to the input terminals of the pull-up circuit and the pull-down circuit respectively via the first capacitor circuit. The output terminal of the ramp generator is connected to the input terminals of the pull-up circuit and the pull-down circuit respectively via the second capacitor circuit. The output terminal of the bias power supply is grounded via the series-connected pull-up circuit and pull-down circuit. The common terminal of the pull-up circuit and the pull-down circuit is connected to the first terminal of the reset switch and the input terminal of the N-bit counter respectively. The second terminal of the reset switch is connected to the input terminals of the pull-up circuit and the pull-down circuit respectively.

5. The voltage-modulated column-stage single-skew analog-to-digital converter as described in claim 4, characterized in that, The pull-up circuit includes a first MOS transistor, which is a PMOS transistor.

6. The voltage-modulated column-stage single-skew analog-to-digital converter as described in claim 4, characterized in that, The pull-down circuit includes a second MOS transistor, which is an NMOS transistor.

7. The voltage-modulated column-stage single-skew analog-to-digital converter as described in any one of claims 1-6, characterized in that, The bias power supply is used to decrease the voltage input to the power supply terminal of the first inverter after the static operating current of the first inverter increases, and to increase the voltage input to the power supply terminal of the first inverter after the static operating current of the first inverter decreases.

8. The voltage-modulated column-stage single-skew analog-to-digital converter as described in claim 1, characterized in that, The operational amplifier is powered by a single power supply.

9. The voltage-modulated column-stage single-skew analog-to-digital converter as described in claim 1, characterized in that, The operational amplifier is an error amplifier.

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