analog-to-digital converter

Abstract

In an analog-to-digital converter, primary latches latch outputs of corresponding ones of the delay cells at respective sampling times of different first clocks. The primary latches include at least first and second primary latches, and the secondary latches include at least first and second secondary latches respectively corresponding to the at least first and second primary latches. Each of the at least first and second secondary latches is configured to latch an output of a corresponding one of the at least first and second primary latches at a sampling time of a common second clock. The common second clock is based on at least one of the first clocks.

Description

Technical Field

[0001] This disclosure relates to an analog-to-digital (A / D) converter for converting input analog signals into digital numerical data. Background Technology

[0002] A / D converters have been developed to simplify their configuration by utilizing higher resolution digital data (i.e., higher resolution digital numerical data), one example of which is disclosed in Japanese Patent Application Publication No. 2004-007385.

[0003] The A / D converter disclosed in this patent includes a pulse delay circuit comprising multiple delay units connected to each other in a ring-cascaded structure; each delay unit includes various gate circuits. The multiple delay units correspond to multiple delay stages.

[0004] The analog input signal, i.e., the analog input voltage, which is the target of the A / D conversion, is configured to be supplied as a power supply voltage to each delay unit. This provides an A / D converter with time-domain processing.

[0005] The A / D converter disclosed in this patent is configured such that a pulse signal input to one of the delay units is sequentially transmitted through the delay units, thereby being delayed. As the pulse signal is transmitted through each delay unit, the transmission speed of the pulse signal through the corresponding delay unit is determined based on the delay time of the pulse signal through the corresponding delay unit; the delay time of the pulse signal through each delay unit depends on the power supply voltage of the corresponding delay unit.

[0006] Counting the number of delay units (i.e., the number of delay units) through which the pulse signal passes during a predetermined sampling period enables the conversion of analog input voltage into digital numerical data. Specifically, the A / D converter disclosed in this patent is called a time-to-A / D converter with a clock edge shifting structure (CKES), which can be abbreviated as "CKES-TAD". Summary of the Invention

[0007] This A / D converter (examples of which are disclosed in the patent publication) is configured as an integrated circuit (IC) chip and includes m (such as four) pulse position digitizers, each pulse position digitizer including a latch and an encoder. m clock pulses, i.e., four clock pulses, are input to the corresponding latches of the m pulse position digitizers.

[0008] The latch of each pulse position digitizer is connected to the corresponding delay unit through the corresponding delay unit wiring, and latches the output of the corresponding delay unit synchronously with the positive edge (rising edge) or negative edge (falling edge) of the corresponding clock in m clock pulses through the corresponding readout wiring.

[0009] The encoder of each pulse position digitizer converts the position of the pulse signal input to the first-stage delay unit into digital data, i.e., digital numerical data.

[0010] The inventors of this disclosure have been considering a primary / secondary latch circuit comprising multiple pairs of primary and secondary latches as a latch for inputting the position of the pulse signal input to the first-stage delay unit to each encoder.

[0011] This consideration necessitates input wiring for inputting clock pulses to the corresponding primary latch, as well as additional input wiring for inputting clock pulses to the corresponding secondary latch. Therefore, this can lead to an increase in the number of clock pulse input lines, resulting in a larger footprint of the primary / secondary latch circuitry within the component layout of the IC chip A / D converter.

[0012] In IC chip A / D converters, an increase in the space occupied by the primary / secondary latch circuitry in the component layout space may lead to an increase in the wiring of each delay unit, resulting in larger parasitic impedances (such as parasitic capacitance and / or parasitic resistance) in each delay unit wiring. This may increase the rise time of the input waveform representing the output of each delay unit to the latch of the pulse position digitizer, causing unstable operation of the primary / secondary latch circuitry.

[0013] The increased space occupied by primary / secondary latch circuits in the component layout of IC chip A / D converters may inhibit performance improvements of A / D converters that have already been achieved through more refined CMOS manufacturing processes.

[0014] From this perspective, this disclosure aims to provide an A / D converter, each A / D converter including primary / secondary latch circuitry, which occupies a small space in the component layout space of the corresponding A / D converter.

[0015] An exemplary measure according to this disclosure provides an analog-to-digital converter (ADC). The ADC includes a pulse delay circuit comprising a plurality of delay units connected in series with each other. The pulse delay circuit is configured to allow a pulse signal to pass through it while delaying the pulse signal through each of the plurality of delay units. The delay time of each of the plurality of delay units depends on the level of an analog input signal input to each of the plurality of delay units. The ADC includes a plurality of latch modules configured for each of the delay units. Each latch module configured for each of the delay units includes a plurality of primary latches configured to latch the output of a corresponding delay unit at a corresponding sampling time of a different first clock cycle. Each latch module configured for each of the delay units includes a plurality of secondary latches for latching the output of a corresponding primary latch. The plurality of secondary latches include at least a first-stage latch and a second-stage latch, and the plurality of primary latches include at least first and second primary latches respectively corresponding to at least the first and second secondary latches. Each of at least the first and second secondary latches is configured to latch the output of a corresponding primary latch among at least the first and second primary latches at a sampling time of a common second clock. The common second clock is based on at least one of the first clocks. The analog-to-digital converter includes an encoder unit configured to encode output data items from each of the plurality of secondary latches into digital numerical data items.

[0016] Multiple latch modules are provided for each delay unit in the delay unit of the pulse delay circuit to suppress the increase in both the A / D converter's footprint and power consumption without increasing the number of pulse delay circuits or delay units in the delay unit.

[0017] Specifically, each of the at least first and second secondary latches is configured to latch the output of the corresponding primary latch of at least the first and second primary latches at the sampling time of a common second clock; the common second clock is based on at least one of the first clocks.

[0018] This allows at least the first and second secondary latches to share the second clock, resulting in a reduction in the amount of wiring required to provide the second clock to each secondary latch. This leads to a smaller footprint for the latch modules within the component layout space of the A / D converter. Attached Figure Description

[0019] Other aspects of this disclosure will become apparent from the following description of embodiments with reference to the accompanying drawings, wherein:

[0020] Figure 1This is a block diagram illustrating a schematic configuration of an A / D converter according to a first embodiment of the present disclosure;

[0021] Figure 2 It is shown Figure 1 A circuit diagram showing a schematic configuration of the clock generator for the A / D converter;

[0022] Figure 3 It is shown Figure 1 An electrical block diagram illustrating a schematic configuration of the encoder unit of the A / D converter shown.

[0023] Figure 4 The following is a schematic enlarged view of the following parts: (i) Figure 1 The diagram shows the electrical configuration of each of the latch modules configured for the first delay unit; and (ii) the electrical connections of the latch modules;

[0024] Figure 5 It is shown Figure 4 A circuit diagram illustrating a schematic configuration of each of the latch modules shown;

[0025] Figure 6 This is a timing diagram schematically illustrating how each of the latches in the latch module according to the first embodiment operates;

[0026] Figure 7 The diagram schematically shows enlarged views of: (i) the electrical configuration of each of the latch modules configured for the first delay unit according to the comparative example; and (ii) the electrical connections of the latch modules according to the comparative example;

[0027] Figure 8 This is a circuit diagram illustrating a schematic configuration of each of the latch modules according to a second embodiment of the present disclosure;

[0028] Figure 9 This is a block diagram illustrating a schematic configuration of an A / D converter according to a third embodiment of the present disclosure;

[0029] Figure 10 This is a timing diagram schematically illustrating how each of the latch modules according to the third embodiment operates; and

[0030] Figure 11 It is shown Figure 9 The diagram shows a schematic configuration of the encoder unit of the A / D converter. Detailed Implementation

[0031] Exemplary embodiments of the present disclosure are described below with reference to the accompanying drawings. In the exemplary embodiments, similar parts assigned similar reference numerals between embodiments are omitted or simplified to avoid repetitive description.

[0032] First Embodiment

[0033] The following is for reference. Figures 1 to 7 A time-based A / D converter (time analog-to-digital converter) 1 according to a first embodiment is described. Figures 1 to 5 An example configuration of a time-based A / D converter 1 is illustrated schematically.

[0034] The time-based A / D converter 1, referred to as A / D converter 1, can be installed in various analog and digital converged devices and / or systems, such as sensor devices with digital communication capabilities, system-on-chips for, for example, 5G communication devices, and semiconductor ICs for systems using the Internet of Things (IoT). For example, A / D converter 1 can be manufactured using complementary metal-oxide-semiconductor (CMOS) fabrication processes.

[0035] refer to Figure 1 and Figure 3 The A / D converter 1 includes a pulse delay circuit 2, a clock generator 3, a pulse position digitization circuit 4, and an adder 5. The A / D converter 1 is configured to receive an analog input voltage signal Vin (output from any device that outputs an analog voltage signal, such as a sensor), and convert the analog input voltage signal Vin into a digital numerical data item DTA. The pulse position digitization circuit 4 will also be referred to as a latch-encoder and subtractor.

[0036] Configuration of pulse delay circuit

[0037] Next, an example of the configuration of the pulse delay circuit 2 will be described below.

[0038] The pulse delay circuit 2 comprises n delay units DU connected in series with each other in a ring configuration; the number n of delay units DU serves as the number n of delay stages. The pulse delay circuit 2 is also referred to as a ring delay line. The number n is set to an odd number, such as 15.

[0039] The delay unit DU used as the first delay stage (also referred to as the first delay unit) includes a NAND gate G1, and the remaining delay units DU used as the second to nth delay units DU (i.e., the second to nth delay stages) respectively include NOT gates G2 to Gn, i.e., inverters G2 to Gn. That is, these first to nth delay units can be referred to as G1 to Gn or DU.

[0040] The first delay unit (AND gate) G1 has first and second input terminals and an output terminal, and a pulse signal is input to the first input terminal of the first delay unit G1.

[0041] Each of the second to nth delay units G2 to Gn has an input terminal and an output terminal.

[0042] The input terminals of each delay unit G2, ..., Gn, except for the first delay unit G1, are cascaded to the output terminals of the immediately preceding delay units G1, ..., Gn-1. Finally, the output terminal of the nth delay unit Gn is connected to the second input terminal of the first delay unit G1.

[0043] When a pulse signal is input to the first input terminal of the first delay unit G1, the first delay unit G1 operates to transmit the pulse signal to the next delay unit G2, while delaying the pulse signal by a predetermined delay time Td.

[0044] Each of the remaining delay units G2 to Gn-1, except for the last delay unit Gn, sequentially transmits the pulse signal from the immediately preceding delay unit to the next delay unit, while delaying the pulse signal by a predetermined delay time Td. The last delay unit Gn transmits the pulse signal from the immediately preceding delay unit to the next first delay unit G1, while delaying the pulse signal by a predetermined delay time Td.

[0045] The output terminals of the corresponding delay units G1 to Gn are also connected to the pulse position digitization circuit 4, so that the pulse signal output from each of the delay units G1 to Gn is input to the pulse position digitization circuit 4.

[0046] The analog input voltage signal Vin is input as a power supply voltage to each of the delay units G1 to Gn, such that the power supply voltage input to each of the delay units G1 to Gn activates the corresponding delay unit in G1 to Gn.

[0047] Each delay unit DU is configured such that the operating time of the corresponding delay unit DU depends on the level of the analog input voltage signal Vin, which results in the delay time of each delay unit DU depending on the level of the analog input voltage signal Vin.

[0048] Its delay time Td depends on the level of the analog input voltage signal Vin. Any gate can be used as each of the delay units DU. For example... Figure 1 As shown, preferably, NAND gates and NOT gates are used as follows: Figure 1 The corresponding delay unit DU is shown.

[0049] For example, each of the NOT gates G2 to Gn includes a single-stage CMOS inverter with a simpler circuit configuration, a smaller delay time Td, and higher time resolution.

[0050] When the level of the pulse signal EN changes from low to high, the output of each of the odd-level delay units DU (i.e., NAND gate G1 and NOT gates G3, G5, ...) changes from high to low, and the output of each of the even-level delay units DU (i.e., NOT gates G2, G4, ...) changes from low to high.

[0051] Since there are an odd number, such as 15, delay units DU are cascaded to form a loop, the pulse signal circulates in the looped delay units DU. At the same time, the rising timing of the pulse signal from low level to high level and the falling timing of the pulse signal from high level to low level are alternately transmitted in the looped delay units DU.

[0052] Since the delay time of each delay unit DU depends on the level of the analog input voltage signal Vin, changing the level of the analog input voltage signal Vin allows the cycle speed of the pulse signal to be changed.

[0053] Clock generator configuration

[0054] like Figure 2 As shown, clock generator 3 includes a CMOS inverter M1 and m CMOS inverters M2a1 to M2am connected in parallel with each other. CMOS inverter M1 serves as the first stage, and the parallel-connected CMOS inverters M2a1 to M2am serve as the second stage and are sequentially connected to CMOS inverter M1. Each of the CMOS inverters M2a1 to M2am is configured to output a corresponding sampling clock from sampling clocks CK1 to CKm; each sampling clock CK1, ..., CKm is a pulse sequence, i.e., a clock pulse. Sampling clocks CK1 to CKm will be simply referred to as clocks CK1 to CKm.

[0055] The first embodiment uses four CMOS inverters M2a1 to M2a4 (m=4) so ​​that four clocks CK1 to CK4 are output from the corresponding CMOS inverters M2a1 to M2a4.

[0056] Each of CMOS inverters M1 and M2a1 through M2a4 includes a P-channel MOS transistor and an N-channel MOS transistor. The gates of the P-channel MOS transistor and the N-channel MOS transistor in each of CMOS inverters M1 and M2a1 through M2a4 are connected together to form the input terminal of the corresponding CMOS inverter in M1 and M2a1 through M2a4. The drains of the P-channel MOS transistor and the N-channel MOS transistor in each of CMOS inverters M1 and M2a1 through M2a4 are connected together to form the output terminal of the corresponding CMOS inverter in M1 and M2a1 through M2a4. An analog input voltage signal Vin is input as a power supply voltage to the source of the P-channel MOS transistor in each of CMOS inverters M1 and M2a1 through M2a4. Additionally, the source of the N-channel MOS transistor in each of CMOS inverters M1 and M2a1 through M2a4 is connected to its ground terminal.

[0057] The input terminals of the second-stage CMOS inverters M2a1 to M2a4 are all connected to the output terminal of the first-stage CMOS inverter M1, and the sampling clock reference signal CKs is input to the input terminal of the first-stage CMOS inverter M1 as a reference clock, i.e., the master clock. That is, the sampling clock reference signal CKs is used as the master clock externally input to the input terminal of the first-stage CMOS inverter M1.

[0058] That is, each pulse of the sampling clock reference signal CKs is input to the input terminal of the first-stage MOS inverter M1.

[0059] The first-stage MOS inverter M1 receives each pulse of the sampling clock reference signal CKs input to it and transmits each pulse of the sampling clock reference signal CKs to each of the second-stage inverters M2a1, M2a2, M2a3 and M2a4.

[0060] Each of the second-stage inverters M2a1, M2a2, M2a3, and M2a4 receives each pulse of the sampling clock reference signal CKs and transmits each pulse of the sampling clock reference signal CKs as a pulse of the corresponding clock in clocks CK1 to CKm (CK4).

[0061] Specifically, each of the CMOS inverters M2a1 to M2a4 has a first length and a first width of the gate of the corresponding PMOS transistor, and a second length and a second width of the gate of the corresponding NMOS transistor. The first length of the gate of the PMOS transistor of any of the CMOS inverters M2a1 to M2a4 is set to be different from the first length of the gate of the PMOS transistor of the other CMOS inverters M2a1 to M2a4. Similarly, the first width of the gate of the PMOS transistor of any of the CMOS inverters M2a1 to M2a4 is set to be different from the first width of the gate of the PMOS transistor of the other CMOS inverters M2a1 to M2a4.

[0062] Furthermore, the second length of the gate of the NMOS transistor in any of the CMOS inverters M2a1 to M2a4 is set to be different from the second length of the gate of the NMOS transistor in the other CMOS inverters M2a1 to M2a4. Similarly, the second width of the gate of the NMOS transistor in any of the CMOS inverters M2a1 to M2a4 is set to be different from the second width of the gate of the NMOS transistor in the other CMOS inverters M2a1 to M2a4.

[0063] This causes the positive edge (rising edge) of clock CK1 to be delayed by a predetermined delay ΔTs(CK1-CKs) relative to the positive edge of the sampling clock reference signal CKs.

[0064] Similarly, the positive edge of clock CK2 is delayed by a predetermined delay ΔTs(CK2-CKs) relative to the positive edge of the sampling clock reference signal CKs, the positive edge of clock CK3 is delayed by a predetermined delay ΔTs(CK3-CKs) relative to the positive edge of the sampling clock reference signal CKs, and the positive edge of clock CK4 is delayed by a predetermined delay ΔTs(CK4-CKs) relative to the positive edge of the sampling clock reference signal CKs.

[0065] The delays ΔTs(CK1-CKs), ΔTs(CK2-CKs), ΔTs(CK3-CKs), and ΔTs(CK4-CKs) are set to be different from each other. In particular, the delays ΔTs(CK1-CKs), ΔTs(CK2-CKs), ΔTs(CK3-CKs), and ΔTs(CK4-CKs) are set to be longer in this order, which can be expressed as the expression ΔTs(CK1-CKs) < ΔTs(CK2-CKs) < ΔTs(CK3-CKs) < ΔTs(CK4-CKs).

[0066] The period Ts of each clock CK1, CK2, CK3, and CK4 is set to be equal to the period Ts of the sampling clock reference signal CKs. The period Ts is set to be longer than the delay time Td of each delay unit DU. For example, the period of each clock CK1, CK2, CK3, and CK4 is set to a constant period several times longer than the delay time Td of each delay unit DU. Each adjacent pair of clocks CK1, CK2, CK3, and CK4 has a phase difference Δt (see...). Figure 6 ), and the product of m (in this embodiment = 4) and Δt, denoted as 4Δt, is set to be substantially equal to the delay time Td of each delay unit DU.

[0067] That is, the delay ΔTs(CK1-CKs) of the positive edge of clock CK1 relative to the positive edge of the sampling clock reference signal CKs can be represented by 1×Δt, and the delay ΔTs(CK2-CKs) of the positive edge of clock CK2 relative to the positive edge of the sampling clock reference signal CKs can be represented by 2×Δt.

[0068] Similarly, the delay ΔTs(CK3-CKs) of the positive edge of clock CK3 relative to the positive edge of the sampling clock reference signal CKs can be represented by 3×Δt, and the delay ΔTs(CK4-CKs) of the positive edge of clock CK4 relative to the positive edge of the sampling clock reference signal CKs can be represented by 4×Δt.

[0069] Configuration of pulse position digitization circuit

[0070] Pulse position digitization circuit 4 Figure 1 and 3 As shown, it includes NOT gate 20, latch modules 21 to 24 for each delay unit DU, and encoder unit 60. Encoder unit 60, as... Figure 3 As shown, encoders 31 to 34 and latch-subtractor modules 50 are shown, and each of latch-subtractor modules 35 to 38 includes subtractors 51 to 54 and latches 41 to 44.

[0071] Will Figure 1 The number of NOT gates 20 shown is set to n, such that n NOT gates 20 are provided for each of the n delay units DU. Specifically, each of the n NOT gates 20 has an input terminal and an output terminal, and the input terminals of the n NOT gates 20 are respectively connected to the output terminals of the n delay units DU. Therefore, the outputs P1 to Pn of the n delay units DU are input to the corresponding n NOT gates 20.

[0072] The latch modules 21 to 24 are configured as n sets of latch modules 21 to 24 for the corresponding n delay units DU, i.e. n NOT gates.

[0073] Each group of latch modules 21 to 24 has input terminals and output terminals. The input terminals of each group of latches 21 to 24 are connected to the output terminal of the corresponding NOT gate 20. That is, the number of groups of latch modules 21 to 24 is the same as the number of outputs P1 to Pn of the corresponding delay unit DU.

[0074] The number of latch modules 21 to 24 is the same as the number of clocks CK1 to CK4.

[0075] Clocks CK1, CK2, CK3, and CK4 are input to latch modules 21 to 24, which are set up for each delay unit DU.

[0076] Let us focus on the four latch modules 21 to 24, which are set in parallel for the output P1 of the first delay unit DU(G1), and are configured to latch the output P1 synchronously with the positive or negative edge of each pulse of the corresponding clock in clocks CK1 to CK4.

[0077] Clocks CK1, CK2, CK3, and CK4 have corresponding phase differences of 1×Δt, 2×Δt, 3×Δt, and 4×Δt relative to the sampling clock reference signal CKs. Therefore, latch module 21 latches output P1 at the sampling time corresponding to the occurrence of each pulse of clock CK1, such as the occurrence of the positive or negative edge of each pulse, with the corresponding pulse of clock CK1 relative to the sampling clock reference signal CKs corresponding to a timing of 1×Δt. Similarly, latch module 22 latches output P1 at the sampling time corresponding to the occurrence of each pulse of clock CK2, with clock CK2 corresponding to a timing of 2×Δt relative to the sampling clock reference signal CKs. Latch module 23 latches output P1 at the sampling time corresponding to the occurrence of each pulse of clock CK3, with clock CK3 corresponding to a timing of 3×Δt relative to the sampling clock reference signal CKs. Latch module 24 latches output P1 at the sampling time corresponding to the occurrence of each pulse of clock CK4, with clock CK4 corresponding to a timing of 4×Δt relative to the sampling clock reference signal CKs.

[0078] Note that the appearance of a pulse represents the appearance of either a positive or negative edge of the pulse.

[0079] The phase difference Δt between each adjacent pair of clocks CK1, CK2, CK3, and CK4 is set to Td / m (m = 4 in this embodiment), making it possible to latch the output P1 at each of the subdivision sampling times 1×(Td / 4), 2×(Td / 4), 3×(Td / 4), and 4×(Td / 4); each of the subdivision sampling times 1×(Td / 4), 2×(Td / 4), 3×(Td / 4), and 4×(Td / 4) is a function of the value (Td / 4) obtained by subdividing the delay time Td of each delay unit DU.

[0080] This configuration of the pulse position digitization circuit 4 enables the latch modules 21 to 24 arranged in parallel for the first delay unit DU(G1) to latch the output P1 of the pass-through gate 20 of the first delay unit DU(G1) at the sampling time corresponding to the corresponding pulses of different clocks CK1, CK2, CK3 and CK4.

[0081] Similarly, this configuration of the pulse position digitization circuit 4 enables the latch modules 21 to 24 arranged in parallel for the second delay unit DU(G2) to latch the output P2 of the NOT gate 20 of the second delay unit DU(G2) at the sampling time corresponding to the corresponding pulses of different clocks CK1, CK2, CK3, CK4, ..., and enables the latch modules 21 to 24 arranged in parallel for the nth delay unit DU(Gn) to latch the output Pn of the NOT gate 20 of the nth delay unit DU(Gn) at the sampling time corresponding to the corresponding pulses of different clocks CK1, CK2, CK3, and CK4.

[0082] Therefore, the pulse position digitization circuit 4 according to the first embodiment has a higher time resolution without increasing the number of pulse delay circuits and the number n of delay units DU in the pulse delay circuit 2.

[0083] As described above, latch modules 21 to 24 for each of the n delay units DU are configured to latch the output of the corresponding delay unit in the delay unit DU through NOT gate 20.

[0084] Each of the latch modules 21 provided for the corresponding delay unit DU includes a primary latch 21m and a secondary latch 21s connected in series with each other, and the primary latches 21m provided for the corresponding delay unit DU are cascaded with each other, and the secondary latches 21s provided for the corresponding delay unit DU are cascaded with each other.

[0085] Similarly, each of the latch modules 22 provided for the corresponding delay unit DU includes a primary latch 22m and a secondary latch 22s connected in series with each other, and the primary latches 22m provided for the corresponding delay unit DU are cascaded with each other, and the secondary latches 22s provided for the corresponding delay unit DU are cascaded with each other.

[0086] Similar to latch module 22, each of the latch modules 23 provided for the corresponding delay unit DU includes a primary latch 23m and a secondary latch 23s connected in series with each other, and the primary latches 23m provided for the corresponding delay unit DU are cascaded with each other, and the secondary latches 23s provided for the corresponding delay unit DU are cascaded with each other.

[0087] Furthermore, each of the latch modules 24 provided for the corresponding delay unit DU includes a primary latch 24m and a secondary latch 24s connected in series with each other, and the primary latches 24m provided for the corresponding delay unit DU are cascaded with each other, and the secondary latches 24s provided for the corresponding delay unit DU are cascaded with each other.

[0088] That is, latch modules 21 to 24 for the first delay unit DU(G1) are configured to latch the state of the delayed pulse P1 output from the first delay unit DU(G1) through the NOT gate 20 at the sampling time corresponding to the corresponding pulses of different clocks CK1, CK2, CK3 and CK4, ..., and latch modules 21 to 24 for the nth delay unit DU(Gn) are configured to latch the state of the delayed pulse Pn output from the nth delay unit DU(Gn) through the NOT gate 20 at the sampling time corresponding to the corresponding pulses of different clocks CK1, CK2, CK3 and CK4.

[0089] Specifically, the primary latches 21m to 24m for the first delay unit DU(G1) are configured to latch the state of the delayed pulse P1 output from the first delay unit DU(G1) through the NOT gate 20 at the sampling time corresponding to the corresponding pulses of different clocks CK1, CK2, CK3, and CK4, ..., and the primary latches 21m to 24m for the nth delay unit DU(Gn) are configured to latch the state of the delayed pulse Pn output from the nth delay unit DU(Gn) through the NOT gate 20 at the sampling time corresponding to the corresponding pulses of different clocks CK1, CK2, CK3, and CK4. Each of the clocks CK1 to CK4 serves as the first clock.

[0090] Conversely, the secondary latches 21s to 24s for the first delay unit DU(G1) are configured to latch the state of the delayed pulse P1 output from the first delay unit DU(G1) through the NOT gate 20 at the sampling time corresponding to the occurrence of each pulse of the clock CK1, ..., and the secondary latches 21s to 24s for the nth delay unit DU(Gn) are configured to latch the state of the delayed pulse Pn output from the nth delay unit DU(Gn) through the NOT gate 20 at the sampling time corresponding to the occurrence of each pulse of the clock CK1.

[0091] That is, the secondary latches 21s to 24s for each of the n delay units DU are configured to latch the output of the corresponding delay unit in the delay unit DU at the sampling time corresponding to the occurrence of each pulse of the clock CK1 included in the clocks CK1 to CK4. The clock CK1 used by each of the secondary latches 21s to 24s serves as a second clock. One specific example of the latch modules 21 to 24 will be described later.

[0092] The number of encoders 31 to 34 is the same as the number of clock pulses CK1 to CK4. That is, four encoders 31 to 34 are provided in the pulse position digitization circuit 4.

[0093] Encoder 31 is configured to encode the output data item Do1 latched by the corresponding latch module 21 into code data, i.e., z-bit data O1 (z is 2), synchronously with the occurrence of each pulse of the sampling clock reference signal CKs. n ).

[0094] Each latched data item in latch module 21 corresponds to the output of the corresponding delay unit in delay unit DU, such that any data item in the data item corresponding to the delay unit DU reached by the cyclic pulse signal input to the ring delay line is a specific value other than the data items corresponding to the other delay units DU. Therefore, it is possible to digitize the position of the cyclic pulse signal input to the ring delay line at its arrival point in the ring delay line, thereby generating z-bit data O1.

[0095] The encoder 32 is configured to encode the data item Do2 latched by the corresponding latch module 22 into code data, i.e., z-bit data O2, synchronously with the occurrence of each pulse of the sampling clock reference signal CKs. Each latched data item in the latch module 22 corresponds to the output of the corresponding delay unit in the delay unit DU, such that any data item in the data item corresponding to the delay unit DU reached by the cyclic pulse signal input to the ring delay line is a specific value other than the data items corresponding to the other delay units DU. Therefore, it is possible to digitize the position of the cyclic pulse signal input to the ring delay line at the location in the ring delay line, thereby generating z-bit data O2.

[0096] The encoder 33 is configured to encode the data item Do3 latched by the corresponding latch module 23 into code data, i.e., z-bit data O3, synchronously with the occurrence of each pulse of the sampling clock reference signal CKs. Each latched data item in the latch module 23 corresponds to the output of the corresponding delay unit in the delay unit DU, such that any data item in the data item corresponding to the delay unit DU reached by the cyclic pulse signal input to the ring delay line is a specific value other than the data items corresponding to the other delay units DU. Therefore, it is possible to digitize the position of the cyclic pulse signal input to the ring delay line at the location in the ring delay line, thereby generating z-bit data O3.

[0097] Encoder 34 is configured to encode the data item Do4 latched by the corresponding latch module 24 into code data, i.e., z-bit data O4, synchronously with the occurrence of each pulse of the sampling clock reference signal CKs. Each latched data item in latch module 24 corresponds to the output of the corresponding delay unit in delay unit DU, such that any data item in the data item corresponding to the delay unit DU reached by the cyclic pulse signal input to the ring delay line is a specific value other than the data items corresponding to the other delay units DU. Therefore, it is possible to digitize the position of the cyclic pulse signal input to the ring delay line at the location in the ring delay line, thereby generating z-bit data O4.

[0098] That is, each of encoders 31 to 34 is configured to read and encode data latched by the corresponding latch in latches 21 to 24 using each pulse of the sampling clock reference signal CKs, which is used to generate clocks CK1 to CKm.

[0099] Therefore, each of encoders 31 to 34 is able to digitize the position of the cyclic pulse signal input to the ring delay line, thereby generating the corresponding z-bit data in z-bit data O1, z-bit data O2, z-bit data O3 and z-bit data O4.

[0100] The latch-subtractor module 35, connected as a subsequent stage to encoder 31, includes latch 41 and subtractor 51, and the latch-subtractor module 36, connected as a subsequent stage to encoder 32, includes latch 42 and subtractor 52. Similarly, the latch-subtractor module 37, connected as a subsequent stage to encoder 33, includes latch 43 and subtractor 53, and the latch-subtractor module 38, connected as a subsequent stage to encoder 34, includes latch 44 and subtractor 54.

[0101] Each of latches 41 to 44 is configured to latch the corresponding code data from code data O1, code data O2, code data O3, and code data O4 output from encoders 31, 32, 33, and 34 at the sampling time corresponding to the occurrence of each pulse of the sampling clock reference signal CKs. That is, each of latches 41 to 44 is configured to store the corresponding code data from code data O1, code data O2, code data O3, and code data O4 output from encoders 31, 32, 33, and 34 as previous code data at the sampling time corresponding to the occurrence of each pulse of the sampling clock reference signal CKs.

[0102] Each of subtractors 51 to 54 is configured to subtract the corresponding code data from code data O1, code data O2, code data O3, and code data O4, which are the current code data, from the previous code data stored in the corresponding latches in latches 41 to 44, at the sampling time corresponding to the occurrence of each pulse of the sampling clock reference signal CKs, thereby calculating the deviation data between the current code data and the previous code data. Then, each of subtractors 51 to 54 is configured to output the deviation data as the corresponding n-bit digital value data item DT1 to DT4 to adder 5.

[0103] Adder 5 is configured to add n-bit numeric data items DT1 to DT4 to each other, thereby generating a numeric data item DTA with (n+log2m) bits; according to the first embodiment, m is set to 4.

[0104] Various processing units can be set up to replace adder 5. Each of the various processing units can be configured to output any numeric data based on n-bit numeric data items DT1 to DT4.

[0105] According to the first embodiment, the encoders 31 to 34, latches 41 to 44 and subtractors 51 to 54 constitute an encoder unit 60.

[0106] That is, encoder unit 60 is configured as follows:

[0107] (I) Calculate the deviation data between the current code data and the previous code data of the output data item DO1 latched by latch module 21 and output from secondary latch 21s, thereby converting the output data item DO1 into an n-bit numeric data item DT1.

[0108] (II) Calculate the deviation data between the current code data and the previous code data of the data item DO2 latched by latch module 22 and output from secondary latch 22s, thereby converting the data item DO2 into an n-bit numeric data item DT2;

[0109] (III) Calculate the deviation data between the current code data and the previous code data of the data item DO3 latched by latch module 23 and output from secondary latch 23s, thereby converting the data item DO3 into an n-bit numeric data item DT3;

[0110] (IV) Calculate the deviation data between the current code data and the previous code data of the data item DO4 latched by latch module 24 and output from secondary latch 24s, thereby converting the data item DO4 into an n-bit numeric data item DT4.

[0111] The aforementioned A / D converter 1 is configured such that the delay time Td of each delay unit DU changes according to the level of the analog input voltage signal Vin. Specifically, the higher the level of the analog input voltage signal Vin, the lower the on-resistance of each transistor constituting each delay unit DU, resulting in a shorter delay time Td for each delay unit DU.

[0112] Conversely, the lower the level of the analog input voltage signal Vin, the higher the on-resistance of each transistor constituting each delay unit DU, resulting in a longer delay time Td for each delay unit DU.

[0113] This causes each of the digital numerical data items DT1 to DT4 digitized by the pulse position digitization circuit 4 to change, thus making it possible to obtain the digital numerical data item DTA based on the digital numerical data items DT1 to DT4 according to the analog input voltage signal Vin.

[0114] The structure and functional significance of each latch module

[0115] The structure and functional significance of latch modules 21 to 24 according to the first embodiment are described below.

[0116] Figure 4 This is an enlarged view of latch modules 21 to 24, for example, provided for the first delay unit DU(G1), and Figure 5 yes Figure 4 Examples of circuit configurations for each of the latch modules 21 to 24 are shown. Hereinafter, the output level of NOT gate 20, i.e., high or low level, will be referred to as Din.

[0117] like Figure 4 and 5 As shown, each of latch modules 21 to 24 is designed as a primary-secondary latch module. Specifically, latch module 21 includes a first-stage primary latch 21m and a second-stage secondary latch 21s connected in series therewith, and latch module 22 includes a first-stage primary latch 22m and a second-stage secondary latch 22s connected in series therewith. Similarly, latch module 23 includes a first-stage primary latch 23m and a second-stage secondary latch 23 connected in series therewith, and latch module 24 includes a first-stage primary latch 24m and a second-stage secondary latch 24s connected in series therewith.

[0118] The output level Din of NOT gate 20 is input to each of the primary latches 21m to 24m.

[0119] Each of the first-stage primary latches 21m to 24m is designed as a CMOS static circuit (which includes a feedback loop including a NOT gate Gb), and latches the corresponding outputs of outputs Dm1 to Dm4.

[0120] The circuit configurations of the corresponding first-stage primary latches 21m to 24m are identical to each other, such that the reference numerals of the corresponding components assigned to the first-stage primary latch 21m are used to assign the corresponding components of each of the other first-stage primary latches 22m to 24m.

[0121] Each of the second-stage primary latches 21s to 24s is designed as a CMOS static circuit (which includes a feedback loop including a NOT gate Gd) and latches the corresponding data items in the output data items Do1 to Do4.

[0122] The circuit configurations of the corresponding second-level secondary latches 21s to 24s are identical to each other, such that the reference numerals of the corresponding components assigned to the second-level secondary latch 21s are used to assign the corresponding components of each of the other second-level secondary latches 22s to 24s.

[0123] The electrical connections between components of primary latch 21m, selected as a typical example of primary latches 21m to 24m, and between components of secondary latch 21s, selected as a typical example of secondary latches 21s to 24s, are described below. Descriptions of the electrical connections between components of each of the other primary latches 22m to 24m are omitted, and similarly, descriptions of the electrical connections between components of each of the other secondary latches 22s to 24s are omitted.

[0124] The primary latch 21m includes switches SW1 and SW2, NOT gate Ga, and NOT gate Gb. Similarly, the secondary latch 21s includes switches SW3 and SW4, NOT gate Gc, and NOT gate Gd.

[0125] Each of the switches SW1 to SW4 has a first terminal and a second terminal, and each of the NOT gates Ga, Gb, Gc and Gd has an input terminal and an output terminal.

[0126] The output level Din of NOT gate 20 is input to the first terminal of switch SW1, and the second terminal of switch SW1 is connected to the input terminal of NOT gate Ga. The output terminal of NOT gate Ga is connected to the input terminal of NOT gate Gb and the first terminal of switch SW3 of secondary latch 21s.

[0127] The output terminal of NOT gate Gb is connected to the first terminal of switch SW2. The second terminal of switch SW2 is connected to the input terminal of NOT gate Ga.

[0128] Each of switches SW1 through SW4 has a control terminal. Clock CK1 is input to the control terminal of switch SW1. The negative edge of clock CK1 (hereinafter referred to as CK1n) turns switch SW1 on, and the positive edge of clock CK1 (hereinafter referred to as CK1p) turns switch SW1 off. Clock CK1 is also input to the control terminal of switch SW2. The positive edge of clock CK1 CK1p turns switch SW2 on, and the negative edge of clock CK1 CK1n turns switch SW2 off.

[0129] This allows switches SW1 and SW2 to be turned on or off complementaryly.

[0130] The conducting state of switch SW1 causes the inverted level of the output level Din of NOT gate 20 to be output as the output level D1m of the primary latch 21m to the secondary latch 21s. Conversely, the conducting state of switch SW2 causes switch SW1 to be turned off. Therefore, when switch SW1 is in the off state, this allows the primary latch 21m to maintain the level D1m independently of changes in the output level Din of NOT gate 20.

[0131] For the secondary latch 21s, the output level Dm1 of the primary latch 21m is input to the first terminal of switch SW3, and the second terminal of switch SW3 is connected to the input terminal of NOT gate Gc. The output terminal of NOT gate Gc is connected to both the input terminal of NOT gate Gd and encoder 31, so that the output of NOT gate Gc is used as the output data item Do1 and input to encoder 31.

[0132] The output terminal of NOT gate Gd is connected to the first terminal of switch SW4. The second terminal of switch SW4 is connected to the input terminal of NOT gate Gc.

[0133] Clock CK1 is input to the control terminal of switch SW3. The positive edge CK1p of clock CK1 turns switch SW3 on, and the negative edge CK1n turns switch SW3 off. Clock CK1 is input to the control terminal of switch SW4. The negative edge CK1n of clock CK1 turns switch SW4 on, and the positive edge CK1p of clock CK1 turns switch SW2 off.

[0134] This allows switches SW3 and SW4 to be turned on or off complementaryly.

[0135] When switch SW3 is turned on, the inverted output level Dm1 of the primary latch 21m is output as the output data item Do1 to encoder 31. Conversely, when switch SW4 is turned on, switch SW3 is turned off. Therefore, when switch SW3 is turned off, this allows the secondary latch 21s to maintain the level of the output data item Do1 independently of changes in the output level Dm1 of the primary latch 21m.

[0136] Except for inputting clocks CK2 to CK4 into the corresponding primary latches 22m to 24m to replace the sampling clock CK1, the operation of each of the other primary latches 22m to 24m is the same as that of primary latch 21m, therefore a description of the operation of each of the other primary latches 22m to 24m is omitted. Similarly, the operation of each of the other secondary latches 22s to 24s is the same as that of secondary latch 21s, therefore a description of the operation of each of the other secondary latches 22s to 24s is omitted.

[0137] Figure 5 The clock CK1 is clearly shown as a common input to switches SW3 and SW4 in the secondary latches from 21s to 24s, such that all switches SW3 in the secondary latches from 21s to 24s are turned on or off synchronously with each other, and all switches SW4 in the secondary latches from 21s to 24s are turned on or off synchronously with each other.

[0138] on the contrary, Figure 5 The different clocks CK1 to CK4 are clearly shown input to the corresponding primary latches 21m to 24m via switches SW1 and SW2.

[0139] Specifically, clock CK2 is input to the control terminal of switch SW1 of primary latch 22m. The negative edge of clock CK2, referred to as CK2n, turns on switch SW1 of primary latch 22m, and the positive edge of clock CK2, referred to as CK2p, turns off switch SW1 of primary latch 22m. Clock CK2 is also input to the control terminal of switch SW2 of primary latch 22m. The positive edge of clock CK2, CK2p, turns on switch SW2 of primary latch 22m, and the negative edge of clock CK2, CK2n, turns off switch SW2 of primary latch 22m.

[0140] Clock CK3 is input to the control terminal of switch SW1 of primary latch 23m. The negative edge of clock CK3, referred to as CK3n, turns on switch SW1 of primary latch 23m, and the positive edge of clock CK3, referred to as CK3p, turns off switch SW1 of primary latch 23m. Clock CK3 is also input to the control terminal of switch SW2 of primary latch 23m. The positive edge of clock CK3, CK3p, turns on switch SW2 of primary latch 23m, and the negative edge of clock CK3, CK3n, turns off switch SW2 of primary latch 23m.

[0141] Clock CK4 is input to the control terminal of switch SW1 of primary latch 24m. The negative edge of clock CK4, referred to as CK4n, turns on switch SW1 of primary latch 24m, and the positive edge of clock CK4, referred to as CK4p, turns off switch SW1 of primary latch 24m. Clock CK4 is also input to the control terminal of switch SW2 of primary latch 24m. The positive edge of clock CK4, CK4p, turns on switch SW2 of primary latch 24m, and the negative edge of clock CK4, CK4n, turns off switch SW2 of primary latch 24m.

[0142] Each of the primary latches 21m to 24m is configured to read the output level Din of NOT gate 20 at the sampling time corresponding to the occurrence of the negative edges CK1n, CK2n, CK3n, CK4n of the corresponding clocks CK1 to CK4.

[0143] In addition, such as Figure 6 As shown, primary latch 21m is configured to hold the output level Din of NOT gate 20 at the sampling time corresponding to the occurrence of the positive edge CK1p of clock CK1 (see reference tlm1 in the figure), and primary latch 22m is configured to hold the output level Din of NOT gate 20 at the sampling time corresponding to the occurrence of the positive edge CK2p of clock CK2 (see reference tlm2 in the figure).

[0144] Similarly, primary latch 23m is configured to hold at the sampling time corresponding to the occurrence of the positive edge CK3p of clock CK3 (see reference tlm3), i.e., latch the output level Din of NOT gate 20, and primary latch 24m is configured to hold at the sampling time corresponding to the occurrence of the positive edge CK4p of clock CK4 (see reference tlm4), i.e., latch the output level Din of NOT gate 20.

[0145] Subsequently, the secondary latches 21s to 24s are configured to hold simultaneously with the timing of the occurrence of the negative edge CK1n of clock CK1 (see attached figure label tls), i.e., latch, output data items Do1 to Do4.

[0146] That is, the primary latches 21m to 24m latch the output level of NOT gate 20 at different sampling times tlm1 to tm4, corresponding to the positive edges of different clocks CK1 to CK4 (CK1p to CK4p). This allows the output level of NOT gate 20 to be latched at different sampling times 1×Δt, 2×Δt, 3×Δt, and 4×Δt relative to the positive edge of each pulse of the sampling clock reference signal CKs, even when clock CK1 is commonly input to the secondary latches 21s to 24s in the second state. This enables the latch modules 21 to 24 to operate stably.

[0147] As described above, each of encoders 31 to 34 is configured to read and encode the corresponding data item latched by the corresponding latch module 21, 22, 23 or 24 into z-bit data in sync with the occurrence of each pulse of the sampling clock reference signal CKs, with clocks CK1 to CKm generated based on the sampling clock reference signal CKs.

[0148] That is, let us consider the case where encoder 31 reads the output data item Do1 latched by latch module 21 at the sampling time corresponding to the occurrence of any pulse (current pulse) of sampling clock reference signal CKs.

[0149] In this case, the output data item Do1 is reliably latched by the latch module 21 at the sampling time corresponding to the occurrence timing tls of the negative edge CK1n of the pulse of the clock CK1 generated immediately before the sampling clock reference signal CKs. Therefore, this allows the encoder 31 to be able to respond to the occurrence of the current pulse of the sampling clock reference signal CKs (see... Figure 6 The output data item Do1 latched by latch module 21 is stably read at the sampling time corresponding to the attached reference tEn, making it possible for encoder 31 to stably encode the output data item Do1.

[0150] Similar to encoder 31, encoder 32 responds to the current pulse of the sampling clock reference signal CKs (see [link]). Figure 6 The data item Do2 latched by latch module 22 is stably read at the sampling time corresponding to the reference tEn in the attached figure, making it possible for encoder 32 to stably encode the output data item Do2.

[0151] Similarly, encoder 33 responds to the current pulse of the sampling clock reference signal CKs (see...) Figure 6 The encoder 33 stably reads the data item Do3 latched by latch module 23 at the sampling time corresponding to the reference tEn in the attached diagram, making it possible for the encoder 33 to stably encode the output data item Do3. Additionally, the encoder 34 reads the data item Do3 at the sampling clock reference signal CKs at the current pulse (see attached diagram). Figure 6 The data item Do4 latched by latch module 24 is stably read at the sampling time corresponding to the reference tEn in the attached figure, making it possible for encoder 34 to stably encode the output data item Do4.

[0152] The output data items Do1 to Do4 from encoders 31 to 34 to the next stage can undergo any processing using the sampling clock reference signal CKs.

[0153] A / D converters based on comparison examples

[0154] Figure 7 This is based on the corresponding Figure 4 Enlarged view of latch modules 21 to 24, such as the first delay unit DU(G1), in the comparative example A / D converter 100.

[0155] like Figure 7 As shown, the secondary latches 21s to 24s for each of the n delay units DU are configured to latch the output of the corresponding delay unit in the delay unit DU at the sampling time corresponding to the corresponding occurrence of different clocks CK1 to CK4, which are used as operating clocks by the corresponding primary latches 21m to 24m.

[0156] The configuration described above for the A / D converter 100 according to the comparative example requires four main wirings W1 to W4 to connect between the CMOS inverters M2a1 to M2a4 used for output sampling clocks CK1 to CK4 and the secondary latches 21s to 24s, respectively. This results in an increase in the number of wirings connecting the clock generator 3 to the corresponding secondary latches 21s to 24s, and an increase in the length of each wiring, leading to a larger footprint of wiring in the component layout space of the A / D converter 100 according to the comparative example.

[0157] Specifically, if the A / D converter 100 according to the comparative example uses three-dimensional transistors such as FinFETs or Gate-All-Around (GAA) FETs, which can be implemented using more refined CMOS manufacturing processes, then the proportion of the wiring used to connect the clock generator 3 and the corresponding secondary latches 21s to 24s in the total component layout space of the A / D converter 100 according to the comparative example is increased. Therefore, this results in a relatively larger footprint for the latch modules 21 to 24 in the component layout space allocated to the pulse delay circuit 2 in the A / D converter 100 according to the comparative example. This may lead to a decrease in the performance of the A / D converter according to the comparative example and an increase in the manufacturing cost of the A / D converter 100 according to the comparative example.

[0158] A / D converter according to the first embodiment

[0159] Conversely, A / D converter 1 is configured such that clock CK1 is commonly input to the secondary latches 21s to 24s of the corresponding latch modules 21 to 24 for each delay unit DU. Therefore, this configuration allows all secondary latches 21s to 24s to share a single clock CK1, enabling the CMOS inverter M2a1 (see [reference]) for outputting the sampling clock CK1 to the secondary latches 21s to 24s to be connected using a single main wiring W1. Figure 3 This makes it possible.

[0160] Therefore, this results in a reduction in the number of wires connecting the clock generator 3 to the corresponding secondary latches 21s to 24s, leading to a smaller footprint of individual wires in the component layout space of the A / D converter 1 according to the first embodiment. This, in turn, results in a reduction in the size of the A / D converter 1 and an effective improvement in the pulse delay characteristics of the A / D converter 1, making it possible to improve the manufacturing yield of the A / D converter 1 at a lower cost.

[0161] The above configuration of A / D converter 1 is attributed to the minimization of the adverse effects of parasitic impedances (such as parasitic capacitance and / or parasitic resistance) in the wiring used for transmitting clocks CK1 to CK4, making it possible to maintain the performance reliability of A / D converter 1.

[0162] The above-described configuration of the A / D converter 1 further reduces the adverse effects of parasitic impedances (such as parasitic capacitance and / or parasitic resistance) in the wiring used to read the pulses P1 to Pn output from the respective delay units G1 to Gn, making it possible for each latch 21 to stably read the state of each of the pulses P1 to Pn output from the respective delay units G1 to Gn.

[0163] Furthermore, in the A / D converter 1 according to the first embodiment, the pulse delay unit 2 is configured such that the delay units DU are cascaded together to form a ring delay line. This results in a further reduction in the size of the A / D converter 1 and a more effective improvement in the pulse delay characteristics of the A / D converter 1.

[0164] Each of the encoders 31 to 34 according to the first embodiment is configured to read and encode data latched by the corresponding latch in latches 21 to 24 using each pulse of the sampling clock reference signal CKs used to generate clocks CK1 to CKm. Therefore, this configuration enables:

[0165] (1) The encoder 31 is capable of stably reading and encoding the data item Do1 output from the secondary latch 21s;

[0166] (2) The encoder 32 is capable of stably reading and encoding the data item Do2 output from the secondary latch 22s;

[0167] (3) The encoder 33 is capable of stably reading and encoding the data item Do3 output from the secondary latch 23s;

[0168] (2) The encoder 34 is able to reliably read and encode the data item Do4 output from the secondary latch 24s.

[0169] Second Embodiment

[0170] The following is for reference. Figure 8A / D converter 1A according to a second embodiment is described. The structure and / or function of A / D converter 1A according to the second embodiment are mainly the same as those of A / D converter 1, except for the following points. Therefore, the main differences are described below.

[0171] According to the second embodiment, the A / D converter 1A includes a pulse position digitization circuit 4A, and the pulse position digitization circuit 4A includes latch modules 221 to 224 in place of latch modules 21 to 24.

[0172] Each of the latch modules 221 provided for a corresponding delay unit DU includes a primary latch 21m and a secondary latch 221s connected in series with each other, and each of the latch modules 222 provided for a corresponding delay unit DU includes a primary latch 22m and a secondary latch 222s connected in series with each other. Similarly, each of the latch modules 223 provided for a corresponding delay unit DU includes a primary latch 23m and a secondary latch 223s connected in series with each other, and each of the latch modules 224 provided for a corresponding delay unit DU includes a primary latch 24m and a secondary latch 224s connected in series with each other.

[0173] Each of the second-stage primary latches 221s to 224s is designed as a CMOS dynamic circuit that latches the corresponding output data item among output data items Do1 to Do4 without using a feedback loop.

[0174] The circuit configurations of the corresponding second-level secondary latches 221s to 224s are identical to each other, such that the reference numerals of the corresponding components assigned to the second-level secondary latch 221s are used to assign the corresponding components of each of the other second-level secondary latches 222s to 224s.

[0175] The electrical connections between the components of secondary latch 221s, which are selected as typical examples of secondary latches 221s to 224s, are described below. Similarly, descriptions of the electrical connections between the components of each of the other secondary latches 222s to 224s are omitted.

[0176] The secondary latch 221s includes switches SW3 and SW4, a NOT gate Gc, and a capacitor C1 having opposing first and second electrodes.

[0177] The output level Dm1 of the primary latch 21m is input to the first terminal of switch SW3, and the second terminal of switch SW3 is connected to the input terminal of the NOT gate Gc. The output terminal of the NOT gate Gc is connected to the encoder 31, so that the output of the NOT gate Gc is input to the encoder 31 as the output data item Do1.

[0178] For example, the NOT gate Gc includes a CMOS inverter (with parasitic capacitance at its input serving as the gate input capacitance), and additional parasitic capacitance is generated on the wiring connecting the second terminal of switch SW3 to the input terminal of the NOT gate Gc.

[0179] These parasitic capacitances are shown as capacitor C1 between the common signal ground of the secondary latch 221s and the wiring connected between the second terminal of switch SW3 and the input terminal of NOT gate Gc. Therefore, it is not necessary to ensure predetermined space in the component layout space allocated to the secondary latch 221s.

[0180] Clock CK1 is input to the control terminal of switch SW3. The positive edge CK1p of clock CK1 turns on switch SW3, and the negative edge CK1n turns off switch SW3.

[0181] When switch SW3 is turned on, the inverted output level Dm1 of primary latch 21m is output as output data item Do1 to encoder 31 and charged into capacitor C1.

[0182] Conversely, the off state of switch SW3 causes switch SW3 to turn off. At this time, the secondary latch 221s maintains the level of the output data item Do1 based on the charged capacitor C1, regardless of the change in the output level Dm1 of the primary latch 21m when switch SW3 is off.

[0183] Compared to the number of components constituting each of the secondary latches 21s to 24s, this configuration of the pulse position digitization circuit 4A reduces the number of components constituting each of the secondary latches 221s to 224s. That is, compared to the space occupied by the corresponding secondary latches 21s to 24s of the pulse position digitization circuit 4 according to the first embodiment, this configuration of the pulse position digitization circuit 4A results in a smaller space occupied by each of the secondary latches 221s to 224s via the NOT gate Gd and the switch SW4. Therefore, it is possible to improve the manufacturing yield of the A / D converter 1A at a lower cost.

[0184] The above configuration of the A / D converter 1A is attributed to the minimization of the adverse effects of parasitic impedances (such as parasitic capacitance and / or parasitic resistance) in the wiring used for transmitting clocks CK1 to CK4, making it possible to maintain the performance reliability of the A / D converter 1A.

[0185] If a certain amount of margin is ensured in the component layout space of the A / D converter 1A, the layout of the pulse position digitization circuit 4A can be designed to obtain an additional capacitor as capacitor C1, so that the level of the output data item Do1 can be more stable.

[0186] Third Embodiment

[0187] The following is for reference. Figures 9 to 11 A / D converter 301 according to a third embodiment is described. The structure and / or function of A / D converter 301 according to the third embodiment are substantially the same as those of A / D converter 1, except for the following points. Therefore, the main differences are described below.

[0188] The pulse delay circuit 2 according to the first embodiment is configured such that the delay units DU including NAND gates G1 and NAND gates G2 to G15 are cascaded in a ring configuration, but this disclosure is not limited to this configuration.

[0189] Specifically, the delay units DU do not need to be connected to each other in a ring shape, as long as they are connected in series.

[0190] From this perspective, the A / D converter 301 according to the third embodiment includes a pulse delay line 302, which includes n delay units DU connected in series with each other in a non-circuitous manner. That is, the n delay units DU are designed to form an open-circuit delay line.

[0191] Specifically, the first to the nth delay units DU include NOT gates G1 to Gn, respectively.

[0192] Each of the first to nth delay units G1 to Gn has an input terminal and an output terminal.

[0193] The input terminals of each delay unit G2, ..., Gn, except for the first delay unit G1, are cascaded to the output terminals of the immediately preceding delay units G1, ..., Gn-1. The pulse signal PA is input to the first input terminal of the first delay unit G1.

[0194] The output terminals of the corresponding delay units G1 to Gn are also connected to the pulse position digitization circuit 4, so that the pulse signal output from each of the delay units G1 to Gn is input to the pulse position digitization circuit 4.

[0195] Similar to the first embodiment, the output terminal of the first delay unit DU(G1) is connected to latch modules 21 to 24 provided for the first delay unit DU(G1) via NOT gate 20. The output terminal of the second delay unit DU(G2) is connected to latch modules 21 to 24 provided for the second delay unit DU(G2) via NOT gate 20, ..., and the output terminal of the nth delay unit DU(Gn) is connected to latch modules 21 to 24 provided for the nth delay unit DU(Gn) via NOT gate 20.

[0196] When the pulse signal PA is input to the input terminal of the first delay unit G1, the first delay unit G1 operates to transmit the pulse signal PA to the next delay unit G2, while delaying the pulse signal by a predetermined delay time Td.

[0197] Each of the remaining delay units G2 to Gn-1, except for the last delay unit Gn, will sequentially transmit the pulse signal PA transmitted from the immediately preceding delay unit to the next delay unit, while delaying the pulse signal by a predetermined delay time Td.

[0198] The analog input voltage signal Vin is input as a power supply voltage to each of the delay units G1 to Gn, such that the power supply voltage input to each of the delay units G1 to Gn activates the corresponding delay unit in G1 to Gn.

[0199] The aforementioned pulse delay unit 302 is configured such that each pulse of the pulse signal PA is input to the first delay unit DU(G1) at each period Ts of the sampling clock reference signal CKs (see...). Figure 10 This enables the transmission of each pulse of the pulse signal PA through the delay unit DU (G1 to Gn) to begin.

[0200] Specifically, each of the encoders 31 to 34 of the pulse position digitization circuit 304 according to the third embodiment is configured as follows:

[0201] (1) Obtain the phase difference between the positive or negative edge of each pulse of the pulse signal PA and the corresponding positive or negative edge of the corresponding pulse of the corresponding clock in clocks CK1 to CK4;

[0202] (2) For each pulse of the pulse signal PA, based on the obtained phase difference, the number of delay units DU that the corresponding pulse of the pulse signal PA passes through is digitized, and the digitized value is output as the corresponding z-bit data in z-bit data O1 to z-bit data O4.

[0203] The digitization of the phase difference between the positive or negative edge of each pulse of the pulse signal PA and the corresponding positive or negative edge of the corresponding pulse of the corresponding clock in clocks CK1 to CK4 makes it possible to eliminate the latch-subtractor modules 35 to 38 (latches 41 to 44 and subtractors 51 to 54), resulting in a simpler configuration of the pulse position digitization circuit 304. That is, z-bit data O1 to z-bit data O4 are directly transmitted as digital numerical data items DT1 to DT4 from the corresponding encoders 31 to 34 to the adder 5.

[0204] The remaining configuration of the A / D converter 301 according to the third embodiment is substantially the same as that of the A / D converter 1 or 1A according to the first or second embodiment, and the description of the remaining configuration of the A / D converter 301 is omitted.

[0205] As described above, the encoder unit 360 according to the third embodiment includes only encoders 31 to 34, which reduces the number of components constituting the encoder unit 360 compared to the number of components constituting each of the encoder units 60 according to the first and second embodiments. Therefore, this results in a smaller footprint for the encoder unit 360 compared to the footprint of each of the encoder units 60 according to the first and second embodiments.

[0206] As described above, the pulse delay circuit 302 of the A / D converter 301 according to the third embodiment includes n delay units DU, which are designed to form an open-circuit delay line.

[0207] This configuration of the A / D converter 301 according to the third embodiment, which achieves the same beneficial effects as described in the first embodiment, eliminates the need for components such as NAND (NAD) gates and subtractors required for the n delay units DU designed as a ring delay line. Therefore, this results in a further reduction in the size of the A / D converter 301 and a further effective improvement in the pulse delay characteristics of the A / D converter 301.

[0208] Revise

[0209] However, this disclosure is not limited to the first to third embodiments described above, and various modifications or extensions can be made as follows.

[0210] Although each of the NOT gates G2 to Gn in each of the first and second embodiments includes a single-stage CMOS inverter, each of the NOT gates G2 to Gn in accordance with the present disclosure may include two-stage CMOS inverters cascaded together.

[0211] Compared to each of the NOT gates G2 to Gn, which include a single-stage CMOS inverter, this modification reduces the dispersion of the digital numerical data item DTA obtained by multiple A / D conversion operations performed by A / D converter 1 or 1A.

[0212] Each of the A / D converters 1, 1A and 301 according to the first to third embodiments is configured such that clock CK1 selected from clocks CK1 to CKm (m=4) is input to all secondary latches 21s to 24s or 221s to 224s as a second clock, but this disclosure is not limited thereto.

[0213] Specifically, multiple clocks such as clocks CK1 and CK2 can be selected from clocks CK1 to CKm (m=4) as second clocks, and each of the selected clocks can be input together to at least two of the secondary latches 21s to 24s or 221s to 224s as second clocks.

[0214] For example, clocks CK1 and CK2 can be selected from clocks CK1 to CKm (m=4) as the second clock, and clock CK1 can be input to the secondary latches 21s and 22s or 221s and 222s together, and clock CK2 can be input to the secondary latches 23s and 24s or 223s and 224s together.

[0215] Furthermore, clocks such as clock CK1 (a first selection) from clocks CK1 to CKm (m=4) can be input to (m-1) secondary latches such as secondary latches 21s, 22s, and 23s, and clocks such as clock CK2 (a second selection) from clocks CK1 to CKm (m=4) can be input to the remaining secondary latches such as secondary latch 24s.

[0216] Specifically, a clock input such as clock CK1 can be selected and fed into up to (m-1) secondary latches.

[0217] The primary latches 21m to 24m for each delay unit DU are configured to latch the state of the delayed pulse output from the corresponding delay unit DU through the NOT gate 20 at the sampling time corresponding to the corresponding pulses of different clocks CK1, CK2, CK3, and CK4. Furthermore, each of the secondary latches 21s to 24s is configured to latch the output of the corresponding primary latch among the primary latches 21m to 24m at the sampling time corresponding to the occurrence of each pulse of clock CK1.

[0218] Each of the secondary latches 21s to 24s can be configured to latch the output of the corresponding primary latch among the primary latches 21m to 24m at the sampling time corresponding to the occurrence of each pulse of a reference clock, the reference clock being generated based on at least one of the clocks CK1 to CK4 used as a second clock. That is, any of the clocks CK1 to CK4 can undergo any pulse shaping process, such as pulse inversion, and then be used as a second clock.

[0219] In summary, each of the A / D converters according to this disclosure can be configured such that:

[0220] (1) A second clock generated based on the first clock is input to at least the first and second secondary latches selected from the secondary latches 21s to 24s, such as secondary latches 21s and 22s;

[0221] (2) The at least first and second secondary latches are each configured to latch output data items from at least the first and second primary latches (such as primary latches 21m and 22m) corresponding to the sampling time corresponding to the occurrence of each pulse of the second clock.

[0222] Reducing the phase difference Δt between each adjacent pair of clocks CK1, CK2, CK3, and CK4 increases the number m (m=4) of latch modules 21 to 24 connected in parallel and configured for each delay unit DU. The larger the number m of latch modules 21 to 24 (m=4) connected in parallel and configured for each delay unit DU, the higher the resolution and accuracy of the digital numerical data item DTA.

[0223] As described in Patent Publication No. 2004-007385, a cycle count counter can be provided after the pulse delay circuit 2. The cycle count counter is configured to count the number of times the pulse signal has cycled through the pulse delay circuit 2.

[0224] Each of the modified subtractors 51 to 54 can be configured to subtract the corresponding code data from code data O1, code data O2, code data O3, and code data O4 output from encoders 31, 32, 33, and 34 at the sampling time corresponding to the occurrence of each pulse of the sampling clock reference signal CKs from the previous code data stored in the corresponding latches in latches 41 to 44, thereby calculating the deviation data between the current code data and the previous code data. Then, each of the subtractors 51 to 54 can be configured to output the deviation data as the corresponding digital value data item DT1 to DT4 to adder 5.

[0225] The configurations and / or functions of the first to third embodiments can be combined with each other. Modified embodiments created by eliminating a portion of the selected embodiments in the first to third embodiments can be considered as embodiments of this disclosure, as long as the modified embodiment solves the above-described problems and falls within the scope of this disclosure.

[0226] Various inventive applications that can be considered within the scope of this disclosure can be considered embodiments of this disclosure.

[0227] Although illustrative embodiments of this disclosure have been described herein, this disclosure is not limited to the embodiments described herein, but includes any and all embodiments having modifications, omissions, combinations (e.g., across aspects of various embodiments), adaptations, and / or alternatives that will be understood by those skilled in the art based on this disclosure. Limitations in the claims are to be interpreted broadly based on the language used in the claims and are not limited to the examples described in this specification or during the implementation of the application, which will be interpreted as non-exclusive.

Claims

1. An analog-to-digital converter, comprising: A pulse delay circuit includes a plurality of delay units connected in series with each other. The pulse delay circuit is configured to allow a pulse signal to pass through it while delaying the pulse signal by each of the plurality of delay units. The delay time of each of the plurality of delay units depends on the level of the analog input signal input to each of the plurality of delay units. as well as A plurality of latch modules are provided for each of the delay units, and each latch module provided for each of the delay units includes: Multiple primary latches are configured to latch the outputs of corresponding delay units in the delay units at the corresponding sampling times of different first clock cycles; Multiple secondary latches are used to latch the outputs of the corresponding primary latches; The plurality of secondary latches include at least first and second secondary latches, and the plurality of primary latches include at least first and second primary latches corresponding to the at least first and second secondary latches, respectively. Each of the at least first and second secondary latches is configured to latch the output of a corresponding primary latch among the at least first and second primary latches at a sampling time of a common second clock, the common second clock being based on at least one of the first clocks; and The encoder unit is configured to encode output data items from each of the plurality of secondary latches into digital numerical data items.

2. The analog-to-digital converter according to claim 1, wherein: Each of the plurality of primary latches is cascaded to a corresponding secondary latch among the plurality of secondary latches.

3. The analog-to-digital converter according to claim 1 or 2, wherein: Each latch module in the latch module includes a plurality of primary latches, all of which are designed as static circuits. These static circuits include feedback loops and are configured to latch the output of the corresponding delay unit in the delay unit. Each latch module in the latch module includes a plurality of secondary latches, which are designed as dynamic circuits configured to latch the output of a corresponding primary latch among the plurality of primary latches.

4. The analog-to-digital converter according to any one of claims 1 to 3, wherein: The plurality of delay units are connected in series with each other in a ring configuration, such that the pulse delay circuit is configured as a ring delay line.

5. The analog-to-digital converter according to any one of claims 1 to 3, wherein: The plurality of delay units are connected in series with each other in a non-circuitous manner, such that the pulse delay circuit is configured as an open-circuit delay line.

6. The analog-to-digital converter according to any one of claims 1 to 5, wherein: The common second clock is configured to be input to all of the plurality of secondary latches; and Each of the plurality of secondary latches is configured to latch the output of the corresponding primary latch among the plurality of primary latches at the sampling time of the common second clock.

7. The analog-to-digital converter according to any one of claims 1 to 6, wherein: The encoder unit includes multiple encoders, each encoder being configured to, in response to a master clock, read the output data item from a corresponding secondary latch among the multiple secondary latches into the digital value data item; and At least one of the first clock and the second clock is generated based on the master clock.

Images