High performance laser communication interface supporting multiple rates

Abstract

The application provides a kind of high-performance laser communication interface supporting multi-rate, wherein SerDes drive module receives a way of communication data through input branch, generates parallel multi-way communication data by duplicating a way of communication data, and outputs a way of multi-way communication data through multiple output branches respectively;SerDes drive module is provided with a filter on each output branch, and the filter filters a way of multi-way communication data output by the output branch according to the corresponding communication rate, to obtain the filter communication data corresponding to the output branch;SerDes multi-way switch connects the target output branch of SerDes drive module, and sends the filter communication data corresponding to the target output branch to the SerDes interface of FPGA.The application is suitable for multi-rate laser communication system, only occupies one SerDes interface inside FPGA, and has higher transmission gain when transmitting at low rate.

Description

Technical Field

[0001] This invention relates to the field of laser communication technology, and more specifically, to a high-performance laser communication interface that supports multiple rates. Background Technology

[0002] Laser communication is a method of information transmission that utilizes the characteristics of lasers (such as pulses and phases), and it has been successfully applied in satellite communication networks. However, traditional single-rate satellite communication methods cannot fully leverage the large bandwidth advantage of laser communication due to the real-time changing channel states caused by the relative motion of satellites. Multi-rate switching communication solves the channel utilization bottleneck between networked satellites, and the highly reliable multi-rate switching transmission based on satellite laser communication signals is of great significance to the development of satellite backbone transmission networks.

[0003] Many existing research papers only implement multi-rate switching in the digital domain without optimizing the receiver communication interface. For example, the master's thesis "Design of Rate-Adaptive Laser Wireless Communication Terminal System" published by Huazhong University of Science and Technology uses a single receiver communication interface with fixed sensitivity, offering no performance gain at low communication rates. Another example is the coherent receiver used in "Adaptive probabilistic shaped modulation for high-capacity free-space optical links, 2020:6529-6541", which is complex and costly to implement.

[0004] Therefore, how to solve the problems of high cost, complex operation, and difficulty in promotion and implementation of existing laser communication rate switching technology has become an urgent issue to be addressed at this stage. Summary of the Invention

[0005] In view of this, to solve the above problems, the present invention provides a high-performance laser communication interface that supports multiple rates, the technical solution of which is as follows:

[0006] A high-performance laser communication interface supporting multiple rates, the high-performance laser communication interface comprising: a SerDes driver module, multiple filters and a SerDes multiplexer, wherein the SerDes driver module has one input branch and multiple output branches, and each output branch is provided with a filter;

[0007] The SerDes driver module is used to receive one channel of communication data through the input branch; copy the one channel of communication data to generate multiple channels of parallel communication data; and output the multiple channels of communication data through the multiple output branches, with each output branch outputting one channel of the multiple channels of communication data.

[0008] The filter is used to filter one of the multiple communication data output by the output branch according to the corresponding communication rate, so as to obtain the filtered communication data corresponding to the output branch.

[0009] The SerDes multiplexer is used to connect the target output branch of the SerDes driver module and send the filtered communication data corresponding to the target output branch to the SerDes interface of the FPGA.

[0010] Preferably, the bandwidth of the filter is a fixed value, and the bandwidth of the filter is the bandwidth corresponding to the corresponding communication rate.

[0011] Preferably, the high-performance laser communication interface further includes: a front-end multi-rate photoelectric conversion module;

[0012] The front-end multi-rate photoelectric conversion module is used to convert the received laser signal into an electrical signal and output the electrical signal to the SerDes driver module.

[0013] Preferably, the communication rate of the front-end multi-rate photoelectric conversion module meets the maximum communication rate specified by the communication protocol.

[0014] Preferably, both the SerDes driver module and the SerDes multiplexer are implemented using Verilog language and programmed onto the FPGA board.

[0015] The plurality of filters are composed of fixed filters soldered onto the peripheral circuitry of the FPGA.

[0016] Preferably, the SerDes multiplexer used to connect the target output branch of the SerDes driver module is specifically used for:

[0017] In the initial state, the output branch containing the filter with the lowest communication rate among the multiple output branches is connected.

[0018] Preferably, the SerDes multiplexer used to connect the target output branch of the SerDes driver module is specifically used for:

[0019] Receive the control signal from the FPGA, the control signal containing the target communication rate to be switched to; connect to one of the output branches where the filter with the communication rate of the target communication rate is located.

[0020] Preferably, the SerDes multiplexer used to connect the target output branch of the SerDes driver module is specifically used for:

[0021] In the absence of a new control signal from the FPGA, maintain connection to one of the output branches containing the filter with a communication rate of the target communication rate among the plurality of output branches.

[0022] Compared with the prior art, the beneficial effects achieved by the present invention are as follows:

[0023] This invention provides a high-performance laser communication interface supporting multiple rates. In this interface, a SerDes driver module receives one communication data stream through an input branch, replicates this stream to generate multiple parallel communication data streams, and outputs one stream from each of the multiple streams through multiple output branches. Each output branch of the SerDes driver module has a filter that filters one stream of communication data output from its corresponding output branch according to the corresponding communication rate, obtaining the filtered communication data for that output branch. A SerDes multiplexer connects to the target output branch of the SerDes driver module and sends the filtered communication data corresponding to the target output branch to the SerDes interface of the FPGA. This invention uses a split-path filtering and output selection structure, is suitable for multi-rate laser communication systems, occupies only one SerDes interface within the FPGA, is low-cost and simple to design, and has high transmission gain at low transmission rates. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0025] Figure 1 A schematic diagram of the structure of a high-performance laser communication interface supporting multiple rates provided in an embodiment of the present invention;

[0026] Figure 2 Another structural schematic diagram of a high-performance laser communication interface supporting multiple rates provided in an embodiment of the present invention;

[0027] Figure 3 This is another schematic diagram of a high-performance laser communication interface supporting multiple rates provided in an embodiment of the present invention;

[0028] Figure 4 This is another schematic diagram of a high-performance laser communication interface supporting multiple rates provided in an embodiment of the present invention;

[0029] Figure 5 This is another schematic diagram of a high-performance laser communication interface supporting multiple rates provided in an embodiment of the present invention;

[0030] Figure 6 An experimental block diagram of a high-performance laser communication interface supporting multiple rates provided in an embodiment of the present invention;

[0031] Figure 7 The image shows the bit error rate curves for low-speed transmission of the traditional filterless scheme and the filter-equipped scheme of this invention. Detailed Implementation

[0032] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0033] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0034] To facilitate understanding of this invention, the relevant concepts mentioned in this invention are briefly explained below:

[0035] SerDes: SerDes is short for SERializer / DESerializer, a mainstream serial communication technology. At the transmitting end, it combines multiple low-speed signals into a high-speed serial signal. After passing through the transmission medium, it is then converted back into multiple low-speed signals at the receiving end. This technology reduces the number of transmission channels and device pins, thus lowering communication costs.

[0036] FPGA stands for Field-Programmable Gate Array. It is a further development based on programmable devices such as PAL, GAL, and CPLD. It emerged as a semi-custom circuit in the field of Application-Specific Integrated Circuits (ASICs), solving the shortcomings of custom circuits and overcoming the limitation of the limited gate count of original programmable devices.

[0037] ADC: The full name of the English word is Analog to Digital Converter, also known as an A / D converter. It is an electronic component that converts an analog signal with continuous time and amplitude into a digital signal with discrete time and amplitude.

[0038] IBERT stands for Integrated Bit Error Ratio Tester. It is a test tool integrated into FPGA circuits by Xilinx and is commonly used by developers to test whether high-speed interfaces have problems.

[0039] See Figure 1 , Figure 1 This is a schematic diagram of the structure of a high-performance laser communication interface supporting multiple rates, provided in an embodiment of the present invention. Figure 1 As shown, the high-performance laser communication interface includes: a SerDes driver module 10, multiple filters 20 and a SerDes multiplexer 30. The SerDes driver module 10 has one input branch and multiple output branches, and each output branch is provided with a filter 20.

[0040] SerDes driver module 10 is used to receive one communication data through the input branch; to copy one communication data to generate multiple parallel communication data, and to output multiple communication data through multiple output branches, with each output branch outputting one of the multiple communication data;

[0041] Filter 20 is used to filter one of the multiple communication data output by the output branch according to the corresponding communication rate, so as to obtain the filtered communication data corresponding to the output branch.

[0042] SerDes multiplexer 30 is used to connect the target output branch of SerDes driver module 10 and send the filtered communication data corresponding to the target output branch to the SerDes interface of FPGA.

[0043] In this embodiment of the invention, the SerDes driver module 10 has one input branch and N output branches, that is, the SerDes driver module 10 is a 1:N SerDes driver module, which can copy one communication data received by the input branch to generate N parallel communication data (each of the N communication data is the same as one communication data received by the input branch), and output these N communication data through the N output branches, wherein each of the N output branches outputs one of the N communication data.

[0044] See Figure 2 , Figure 2 This is another schematic diagram of a high-performance laser communication interface supporting multiple rates, provided as an embodiment of the present invention. (See diagram below.) Figure 2As shown, the SerDes driver module 10 is a 1:N SerDes driver module. Correspondingly, each of the N output branches of the 1:N SerDes driver module is equipped with a filter 20, meaning there are N filters 20, and each of the N filters 20 has a corresponding communication rate (…). Figure 2 (In this context, communication rates are represented as communication rate 1, communication rate 2, ..., communication rate N).

[0045] Furthermore, since each output branch of the SerDes driver module 10 is equipped with a filter 20, which is a fixed-current filter. See also... Figure 2 Each of the N filters 20 has a corresponding communication rate. Therefore, for each filter 20, it can filter one of the multiple communication data output by its output branch according to its corresponding communication rate, thereby filtering out out-of-band noise and obtaining the filtered data corresponding to its output branch, i.e., the filtered communication data.

[0046] It should be noted that in the embodiments of the present invention, all filters 20 are fixed bandwidth filters, that is, the bandwidth of filter 20 is a fixed value, and the bandwidth of filter 20 is specified by the communication protocol and is the bandwidth corresponding to the corresponding communication rate.

[0047] Furthermore, the SerDes multiplexer 30 is connected to multiple output branches of the SerDes driver module 10. See also... Figure 2 The N output branches of the 1:N SerDes driver module are filtered by their respective filters 20, each outputting a filtered communication data path. The SerDes multiplexer 30 can select and connect an output branch (i.e., the target output branch) corresponding to a certain communication rate of the 1:N SerDes driver module based on the received control signal. This sends the filtered communication data path corresponding to the target output branch to the SerDes interface of the FPGA for subsequent signal processing. This allows the SerDes multiplexer 30 to select the filter path currently connected to the FPGA.

[0048] In specific implementation, the initial state of the SerDes multiplexer 30 is the filter path corresponding to the lowest communication rate. That is, the SerDes multiplexer 30, used to connect the target output branch of the SerDes driver module 10, is specifically used for:

[0049] In the initial state, the output branch containing the filter 20 with the lowest communication rate among the multiple output branches is connected.

[0050] See also Figure 2Since each of the N filters 20 has a corresponding communication rate, the SerDes multiplexer 30 can select to connect to the output branch (i.e., the target output branch) of the filter 20 with the lowest communication rate in the initial state (i.e., the state in which no control signal is received).

[0051] Furthermore, in this embodiment of the invention, the SerDes multiplexer 30 can quickly switch the corresponding filter path according to FPGA instructions. That is, the control signal for switching the communication rate of the SerDes multiplexer 30 can be generated by the FPGA, and the supported switching communication rate is constrained by the communication protocol. The SerDes multiplexer 30, used to connect the target output branch of the SerDes driver module 10, is specifically used for:

[0052] Receives control signals from the FPGA, which include the target communication rate to be switched to; connects to one of the output branches where the filter 20 with the target communication rate is located among multiple output branches.

[0053] See Figure 3 , Figure 3 This is another schematic diagram of a high-performance laser communication interface supporting multiple rates, provided as an embodiment of the present invention. Figure 3 In the high-performance laser communication interface shown, the SerDes driver module 10 is a 1:N SerDes driver module, and correspondingly, there are N filters 20. Figure 3 The FPGA sends control signals to the SerDes multiplexer 30 to perform rate control for switching communication rates.

[0054] In this embodiment of the invention, the control signal of the SerDes multiplexer 30 is generated by an FPGA. The SerDes multiplexer 30 selects and connects the corresponding filter path based on the control signal from the FPGA, eliminating the need for a high-precision ADC and a tunable filter, thus simplifying implementation and reducing cost. Specifically, the FPGA control signal includes the communication rate (i.e., the target communication rate) of the filter path to which the SerDes multiplexer 30 is to be switched. Based on this, the SerDes multiplexer 30 can select and connect to an output branch (i.e., the target output branch) containing the filter 20 with the target communication rate.

[0055] Based on this, in this embodiment of the invention, the SerDes multiplexer 30 only performs the filter path switching operation after receiving an instruction from the FPGA; otherwise, it will maintain the selected path from the previous instruction. That is, the SerDes multiplexer 30, used to connect the target output branch of the SerDes driver module 10, is specifically used for:

[0056] In the absence of a new control signal from the FPGA, maintain connection to one of the output branches where filter 20 with the target communication rate is located among the multiple output branches.

[0057] In this embodiment of the invention, when the SerDes multiplexer 30 does not receive a new control signal from the FPGA, it maintains the connection to the filter path connected in response to the previous control signal, that is, the output branch where the filter 20 with the target communication rate is located.

[0058] See Figure 4 , Figure 4 This is another schematic diagram of a high-performance laser communication interface supporting multiple rates, provided as an embodiment of the present invention. (See diagram below.) Figure 4 As shown, in Figure 1 Based on the high-performance laser communication interface shown, a front-end multi-rate photoelectric conversion module 40 may also be included.

[0059] The front-end multi-rate photoelectric conversion module 40 is used to convert the received laser signal into an electrical signal and output the electrical signal to the SerDes driver module 10.

[0060] In this embodiment of the invention, the front-end multi-rate photoelectric conversion module 40 can receive laser signals and convert them into electrical signals, which are then output to the SerDes driver module 10. These electrical signals serve as one channel of communication data received by the input branch of the SerDes driver module 10. Therefore, the high-performance laser communication interface of this embodiment uses a multi-rate optical module, occupies only one SerDes interface within the FPGA, and exhibits good performance gain at low-rate transmission speeds. It is simple to implement and low in cost.

[0061] It should be noted that the front-end multi-rate photoelectric conversion module 40 should support the maximum communication rate allowed by the communication protocol. In other words, the communication rate of the front-end multi-rate photoelectric conversion module 40 meets the maximum communication rate specified by the communication protocol.

[0062] See Figure 5 , Figure 5 This is another schematic diagram of a high-performance laser communication interface supporting multiple rates, provided as an embodiment of the present invention. (See diagram below.) Figure 5 As shown, in Figure 3 Based on the high-performance laser communication interface shown, a front-end multi-rate photoelectric conversion module 40 may also be included.

[0063] To facilitate understanding of the embodiments of the present invention, the following section uses a rate switching experiment to illustrate the specific implementation process of the high-performance laser communication interface supporting multiple rates provided by the embodiments of the present invention. It is understood that the rate switching process from communication rate A to communication rate B is the same as the rate switching process from communication rate B to communication rate A. Therefore, this section uses communication rate A as the initial communication rate and communication rate B as the target communication rate as an example for illustration. The high-performance laser communication interface module supporting multiple rates provided by the embodiments of the present invention includes the following components:

[0064] 1) After the laser signal arrives, the front-end multi-rate photoelectric conversion module 40 performs photoelectric conversion, converting the laser signal into an electrical signal with a communication rate of A (i.e., a single communication data stream with a communication rate of A). Of course, the front-end multi-rate photoelectric conversion module 40 should support the maximum communication rate allowed by the communication protocol.

[0065] 2) Taking SerDes driver module 10 as a 1:N SerDes driver module as an example. After receiving one channel of communication data with a communication rate of A, the 1:N SerDes driver module copies the input electrical signal and outputs N channels of communication data in parallel. The number of parallel output channels N is determined by the number of communication rates that the communication protocol allows to switch.

[0066] 3) For the filters 20 located on each output branch of the 1:N SerDes driver module, the N parallel communication data output by the 1:NS SerDes driver module are filtered out of out-of-band noise by the filters 20 on each output branch, thereby obtaining the filtered communication data corresponding to each output branch. The bandwidth of the filters 20 is limited by the bandwidth corresponding to the communication rate allowed by the communication protocol.

[0067] 4) The SerDes multiplexer 30 selects the currently connected filter path according to the instructions of the FPGA and inputs the corresponding filtered communication data into the SerDes interface of the FPGA to complete the subsequent demodulation processing.

[0068] It should be noted that when the communication rate needs to be switched, the above steps 1), 2), and 3) do not need to be changed. The FPGA sends a control signal to the SerDes multiplexer 30 according to the communication protocol, and the SerDes multiplexer 30 connects the output branch of the filter 20 with a communication rate of B. Then, the filtered communication data of the output branch is input into the SerDes interface of the FPGA to complete the subsequent demodulation processing.

[0069] In the above process, the key to rate switching lies in the reasonable matching of filter bandwidth and signal rate. In this embodiment of the invention, filter 20 (a fixed electrical filter) and SerDes multiplexer 30 are used to achieve efficient matching of filter bandwidth and signal rate.

[0070] It should also be noted that, in practical applications, in this embodiment of the invention, both the SerDes driver module 10 and the SerDes multiplexer 30 are implemented using Verilog language and programmed onto the FPGA board. Furthermore, the multiple filters 20 are composed of fixed filters soldered onto the peripheral circuitry of the FPGA. The communication rate switching method of this invention is easy to implement and promote.

[0071] This invention provides a high-performance laser communication interface that supports multiple data rates. In this embodiment, a bit error rate curve will be used to illustrate the good performance gain of the invention at low data rates. See also... Figure 6 , Figure 6 An experimental block diagram illustrating a high-performance laser communication interface supporting multiple rates, provided as an embodiment of the present invention. (See diagram below.) Figure 6 As shown, in this embodiment of the invention, the generation of transmitted data and the calculation of the bit error rate are implemented by the IBERT function of the FPGA. The transmitting signal is sent through the SerDesA interface of the FPGA by an independent high-speed optical module A, and the received optical power is adjusted by an adjustable optical attenuator. Finally, the high-performance laser communication interface designed in this embodiment of the invention (i.e., Figure 6 The high-performance laser communication interface designed in this embodiment of the invention receives the data from the multi-rate optical module and returns the output data to the SerDes B interface of the FPGA via a 2.5G electrical filter.

[0072] In this embodiment of the invention, the signal modulation format is NRZ, the maximum supported rate of the multi-rate optical module is 10Gbps, and the low-rate transmission rate is 2.5Gbps. See also Figure 7 , Figure 7 For traditional filterless schemes (i.e.) Figure 7 The 10G optical module (without filtering) and the filter-equipped solution of this invention (i.e.) Figure 7 The low-rate transmission bit error rate curve of the 10G optical module + electrical filter shows that the solution of this invention has a significant gain. Taking the case of received optical power (ROP) of -34dBm as an example, the bit error rate of the solution of this invention is three orders of magnitude lower than that of the traditional solution.

[0073] The above provides a detailed description of a high-performance laser communication interface supporting multiple rates provided by the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

[0074] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to the method section.

[0075] It should also be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that elements inherent to a process, method, article, or apparatus that comprises a list of elements, or elements inherent to such processes, methods, articles, or apparatus, are also included. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0076] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A high-performance laser communication interface supporting multiple rates, characterized in that, The high-performance laser communication interface occupies only one SerDes interface inside the FPGA. The high-performance laser communication interface includes: a SerDes driver module, multiple filters and a SerDes multiplexer. The SerDes driver module has one input branch and multiple output branches, and each output branch is equipped with a filter. The SerDes driver module is used to receive one channel of communication data through the input branch; copy the one channel of communication data to generate multiple channels of parallel communication data; and output the multiple channels of communication data through the multiple output branches, with each output branch outputting one channel of the multiple channels of communication data. The filter is used to filter one of the multiple communication data output by the output branch according to the corresponding communication rate, so as to obtain the filtered communication data corresponding to the output branch. The SerDes multiplexer is used to connect the target output branch of the SerDes driver module and send the filtered communication data corresponding to the target output branch to the SerDes interface of the FPGA. Both the SerDes driver module and the SerDes multiplexer are implemented using Verilog language and programmed onto the FPGA board. Multiple filters are composed of fixed filters soldered onto the peripheral circuitry of the FPGA; When the communication rate needs to be switched, the copy output of the SerDes driver module and the filtering operation of the multiple filters remain unchanged. The SerDes multiplexer switches the connected target output branch according to the control signal of the FPGA.

2. The high-performance laser communication interface according to claim 1, characterized in that, The bandwidth of the filter is a fixed value, and the bandwidth of the filter is the bandwidth corresponding to the corresponding communication rate.

3. The high-performance laser communication interface according to claim 1, characterized in that, The high-performance laser communication interface also includes: a front-end multi-rate photoelectric conversion module; The front-end multi-rate photoelectric conversion module is used to convert the received laser signal into an electrical signal and output the electrical signal to the SerDes driver module.

4. The high-performance laser communication interface according to claim 3, characterized in that, The communication rate of the front-end multi-rate photoelectric conversion module meets the maximum communication rate specified by the communication protocol.

5. The high-performance laser communication interface according to claim 1, characterized in that, The SerDes multiplexer used to connect the target output branch of the SerDes driver module is specifically used for: In the initial state, the output branch containing the filter with the lowest communication rate among the multiple output branches is connected.

6. The high-performance laser communication interface according to claim 1, characterized in that, The SerDes multiplexer used to connect the target output branch of the SerDes driver module is specifically used for: Receive the control signal from the FPGA, the control signal containing the target communication rate to be switched to; connect to one of the output branches where the filter with the communication rate of the target communication rate is located.

7. The high-performance laser communication interface according to claim 6, characterized in that, The SerDes multiplexer used to connect the target output branch of the SerDes driver module is specifically used for: In the absence of a new control signal from the FPGA, maintain connection to one of the output branches containing the filter with a communication rate of the target communication rate among the plurality of output branches.

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