Circuit board and method of manufacturing the same
By setting photosensitive dielectric layers and inner circuit layers on both sides of the peelable substrate of the circuit board, the problem of heat dissipation thick copper occupying the space of fine circuits is solved, and high wiring density and efficient manufacturing of the circuit board are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HONGQISHENG PRECISION ELECTRONICS (QINHUANGDAO) CO LTD
- Filing Date
- 2021-08-18
- Publication Date
- 2026-07-14
AI Technical Summary
In embedded circuit boards, the heat dissipation thick copper and the fine line thin copper are arranged on the same side of the layer section, which causes the heat dissipation thick copper to occupy the space of the fine line thin copper, which is not conducive to improving the line density.
A first photosensitive dielectric layer is disposed on each of the opposite sides of the peelable substrate, and the first dielectric layer and the inner circuit layer are formed by exposure and development. The first connecting pad and the inner circuit layer are respectively disposed on both sides of the first dielectric layer to avoid occupying the wiring space of the inner circuit layer. An outer circuit layer is formed by electroplating and etching to achieve electrical connection.
This increased the wiring density and the number of connection pads on the circuit board, while also enabling differentiated settings for heat dissipation structures and connection lines, thereby improving the efficiency of circuit board manufacturing.
Smart Images
Figure CN115915604B_ABST
Abstract
Description
Technical Field
[0001] This application relates to a circuit board and a method for manufacturing the same. Background Technology
[0002] In general, in embedded circuit boards, the heat dissipation thick copper and the fine line thin copper are arranged on the same side of the layer section, which causes the heat dissipation thick copper to occupy the space of the fine line thin copper, which is not conducive to increasing the line density. Summary of the Invention
[0003] In view of the above, it is necessary to provide a method for manufacturing a circuit board to solve the above problems.
[0004] In addition, it is necessary to provide a circuit board.
[0005] A method for manufacturing a circuit board includes the steps of: providing a peelable substrate, the peelable substrate including a substrate layer and a release film disposed on the substrate layer; disposing a first dielectric layer on the release film, the first dielectric layer having a plurality of first openings through it, with a portion of the release film exposed at the bottom of the first openings; disposing an inner circuit layer on the first dielectric layer, with a portion of the inner circuit layer filling the first openings to form a first connection pad; disposing a second dielectric layer on the inner circuit layer and a second connection pad on the second dielectric layer; and removing the release film to obtain the circuit board.
[0006] Furthermore, the peelable substrate further includes a first copper foil layer disposed on the side of the release film opposite to the substrate layer. The steps further include: disposing a first dielectric layer on the first copper foil layer, with a portion of the first copper foil layer exposed at the bottom of the first opening, and removing the first copper foil layer.
[0007] Further, the step of "depositing the first dielectric layer on the first copper foil layer" includes: depositing a first photosensitive dielectric layer on the first copper foil layer, and exposing and developing the first photosensitive dielectric layer to obtain the first dielectric layer.
[0008] Further, the step "depositing an inner circuit layer on the first dielectric layer" includes: depositing a first electroplated layer on the first dielectric layer, with a portion of the first electroplated layer filling the first opening to form a first connecting pad, the first connecting pad being electrically connected to the first copper foil layer and the first electroplated layer. A first dry film layer is deposited on the first electroplated layer. The first dry film layer is exposed and developed to form a first dry film photosensitive pattern, the first dry film photosensitive pattern having multiple first through-holes, with a portion of the first electroplated layer exposed at the bottom of the first through-holes. A first conductor is deposited within the first through-holes, the first conductor covering a portion of the first electroplated layer. The first dry film photosensitive pattern is removed, and another portion of the first electroplated layer is removed to obtain the inner circuit layer.
[0009] Further, the step "depositing a second dielectric layer on the inner circuit layer" includes: depositing a single-sided copper-clad substrate on the inner circuit layer, wherein the single-sided copper-clad substrate includes a second dielectric layer and a second copper foil layer, and the second dielectric layer is disposed between the first dielectric layer and the second copper foil layer.
[0010] Furthermore, the circuit board also includes a second conductor. The step of "determining a second connection pad on the second dielectric layer" includes: forming a plurality of second openings on the single-sided copper-clad substrate, the second openings penetrating the second copper foil layer and the second dielectric layer, with a portion of the first connection pad and a portion of the inner circuit layer at the bottom of the second openings. A second electroplated layer is formed on the second copper foil layer, and a portion of the second electroplated layer fills the second openings to form the second conductor, the second conductor being electrically connected to the first connection pad or the inner circuit layer.
[0011] The second electroplated layer and the second copper foil layer are etched to form an outer circuit layer, the outer circuit layer including a plurality of second connection pads, the second connection pads being electrically connected to the second conductor or the first connection pad.
[0012] Furthermore, the method also includes the step of: setting a first solder resist pattern on the side of the first dielectric layer opposite to the second dielectric layer, with the first connector pad exposed in the first solder resist pattern.
[0013] Furthermore, the method also includes the step of: providing a second solder mask pattern on the side of the second dielectric layer opposite to the first dielectric layer, with the second bonding pad exposed in the second solder mask pattern.
[0014] A circuit board includes a first dielectric layer, a second dielectric layer, a first connection pad, a second connection pad, and an inner circuit layer. The first connection pad is disposed on one side of the first dielectric layer, the inner circuit layer is disposed on the other side of the first dielectric layer, the second dielectric layer is disposed on the inner circuit layer, and the second connection pad is disposed on the side of the second dielectric layer opposite to the first dielectric layer.
[0015] Furthermore, the circuit board also includes a conductor that electrically connects the first connecting pad and the second connecting pad.
[0016] The circuit board provided in this application places the first connecting pad and the inner circuit layer on both sides of the first dielectric layer, so that the first connecting pad does not occupy the wiring space of the inner circuit, thereby facilitating an increase in the number of the first connecting pads or the wiring density of the inner circuit layer. Attached Figure Description
[0017] Figure 1 This is a schematic diagram of a peelable substrate provided in an embodiment of this application.
[0018] Figure 2 for Figure 1 The diagram shows a first photosensitive medium layer disposed on a peelable substrate.
[0019] Figure 3 for Figure 1 The diagram shows a first dielectric layer disposed on a peelable substrate.
[0020] Figure 4 for Figure 3 The diagram shows a first electroplated layer disposed on a first dielectric layer.
[0021] Figure 5 for Figure 4 The diagram shows a first dry film photosensitive pattern disposed on the first electroplated layer.
[0022] Figure 6 for Figure 5 The diagram shows a first conductor disposed on the first electroplated layer.
[0023] Figure 7 for Figure 3 The diagram shows an inner circuit layer disposed on the first dielectric layer.
[0024] Figure 8 for Figure 7 The diagram shows a single-sided copper-clad substrate mounted on the inner circuit layer.
[0025] Figure 9 for Figure 8 The diagram shows a single-sided copper-clad substrate with a second opening.
[0026] Figure 10 for Figure 9 The diagram shows a second electroplated layer on a single-sided copper-clad substrate.
[0027] Figure 11 for Figure 10 The diagram shows an outer circuit layer disposed on the second dielectric layer.
[0028] Figure 12 For stripping Figure 11 The diagram shown illustrates the release film process.
[0029] Figure 13 For stripping Figure 11 The diagram shown is a schematic of the release film.
[0030] Figure 14 This is a schematic diagram of a circuit board provided in one embodiment of this application.
[0031] Explanation of main component symbols
[0032] Circuit board 100
[0033] Peelable substrate 10
[0034] Substrate layer 11
[0035] Release film 12
[0036] First copper foil layer 13
[0037] First photosensitive medium layer 20
[0038] First dielectric layer 21
[0039] First opening 211
[0040] First electroplating layer 30
[0041] First connecting pad 31
[0042] Inner circuit layer 32
[0043] First dry film photosensitive pattern 41
[0044] First through hole 411
[0045] First conductor 42
[0046] Single-sided copper-clad substrate 50
[0047] Second dielectric layer 51
[0048] Second copper foil layer 52
[0049] Second opening 53
[0050] Second electroplating layer 61
[0051] Second conductor 62
[0052] Outer line layer 63
[0053] Second connecting pad 631
[0054] First Weld Resistance Pattern 71
[0055] First window opening 711
[0056] Second anti-welding pattern 72
[0057] Second window 721
[0058] The following detailed description, in conjunction with the accompanying drawings, will further illustrate this application. Detailed Implementation
[0059] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.
[0060] Please see Figures 1 to 14 This application provides a method for manufacturing a circuit board 100, including the following steps:
[0061] S1: Please see Figure 1 A peelable substrate 10 is provided, comprising a substrate layer 11, two release films 12, and two first copper foil layers 13. The two release films 12 are respectively disposed on opposite sides of the substrate layer 11, and the two first copper foil layers 13 are respectively disposed on the side of the two substrate layers 11 opposite to the substrate layer 11. In other embodiments of this application, the first copper foil layers 13 may be omitted.
[0062] S2: Please see Figure 2 A first photosensitive dielectric layer 20 is respectively disposed on the two first copper foil layers 13. Please refer to [link to relevant documentation]. Figure 3 The first photosensitive medium layer 20 is exposed and developed to obtain the first medium layer 21. The first medium layer 21 is provided with a plurality of first openings 211, and a portion of the first copper foil layer 13 is exposed at the bottom of the first openings 211.
[0063] S3: Please see Figure 4 A first electroplated layer 30 is formed by electroplating on the two first dielectric layers 21. A portion of the first electroplated layer 30 is filled into the first opening 211 to form a first connecting pad 31. The first connecting pad 31 is electrically connected to the first copper foil layer 13 and the first electroplated layer 30.
[0064] S4: Please see Figure 5 A first dry film layer (not shown) is provided on the first electroplated layer 30. The first dry film layer is exposed and developed to form a first dry film photosensitive pattern 41. The first dry film photosensitive pattern 41 has a plurality of first through holes 411, and part of the first electroplated layer 30 is exposed at the bottom of the first through holes 411.
[0065] S5: Please see Figure 6 A first conductive body 42 is formed by electroplating inside the first through hole 411. The first conductive body 42 is electrically connected to the first electroplated layer 30. The first conductive body 42 and the portion of the first electroplated layer 30 covered by the first conductive body 42 together constitute the inner circuit layer 32.
[0066] S6: Please see Figure 7 Remove the first dry film photosensitive pattern 41 and etch away the first electroplated layer 30 that does not correspond to the first conductor 42 to expose the inner circuit layer 32.
[0067] S7: Please see Figure 8 A single-sided copper-clad substrate 50 is laminated onto the inner circuit layer 32. The single-sided copper-clad substrate 50 includes a second dielectric layer 51 and a second copper foil layer 52. The second dielectric layer 51 is disposed between the first dielectric layer 21 and the second copper foil layer 52.
[0068] S8: Please see Figure 9 A plurality of second openings 53 are provided on the single-sided copper-clad substrate 50, and the second openings 53 penetrate the second copper foil layer 52 and the second dielectric layer 51. Part of the first connecting pad 31 and part of the inner circuit layer 32 are exposed at the bottom of the second openings 53.
[0069] S9: Please see Figure 10 A second electroplated layer 61 is formed on the second copper foil layer 52 by electroplating, and a portion of the second electroplated layer 61 is filled into the second opening 53 to form a second conductor 62.
[0070] S10: Please refer to Figure 11 The second electroplated layer 61 and the second copper foil layer 52 are etched to form an outer circuit layer 63. The outer circuit layer 63 includes a plurality of second connection pads 631, some of which are electrically connected to the second conductor 62, so that the inner circuit layer 32 and the outer circuit layer 63 are electrically connected through the second conductor 62.
[0071] S11: Please refer to Figure 12Two release films 12 are removed, separating the substrate layer 11 and the first copper foil layer 13 to obtain two intermediates 60. Each intermediate 60 includes the first copper foil layer 13, a first dielectric layer 21, a second dielectric layer 51, a first connecting pad 31, an inner circuit layer 32, and an outer circuit layer 63. The first dielectric layer 21 is disposed on the first copper foil layer 13 and has a first opening 211. The first connecting pad 31 is disposed within the first opening 211. The inner circuit layer 32 is disposed on one side of the first dielectric layer 21, and a portion of the first connecting pad 31 is electrically connected to the inner circuit layer 32. The second dielectric layer 51 is disposed on the inner circuit layer 32, and the outer circuit layer 63 is disposed on the second dielectric layer 51. The outer circuit layer 63 includes a plurality of second connecting pads 631, a portion of which are electrically connected to the inner circuit layer 32.
[0072] S12: Please refer to Figure 13 The first copper foil layer 13 is etched away, so that the first connection pad 31 is exposed in the first dielectric layer 21. The exposed portion of the first connection pad 31 can be used to connect electronic components such as chips.
[0073] S13: Please see Figure 14 A first solder resist pattern 71 is provided on the first dielectric layer 21. The first solder resist pattern 71 has a first opening 711, and the first connecting pad 31 is exposed at the bottom of the first opening 711. A second solder resist pattern 72 is provided on the outer circuit layer 63. The second solder resist pattern 72 has a second opening 721, and the second connecting pad 631 is exposed at the bottom of the second opening 721, thus obtaining the circuit board 100. The second connecting pad 631 can be used to connect other circuit parts.
[0074] Compared with the prior art, the manufacturing method of the circuit board 100 provided in this application has the following advantages:
[0075] (i) By providing a first photosensitive medium layer 20 on opposite sides of the peelable substrate 10 and exposing and developing the first photosensitive medium layer 20 to obtain a first medium layer 21, the two circuit boards 100 can be obtained simultaneously by peeling off the peelable substrate 10, which is beneficial to improving manufacturing efficiency.
[0076] (ii) By placing the first connecting pad 31 and the inner circuit layer 32 on both sides of the first dielectric layer 21, the first connecting pad 31 does not occupy the wiring space of the inner circuit layer 32, which is beneficial to increase the number of the first connecting pad 31 or the wiring density of the inner circuit layer 32.
[0077] (iii) By separately fabricating the first connecting pad 31 and the inner circuit layer 32, it is beneficial to achieve differentiated settings for the first connecting pad 31 and the inner circuit layer 32. For example, the first connecting pad 31 can be fabricated as a heat dissipation structure with a larger thickness, and the inner circuit layer 32 can be fabricated as a connecting line with a smaller thickness.
[0078] One embodiment of this application also provides a circuit board 100, which includes a first dielectric layer 21, a second dielectric layer 51, a first connection pad 31, a second connection pad 631, and an inner circuit layer 32. The first connection pad 31 is disposed on one side of the first dielectric layer 21, the inner circuit layer 32 is disposed on the other side of the first dielectric layer 21, the second dielectric layer 51 is disposed on the inner circuit layer 32, and the second connection pad 631 is disposed on the side of the second dielectric layer 51 opposite to the first dielectric layer 21.
[0079] Compared to the prior art, the circuit board 100 provided in this application places the first connecting pad 31 and the inner circuit layer 32 on both sides of the first dielectric layer 21, so that the first connecting pad 31 does not occupy the wiring space of the inner circuit layer 32, thereby facilitating an increase in the number of the first connecting pad 31 or the wiring density of the inner circuit layer 32.
[0080] In this embodiment, the circuit board 100 further includes the second conductor 62, which is electrically connected to the first connecting pad 31 and the second connecting pad 631.
Claims
1. A method for manufacturing a circuit board, characterized in that, Including the following steps: A peelable substrate is provided, the peelable substrate including a substrate layer and a release film disposed on the substrate layer; A first dielectric layer is disposed on the release film, and the first dielectric layer is provided with a plurality of first openings, with a portion of the release film exposed at the bottom of the first openings; An inner circuit layer is provided on the first dielectric layer, and a portion of the inner circuit layer is filled into the first opening to form a first connection pad; A second dielectric layer is disposed on the inner circuit layer; and A second connection pad is disposed on the second dielectric layer; as well as Remove the release film to obtain the circuit board; in The peelable substrate further includes a first copper foil layer, the first copper foil layer being disposed on the side of the release film opposite to the substrate layer, and the step further includes: The first dielectric layer is disposed on the first copper foil layer, and a portion of the first copper foil layer is exposed at the bottom of the first opening; and Remove the first copper foil layer; The step "to form an inner circuit layer on the first dielectric layer" includes: A first electroplated layer is disposed on the first dielectric layer, and a portion of the first electroplated layer is filled into the first opening to form the first connecting pad. The first connecting pad is electrically connected to the first copper foil layer and the first electroplated layer. A first dry film layer is formed on the first electroplated layer; The first dry film layer is exposed and developed to form a first dry film photosensitive pattern. The first dry film photosensitive pattern has a plurality of first through holes, and part of the first electroplated layer is exposed at the bottom of the first through holes. A first conductive body is provided in the first through hole, and the first conductive body covers part of the first electroplated layer; Remove the first dry film photosensitive pattern, and Remove another portion of the first electroplated layer to obtain the inner circuit layer.
2. The manufacturing method as described in claim 1, characterized in that, The step of "depositing the first dielectric layer on the first copper foil layer" includes: A first photosensitive medium layer is disposed on the first copper foil layer, and The first photosensitive medium layer is exposed and developed to obtain the first medium layer.
3. The manufacturing method as described in claim 1, characterized in that, The step of "constructing a second dielectric layer on the inner circuit layer" includes: A single-sided copper-clad substrate is disposed on the inner circuit layer. The single-sided copper-clad substrate includes a second dielectric layer and a second copper foil layer, with the second dielectric layer disposed between the first dielectric layer and the second copper foil layer.
4. The manufacturing method as described in claim 3, characterized in that, The circuit board further includes a second conductor, and the step of "depositing a second connection pad on the second dielectric layer" includes: A plurality of second openings are provided on the single-sided copper-clad substrate. The second openings penetrate the second copper foil layer and the second dielectric layer. A portion of the first connecting pad and a portion of the inner circuit layer are located at the bottom of the second opening. A second electroplating layer is provided on the second copper foil layer, and a portion of the second electroplating layer is filled into the second opening to form the second conductor. The second conductor is electrically connected to the first connecting pad or the inner circuit layer. The second electroplated layer and the second copper foil layer are etched to form an outer circuit layer, the outer circuit layer including a plurality of second connection pads, the second connection pads being electrically connected to the second conductor or the first connection pad.
5. The manufacturing method as described in claim 1, characterized in that, The method also includes the step of: setting a first solder resist pattern on the side of the first dielectric layer opposite to the second dielectric layer, with the first connector pad exposed in the first solder resist pattern.
6. The manufacturing method as described in claim 1, characterized in that, The method also includes the step of: setting a second solder resist pattern on the side of the second dielectric layer opposite to the first dielectric layer, with the second connector pad exposed in the second solder resist pattern.
7. A circuit board manufactured by the method of manufacturing a circuit board according to any one of claims 1 to 6, characterized in that, The circuit board includes a first dielectric layer, a second dielectric layer, a first connection pad, a second connection pad, and an inner circuit layer. The first connection pad is disposed on one side of the first dielectric layer, the inner circuit layer is disposed on the other side of the first dielectric layer, the second dielectric layer is disposed on the inner circuit layer, and the second connection pad is disposed on the side of the second dielectric layer opposite to the first dielectric layer. The thickness of the first connection pad is greater than the thickness of the inner circuit layer. The circuit board also includes a conductor that electrically connects the first connection pad and the second connection pad.