Semiconductor memory device

Abstract

The embodiments provide a semiconductor memory device that is easily highly integrated. The semiconductor memory device of the embodiments includes: a substrate having a memory region and a bonding region arranged in a first direction; and a plurality of memory structures arranged in a second direction intersecting the first direction. The plurality of memory structures include: a plurality of conductive layers arranged in a third direction intersecting the surface of the substrate and extending across the memory region and the bonding region in the first direction; and a plurality of contact electrodes disposed in the bonding region, extending in the third direction, having an outer peripheral surface surrounded by a portion of the plurality of conductive layers, and respectively connected to any one of the plurality of conductive layers. The bonding region includes a first region and a second region arranged in the first direction. The first region includes a first contact electrode and a second contact electrode, and the second region includes a third contact electrode. The length of the third contact electrode in the third direction is longer than the length of the first contact electrode in the third direction and shorter than the length of the second contact electrode in the third direction.

Description

[0001] This application enjoys priority based on Japanese Patent Application No. 2021-153611 (filed on September 21, 2021). This application incorporates the entire contents of the basic application by reference. Technical Field

[0002] This embodiment relates to a semiconductor memory device. Background Technology

[0003] A semiconductor memory device is known, comprising a substrate, a plurality of conductive layers stacked in a direction intersecting the surface of the substrate, a semiconductor layer opposite to the plurality of conductive layers, and a gate insulating layer disposed between the conductive layers and the semiconductor layer. The gate insulating layer is, for example, a charge storage layer having insulating properties such as silicon nitride (Si3N4) or a conductive charge storage layer such as a floating gate, which is capable of storing data. Summary of the Invention

[0004] The problem to be solved by the present invention is to provide a semiconductor memory device that is easy to integrate.

[0005] One embodiment of a semiconductor memory device includes: a substrate having a memory region and a bonding region arranged in a first direction; and a plurality of memory structures arranged in a second direction intersecting the first direction. Each of the plurality of memory structures includes: a plurality of conductive layers arranged in a third direction intersecting the surface of the substrate and extending in the first direction across the memory region and the bonding region; a semiconductor layer disposed in the memory region, extending in the third direction, and opposite to the plurality of conductive layers; a charge storage film disposed between the plurality of conductive layers and the semiconductor layer; and a plurality of contact electrodes disposed in the bonding region, extending in the third direction, and having an outer peripheral surface surrounded by a portion of the plurality of conductive layers, respectively connected to any one of the plurality of conductive layers. The bonding region includes a first region and a second region arranged in the first direction. The first region includes a first contact electrode and a second contact electrode, and the second region includes a third contact electrode. The length of the third contact electrode in the third direction is longer than the length of the first contact electrode in the third direction and shorter than the length of the second contact electrode in the third direction. Attached Figure Description

[0006] Figure 1 This is a schematic top view of the memory die (MD) of the first embodiment.

[0007] Figure 2 yes Figure 1 A schematic enlarged view of part A and part B.

[0008] Figure 3 yes Figure 2 A schematic enlarged view of part C.

[0009] Figure 4 It is Figure 3 The diagram shows a schematic cross-sectional view of the structure when cut along line DD′ and viewed in the direction of the arrow.

[0010] Figure 5 yes Figure 4 A schematic enlarged view of the portion shown as E.

[0011] Figure 6 It is Figure 2 The diagram shows a schematic cross-sectional view of the structure when cut along line FF′ and viewed in the direction of the arrow.

[0012] Figure 7 It is Figure 2 The diagram shows a schematic cross-sectional view of the structure when cut along line GG′ and viewed in the direction of the arrow.

[0013] Figure 8 yes Figure 2 A schematic enlarged view of the joint area shown.

[0014] Figure 9 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0015] Figure 10 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0016] Figure 11 This is a schematic top view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0017] Figure 12 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0018] Figure 13 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0019] Figure 14 This is a schematic top view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0020] Figure 15 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0021] Figure 16 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0022] Figure 17 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0023] Figure 18 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0024] Figure 19 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0025] Figure 20 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0026] Figure 21 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0027] Figure 22 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0028] Figure 23 This is a schematic top view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0029] Figure 24 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0030] Figure 25 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0031] Figure 26 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0032] Figure 27 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0033] Figure 28 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0034] Figure 29 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0035] Figure 30 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0036] Figure 31 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0037] Figure 32 This is a schematic top view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0038] Figure 33 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0039] Figure 34 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0040] Figure 35 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0041] Figure 36 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0042] Figure 37 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0043] Figure 38 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0044] Figure 39 This is a schematic top view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0045] Figure 40 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0046] Figure 41 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0047] Figure 42 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0048] Figure 43This is a schematic top view of a comparative example semiconductor memory device.

[0049] Figure 44 yes Figure 43 A schematic enlarged view of the joint area shown.

[0050] Figure 45 This is a schematic cross-sectional view used to illustrate the manufacturing method of a comparative example semiconductor memory device.

[0051] Figure 46 This is a schematic cross-sectional view used to illustrate the manufacturing method of a comparative example semiconductor memory device.

[0052] Figure 47 This is a schematic top view showing a portion of the structure of the semiconductor memory device according to the second embodiment.

[0053] Figure 48 It is Figure 47 The diagram shows a schematic cross-sectional view of the structure when cut along line HH′ and viewed in the direction of the arrow.

[0054] Figure 49 It is Figure 47 The diagram shows a schematic cross-sectional view of the structure when cut along line II′ and viewed in the direction of the arrow.

[0055] Figure 50 It is Figure 47 The diagram shows a schematic cross-sectional view of the structure when cut along line JJ′ and viewed in the direction of the arrow.

[0056] Figure 51 yes Figure 47 A schematic enlarged view of the joint area shown.

[0057] Figure 52 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the second embodiment.

[0058] Figure 53 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the second embodiment.

[0059] Figure 54 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the second embodiment.

[0060] Figure 55 This is a schematic top view of a comparative example semiconductor memory device.

[0061] Figure 56 yes Figure 55 A schematic enlarged view of the joint area shown.

[0062] Figure 57 This is a schematic cross-sectional view used to illustrate the manufacturing method of a comparative example semiconductor memory device.

[0063] Figure 58 This is a schematic cross-sectional view used to illustrate the manufacturing method of a comparative example semiconductor memory device.

[0064] Figure 59 This is a schematic cross-sectional view used to illustrate the manufacturing method of a comparative example semiconductor memory device.

[0065] Figure 60 This is a schematic enlarged view of the bonding area of ​​the semiconductor memory device according to the third embodiment.

[0066] Figure 61 This is a schematic enlarged view of the bonding area of ​​the semiconductor memory device according to the fourth embodiment.

[0067] Explanation of reference numerals in the attached figures

[0068] 100…Semiconductor substrate, 110…Conductive layer, 120…Semiconductor layer, 130…Gate insulating film, CC…Contact electrode, CCG…Contact electrode array, CH…Contact hole, CHC…Contact hole array, ST…Inter-block insulating layer, R HU …joint region, R HU1 …Region 1, R HU2 …Region 2, R11~R18, R21~R28, S11~S14, T11~T18, U11~U18…Unit region. Detailed Implementation

[0069] Next, the semiconductor memory device according to the embodiments will be described in detail with reference to the accompanying drawings. Furthermore, the following embodiments are merely examples and are not intended to limit the scope of the invention. Additionally, the following drawings are schematic, and for ease of explanation, some structures may be omitted. Furthermore, common parts in multiple embodiments may be labeled with the same reference numerals and their descriptions may be omitted.

[0070] Additionally, when referred to as "semiconductor memory device" in this specification, it sometimes means a memory die, and sometimes it means a memory chip, memory card, SSD (Solid State Drive), or other storage system including a controller die. Furthermore, it sometimes also refers to the structure of a smartphone, tablet, personal computer, or other computer-based device.

[0071] Furthermore, in this specification, when referring to the first structure and the second structure as "electrically connected," the first structure can be directly connected to the second structure, or the first structure can be connected to the second structure via wiring, semiconductor components, or transistors. For example, when three transistors are connected in series, even if the second transistor is in the off state, the first transistor is still "electrically connected" to the third transistor.

[0072] Additionally, when this specification states that the first structure is connected between the second and third structures, it sometimes means that the first, second, and third structures are connected in series and the second structure is connected to the third structure via the first structure.

[0073] In addition, in this specification, a predetermined direction parallel to the upper surface of the substrate is referred to as the X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is referred to as the Y direction, and a direction perpendicular to the upper surface of the substrate is referred to as the Z direction.

[0074] In addition, in this specification, the direction along the predetermined surface is sometimes referred to as the first direction, the direction along the predetermined surface that intersects the first direction is referred to as the second direction, and the direction that intersects the predetermined surface is referred to as the third direction. These first, second, and third directions may correspond to any one of the X, Y, and Z directions, or they may not correspond to each other.

[0075] Furthermore, in this specification, the terms "upper" and "lower" are used with reference to the substrate. For example, the direction that moves away from the substrate along the Z direction is called "upper," and the direction that moves towards the substrate along the Z direction is called "lower." Additionally, when referring to a structure as a lower surface or lower end, it means the surface or end of the structure on the substrate side; when referring to it as an upper surface or upper end, it means the surface or end of the structure on the side opposite to the substrate. Furthermore, a surface that intersects the X or Y direction is called a side surface, etc.

[0076] In addition, when referring to structures, components, etc., in this specification as "width," "length," or "thickness" in a predetermined direction, it sometimes means the width, length, or thickness of a cross-section, etc., as observed by SEM (Scanning electron microscopy), TEM (Transmission electron microscopy), etc.

[0077] [First Implementation]

[0078] [structure]

[0079] Figure 1 This is a schematic top view of a memory die (MD). Figure 2 yes Figure 1 A schematic enlarged view of part A and part B. Figure 3 yes Figure 2 A schematic enlarged view of part C. Figure 4 It is Figure 3 The diagram shows a schematic cross-sectional view of the structure when cut along line DD′ and viewed in the direction of the arrow. Figure 5 yes Figure 4 A schematic enlarged view of the portion shown as E. Figure 6 It is Figure 2 The diagram shows a schematic cross-sectional view of the structure when cut along line FF′ and viewed in the direction of the arrow. Figure 7 It is Figure 2 The diagram shows a schematic cross-sectional view of the structure when cut along line GG′ and viewed in the direction of the arrow. Figure 8 yes Figure 2 A schematic enlarged view of the joint area shown.

[0080] For example, such as Figure 1 As shown, the memory die MD includes a semiconductor substrate 100. The semiconductor substrate 100 is, for example, a semiconductor substrate formed of P-type silicon (Si) containing P-type impurities such as boron (B). On the surface of the semiconductor substrate 100 are provided N-type well regions containing N-type impurities such as phosphorus (P), P-type well regions containing P-type impurities such as boron (B), semiconductor substrate regions without N-type well regions and P-type well regions, and insulating regions.

[0081] In addition, the memory die MD has four memory cell array regions R arranged in the X and Y directions. MCA Storage cell array region R MCA It has two storage hole regions R arranged in the X direction. MH (Also, there is the storage hole area R) MH (The case referred to as the storage area) and the storage hole areas R located in these storage areas MH The joint area R between HU .

[0082] In the storage cell array region R MCA Multiple storage blocks (BLKs) are configured and arranged in the Y direction. For example, such as... Figure 2 As shown, the storage block BLK has two finger-like structures FS arranged in the Y direction (there are also cases where the finger-like structures FS are referred to as storage structures). For example, as Figure 2 As shown, the finger structure FS has two string units SU arranged in the Y direction.

[0083] An inter-bulk insulating layer ST, such as silicon oxide (SiO2), is provided between two adjacent finger-like structures FS in the Y direction. Additionally, for example, such as... Figure 2 and Figure 3 As shown, an inter-string insulating layer SHE, such as silicon oxide (SiO2), is provided between two adjacent string units SU in the Y direction.

[0084] For example, such as Figure 4 As shown, the storage hole region R of storage block BLK MH It includes a plurality of conductive layers 110 arranged in the Z direction, a plurality of semiconductor layers 120 extending in the Z direction, and a plurality of gate insulating films 130 disposed between the plurality of conductive layers 110 and the plurality of semiconductor layers 120.

[0085] The conductive layer 110 is a generally plate-shaped conductive layer extending in the X direction. The conductive layer 110 may include a stacked film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). Alternatively, the conductive layer 110 may also include, for example, polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). An insulating layer 101, such as silicon oxide (SiO2), is disposed between the plurality of conductive layers 110 arranged in the Z direction. Furthermore, the conductive layer 110 functions as the gate electrode and word line of a memory cell or the gate electrode and select gate line of a select transistor.

[0086] A semiconductor layer 112 is disposed below the conductive layer 110. The semiconductor layer 112 may, for example, contain polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). In addition, an insulating layer 101 such as silicon oxide (SiO2) is disposed between the semiconductor layer 112 and the conductive layer 110. Furthermore, the semiconductor layer 112 functions as part of the source line.

[0087] For example, such as Figure 3 As shown, the semiconductor layer 120 is arranged in a predetermined pattern in the X and Y directions. The semiconductor layer 120 functions as the channel region for multiple memory cells and selection transistors. The semiconductor layer 120 is, for example, a semiconductor layer of polysilicon (Si). For example, such as... Figure 4 As shown, the semiconductor layer 120 has a generally cylindrical shape, and an insulating layer 125 such as silicon oxide is disposed in the central portion. In addition, the outer peripheral surfaces of the semiconductor layer 120 are surrounded by conductive layers 110, which are opposite to each other.

[0088] An impurity region 121 containing N-type impurities such as phosphorus (P) is provided at the upper end of the semiconductor layer 120. Figure 4 In this example, the boundary line between the upper end of the semiconductor layer 120 and the lower end of the impurity region 121 is shown using a dashed line. The impurity region 121 is connected by contact portion Ch and contact portion Vy. Figure 3 And connected to bit line BL.

[0089] The lower end of semiconductor layer 120 is connected to semiconductor layer 112.

[0090] The gate insulating film 130 has a generally cylindrical shape covering the outer peripheral surface of the semiconductor layer 120. For example, as Figure 5 As shown, the gate insulating film 130 includes a tunnel insulating film 131, a charge storage film 132, and a bulk insulating film 133 stacked between the semiconductor layer 120 and the conductive layer 110. The tunnel insulating film 131 and the bulk insulating film 133 are insulating films such as silicon oxide (SiO2). The charge storage film 132 is a film capable of storing charge, such as silicon nitride (Si3N4). The tunnel insulating film 131, the charge storage film 132, and the bulk insulating film 133 have a generally cylindrical shape and extend in the Z direction along the outer peripheral surface of the semiconductor layer 120, excluding the contact portion between the semiconductor layer 120 and the semiconductor layer 112.

[0091] In addition, Figure 5 An example is shown where the gate insulating film 130 has a charge storage film 132 such as silicon nitride. However, the gate insulating film 130 may also have a floating gate such as polysilicon containing N-type or P-type impurities.

[0092] For example, such as Figure 2 As shown, the junction region R of the storage block BLK HU It has a portion of a conductive layer 110 and multiple contact electrodes CC arranged in a matrix in the X and Y directions.

[0093] Furthermore, regarding the configuration in the joint area R HU In multiple contact electrodes CC Figure 2 The multiple contact electrodes CC shown are sometimes referred to as contact electrode CCab, specifically the a-th (where a is an integer greater than or equal to 1) contact electrode counted from the +Y direction to the -Y direction and the b-th (where b is an integer greater than or equal to 1) contact electrode counted from the -X direction to the +X direction. For example, sometimes the second contact electrode CC counted from the +Y direction to the -Y direction and the fourth contact electrode CC counted from the -X direction to the +X direction is referred to as contact electrode CC24.

[0094] Sometimes, a column of eight contact electrodes (CC) arranged in the X direction is called a contact electrode column (CCG). Additionally, sometimes the regions corresponding to the contact electrode column (CCG) are called contact electrode regions. For example... Figure 2 As shown, in the joint region R HU The contact electrode arrays CCG(0) and CCG(1) are arranged alternately in the Y direction.

[0095] like Figure 6 and Figure 7As shown, multiple contact electrodes CC extend in the Z direction and are connected to the conductive layer 110 at their lower ends. The contact electrodes CC may, for example, comprise a stacked film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). Furthermore, an insulating layer 103, such as silicon oxide (SiO2), is provided on the outer peripheral surface of the contact electrodes CC.

[0096] Furthermore, in the following description, the nth conductive layer 110 (where n is an integer greater than or equal to 1) from the top is sometimes referred to as conductive layer 110(n-1). Also, the contact electrode CC connected to conductive layer 110(n) among the plurality of contact electrodes CC is sometimes referred to as contact electrode CC(n). Additionally, conductive layer 110(n-1) is sometimes referred to as the nth conductive layer 110. For example... Figure 4 , Figure 6 and Figure 7 As shown, multiple conductive layers 110(n) are arranged at equal intervals in the Z direction. Therefore, n in the contact electrode CC(n) represents the level of the length (depth) of the contact electrode CC in the Z direction.

[0097] like Figure 6 As shown, the contact electrode array CCG(0) extends from the storage hole region R MH Starting from the nearest side, contact electrodes CC11(0), CC12(1), CC13(2), CC14(3), CC15(4), CC16(5), CC17(6), and CC18(7) are sequentially provided. Thus, in the contact electrode array CCG(0), whenever from the storage hole region R... MH As the distance increases, the depth of the contact electrode CC gradually increases (i.e., the length of the contact electrode CC in the Z direction increases).

[0098] like Figure 7 As shown, the contact electrode array CCG(1) extends from a distance R from the storage hole region. MH Starting from the nearest side, contact electrodes CC21(7), CC22(6), CC23(5), CC24(4), CC25(3), CC26(2), CC27(1), and CC28(0) are sequentially provided. Thus, in the contact electrode array CCG(1), whenever from the storage hole region R... MH As the distance increases, the depth of the contact electrode CC gradually decreases (i.e., the length of the contact electrode CC in the Z direction becomes shorter).

[0099] like Figure 8As shown, multiple contact electrodes CC11(0), CC12(1), CC13(2), CC14(3), CC15(4), CC16(5), CC17(6), and CC18(7) in contact electrode array CCG(0) are arranged in the Y direction with multiple contact electrodes CC21(7), CC22(6), CC23(5), CC24(4), CC25(3), CC26(2), CC27(1), and CC28(0) in contact electrode array CCG(1).

[0100] In addition, multiple contact electrodes CC31(0), CC32(1), CC33(2), CC34(3), CC35(4), CC36(5), CC37(6), and CC38(7) in contact electrode array CCG(0) are arranged in the Y direction with multiple contact electrodes CC41(7), CC42(6), CC43(5), CC44(4), CC45(3), CC46(2), CC47(1), and CC48(0) in contact electrode array CCG(1).

[0101] Sometimes, a region comprising a certain number of contact electrodes CC (where m is an integer greater than or equal to 2) is called a unit region. Figure 8 In this example, a region comprising a certain area of ​​two contact electrodes CC arranged in the Y direction is defined as the unit region. The bonding region R HU It is hypothetically divided into multiple unit areas.

[0102] exist Figure 8 In the diagram, unit region R11 includes two contact electrodes CC11(0) and CC21(7). Unit region R12 includes two contact electrodes CC12(1) and CC22(6). Unit region R13 includes two contact electrodes CC13(2) and CC23(5). Unit region R14 includes two contact electrodes CC14(3) and CC24(4). Unit region R15 includes two contact electrodes CC15(4) and CC25(3). Unit region R16 includes two contact electrodes CC16(5) and CC26(2). Unit region R17 includes two contact electrodes CC17(6) and CC27(1). Unit region R18 includes two contact electrodes CC18(7) and CC28(0).

[0103] Additionally, unit region R21 includes two contact electrodes CC31(0) and CC41(7). Unit region R22 includes two contact electrodes CC32(1) and CC42(6). Unit region R23 includes two contact electrodes CC33(2) and CC43(5). Unit region R24 includes two contact electrodes CC34(3) and CC44(4). Unit region R25 includes two contact electrodes CC35(4) and CC45(3). Unit region R26 includes two contact electrodes CC36(5) and CC46(2). Unit region R27 includes two contact electrodes CC37(6) and CC47(1). Unit region R28 includes two contact electrodes CC38(7) and CC48(0).

[0104] For example, the average depth level "0" of contact electrode CC11(0) and the average depth level "7" of contact electrode CC11(7) disposed in unit region R11 is "3.5". Similarly, the average depth level n of the two contact electrodes CC disposed in unit regions R12~R18 and R21~R28 is "3.5". That is, the average length of the two contact electrodes CC disposed in all unit regions R11~R18 and R21~R28 in the Z direction is the same value.

[0105] In addition, such as Figure 2 As shown, the junction region R of multiple contact electrodes CC is configured. HU The region R is divided into the first region arranged in the X direction. HU1 and Region 2 R HU2 For example, region R1 HU1 It includes the region containing contact electrodes CC11~CC14, CC21~CC24, ..., and the second region R. HU2 It includes the region containing contact electrodes CC15~CC18, CC25~CC28, ...

[0106] Furthermore, the number of contact electrodes CC contained in multiple unit regions is set to m (m is an integer greater than or equal to 2). Also, the average length of the m contact electrodes CC with the longest Z-direction length (from the 1st to the mth longest) is set as "the 1st length". Additionally, the average length of the m contact electrodes CC with the shortest Z-direction length (from the 1st to the mth shortest) is set as "the 2nd length".

[0107] For example, in Figure 8In the example, the number m of contact electrodes CC contained in multiple unit regions is "2". Furthermore, the average length in the Z direction of the two longest contact electrodes (e.g., contact electrodes CC18(7) and CC17(6)) is "6.5". Therefore, "first length" becomes "6.5". Additionally, the average length in the Z direction of the two shortest contact electrodes (e.g., contact electrodes CC11(0) and CC12(1)) is "0.5". Therefore, "second length" becomes "0.5".

[0108] As described above, the average length (average for each depth level) of the two contact electrodes CC in the Z direction within each unit region R11~R18 and R21~R28 is "3.5". Therefore, the average length of the two contact electrodes CC in the Z direction within each unit region R11~R18 and R21~R28 is smaller than "first length" and larger than "second length".

[0109] [Manufacturing Method]

[0110] Next, refer to Figures 9 to 42 This section explains the manufacturing method of memory die MD. Figure 11 , Figure 14 , Figure 23 , Figure 32 , Figure 39 This is a schematic top view used to illustrate the manufacturing method, showing the relationship with... Figure 2 The corresponding plane. Figure 9 , Figure 10 , Figure 12 , Figure 13 , Figure 15 , Figure 17 , Figure 19 , Figure 21 , Figure 24 , Figure 26 , Figure 28 , Figure 30 , Figure 33 , Figure 35 , Figure 37 , Figures 40-42 This is a schematic cross-sectional view used to illustrate the manufacturing method, showing the relationship with... Figure 6 The corresponding cross section. Figure 9 , Figure 10 , Figure 16 , Figure 18 , Figure 20 , Figure 22 , Figure 25 , Figure 27 , Figure 29 , Figure 31 , Figure 34 , Figure 36 , Figure 38 This is a schematic cross-sectional view used to illustrate the manufacturing method, showing the relationship with... Figure 7 The corresponding cross section.

[0111] During the manufacturing of the memory die MD in this embodiment, for example, as Figure 9 As shown, a semiconductor layer 112 is formed. Furthermore, multiple insulating layers 101 and multiple sacrificial layers 111 are alternately formed above the semiconductor layer 112. This process is performed, for example, by a method such as CVD (Chemical Vapor Deposition).

[0112] Next, for example, such as Figure 10 As shown, multiple semiconductor layers 120 are formed. In this process, for example, in reference... Figure 9 The described structure has an insulating layer 104 of silicon oxide (SiO2) or the like formed on its upper surface using methods such as CVD. Next, through-holes are formed through the insulating layer 104, multiple insulating layers 101, and multiple sacrificial layers 111 using methods such as RIE (Reactive Ion Etching). Furthermore, a gate insulating film 130 is formed on the inner peripheral surface of these through-holes using methods such as CVD. Figure 5 ) and semiconductor layer 120.

[0113] Next, for example, such as Figure 11 and Figure 12 As shown, multiple contact holes CH(0) are formed at positions corresponding to the contact electrode CC. For example, in the reference... Figure 10 A hard mask 105 is formed on the upper surface of the described structure. Then, through holes are formed through the hard mask 105 and the insulating layer 104 by methods such as RIE, exposing the upper surface of the sacrificial layer 111.

[0114] Furthermore, in the following description, the nth (n is an integer greater than or equal to 1) sacrificial layer 111 from the top is sometimes referred to as sacrificial layer 111(n-1). Also, sometimes the contact hole CH that exposes the upper surface of sacrificial layer 111(n) and penetrates all the sacrificial layers 111 located above it is referred to as contact hole CH(n). Additionally, sometimes sacrificial layer 111(n-1) is referred to as the nth sacrificial layer 111. For example... Figure 12 As shown, multiple sacrificial layers 111(n) are arranged at equal intervals in the Z direction. Therefore, n in the contact hole CH(n) represents the order of the length (depth) of the contact hole CH in the Z direction.

[0115] Additionally, regarding the configuration in the joint area R HU In multiple contact holes CH, Figure 11The multiple contact holes CH shown are sometimes referred to as contact hole CHab, specifically the a-th (a is an integer greater than 1) contact hole counted from the +Y direction to the -Y direction and the b-th (b is an integer greater than 1) contact hole counted from the -X direction to the +X direction.

[0116] Sometimes, a column of eight contact holes (CH) arranged in the X direction is called a contact hole column (CHG). For example... Figure 11 As shown, in the joint region R HU In the process, two contact hole rows CHG(0) and CHG(1) are arranged alternately in the Y direction. Furthermore, the contact hole row CHG(0) is formed at the same position as the contact electrode row CCG(0), and the contact hole row CHG(1) is formed at the same position as the contact electrode row CCG(1).

[0117] Next, photolithography (sometimes called PEP (Photo Engraving Process)) is used to generate the resist pattern for processing the contact hole CH.

[0118] For example, such as Figure 13 As shown, in reference Figure 12 The upper surface of the described structure is coated with resist 151.

[0119] also, Figure 12 and Figure 13 The cross-section corresponding to contact hole column CHG(0) is shown. The construction of the cross-section corresponding to contact hole column CHG(1) is also similar. Figure 12 and Figure 13 The construction of the cross section shown is the same. Therefore, the cross-sectional view corresponding to the contact hole row CHG(1) is omitted.

[0120] Next, for example, such as Figures 14-16 As shown, the exposure apparatus (not shown) exposes the positions of contact holes CH12(0), CH14(0), CH16(0), CH18(0), CH21(0), CH23(0), CH25(0), CH27(0), CH32(0), CH34(0), CH36(0), CH38(0), CH41(0), CH43(0), CH45(0), and CH47(0) based on a photomask.

[0121] Then, by developing with a developer corresponding to resist 151, the resist at the locations of contact holes CH12(0), CH14(0), CH16(0), CH18(0), CH21(0), CH23(0), CH25(0), CH27(0), CH32(0), CH34(0), CH36(0), CH38(0), CH41(0), CH43(0), CH45(0), and CH47(0) is removed. This opens the contact holes.

[0122] Next, for example, such as Figure 17 and Figure 18 As shown, for the open contact holes CH12(0), CH14(0), CH16(0), CH18(0), CH21(0), CH23(0), CH25(0), and CH27(0) in the contact hole CH, one layer each of the sacrificial layer 111 and the insulating layer 101 is removed. This forms contact holes CH12(1), CH14(1), CH16(1), CH18(1), CH21(1), CH23(1), CH25(1), and CH27(1) that reach the second sacrificial layer 111(1). This process is performed, for example, by a RIE (Residual Insulation Equipment).

[0123] In addition, at CH32(0), CH34(0), CH36(0), CH38(0), CH41(0), CH43(0), CH45(0), and CH47(0), the sacrificial layer 111 and the insulating layer 101 are each removed by one layer.

[0124] Then, as Figure 19 and Figure 20 As shown, remove resist 151.

[0125] Next, as Figure 21 and Figure 22 As shown, in reference Figure 19 and Figure 20 The upper surface of the described structure is coated with resist 151.

[0126] Next, for example, such as Figures 23-25 As shown, the exposure apparatus (not shown) exposes the positions of contact holes CH13(0), CH14(1), CH17(0), CH18(1), CH21(1), CH22(0), CH25(1), CH26(0), CH33(0), CH34(1), CH37(0), CH38(1), CH41(1), CH42(0), CH45(1), and CH46(0) based on a photomask.

[0127] Then, by developing with a developer corresponding to resist 151, the resist at the locations of contact holes CH13(0), CH14(1), CH17(0), CH18(1), CH21(1), CH22(0), CH25(1), CH26(0), CH33(0), CH34(1), CH37(0), CH38(1), CH41(1), CH42(0), CH45(1), and CH46(0) is removed. This opens the contact holes.

[0128] Next, for example, such as Figure 26 and Figure 27 As shown, for the open contact holes CH13(0), CH14(1), CH17(0), CH18(1), CH21(1), CH22(0), CH25(1), and CH26(0) in the contact hole CH, two layers of sacrificial layer 111 and insulating layer 101 are removed. This forms contact holes CH13(2), CH14(3), CH17(2), CH18(3), CH21(3), CH22(2), CH25(3), and CH26(2) that reach the third and fourth layers, respectively. This process is performed, for example, by a RIE (Residual Insulation Equipment).

[0129] In addition, at contact holes CH33(0), CH34(1), CH37(0), CH38(1), CH41(1), CH42(0), CH45(1), and CH26(0), sacrificial layer 111 and insulating layer 101 are also removed in two layers each.

[0130] Then, as Figure 28 and Figure 29 As shown, remove resist 151.

[0131] Next, as Figure 30 and Figure 31 As shown, in reference Figure 28 and Figure 29 The upper surface of the described structure is coated with resist 151.

[0132] Next, for example, such as Figures 32-34 As shown, the exposure apparatus (not shown) exposes the positions of contact holes CH15(0), CH16(1), CH17(2), CH18(3), CH21(3), CH22(2), CH23(1), CH24(0), CH35(0), CH36(1), CH37(2), CH38(3), CH41(3), CH42(2), CH43(1), and CH44(0) based on a photomask.

[0133] Then, by developing with a developer corresponding to resist 151, the resist at the locations of contact holes CH15(0), CH16(1), CH17(2), CH18(3), CH21(3), CH22(2), CH23(1), CH24(0), CH35(0), CH36(1), CH37(2), CH38(3), CH41(3), CH42(2), CH43(1), and CH44(0) is removed. This opens the contact holes.

[0134] Next, for example, such as Figure 35 and Figure 36 As shown, for the open contact holes CH15(0), CH16(1), CH17(2), CH18(3), CH21(3), CH22(2), CH23(1), and CH24(0) in the contact hole CH, four layers of sacrificial layer 111 and insulating layer 101 are removed. This forms contact holes CH15(4), CH16(5), CH17(6), CH18(7), CH21(7), CH22(6), CH23(5), and CH24(4) that extend to the 5th to 8th layers. This process is performed, for example, by a RIE (Residual Insulation Equipment).

[0135] In addition, at contact holes CH35(0), CH36(1), CH37(2), CH38(3), CH41(3), CH42(2), CH43(1), and CH44(0), four layers of sacrificial layer 111 and insulating layer 101 are also removed.

[0136] Then, as Figure 37 and Figure 38 As shown, remove resist 151. Figure 39 As shown, in the joint region R HU In this configuration, contact hole columns CHG(0) and CHG(1) are arranged alternately in the Y direction. Furthermore, in contact hole column CHG(0), whenever a hole is located in storage hole region R... MH As the distance increases, the depth of the contact hole CH increases layer by layer. Furthermore, in the contact hole column CHG(1), each time from the storage hole region R... MH As the contact hole CH moves further away, its depth becomes shallower layer by layer.

[0137] Next, for example, such as Figure 40 As shown, an insulating layer 103 and a sacrificial layer 106 are formed inside the contact holes CH11(0) to CH18(7). This process is performed, for example, by CVD.

[0138] Next, for example, such as Figure 41As shown, a conductive layer 110 is formed. In this process, for example, a conductive layer ST is formed between the conductive layer and the inter-block insulating layer using methods such as RIE. Figure 2 A trench is formed at the corresponding position, penetrating multiple insulating layers 101 and multiple sacrificial layers 111. Then, the multiple sacrificial layers 111 are removed by methods such as wet etching through the trench. Next, multiple conductive layers 110 are formed by methods such as CVD.

[0139] Next, for example, such as Figure 42 As shown, contact electrodes CC11(0) to CC18(7) are formed. In this process, for example, the sacrificial layer 106 is removed. Next, a portion of the insulating layer 103 is removed by methods such as RIE, exposing the upper surfaces of the conductive layers 110(0) to 110(7). Next, contact electrodes CC11(0) to CC18(7) are formed by methods such as CVD.

[0140] Subsequently, a reference is formed by creating bit lines (BL), etc. Figures 1 to 8 Explained semiconductor memory devices.

[0141] Furthermore, based on Figures 40-42 The process of forming the contact electrode array CCG(0) from the contact hole array CHG(0) has been described. However, the process of forming the contact electrode array CCG(1) from the contact hole array CHG(1) is also described in the reference. Figures 40-42 The content described is the same. Therefore, the cross-sectional views and descriptions corresponding to the contact hole row CHG(1) and the contact electrode row CCG(1) are omitted.

[0142] [Comparative Example]

[0143] [structure]

[0144] Next, refer to Figure 43 and Figure 44 The structure of the comparative example semiconductor memory device will be described. Figure 43 This is a schematic top view of a comparative example semiconductor memory device. Figure 44 yes Figure 43 A schematic enlarged view of the joint area shown.

[0145] Furthermore, regarding the configuration in the joint area R HU Among the multiple contact electrodes CC, Figure 43 and Figure 44 The multiple contact electrodes CC shown are sometimes referred to as contact electrode CCab, specifically the a-th (a is an integer greater than 1) contact electrode counted from the +Y direction to the -Y direction and the b-th (b is an integer greater than 1) contact electrode counted from the -X direction to the +X direction.

[0146] In the semiconductor memory device of the first embodiment, such as Figure 2 and Figure 8 As shown, the two contact electrode arrays CCG(0) and CCG(1) are arranged alternately in the Y direction. On the other hand, in the semiconductor memory device of the comparative example, as... Figure 43 and Figure 44 As shown, only the contact electrode array CCG(0) is arranged in the Y direction.

[0147] Multiple contact electrode arrays CCG(0) are located from the storage hole region R. MH Starting from the nearest side, the contact electrodes are arranged in the X direction in the order of CC(0), CC(1), CC(2), CC(3), CC(4), CC(5), CC(6), CC(7). That is, multiple contact electrode rows CCG(0) are arranged in the order of contact electrodes CC(0), CC(1), CC(2), CC(3), CC(4), CC(5), CC(6), CC(7) whenever they are from the storage hole region R. MH As the distance increases, the depth of the contact hole CH increases layer by layer.

[0148] In comparative examples, the region comprising a certain number m (m is an integer greater than 2) of contact electrodes CC is sometimes referred to as the unit region. Figure 44 In this example, a region comprising a certain area of ​​two contact electrodes CC arranged in the Y direction is defined as the unit region. The bonding region R HU It is hypothetically divided into multiple unit areas.

[0149] exist Figure 44 In the diagram, unit region R11 includes two contact electrodes CC11(0) and CC21(0). Unit region R12 includes two contact electrodes CC12(1) and CC22(1). Unit region R13 includes two contact electrodes CC13(2) and CC23(2). Unit region R14 includes two contact electrodes CC14(3) and CC24(3). Unit region R15 includes two contact electrodes CC15(4) and CC25(4). Unit region R16 includes two contact electrodes CC16(5) and CC26(5). Unit region R17 includes two contact electrodes CC17(6) and CC27(6). Unit region R18 includes two contact electrodes CC18(7) and CC28(7).

[0150] Additionally, unit region R21 includes two contact electrodes CC31(0) and CC41(0). Unit region R22 includes two contact electrodes CC32(1) and CC42(1). Unit region R23 includes two contact electrodes CC33(2) and CC43(2). Unit region R24 includes two contact electrodes CC34(3) and CC44(3). Unit region R25 includes two contact electrodes CC35(4) and CC45(4). Unit region R26 includes two contact electrodes CC36(5) and CC46(5). Unit region R27 includes two contact electrodes CC37(6) and CC47(6). Unit region R28 includes two contact electrodes CC38(7) and CC48(7).

[0151] The average depth level n of the two contact electrodes CC located in unit regions R11 and R21 is "0". The average depth level n of the two contact electrodes CC located in unit regions R12 and R22 is "1". The average depth level n of the two contact electrodes CC located in unit regions R13 and R23 is "2". The average depth level n of the two contact electrodes CC located in unit regions R14 and R24 is "3".

[0152] The average depth level n of the two contact electrodes CC located in unit areas R15 and R25 is "4". The average depth level n of the two contact electrodes CC located in unit areas R16 and R26 is "5". The average depth level n of the two contact electrodes CC located in unit areas R17 and R27 is "6". The average depth level n of the two contact electrodes CC located in unit areas R18 and R28 is "7".

[0153] Furthermore, in the comparative example semiconductor memory device, for example, such as Figure 44 As shown, the number m of contact electrodes CC contained in multiple unit regions is "2". Furthermore, the average length in the Z direction of the two contact electrodes with the longest and second longest Z-direction lengths (e.g., contact electrodes CC18(7) and CC17(6)) is "6.5". Therefore, "the first length" is "6.5". Additionally, the average length in the Z direction of the two contact electrodes with the shortest and second shortest Z-direction lengths (e.g., contact electrodes CC11(0) and CC12(1)) is "0.5". Therefore, "the second length" is "0.5".

[0154] As described above, the maximum value of the average length (average value for each depth level) of the Z-direction length of the two contact electrodes CC in each unit area is "7" (the average value of the Z-direction length of the two contact electrodes CC18, CC28, CC38, and CC48 in unit areas R18 and R28). Therefore, the average value of the Z-direction length of the two contact electrodes CC18, CC28, CC38, and CC48 in unit areas R18 and R28 is greater than "6.5" (the "first length"). Furthermore, the minimum value of the average length of the Z-direction length of the two contact electrodes CC in each unit area is "0" (the average value of the Z-direction length of the two contact electrodes CC11, CC21, CC31, and CC41 in unit areas R11 and R21). Therefore, the average value of the Z-direction length of the two contact electrodes CC11, CC21, CC31, and CC41 in unit areas R11 and R21 is less than "0.5" (the "second length").

[0155] [Manufacturing Method]

[0156] Next, refer to Figure 45 and Figure 46 The manufacturing method of the comparative example semiconductor memory device will be described. Figure 45 and Figure 46 This is a schematic cross-sectional view used to illustrate the manufacturing method of a comparative example semiconductor memory device.

[0157] In the manufacturing of the comparative example semiconductor memory device, the same procedures as referenced are performed. Figure 9 The explained procedures are for reference only. Figure 42 The process described above is the same as the process for forming the contact hole array CHG(0) and the contact electrode array CCG(0).

[0158] Figure 45 and Figure 46 The structures shown are respectively compared with the reference Figure 30 and Figure 33 The construction correspondences have been explained. Figure 30 and Figure 33 The illustrated resist 151 in the bonding region R HU It has a constant film thickness (thickness in the Z direction) and a flat upper surface. On the other hand, Figure 45 and Figure 46 The illustrated resist 151 in the bonding region R HU In the middle, there is a deviation in film thickness (thickness in the Z direction), resulting in a height difference d3 on the upper surface.

[0159] Specifically, for example in Figure 45 and Figure 46 In the structure shown, the storage hole region R MHThe film thickness of resist 151 is d1. The film thickness of resist 151 increases with the distance from the storage hole region R. MH The thickness of the resist 151 gradually decreases as it moves away from the contact hole CH14(3). The film thickness of the resist 151 above the contact hole CH14(3) increases sharply towards the contact hole CH15(0). Furthermore, the film thickness of the resist 151 again increases from the storage hole region R. MH As the distance increases, the thickness gradually decreases. The difference in film thickness of the resist 151 as described above results in a height difference d3.

[0160] In the comparative example semiconductor memory device, the same row of contact holes CHG(0) is arranged in the Y direction. Therefore, a bias occurs in the depth of the contact holes CH. That is, the contact holes CH with shallower depths are positioned at a distance of R from the memory hole region. MH In nearby areas (e.g., unit areas R11, R21, R15, R25), the contact holes CH with a greater depth are positioned at a distance of R from the storage hole area. MH In distant regions (e.g., unit areas R14, R24, R18, R28), when applying resist 151, the amount of resist 151 absorbed is greater for contact holes CH with deeper depths compared to contact holes CH with shallower depths. As a result, the resist 151 film thickness above contact holes CH with deeper depths is thinner than that above contact holes CH with shallower depths.

[0161] Thus, due to the deviation in the depth of the contact hole CH, a deviation occurs in the film thickness of the resist 151. Therefore, the optimal focus of the exposure apparatus will deviate at locations where the resist 151 is thick and where it is thin. Consequently, the process margin of the photolithography decreases relative to the focus deviation of the exposure apparatus. As a result, there is a possibility that the contact hole CH may become unopened, or that the dimensional uniformity of the contact hole CH may decrease. Furthermore, at locations with deep contact hole CHs, there is a possibility of insufficient resist 151 film thickness. In particular, the more layers of conductive layer 110 there are, the deeper the contact hole CH becomes, and the more likely insufficient resist 151 film thickness will occur.

[0162] In contrast, in the semiconductor memory device of the first embodiment, whenever a signal is received from the memory hole region R... MH As the contact hole CH moves further away, the depth of the contact hole column CHG(0) increases layer by layer, and each time it moves away from the storage hole region R... MH As the contact hole CH depth decreases layer by layer, the contact hole rows CHG(1) are arranged alternately in the Y direction. Therefore, there is no bias in the depth of the contact hole CH per unit area, and the film thickness of the resist 151 is uniform.

[0163] For example, such as Figure 32As shown, it is configured in all unit areas R11~R18 and R21~R28 (refer to...). Figure 8 The average value of the depth grade n of the two contact holes CH within each unit region R11-R18 and R21-R28 is the same value, "1.5". Furthermore, the diameters of all contact holes CH are the same or approximately the same. In this case, the amount of resist 151 absorbed by the two contact holes CH disposed in each unit region R11-R18 and R21-R28 is the same or approximately the same in each unit region R11-R18 and R21-R28. As a result, in the joint region R... HU In the process, the film thickness of resist 151 is the same or approximately the same.

[0164] Therefore, a decrease in photolithography process margin can be avoided. As a result, it is possible to prevent the formation of unopened contact holes CH and to prevent a decrease in the dimensional uniformity of contact hole CH. In addition, it is possible to prevent insufficient film thickness of resist 151.

[0165] [Second Implementation]

[0166] [structure]

[0167] Next, refer to Figures 47-51 The semiconductor memory device of the second embodiment will be described. Figure 47 This is a schematic top view showing a portion of the structure of the semiconductor memory device according to the second embodiment. Figure 48 It is Figure 47 The diagram shows a schematic cross-sectional view of the structure when cut along line HH′ and viewed in the direction of the arrow. Figure 49 It is Figure 47 The diagram shows a schematic cross-sectional view of the structure when cut along line II′ and viewed in the direction of the arrow. Figure 50 It is Figure 47 The diagram shows a schematic cross-sectional view of the structure when cut along line JJ′ and viewed in the direction of the arrow. Figure 51 yes Figure 47 A schematic enlarged view of the joint area shown.

[0168] In the semiconductor memory device of the first embodiment, as referred to Figure 2 and Figure 3 As explained, a column of contact electrodes CCG, each having eight contact electrodes CC, is provided between the inter-block insulating layers ST. In contrast, in the semiconductor memory device of the second embodiment, as... Figure 47 As shown, three rows of contact electrode columns CCG2, each with eight contact electrodes CC, are arranged between the inter-block insulating layers ST. Furthermore, multiple memory blocks BLK arranged in the Y direction are formed as the region between the inter-block insulating layers ST.

[0169] Furthermore, in the semiconductor memory device of the first embodiment, as referred to... Figure 2 , Figure 4 , Figure 6 As explained above, eight layers of conductive layer 110 and insulating layer 101 are formed. In contrast, in the semiconductor memory device of the second embodiment, as... Figures 48-50 As shown, the conductive layer 110 and the insulating layer 101 are formed in 24 layers.

[0170] For example, such as Figure 47 As shown, the junction region R of the storage block BLK HU It has a portion of a conductive layer 110 and multiple contact electrodes CC arranged in a matrix in the X and Y directions.

[0171] Furthermore, regarding the configuration in the joint area R HU In multiple contact electrodes CC Figure 47 The multiple contact electrodes CC shown are sometimes referred to as contact electrode CCab, specifically the a-th (a is an integer greater than 1) contact electrode counted from the +Y direction to the -Y direction and the b-th (b is an integer greater than 1) contact electrode counted from the -X direction to the +X direction.

[0172] Sometimes, the column of eight contact electrodes CC arranged in the X direction is called contact electrode column CCG2. Additionally, the regions corresponding to contact electrode column CCG2 are sometimes referred to as contact electrode regions. For example... Figure 47 As shown, in the joint region R HU Between the inter-block insulating layers ST, three contact electrode columns CCG2(0), CCG2(1), and CCG2(2) are arranged in the Y direction.

[0173] like Figure 48 As shown, the contact electrode array CCG2(0) extends from a distance R from the storage hole region. MH Starting from the nearest side, the contact electrodes are sequentially provided as follows: CC11(0), CC12(12), CC13(3), CC14(15), CC15(6), CC16(18), CC17(9), and CC18(21).

[0174] like Figure 49 As shown, the contact electrode array CCG2(1) extends from the storage hole region R MH Starting from the nearest side, the contact electrodes are sequentially provided as follows: CC21(1), CC22(13), CC23(4), CC24(16), CC25(7), CC26(19), CC27(10), and CC28(22).

[0175] like Figure 50 As shown, the contact electrode array CCG2(2) extends from the storage hole region R MHStarting from the nearest side, the contact electrodes are sequentially provided as follows: CC31(2), CC32(14), CC33(5), CC34(17), CC35(8), CC36(20), CC37(11), and CC38(23).

[0176] exist Figure 51 In the example, a certain area comprising six contact electrodes CC arranged in 3 rows and 2 columns (3 rows in the Y direction and 2 columns in the X direction) is defined as the unit region. The bonding region R... HU It is hypothetically divided into multiple unit areas.

[0177] exist Figure 51 In the diagram, unit region S11 is the region containing 6 contact electrodes CC11(0), CC12(12), CC21(1), CC22(13), CC31(2), and CC32(14). Unit region S12 is the region containing 6 contact electrodes CC13(3), CC14(15), CC23(4), CC24(16), CC33(5), and CC34(17). Unit region S13 is the region containing 6 contact electrodes CC15(6), CC16(18), CC25(7), CC26(19), CC35(8), and CC36(20). Unit region S14 is the region containing 6 contact electrodes CC17(9), CC18(21), CC27(10), CC28(22), CC37(11), and CC38(23).

[0178] The average depth grade n of the six contact electrodes CC disposed in unit area S11 is "7" (=42 / 6). The average depth grade n of the six contact electrodes CC disposed in unit area S12 is "10" (=60 / 6). The average depth grade n of the six contact electrodes CC disposed in unit area S13 is "13" (=78 / 6). The average depth grade n of the six contact electrodes CC disposed in unit area S14 is "16" (=96 / 6).

[0179] The minimum average of the depth levels n of the six contact electrodes CC is “7” for unit region S11, and the maximum average of the depth levels n of the six contact electrodes CC is “16” for unit region S14.

[0180] In addition, such as Figure 51As shown, the contact electrode array CCG2(0) with contact electrodes CC41(0), CC42(12), CC43(3), CC44(15), CC45(6), CC46(18), CC47(9), CC48(21) is the same contact electrode array CCG2(0) with contact electrodes CC11(0), CC12(12), CC13(3), CC14(15), CC15(6), CC16(18), CC17(9), CC18(21) as the contact electrode array CCG2(0).

[0181] In addition, such as Figure 47 As shown, the junction region R of multiple contact electrodes CC is configured. HU The region R is divided into the first region arranged in the X direction. HU1 and Region 2 R HU2 For example, region R1 HU1 It includes the region containing contact electrodes CC11~CC14, CC21~CC24, ..., and the second region R. HU2 It includes the region containing contact electrodes CC15~CC18, CC25~CC28, ...

[0182] Furthermore, the number of contact electrodes CC contained in multiple unit regions is set to m (m is an integer greater than or equal to 2). Also, the average length of the m contact electrodes CC with the longest Z-direction length from the 1st to the mth longest is set as the "3rd length". Additionally, the average length of the m contact electrodes CC with the shortest Z-direction length from the 1st to the mth shortest is set as the "4th length".

[0183] For example, in Figure 51 In the example, the number m of contact electrodes CC contained in multiple unit regions is "6". Furthermore, the average length in the Z direction of the six contact electrodes with the longest Z-direction lengths from the 1st to the 6th longest (e.g., contact electrodes CC38(23), CC28(22), CC18(21), CC36(20), CC26(19), CC16(18)) is "20.5". Therefore, the "3rd length" is "20.5". Additionally, the average length in the Z direction of the six contact electrodes with the shortest Z-direction lengths from the 1st to the 6th shortest (e.g., contact electrodes CC11(0), CC21(1), CC31(2), CC13(3), CC23(4), CC33(5)) is "2.5". Therefore, the "4th length" is "2.5".

[0184] As described above, the minimum value of the average value of the depth level n of the six contact electrodes CC is "7" in unit region S11, and the maximum value of the average value of the depth level n of the six contact electrodes CC is "16" in unit region S14. Therefore, the average value of the Z-direction length of the six contact electrodes CC in each unit region S11 to S14 is smaller than the "third length" and larger than the "fourth length".

[0185] [Manufacturing Method]

[0186] Next, refer to Figures 52-54 The manufacturing method of the semiconductor memory device according to the second embodiment will be described. Figures 52-54 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the second embodiment.

[0187] The manufacturing method of the semiconductor memory device in the second embodiment is substantially the same as that in the manufacturing method of the semiconductor memory device in the first embodiment.

[0188] However, in the manufacturing method of the semiconductor memory device in the second embodiment, in conjunction with Figure 9 In the corresponding process, a 24-layer sacrificial layer 111 is formed.

[0189] Furthermore, in the semiconductor memory device manufacturing method of the first embodiment, the processing of the 1st, 2nd, and 4th layers of the contact hole CH (processing of layers raised to powers of 2) is combined to form the sacrificial layers 111(0) to 111(7) reaching the 1st to 8th layers. In contrast, in the semiconductor memory device manufacturing method of the second embodiment, the processing of the 1st, 2nd, 3rd, 6th, and 12th layers of the contact hole CH is combined to form the sacrificial layers 111(0) to 111(23) reaching the 1st to 24th layers.

[0190] In addition, Figures 52-54 The diagram shows the situation after the 6-layer processing is completed, when the corresponding resist 151 is removed and the resist 151 is recoated.

[0191] [Comparative Example]

[0192] [structure]

[0193] Next, refer to Figure 55 and Figure 56 The structure of the comparative example semiconductor memory device will be described. Figure 55 This is a schematic top view of a comparative example semiconductor memory device. Figure 56 yes Figure 55 A schematic enlarged view of the joint area shown.

[0194] For example, such as Figure 55 As shown, the junction region R of the storage block BLK HU It has a portion of a conductive layer 110 and multiple contact electrodes CC arranged in a matrix in the X and Y directions.

[0195] Furthermore, regarding the configuration in the joint area R HU In multiple contact electrodes CC Figure 55 and Figure 56 The multiple contact electrodes CC shown are sometimes referred to as contact electrode CCab, specifically the a-th (a is an integer greater than 1) contact electrode counted from the +Y direction to the -Y direction and the b-th (b is an integer greater than 1) contact electrode counted from the -X direction to the +X direction.

[0196] Sometimes, a column of eight contact electrodes CC arranged in the X direction is called contact electrode column CCG2′. For example... Figure 55 As shown, in the joint region R HU Between the inter-block insulating layer ST, three contact electrode columns CCG2′(0), CCG2′(1), and CCG2′(2) are arranged in the Y direction.

[0197] like Figure 55 and Figure 56 As shown, the contact electrode array CCG2′(0) extends from the storage hole region R MH Starting from the nearest side, the contact electrodes are sequentially provided as follows: CC11(0), CC12(3), CC13(6), CC14(9), CC15(12), CC16(15), CC17(18), and CC18(21).

[0198] Additionally, the contact electrode array CCG2′(1) extends from the storage hole region R MH Starting from the nearest side, the contact electrodes are sequentially provided as follows: CC21(1), CC22(4), CC23(7), CC24(10), CC25(13), CC26(16), CC27(19), and CC28(22).

[0199] Additionally, the contact electrode array CCG2′(2) extends from the storage hole region R MH Starting from the nearest side, the contact electrodes are sequentially provided as follows: CC31(2), CC32(5), CC33(8), CC34(11), CC35(14), CC36(17), CC37(20), and CC38(23).

[0200] exist Figure 56 In the example, a certain area comprising six contact electrodes CC arranged in 3 rows and 2 columns (3 rows in the Y direction and 2 columns in the X direction) is defined as the unit region. The bonding region R... HUIt is hypothetically divided into multiple unit areas.

[0201] exist Figure 56 In the diagram, unit region S11 is the region containing 6 contact electrodes CC11(0), CC12(3), CC21(1), CC22(4), CC31(2), and CC32(5). Unit region S12 is the region containing 6 contact electrodes CC13(6), CC14(9), CC23(7), CC24(10), CC33(8), and CC34(11). Unit region S13 is the region containing 6 contact electrodes CC15(12), CC16(15), CC25(13), CC26(16), CC35(14), and CC36(17). Unit region S14 is the region containing 6 contact electrodes CC17(18), CC18(21), CC27(19), CC28(22), CC37(20), and CC38(23).

[0202] The average depth grade n of the six contact electrodes CC disposed in unit area S11 is "2.5" (=15 / 6). The average depth grade n of the six contact electrodes CC disposed in unit area S12 is "8.5" (=51 / 6). The average depth grade n of the six contact electrodes CC disposed in unit area S13 is "14.5" (=87 / 6). The average depth grade n of the six contact electrodes CC disposed in unit area S14 is "20.5" (=123 / 6).

[0203] The minimum average of the depth level n of the 6 contact electrodes CC is “2.5” for unit area S11, and the maximum average of the depth level n of the 6 contact electrodes CC is “20.5” for unit area S14.

[0204] In addition, such as Figure 56 As shown, the contact electrode array CCG2′(0) with contact electrodes CC41(0), CC42(3), CC43(6), CC44(9), CC45(12), CC46(15), CC47(18), CC48(21) is the same contact electrode array CCG2′(0) with contact electrodes CC11(0), CC12(3), CC13(6), CC14(9), CC15(12), CC16(15), CC17(18), CC18(21) as the contact electrode array CCG2′(0).

[0205] Furthermore, in the comparative example semiconductor memory device, for example, such as Figure 56As shown, the number m of contact electrodes CC contained in the multiple unit regions is "6". In addition, the "third length" as described in the second embodiment is "20.5" and the "fourth length" is "2.5".

[0206] As described above, the minimum average value of the depth level n of the six contact electrodes CC is "2.5" for unit region S11, and the maximum average value of the depth level n of the six contact electrodes CC is "20.5" for unit region S14. Therefore, the average length of the six contact electrodes CC in the Z direction within unit region S14 is the same as the "third length", and the average length of the six contact electrodes CC in the Z direction within unit region S11 is the same as the "fourth length". Thus, the average length of the six contact electrodes CC in the Z direction within each unit region S11 to S14 is not smaller than the "third length". Furthermore, the average length of the six contact electrodes CC in the Z direction within each unit region S11 to S14 is not larger than the "fourth length".

[0207] [Manufacturing Method]

[0208] Next, refer to Figures 57-59 The manufacturing method of the comparative example semiconductor memory device will be described. Figures 57-59 This is a schematic cross-sectional view used to illustrate the manufacturing method of a comparative example semiconductor memory device.

[0209] In the manufacture of the comparative example semiconductor memory device, the same processes as those described in the second embodiment are performed.

[0210] Figures 57-59 The structures shown are respectively compared with the reference Figures 52-54 The construction correspondences have been explained. Figures 52-54 The illustrated resist 151 in the bonding region R HU It has a constant film thickness (thickness in the Z direction) and a flat upper surface.

[0211] on the other hand, Figures 57-59 The illustrated resist 151 in the bonding region R HU In the middle, there is a deviation in film thickness (thickness in the Z direction), resulting in a height difference d3 on the upper surface.

[0212] Specifically, for example in Figures 57-59 In the structure shown, the storage hole region R MH The film thickness of resist 151 is d1. The film thickness of resist 151 increases with the distance from the storage hole region R. MHThe thickness of the resist 151 gradually decreases as it moves away from the contact hole CH14(9). The film thickness of the resist 151 above the contact hole CH14(9) is d2. The film thickness of the resist 151 increases sharply from above the contact hole CH14(9) toward above the contact hole CH15(0). Furthermore, the film thickness of the resist 151 again increases from the storage hole region R. MH As the distance increases, the thickness gradually decreases. The difference in film thickness of the resist 151 as described above results in a height difference d3.

[0213] In the comparative example semiconductor memory device, the minimum average value of the depth grade n of the six contact electrodes CC is "2.5" per unit area S11, and the maximum average value of the depth grade n of the six contact electrodes CC is "20.5" per unit area S14. This creates a bias in the depth of the contact hole CH per unit area. In this case, when coating the resist 151, the amount of resist 151 absorbed by the deeper contact hole CH is greater than that of the shallower contact hole CH. As a result, the resist 151 film thickness above the deeper contact hole CH is thinner than that above the shallower contact hole CH.

[0214] Thus, due to the deviation in the depth of the contact hole CH, a deviation occurs in the film thickness of the resist 151. Therefore, the optimal focus of the exposure apparatus will deviate at locations where the resist 151 film is thick and where it is thin. Consequently, the process margin of the photolithography decreases relative to the focus deviation of the exposure apparatus. As a result, there is a possibility that the contact hole CH may become unopened, or that the dimensional uniformity of the contact hole CH may decrease. Furthermore, at locations with deeper contact hole CH, there is a possibility that the resist 151 film thickness may be insufficient.

[0215] In contrast, in the semiconductor memory device of the second embodiment, the minimum average value of the depth level n of the six contact electrodes CC is "7" per unit area S11, and the maximum average value of the depth level n of the six contact electrodes CC is "16" per unit area S14. Thus, compared to the semiconductor memory device of the comparative example, the semiconductor memory device of the second embodiment has a smaller deviation in the depth of the contact hole CH per unit area. As a result, compared to the semiconductor memory device of the comparative example, the semiconductor memory device of the second embodiment has a smaller deviation in the film thickness of the resist 151.

[0216] Therefore, process margin in photolithography can be ensured. As a result, the generation of unopened contact holes CH and the decrease in the dimensional uniformity of contact hole CH can be prevented. In addition, insufficient film thickness of resist 151 can be prevented.

[0217] [Third Implementation]

[0218] Next, refer to Figure 60The semiconductor memory device of the third embodiment will be described. Figure 60 This is a schematic enlarged view of the bonding area of ​​the semiconductor memory device according to the third embodiment.

[0219] In the semiconductor memory device of the third embodiment, such as Figure 60 As shown, three rows of contact electrode columns CCG3, each containing eight contact electrodes CC, are provided between the inter-block insulating layers ST. Furthermore, in the semiconductor memory device of the third embodiment, 24 layers are formed of the conductive layer 110 and the insulating layer 101.

[0220] Sometimes, a column of eight contact electrodes CC arranged in the X direction is called contact electrode column CCG3. Additionally, the regions corresponding to contact electrode column CCG3 are sometimes referred to as contact electrode regions. For example... Figure 60 As shown, in the joint region R HU Between the inter-block insulating layers ST, three contact electrode columns CCG3(0), CCG3(1), and CCG3(2) are arranged in the Y direction.

[0221] like Figure 60 As shown, the contact electrode array CCG3(0) extends from the storage hole region R MH Starting from the nearest side, the contact electrodes are sequentially provided as CC11(0), CC12(1), CC13(2), CC14(3), CC15(4), CC16(5), CC17(6), and CC18(7).

[0222] Contact electrode array CCG3(1) from the storage hole region R MH Starting from the nearest side, the contact electrodes are sequentially provided as follows: CC21(8), CC22(9), CC23(10), CC24(11), CC25(12), CC26(13), CC27(14), and CC28(15).

[0223] Contact electrode array CCG3(2) from the storage hole region R MH Starting from the nearest side, the contact electrodes are sequentially provided as follows: CC31(16), CC32(17), CC33(18), CC34(19), CC35(20), CC36(21), CC37(22), and CC38(23).

[0224] exist Figure 60 In the example, a certain area comprising three contact electrodes CC arranged in the Y direction is defined as the unit region. The bonding region R HU It is hypothetically divided into multiple unit areas.

[0225] exist Figure 60In the diagram, unit region T11 is the region containing three contact electrodes CC11(0), CC21(8), and CC31(16). Unit region T12 is the region containing three contact electrodes CC12(1), CC22(9), and CC32(17). Unit region T13 is the region containing three contact electrodes CC13(2), CC23(10), and CC33(18). Unit region T14 is the region containing three contact electrodes CC14(3), CC24(11), and CC34(19). Unit region T15 is the region containing three contact electrodes CC15(4), CC25(12), and CC35(20). Unit region T16 is the region containing three contact electrodes CC16(5), CC26(13), and CC36(21). Unit region T17 is the region containing three contact electrodes CC17(6), CC27(14), and CC37(22). The unit region T18 is the region that includes three contact electrodes CC18(7), CC28(15), and CC38(23).

[0226] The average depth level n of the three contact electrodes CC disposed in unit area T11 is "8" (=24 / 3). The average depth level n of the three contact electrodes CC disposed in unit area T12 is "9" (=27 / 3). The average depth level n of the three contact electrodes CC disposed in unit area T13 is "10" (=30 / 3). The average depth level n of the three contact electrodes CC disposed in unit area S14 is "11" (=33 / 3).

[0227] The average depth grade n of the three contact electrodes CC disposed within unit area T15 is "12" (=36 / 3). The average depth grade n of the three contact electrodes CC disposed within unit area T16 is "13" (=39 / 3). The average depth grade n of the three contact electrodes CC disposed within unit area T17 is "14" (=42 / 3). The average depth grade n of the three contact electrodes CC disposed within unit area S18 is "15" (=45 / 3).

[0228] The minimum average of the depth levels n of the three contact electrodes CC is “8” for unit area T11, and the maximum average of the depth levels n of the three contact electrodes CC is “15” for unit area T18.

[0229] In this way, shallow-depth contact electrodes CC and deep-depth contact electrodes CC are arranged in each unit region T11 to T18. Therefore, the difference between the minimum and maximum values ​​of the average values ​​of the depth grades n of the contact electrodes CC is reduced. This ensures the process margin of photolithography. As a result, it is possible to prevent the formation of unopened contact holes CH and to prevent a decrease in the dimensional uniformity of the contact holes CH. In addition, it is possible to prevent insufficient film thickness of the resist 151 and to form the desired pattern on the resist 151.

[0230] [Fourth Implementation]

[0231] Next, refer to Figure 61 The semiconductor memory device of the fourth embodiment will be described. Figure 61 This is a schematic enlarged view of the bonding area of ​​the semiconductor memory device according to the fourth embodiment.

[0232] In the semiconductor memory device of the fourth embodiment, such as Figure 61 As shown, three rows of contact electrode columns CCG4, each containing eight contact electrodes CC, are provided between the inter-block insulating layers ST. Furthermore, in the semiconductor memory device of the fourth embodiment, 24 layers of conductive layer 110 and insulating layer 101 are formed.

[0233] Sometimes, a column of eight contact electrodes CC arranged in the X direction is called contact electrode column CCG4. Additionally, the regions corresponding to contact electrode column CCG4 are sometimes referred to as contact electrode regions. For example... Figure 61 As shown, in the joint region R HU Between the inter-block insulating layers ST, three contact electrode columns CCG4(0), CCG4(1), and CCG4(2) are arranged in the Y direction.

[0234] like Figure 61 As shown, the contact electrode array CCG4(0) extends from the storage hole region R MH Starting from the nearest side, the contact electrodes are sequentially provided as CC11(0), CC12(1), CC13(2), CC14(3), CC15(4), CC16(5), CC17(6), and CC18(7).

[0235] Contact electrode array CCG4(1) from the storage hole region R MH Starting from the nearest side, the contact electrodes are sequentially provided as CC21(15), CC22(14), CC23(13), CC24(12), CC25(11), CC26(10), CC27(9), and CC28(8).

[0236] Contact electrode array CCG4(2) from the storage hole region R MHStarting from the nearest side, the contact electrodes are sequentially provided as follows: CC31(16), CC32(17), CC33(18), CC34(19), CC35(20), CC36(21), CC37(22), and CC38(23).

[0237] exist Figure 61 In the example, a certain area comprising three contact electrodes CC arranged in the Y direction is defined as the unit region. The bonding region R HU It is hypothetically divided into multiple unit areas.

[0238] exist Figure 61 In the diagram, unit region U11 is the region containing three contact electrodes CC11(0), CC21(15), and CC31(16). Unit region U12 is the region containing three contact electrodes CC12(1), CC22(14), and CC32(17). Unit region U13 is the region containing three contact electrodes CC13(2), CC23(13), and CC33(18). Unit region U14 is the region containing three contact electrodes CC14(3), CC24(12), and CC34(19). Unit region U15 is the region containing three contact electrodes CC15(4), CC25(11), and CC35(20). Unit region U16 is the region containing three contact electrodes CC16(5), CC26(10), and CC36(21). Unit region U17 is the region containing three contact electrodes CC17(6), CC27(9), and CC37(22). Unit region U18 is the region that includes three contact electrodes CC18(7), CC28(8), and CC38(23).

[0239] The average depth grade n of the three contact electrodes CC located within unit area U11 is approximately "10.33" (=3 1 / 3). The average depth grade n of the three contact electrodes CC located within unit area U12 is approximately "10.67" (=3 2 / 3). The average depth grade n of the three contact electrodes CC located within unit area U13 is "11" (=3 3 / 3). The average depth grade n of the three contact electrodes CC located within unit area U14 is approximately "11.33" (=3 4 / 3).

[0240] The average depth grade n of the three contact electrodes CC located within unit area U15 is approximately "11.67" (=35 / 3). The average depth grade n of the three contact electrodes CC located within unit area U16 is "12" (=36 / 3). The average depth grade n of the three contact electrodes CC located within unit area U17 is approximately "12.33" (=37 / 3). The average depth grade n of the three contact electrodes CC located within unit area U18 is approximately "12.67" (=38 / 3).

[0241] The minimum average of the depth level n of the three contact electrodes CC is approximately “10.33” per unit area U11, and the maximum average of the depth level n of the three contact electrodes CC is approximately “12.67” per unit area U18.

[0242] Thus, shallow-depth contact electrodes CC and deep-depth contact electrodes CC are disposed in each unit region U11 to U18. Therefore, in the semiconductor memory device of the fourth embodiment, compared with the semiconductor memory device of the third embodiment, the difference between the minimum value and the maximum value of the average value of the depth level n of the contact electrode CC is smaller. As a result, the process margin of photolithography can be ensured. Consequently, the generation of unopened contact holes CH and the decrease in the uniformity of the size of the contact holes CH can be prevented. In addition, insufficient film thickness of the resist 151 can be prevented.

[0243] [Other implementation methods]

[0244] The semiconductor memory devices of the first to fourth embodiments have been described above. However, the structures and manufacturing methods of the semiconductor memory devices of the first to fourth embodiments are merely illustrative, and the specific structures and manufacturing methods can be appropriately adjusted.

[0245] For example, in the junction region R of storage block BLK HU In this context, as a whole, the difference in the average value of the depth of the contact hole CH (contact electrode CC) in each unit area should be reduced.

[0246] For example, in the first embodiment, the deep contact holes CH (contact electrodes CC) and the shallow contact holes CH (contact electrodes CC) are arranged in the Y direction. However, the deep contact holes CH (contact electrodes CC) and the shallow contact holes CH (contact electrodes CC) may also be arranged alternately in the X direction.

[0247] Additionally, for example, in embodiments 1 to 4, the contact hole CH (multiple contact electrodes CC) is located in the bonding region R. HUThe contacts are arranged in a matrix shape in the X and Y directions. However, multiple contact holes CH (contact electrodes CC) can also be arranged in various geometric patterns composed of triangles, squares, etc.

[0248] Furthermore, for example, in the first embodiment, one contact hole row CHG (contact electrode row CCG) is provided between two adjacent inter-block insulating layers ST in the Y direction, and in the second to fourth embodiments, three contact hole rows CHG (contact electrode rows CCG) are provided between two adjacent inter-block insulating layers ST in the Y direction. However, the number of contact hole rows CHG (contact electrode rows CCG) provided between two adjacent inter-block insulating layers ST in the Y direction is not limited to "1" or "3", and may also be "2" or "4 or more".

[0249] Additionally, for example, in embodiments 1 to 4, the contact hole array CHG (contact electrode array CCG) includes 8 contact holes CH (contact electrodes CC). However, the number of contact holes CH (contact electrodes CC) included in the contact hole array CHG (contact electrode array CCG) is not limited to "8", and may be other than that.

[0250] Furthermore, for example, in the first embodiment, the number of conductive layers 110 is "8", and in the second to fourth embodiments, the number of conductive layers 110 is "24". However, the number of conductive layers 110 is not limited to "8" or "24", and may be other than these.

[0251] Furthermore, when applying the resist 151, the amount of resist 151 applied when the depth of the contact hole CH is shallow can be increased compared to when the depth of the contact hole CH is shallow. This is because the amount of resist 151 absorbed by the contact hole CH increases.

[0252] Furthermore, in the first embodiment, unit regions R11-R18 and R21-28 are regions including two contact electrodes CC; in the second embodiment, unit regions S11-S14 are regions including six contact electrodes CC; and in the third and fourth embodiments, unit regions T11-T18 and U11-U18 are regions including three contact electrodes CC. The unit region can be set arbitrarily, but at least the number of contact electrodes contained in the unit region (a certain number) is smaller than the number of conductive layers. Generally, the fewer the number of contact electrodes contained in the unit region (that is, the smaller the area of ​​the unit region), and the smaller the average difference in the depth levels of the contact electrodes within the unit region, the easier it is to achieve a uniform film thickness for the resist 151.

[0253] Additionally, for example, in embodiments 1 to 4, one end of semiconductor layer 120 in the Z direction is connected to semiconductor layer 112. However, one end of semiconductor layer 120 in the Z direction may also be connected to semiconductor substrate 100. Furthermore, for example, in embodiments 1 to 4, contact electrode CC is connected to the upper surface of conductive layer 110. However, contact electrode CC may also be connected to the lower surface of conductive layer 110.

[0254] Additionally, for example, as referenced Figure 10 and Figure 11 As explained, a hard mask 105 is used in the manufacturing methods of the first to fourth embodiments. However, such methods are merely illustrative, and specific methods can be appropriately adjusted. For example, the semiconductor memory device of any embodiment can also be manufactured without using the hard mask 105.

[0255] [other]

[0256] While some embodiments of the invention have been described, these embodiments are provided by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in a wide variety of other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and / or variations thereof are included within the scope and spirit of the invention, and are included within the scope of the claims and their equivalents.

Claims

1. A semiconductor memory device comprising: Storage areas and junction areas arranged in the first direction; and Multiple storage blocks are configured in the storage region and the junction region, and arranged in a second direction intersecting the first direction. Each of the plurality of storage blocks has: Multiple conductive layers are arranged in a third direction that intersects the first direction and the second direction; A semiconductor layer is disposed in the storage region, extends in the third direction, and is opposite to the plurality of conductive layers; A charge storage film is disposed between the plurality of conductive layers and the semiconductor layer; and Multiple contact electrodes are disposed in the bonding region, extend in the third direction, and are respectively connected to any one of the multiple conductive layers. The joining region includes a first region and a second region arranged in the first direction. The first region includes a first contact electrode and a second contact electrode. The second region includes the third contact electrode and the fourth contact electrode. The first average length of the first contact electrode and the second contact electrode in the third direction is equal to the second average length of the third contact electrode and the fourth contact electrode in the third direction.

2. The semiconductor memory device according to claim 1, The plurality of contact electrodes are respectively contained in the first region or the second region. The number of contact electrodes contained in the first region is equal to the number of contact electrodes contained in the second region.

3. The semiconductor memory device according to claim 1, The contact electrodes contained in the first region are respectively arranged in the first direction with the contact electrodes contained in the second region.

4. The semiconductor memory device according to any one of claims 1 to 3, The bonding region includes a first contact electrode region and a second contact electrode region arranged in the second direction. The first contact electrode region and the second contact electrode region each have a predetermined number of contact electrodes arranged in the first direction. The closer the predetermined number of contact electrodes in the first contact electrode region are to one side of the first direction, the longer the length in the third direction. The more the predetermined number of contact electrodes contained in the second contact electrode region are positioned on the other side of the first direction, the longer the length of the third direction becomes.

5. The semiconductor memory device according to any one of claims 1 to 3, The bonding region includes the third contact electrode region. The third contact electrode region includes a fourth contact electrode, a fifth contact electrode, and a sixth contact electrode arranged in the first direction. The fifth contact electrode is disposed between the fourth contact electrode and the sixth contact electrode. The length of the fifth contact electrode in the third direction is either longer or shorter than the length of the fourth contact electrode in the third direction and the length of the sixth contact electrode in the third direction.

6. The semiconductor memory device according to claim 1, It also includes a plurality of insulating layers disposed along the third direction and between the plurality of conductive layers. The first contact electrode is opposite to the first portion of the plurality of insulating layers. The second contact electrode is opposite to the second portion of the plurality of insulating layers. The third contact electrode is opposite to the third portion of the plurality of insulating layers. The fourth contact electrode is opposite to the fourth portion of the plurality of insulating layers.

7. The semiconductor memory device according to claim 1, The joining region includes the third region. The third region includes the fifth contact electrode and the sixth contact electrode. In the third direction, the third average length of the fifth contact electrode and the sixth contact electrode is equal to the first average length and the second average length.

8. A semiconductor memory device comprising: Storage areas and junction areas arranged in the first direction; and The first storage block and the second storage block are disposed in the storage area and the junction area, and are arranged in a second direction intersecting the first direction. The first storage block and the second storage block each have: Multiple conductive layers are arranged in a third direction that intersects the first direction and the second direction; A semiconductor layer is disposed in the storage region, extends in the third direction, and is opposite to the plurality of conductive layers; A charge storage film is disposed between the plurality of conductive layers and the semiconductor layer; and Multiple contact electrodes are disposed in the bonding region, extend in the third direction, and are respectively connected to any one of the multiple conductive layers. The joining region comprises a plurality of unit regions arranged in the first direction. The plurality of contact electrodes contained in the first storage block and the plurality of contact electrodes contained in the second storage block are respectively contained in any of the plurality of unit regions. If the number of contact electrodes contained in each of the plurality of unit regions is set as m, where m is an integer greater than or equal to 2, The average length of the m contact electrodes in the third direction in the first region of the plurality of unit regions is set as the first length. The average length of the m contact electrodes in the third direction in the second region of the plurality of unit regions is set as the second length. Then the first length is equal to the second length.

9. The semiconductor memory device according to claim 8, The average length of the m contact electrodes in the third direction within each of the plurality of unit regions is constant.

10. The semiconductor memory device according to claim 8 or 9, The bonding region includes a first contact electrode region and a second contact electrode region arranged in the second direction. The first contact electrode region and the second contact electrode region each have a predetermined number of contact electrodes arranged in the first direction. The closer the predetermined number of contact electrodes in the first contact electrode region are to one side of the first direction, the longer the length in the third direction. The more the predetermined number of contact electrodes contained in the second contact electrode region are positioned on the other side of the first direction, the longer the length of the third direction becomes.

11. The semiconductor memory device according to claim 8 or 9, The bonding region includes the third contact electrode region. The third contact electrode region includes a fourth contact electrode, a fifth contact electrode, and a sixth contact electrode arranged in the first direction. The fifth contact electrode is disposed between the fourth contact electrode and the sixth contact electrode. The length of the fifth contact electrode in the third direction is either longer or shorter than the length of the fourth contact electrode in the third direction and the length of the sixth contact electrode in the third direction.

12. The semiconductor memory device according to claim 8, It also includes a plurality of insulating layers disposed along the third direction and between the plurality of conductive layers. The m contact electrodes in the first region of the plurality of unit regions are respectively opposite to a portion of the plurality of insulating layers. The m contact electrodes in the second region of the plurality of unit regions are respectively opposite to a portion of the plurality of insulating layers.

13. A semiconductor memory device comprising: Two storage areas arranged in the first direction; A junction area configured between the two storage areas; Multiple conductive layers are disposed in the two storage regions and the bonding region, and arranged in a third direction intersecting the first direction and the second direction; A semiconductor layer is disposed in the storage region, extends in the third direction, and is opposite to the plurality of conductive layers; A charge storage film is disposed between the plurality of conductive layers and the semiconductor layer; and Multiple contact electrodes are disposed in the bonding region, extend in the third direction, and are respectively connected to any one of the multiple conductive layers. The joining region comprises a plurality of unit regions arranged in the first direction. The contact electrode is contained in any of the plurality of unit regions. If the number of contact electrodes contained in each of the plurality of unit regions is set as m, where m is an integer greater than or equal to 2, The average length of the m contact electrodes in the third direction in one of the plurality of unit regions is set as the first length. The average length of the m contact electrodes in the third direction in another unit region of the plurality of unit regions is set as the second length. Then the first length is equal to the second length.

14. The semiconductor memory device according to claim 13, The average length of the m contact electrodes in the third direction within each of the plurality of unit regions is constant.

15. The semiconductor memory device according to claim 13 or 14, The bonding region includes a first contact electrode region and a second contact electrode region arranged in a second direction intersecting the first direction and the third direction. The first contact electrode region and the second contact electrode region each have a predetermined number of contact electrodes arranged in the first direction. The closer the predetermined number of contact electrodes in the first contact electrode region are to one side of the first direction, the longer the length in the third direction. The more the predetermined number of contact electrodes contained in the second contact electrode region are positioned on the other side of the first direction, the longer the length of the third direction becomes.

16. The semiconductor memory device according to claim 13 or 14, The bonding region includes the third contact electrode region. The third contact electrode region includes a fourth contact electrode, a fifth contact electrode, and a sixth contact electrode arranged in the first direction. The fifth contact electrode is disposed between the fourth contact electrode and the sixth contact electrode. The length of the fifth contact electrode in the third direction is either longer or shorter than the length of the fourth contact electrode in the third direction and the length of the sixth contact electrode in the third direction.

17. The semiconductor memory device according to claim 13, It also includes a plurality of insulating layers disposed along the third direction and between the plurality of conductive layers. The m contact electrodes in one of the plurality of unit regions are respectively opposite to a portion of the plurality of insulating layers. The m contact electrodes in another unit region of the plurality of unit regions are respectively opposite to a portion of the plurality of insulating layers.

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