A method of manufacturing a NOR flash memory device
By employing an ONO layer structure with thinned HTO, SiN, and thickened TEOS layers during the Nor flash memory device manufacturing process, and retaining the TEOS layer during etching, the problem of small etching window was solved, thereby improving the ILD filling performance of Nor flash memory devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HUA HONG SEMICON WUXI LTD
- Filing Date
- 2023-01-09
- Publication Date
- 2026-06-05
AI Technical Summary
During the manufacturing process of 4Xnm Nor Flash, the Dual Spacer DEWDE process results in a small sidewall etching window that cannot be accurately controlled, causing damage to the active region and SIN residue, which affects the ILD filling performance.
An ONO layer structure is adopted, consisting of a thinned HTO layer, a thinned SiN layer, and a thickened TEOS layer. A certain thickness of TEOS layer is retained during etching. The TEOS layer in the memory cell area and the peripheral area are removed by two wet etching processes to avoid SiN loss and form a second sidewall.
The etching window was improved, avoiding damage to the active area and SIN residue, thus improving the ILD filling performance of Nor flash memory devices.
Smart Images
Figure CN115915765B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing technology, and more specifically to a method for manufacturing a NOR flash memory device. Background Technology
[0002] Compared to 55nm NOR Flash (or non-flash memory), at higher technology nodes, 4Xnm Nor Flash, due to a 10-30nm reduction in Y-pitch and an overall area reduction of over 15%, makes ILD (Insulating Diode) filling in the dielectric layer more difficult. To address the ILD filling issue in the Cell region (memory cell area) without altering the Periphery region's sidewall (spacer) thickness, maintaining consistency with 55nm Nor BSL (Periphery BSL), existing technologies employ a Dual Spacer DEWDE process route for HTO (High-Temperature Tolerance) thinning. However, due to the inability to accurately control SIN Loss during the first sidewall partial etching, the final sidewall etching window is relatively small. Figure 1 As shown in the coil, active area damage (AA Damage) or SIN residue appears. Summary of the Invention
[0003] In view of this, the present invention provides a method for manufacturing a NOR flash memory device to improve the Dual Spacer etching window, thereby improving the fill performance of the NOR Flash ILD.
[0004] This invention provides a method for manufacturing a NOR flash memory device, the NOR flash memory device comprising a memory cell area and a peripheral area, comprising the following steps:
[0005] Step 1: Provide a substrate on which a gate structure is formed;
[0006] Step 2: Deposit an ONO layer, which includes a thinned HTO layer, a thinned SiN layer, and a thickened TEOS layer;
[0007] Step 3: Etch the ONO layer to form a first sidewall, the first sidewall including the TEOS layer;
[0008] Step 4: Etch away the TEOS layer in the outer region;
[0009] Step 5: Form the source and drain regions in the substrate using photolithography.
[0010] Step 6: Etch away the TEOS layer in the memory cell area;
[0011] Step 7: Perform source and drain ion implantation on the memory cell region;
[0012] Step 8: Deposit a TEOS layer and etch it to form a second sidewall;
[0013] Step 9: Perform source and drain ion implantation on the peripheral region.
[0014] Preferably, the substrate in step one is a silicon substrate.
[0015] Preferably, the gate structure described in step one is a control gate.
[0016] Preferably, in step two, the HTO layer is thinned by 20–50 angstroms, the SiN layer is thinned by 50–90 angstroms, and the TEOS layer has a thickness of 300–500 angstroms.
[0017] Preferably, the etching in step three includes partially etching the TEOS layer over time.
[0018] Preferably, the thickness of the TEOS layer in step three is within 50 to 200 angstroms.
[0019] Preferably, the thickness of the TEOS layer is 100 to 200 angstroms.
[0020] Preferably, the etching in step four employs a barrier-free wet etching process.
[0021] Preferably, the etching in step six employs a wet cleaning process with photoresist.
[0022] Preferably, the thickness of the TEOS layer in step eight is 200–400 angstroms.
[0023] This invention deposits a thinned HTO layer, a thinned SiN layer, and a thickened TEOS layer to form an ONO layer. When etching the ONO layer to form the first sidewall, etching is performed over time to retain a certain thickness of the TEOS layer, ensuring no loss of the SiN layer. The TEOS layer on the memory cell area and the peripheral area are then removed by two different wet etching processes, and the TEOS layer is deposited again. This effectively improves the subsequent sidewall etching window, avoids damage to the active area or SiN residue, and improves the filling performance of the ILD in Nor flash memory devices. Attached Figure Description
[0024] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings, in which:
[0025] Figure 1 This diagram illustrates the active region damage observed in existing technologies.
[0026] Figure 2The flowchart shown is a method for manufacturing a NOR flash memory device according to an embodiment of the present invention;
[0027] Figure 3 The diagram shown is a structural schematic of the ONO layer after deposition according to an embodiment of the present invention.
[0028] Figure 4 The diagram shows the structure after etching the ONO layer according to an embodiment of the present invention.
[0029] Figure 5 The diagram shown is a structural schematic of the TEOS layer after etching and removal according to an embodiment of the present invention.
[0030] Figure 6 The diagram shows the structure after the TEOS layer is re-deposited according to an embodiment of the present invention.
[0031] Figure 7 The diagram shows a structural schematic of the formation of the second sidewall according to an embodiment of the present invention.
[0032] Figure 8 The diagram shows the effect of a method for manufacturing a NOR flash memory device according to an embodiment of the present invention. Detailed Implementation
[0033] The present invention is described below based on embodiments, but the invention is not limited to these embodiments. In the detailed description of the invention below, certain specific details are described in detail. Those skilled in the art will fully understand the invention even without these details. To avoid obscuring the essence of the invention, well-known methods, processes, flows, elements, and circuits are not described in detail.
[0034] Furthermore, those skilled in the art should understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.
[0035] Unless the context explicitly requires it, words such as "including" or "contains" throughout the application should be interpreted as including rather than exclusive or exhaustive; that is, meaning "including but not limited to".
[0036] In the description of this invention, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this invention, unless otherwise stated, "a plurality of" means two or more.
[0037] In existing technologies, NOR Flash uses a two-spacer process. The first spacer, composed of an ONO (oxide-nitride-oxide) structure, serves as the sidewall for ion implantation in the Cell region (memory cell region). The second spacer, composed of SiN (silicon nitride), serves as the sidewall for ion implantation in the Periphery region (peripheral region). Currently, for 4Xnm NOR Flash, using the Dual Spacer DEWDE process route with HTO thinning, the first sidewall etching uses the SIN layer as the etch stop layer. However, the relatively thick TEOS layer affects the etching process, causing SIN loss, resulting in a smaller etching window for subsequent sidewalls, making it difficult to accurately control the contour, and also causing damage to the active region. Therefore, this invention proposes a new method for manufacturing NOR flash memory devices. The technical solution of this invention will be further described below with reference to the accompanying drawings and specific embodiments.
[0038] Figure 2 The flowchart shown is a method for manufacturing a NOR flash memory device according to an embodiment of the present invention. Figures 3-7 The diagram shows the structural schematics of each step in the manufacturing method of a NOR flash memory device according to an embodiment of the present invention. Figure 2 As shown, the manufacturing method of the NOR flash memory device according to an embodiment of the present invention includes the following steps:
[0039] Step 1: Provide a substrate on which a gate structure is formed.
[0040] The substrate material can be silicon, germanium, silicon-germanium, or silicon carbide, or it can be silicon-on-insulator (SOI) or germanium-on-insulator (GOI), or other materials such as gallium arsenide or other group III or V compounds. In other embodiments, the substrate may include various doped regions depending on the design requirements of the memory. The substrate may include isolation structures (e.g., shallow trench isolation, STI) to isolate the regions and / or semiconductor devices formed on the substrate. The substrate in this embodiment is a silicon substrate, and further, it may be an undoped or lightly doped silicon substrate.
[0041] In this embodiment of the invention, a control gate is formed on the substrate. The NOR flash memory device includes a memory cell region and a peripheral region. A gate oxide layer, a floating gate, a dielectric layer, and a control gate are formed on the memory cell region, and a gate oxide layer and a control gate are formed on the peripheral region.
[0042] Step 2, as follows Figure 3 As shown, an ONO layer is deposited, which includes a thinned HTO layer 11, a thinned SiN layer 12, and a thickened TEOS layer 13.
[0043] In this embodiment of the invention, the HTO layer is thinned by 20–50 angstroms, the SiN layer by 50–90 angstroms, and the TEOS layer is 300–500 angstroms thick. The thickness of the TEOS layer is sufficient to ensure that the Cell region's SAS (Source Self-Alignment) area is filled. In one specific embodiment, the HTO layer is thinned by 40 angstroms, the SiN layer by 60 angstroms, and the TEOS layer is 415 angstroms thick. In existing manufacturing processes for the ONO layer, the bottom silicon dioxide is generally deposited using thermal growth (consuming a silicon substrate) or LPCVD (low-pressure chemical vapor deposition) deposition (not consuming a silicon substrate). This typically includes furnace tube thermal oxidation, nitrogen doping, and thermal annealing. The silicon dioxide surface is then ion-implanted and thermally annealed, or high-temperature N2O nitriding of the surface silicon dioxide followed by thermal annealing introduces Si-N bonds, improving the reliability of the silicon dioxide and its bonding strength with silicon nitride. The sandwich silicon nitride layer is generally deposited using furnace tube LPCVD deposition. To obtain better uniformity and controllability, a low-temperature silicon nitride process is often used, followed by a high-temperature silicon nitride densification process. The top silicon dioxide layer is generally deposited using a furnace tube HTO (high-temperature oxidation) process, followed by an HTO densification process. The deposition of the ONO layer in this embodiment can employ a similar method, depending on the specific circumstances.
[0044] Step 3, as follows Figure 4 As shown, the ONO layer is etched to form the first sidewall.
[0045] In this embodiment of the invention, the first sidewall still consists of an HTO layer, a SiN layer, and a TEOS layer. Etching the ONO layer includes etching the thickened TEOS layer; specifically, the thickened TEOS layer is partially etched over time, and as follows... Figure 4 As shown by the center coil, the thickness of the TEOS layer is kept within 50 to 200 angstroms. In a preferred embodiment, the thickness of the retained TEOS layer is 100 to 200 angstroms, and more preferably, the thickness of the retained TEOS layer is 120 angstroms.
[0046] Step 4: Etch away the TEOS layer in the outer area.
[0047] In this embodiment of the invention, a blanket wet etch process is used to remove the TEOS layer in the peripheral region. This ensures that the bottom of the Peri region sidewall has the same thickness as the BSL.
[0048] Step 5: Use photolithography to form the source and drain regions in the substrate.
[0049] Specifically, a patterned interlayer dielectric layer can be formed above the substrate and gate structure; then, the source and drain regions can be formed in the substrate through the patterned interlayer dielectric layer. Of course, other suitable methods can also be used.
[0050] Step 6: Etch away the TEOS layer in the storage cell area.
[0051] In this embodiment of the invention, a wet cleaning process with photoresist (PR) is used to remove the TEOS layer in the peripheral area. This allows for the complete cleaning of the TEOS in the cell area without loss of SIN. Figure 5 The diagram shown is a schematic of the TEOS layer after etching.
[0052] Step 7: Perform source and drain ion implantation on the memory cell area.
[0053] Specifically, it is achieved using photolithography and imp (ion implantation) processes, which will not be described in detail here. Steps five and seven share the same mask.
[0054] Step 8, as Figure 6 and Figure 7 As shown, a TEOS layer is deposited and etched to form a second sidewall.
[0055] In practice, this step employs a blanket etching process without a mask layer, using a dry etching technique. Of course, other suitable methods can also be used. In this embodiment, the second deposition of the TEOS layer is of the same thickness as the deposition of the BSL second sidewall SIN layer; the thickness of the second sidewall remains unchanged, the same as that formed by existing processes. Specifically, the thickness of the deposited TEOS layer is 200–400 angstroms. In a preferred embodiment, the thickness of the TEOS layer is 315 angstroms.
[0056] Step 9: Perform source and drain ion implantation on the peripheral region.
[0057] Similarly, it is achieved using photo (referring to photolithography) and imp (ion implantation) processes, which will not be described in detail here.
[0058] The manufacturing method of the NOR flash memory device in this embodiment of the invention also includes subsequent process steps such as SAB oxide deposition, SAB PH, dry etching and wet etching, which will not be described in detail here.
[0059] This invention addresses the problem that the first sidewall etching stage, using SiN as the etching stop layer, suffers from poor etching uniformity and is prone to SiN loss, leading to a smaller subsequent sidewall etching window. The invention modifies the first sidewall etching method by etching over time, retaining a certain thickness of TOES (Total Electron Effluent) without touching SiN, thus preventing SiN loss and residue issues. Subsequent wet-dip etching removes the TEOS from the PERI region and wet-cleans the sidewall TEOS from the CELL region with photoresist, before depositing TEOS for etching without damaging the active region.
[0060] Figure 8 The diagram shows the effect of a method for manufacturing a NOR flash memory device according to an embodiment of the present invention. Figure 8 As shown, the active region remains undamaged. (Comparison) Figure 1 As can be seen, the method of this embodiment avoids the occurrence of active area damage or SIN residue, and effectively improves the etching window.
[0061] This invention deposits a thinned HTO layer, a thinned SiN layer, and a thickened TEOS layer to form an ONO layer. When etching the ONO layer to form the first sidewall, etching is performed over time to retain a certain thickness of the TEOS layer, ensuring no loss of the SiN layer. The TEOS layer on the memory cell area and the peripheral area are then removed by two different wet etching processes, and the TEOS layer is deposited again. This effectively improves the subsequent sidewall etching window, avoids damage to the active area or SiN residue, and improves the filling performance of the ILD in Nor flash memory devices.
[0062] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. For those skilled in the art, the present invention can be modified and varied in various ways. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principle of the present invention should be included within the scope of protection of the present invention.
Claims
1. A method for manufacturing a NOR flash memory device, the NOR flash memory device comprising a memory cell region and a peripheral region, characterized in that, Includes the following steps: Step 1: Provide a substrate on which a gate structure is formed; Step 2: Deposit an ONO layer, which includes a thinned HTO layer, a thinned SiN layer, and a thickened TEOS layer; Step 3: Etch the ONO layer to form a first sidewall, the first sidewall including the TEOS layer; etching the ONO layer includes partially etching the TEOS layer over time, so that the thickness of the TEOS layer is within 50 to 200 angstroms; Step 4: Etch away the TEOS layer in the outer region; Step 5: Form the source and drain regions in the substrate using photolithography. Step 6: Etch away the TEOS layer in the memory cell area; Step 7: Perform source and drain ion implantation on the memory cell region; Step 8: Deposit a TEOS layer and etch it to form a second sidewall; Step 9: Perform source and drain ion implantation on the peripheral region.
2. The method for manufacturing a NOR flash memory device according to claim 1, characterized in that, The substrate mentioned in step one is a silicon substrate.
3. The method for manufacturing a NOR flash memory device according to claim 1, characterized in that, The gate structure described in step one is a control gate.
4. The method for manufacturing a NOR flash memory device according to claim 1, characterized in that, In step two, the HTO layer is thinned by 20–50 angstroms, the SiN layer is thinned by 50–90 angstroms, and the TEOS layer has a thickness of 300–500 angstroms.
5. The method for manufacturing a NOR flash memory device according to claim 1, characterized in that, The thickness of the TEOS layer after etching in step three is 100–200 angstroms.
6. The method for manufacturing a NOR flash memory device according to claim 1, characterized in that, The etching described in step four employs a barrier-free wet etching process.
7. The method for manufacturing a NOR flash memory device according to claim 1, characterized in that, The etching described in step six employs a wet cleaning process with photoresist.
8. The method for manufacturing a NOR flash memory device according to claim 1, characterized in that, The thickness of the TEOS layer described in step eight is 200–400 angstroms.