Memory component and method of manufacturing the same

Abstract

The present application provides a memory assembly, comprising: a substrate; a plurality of word lines extending in a first direction and arranged in a second direction on the substrate; a dummy structure adjacent to ends of the plurality of word lines on the substrate, wherein the dummy structure comprises: a main body part extending in the second direction; and a plurality of extension parts extending in the first direction and connected with the main body part and interposed between the main body part and the plurality of word lines.

Description

Technical Field

[0001] This invention relates to a semiconductor component and a method for manufacturing the same, and more particularly to a memory component and a method for manufacturing the same. Background Technology

[0002] With advancements in technology, electronic products are trending towards thinner, lighter, and smaller designs, leading to a gradual reduction in the critical dimensions of memory components. This, in turn, makes photolithography increasingly challenging. Current photolithography techniques for minimizing critical dimensions include using optical components with larger numerical apertures (NA), shorter exposure wavelengths (e.g., EUV), or interface media other than air (e.g., water immersion). As the resolution of current photolithography processes approaches its theoretical limit, manufacturers have begun to shift towards double-patterning (DP) methods to overcome optical limitations and improve the integration density of memory components.

[0003] However, in current patterning methods, the different pattern densities at the center and ends of the array region cause the etching process to face a loading effect, which in turn leads to inconsistent outlines of the memory cells at the center and ends of the array region, resulting in electrical problems. Summary of the Invention

[0004] The present invention relates to a storage component, comprising: a substrate; a plurality of word lines extending in a first direction and arranged in a second direction on the substrate; and a dummy structure adjacent to the ends of the plurality of word lines on the substrate, wherein the dummy structure comprises: a main body extending in the second direction; and a plurality of extensions extending in the first direction and connected to the main body and located between the main body and the plurality of word lines.

[0005] The present invention relates to a method for manufacturing a memory component, comprising: providing a substrate; forming a target layer and a hard mask layer on the substrate; patterning the hard mask layer to form a patterned hard mask layer, the patterned hard mask layer comprising: a plurality of first patterns, a second pattern and a plurality of third patterns, wherein the plurality of first patterns extend in a first direction and are arranged in a second direction, the second patterns are comb-shaped and located between the plurality of first patterns and the third patterns, and the plurality of third patterns extend in the second direction and are arranged in the first direction; and transferring the plurality of first patterns, the second patterns and the plurality of third patterns to the target layer using the patterned hard mask layer to form a plurality of word lines, a comb-shaped dummy structure and a plurality of landing pads.

[0006] Based on the above, the addition of dummy patterns to the array region and the winding region in this embodiment of the invention can reduce the load effect between the end and center of the array region during the etching process. Attached Figure Description

[0007] Figure 1A This is a top view of a storage component according to an embodiment of the present invention;

[0008] Figure 1B yes Figure 1A A magnified view of a portion of region 50;

[0009] Figures 2A to 2H This is a top view of a method for manufacturing a storage component according to an embodiment of the present invention;

[0010] Figures 3A to 3H yes Figures 2A to 2H Sectional view of line III-III;

[0011] Figures 4A to 4H yes Figures 2A to 2H A cross-sectional view of line IV-IV;

[0012] Figures 5A to 5H yes Figures 2A to 2H A cross-sectional view of line VV. Detailed Implementation

[0013] Please refer to Figure 1A and Figure 1B The storage component 100 is formed on the substrate 10. In the direction D2, the substrate 10 can be divided into multiple blocks A0, A1, A2, A3, ... etc. Each block, denoted as block A1, can include an array region R1, a transition region R2, and a winding region R3, with the transition region R2 located between the array region R1 and the winding region R3.

[0014] The storage component 100 includes a plurality of word lines (WLs) and a plurality of select gates (SGs). One end of each word line (WL) is located in the array area, and the other end extends into the winding area. In some embodiments, one end of the plurality of word lines (WLs) is aligned with each other and arranged in an "I" shape; the other ends of the plurality of word lines (WLs) are not aligned and are arranged in a horizontal "V" shape.

[0015] For example, multiple word lines WL include multiple word lines WL0, WL1, and WL2. Multiple word lines WL0 / WL2 are located in array region R1 of block A0 / A2, and their ends E... 00 / E 20It also extends to the winding area R3, and is arranged in a horizontal "V" shape. The other ends (not shown) of multiple word lines WL0 / WL2 are located in the array area R1, and do not extend to another winding area (not shown), and are respectively cut and arranged in an "I" shape. Multiple word lines WL1 / WL3 are located in the array area R1 of block A1 / A3, and their ends E... 10 / E 30 The lines do not extend into the winding area R3 and are cut and arranged in an "I" shape. The other end (not shown) of the multiple word lines WL1 / WL3 is located in the array area R1 and extends into another winding area (not shown), and is arranged in a horizontal "V" shape.

[0016] The storage component 100 also includes multiple selection gates SG, which are respectively disposed on both sides of multiple word lines WL. The multiple selection gates SG are disposed in the array area R1.

[0017] Multiple selection gates SG include selection gates SG disposed on both sides of multiple word lines WL0. 00 (not shown) with SG 01 Multiple selection gates SG are set on both sides of multiple word lines WL1. 10 With SG 11 Multiple selection gates SG are set on both sides of multiple word lines WL2. 20 With SG 21 and multiple selection gates SG located on both sides of multiple word lines WL3. 30 With SG 31 (Not shown).

[0018] Storage component 100 also includes multiple landing pads LP disposed in winding area R3 as pick-up points for word lines WL. The landing pads LP include landing pads LP 01 LP 20 LP 21 (shown in) Figure 1A (Left side). Landing pad LP 01 LP 20 LP 21 They extend in direction D2 and are arranged in direction D1. Additionally, the landing pad LP... 01 LP 20 LP 21 They are aligned with each other in direction D2. Landing pads LP 01 With LP 20 Separate from each other, set at the end E of multiple word lines WL1 10 And they are arranged along direction D2. Landing pad LP 01 Extending from block A1 to block A0, and connecting with the end E of multiple word lines WL0 in part. 00 Connection. Landing pad LP 20Extending from block A1 to block A2, and connecting with the end E of multiple word lines WL2 in part. 20 Connection. Landing pad LP 21 Set at the end E of multiple word lines WL3 30 And it extends from block A3 to block A2, while the end of multiple word lines WL2 in another part is E. 20 Connection. The landing pad LP also includes other landing pads, respectively set at the E position relative to multiple word lines WL0 and WL2. 00 With E 20 The other end ( Figure 1A (On the right side, not shown), and connected to WL1 and WL3.

[0019] In an embodiment of the invention, the storage component 100 further includes a dummy structure DS disposed between the winding region R3 and the array region R1. The dummy structure DS is disposed beside a plurality of word lines WL arranged flush at their ends. Figure 1A In this context, the dummy structure DS can include dummy structures DS1 and DS3. Dummy structure DS1 is set in block A1, located at the end E of multiple word lines WL1. 10 Adjacent; the virtual structure DS3 is set in block A3, located at the end E of multiple word lines WL3. 30 The dummy structure DS may also include other dummy structures, which are respectively located in blocks A0 and A2, and are situated beside the other ends (not shown) of multiple word lines WL0 and WL2. The dummy structure DS may be floating and not connected to external circuitry.

[0020] The dummy structure DS is, for example, comb-shaped. The dummy structure DS includes a main body MP and multiple extensions EP. The main body MP is located in the transition zone R2 and is adjacent to the landing pad LP at a non-zero distance. The shape and orientation of the main body MP are more similar to the shape and orientation of the landing pad LP than the multiple extensions EP. Both the main body MP and the landing pad LP are solid blocks. The extension direction of the main body MP is the same as that of the landing pad LP, both extending along direction D2.

[0021] Multiple extensions EP are located in array region R1. The shape and orientation of the multiple extensions EP are more similar to the shape and orientation of the word lines WL than the main body MP. The extension direction of the multiple extensions EP is the same as the extension direction of the word lines WL, both extending along direction D1. The arrangement direction of the multiple extensions EP is also the same as the arrangement direction of the word lines WL, both arranged along direction D2. The multiple extensions EP are connected to the main body MP and are adjacent to the multiple word lines WL at a non-zero distance. The distance d1 between the extensions EP and the multiple word lines WL is less than 114 nanometers (nm), for example, between 30 nm and 114 nm. Selection gate SG 10 With SG 11The extension protrudes beyond the end of word line WL1, and the length L of the main body MP is less than the selection gates SG on both sides of word line WL1. 10 With SG 11 The distance d3 between them.

[0022] The width W2 of the extension EP is greater than twice the width W1 of the multiple character lines WL, for example, it is 2.5 to 3.5 times the width W1 of the multiple character lines WL. The width W3 of the main body MP is greater than the width W2 of the extension EP, for example, it is 6 to 9 times the width W1 of the multiple character lines WL.

[0023] The dummy structure DS is formed through hard mask pattern (also known as dummy pattern) pattern transfer. The dummy structure DS can improve the loading effect during the etching process of forming the word line WL and landing pad LP, resulting in similar contours at the center and ends of the array region. The process of the above-described memory component 100 can be described with reference to the following embodiments, but is not limited thereto.

[0024] An embodiment of the present invention provides a method for manufacturing a storage component, the steps of which are as follows. First, please refer to... Figures 2A to 5A A substrate 10 is provided. The substrate 10 may include an array region R1, a transition region R2, and a winding region R3. In this embodiment, the array region R1 may be a memory array region having one or more memory cells, and the winding region R3 may be a winding region having one or more word line contacts. The transition region R2 is located between the array region R1 and the winding region R3. In one embodiment, the substrate 10 may be, for example, a semiconductor substrate, a semiconductor compound substrate, or a semiconductor-on-insulator (SOI) substrate. In this embodiment, the substrate 10 is a silicon substrate.

[0025] Next, a target layer 12 is formed on the substrate 10. The target layer 12 may be a stacked layer 110 stacked in direction D3. Specifically, as... Figure 5A As shown in the enlarged view, the stacked layer 110 may include, from bottom to top, a tunneling dielectric layer 102, a patterned floating gate layer 104, an inter-gate dielectric layer 106, a control gate layer 108, a metal layer 112, and a top cap layer 114.

[0026] The tunneling dielectric layer 102 may be made of, for example, silicon oxide. The patterned floating gate layer 104 may extend along direction D2 and may be made of a conductive material, such as doped polysilicon, undoped polysilicon, or a combination thereof. The inter-gate dielectric layer 106 may be, for example, a composite layer composed of nitride / oxide / nitride / oxide / nitride (NONON), but the invention is not limited thereto; this composite layer may be three, five, or more layers. The control gate layer 108 may be made of a conductive material, such as doped polysilicon, undoped polysilicon, or a combination thereof. The metal layer 112 may be made of, for example, W, TiN, or a combination thereof. The capping layer 114 may be made of a dielectric material, such as silicon nitride, silicon oxynitride, or a combination thereof.

[0027] Then, a sacrificial layer 14 and a hard mask layer 16 are formed on the stacked layer 110. The sacrificial layer 14 may also be called a hard mask layer. The sacrificial layer 14 may be a silicon oxide layer. The hard mask layer 16 may be a single layer or multiple layers. The hard mask layer 16 may be, for example, a polysilicon layer. Subsequently, a core layer 18 is formed on the hard mask layer 16. The core layer 18 includes core patterns 18a, 18b, and 18c respectively in the array region R1, the transition region R2, and the winding region R3. Core pattern 18a extends in direction D1; core patterns 18b and 18c extend in direction D2. Directions D1 and D2 are perpendicular to each other. Core pattern 18b is connected to core pattern 18a and separate from core pattern 18c.

[0028] In one embodiment, the core layer 18 may include a carbide layer. In another embodiment, the core layer 18 may include a carbide layer and an anti-reflective layer. The material of the carbide layer may be, for example, spin-on carbon (SoC). The material of the anti-reflective layer may be, for example, silicon oxynitride. The core layer 18 may be formed by first forming a carbide material layer and an anti-reflective material layer, and then forming a photoresist pattern on the anti-reflective material layer via a photolithography process. In some embodiments, after forming the photoresist pattern, a trimming process is performed to reduce the width of the formed photoresist pattern. Subsequently, an etching process is performed to transfer the pattern of the photoresist pattern down to the anti-reflective material layer and the carbide material layer. The photoresist pattern is then removed.

[0029] Please refer to Figures 2B to 5B as well as Figures 2C to 5CA self-aligned double patterning (SADP) process is performed to form spacers 20 on the hard mask layer 16. The material of the spacers 20 includes oxides, such as silicon oxide. In an alternative embodiment, a self-aligned quadruple patterning (SAQP) process can also be performed to form spacers 20 with a higher pattern density. The spacers 20 can be formed, for example, by first forming a spacer material layer 19 on the hard mask layer 16 and on the top surface and sidewalls of the core layer 18, such as... Figures 2B to 5B As shown. Then, an anisotropic etching process is performed on the spacer material layer 19 to remove part of the spacer material layer 19 until the top surfaces of the hard mask layer 16 and the core layer 18 are exposed, so that spacers 20 are formed on the sidewalls of the core layer 18. Afterwards, using the spacers 20 and the core layer 18 as masks, etching continues to remove the hard mask layer 16 not covered by the spacers 20 and the core layer 18, so that hard mask patterns 16a, 16b, and 16c are formed in the array region R1, the transition region R2, and the winding region R3, respectively. During the etching of the hard mask layer 16, the core layer 18 is also etched and removed, exposing part of the top surfaces of the hard mask patterns 16a, 16b, and 16c, as shown. Figures 2C to 5C As shown. Hard mask pattern 16a extends in direction D1; hard mask patterns 16b and 16c extend in direction D2. Hard mask pattern 16b is connected to hard mask pattern 16a and separate from hard mask pattern 16c.

[0030] Please refer to Figures 2D to 5D And please refer to Figures 2E to 5E The spacer 20 is then cut into separate spacers 20a, 20b, and 20c. The cutting process for spacer 20 is described below.

[0031] First, please refer to Figures 2D to 5DA mask layer 22 is formed on the sacrificial layer 14. The mask layer 22 is, for example, a patterned photoresist layer. The mask layer 22 includes mask patterns 22a, 22b, and 22c. Mask pattern 22a partially covers the array region R1; mask pattern 22b covers a portion of the winding region R3 and the transition region R2; mask pattern 22c covers another portion of the winding region R3 and the transition region R2. Mask patterns 22a, 22b, and 22c are separated from each other. Between mask patterns 22a and 22b, and between mask patterns 22a and 22c, spacers 20 located at the end of the array region R1 and one side (close to the array region R1) of the transition region R2 are exposed, as are hard mask patterns 16a and 16b and the sacrificial layer 14. The spacer 20, hard mask patterns 16c and 16b, and sacrificial layer 14 are exposed between mask patterns 22b and 22c, located in the winding region R3 and on the other side of the transition region R2 (away from the array region R1).

[0032] Please refer to Figures 2E to 5E An etching process, such as an anisotropic etching process, is performed to remove spacers 20 not covered by mask patterns 22a, 22b, and 22c to form spacers 20a, 20b, and 20c. Then, mask patterns 22a, 22b, and 22c are removed. Spacers 20a are separated from each other in the array region R1, and their length in direction D1 is less than the length of the sacrificial layer 14 not covered by the hard mask pattern 16a in the array region R1. Spacers 20b are located in the transition region R2, extending in direction D2 and arranged separately from each other in direction D2. Spacers 20c are located in the winding region R3, extending in direction D2 and arranged separately from each other in direction D2.

[0033] Please refer to Figures 2F to 5H The target layer 12 is patterned to form target patterns 12a, 12b, and 12c. The patterning process for target layer 12 is described below. In target layer 12, the patterning is performed using... Figure 2G The hard mask layer 16' shown serves as an etching mask, and the method for forming the hard mask layer 16' can be referred to Figures 2F to 5G The explanation is as follows.

[0034] Please refer to Figures 2F to 5G A mask layer 24 is formed on the substrate 10. The mask layer 24 is, for example, a patterned photoresist layer. The mask layer 24 has openings OP1 and OP2. Opening OP1 exposes the spacer 20a, hard mask pattern 16a, and sacrificial layer 14 in the array region R1. Opening OP2 extends in directions D1 and D2. The shape of opening OP2 is, for example, a double-row comb shape composed of multiple crosses. Opening OP2 exposes the hard mask pattern 16c and sacrificial layer 14 in the winding region R3 in direction D1. Opening OP2 exposes the hard mask pattern 16c in the winding region R3 in direction D2.

[0035] Please refer to Figure 2G to Figure 5G Using mask layer 24 and spacer 20a as masks, hard mask patterns 16a, 16b, and 16c are patterned into hard mask layer 16'. Hard mask layer 16' includes hard mask patterns 16a', 16b', and 16c'. Hard mask pattern 16a' covers array region R1; hard mask pattern 16b' covers transition region R2 and extends to array region R1; hard mask pattern 16c' covers winding region R3.

[0036] The hard mask pattern 16b' can also be called a dummy pattern. The hard mask pattern 16b' is, for example, comb-shaped. The hard mask pattern 16b' includes a main body mp and multiple extensions ep. The main body mp is a solid block extending along direction D2, located in the transition region R2, and adjacent to the hard mask pattern 16c' at a non-zero distance d2'. The multiple extensions ep extend along direction D1, are arranged along direction D2, and are located in the array region R1. The multiple extensions ep are connected to the main body mp and adjacent to the hard mask pattern 16a' at a non-zero distance d1'. The width W3' of the main body mp is greater than the width W2' of each extension ep, and the width W2' of each extension ep is greater than the width W1' of each hard mask pattern 16a'. The distance d1' between the hard mask pattern 16b' and the hard mask pattern 16a' is controlled according to the process capability to reduce the load effect of subsequent etching processes. For example, the distance d1' can be controlled to be less than 114nm, such as between 30nm and 114nm.

[0037] Please refer to Figures 2H to 5H Using a hard mask layer 16' as a mask, an etching process is performed, which can be an anisotropic etching process, such as reactive ion etching (RIE), to pattern the sacrificial layer 14 and the target layer 12, thereby forming a patterned oxide layer and target patterns 12a, 12b, and 12c. The mask layer 24 and spacer 20a are then removed. Because the distance d1' between the hard mask patterns 16b' and 16a' is controlled within an appropriate range and is a solid block, the loading effect between the center and end regions of the array region R1 can be reduced during etching, resulting in similar contours for the target patterns 12a between the center and end regions.

[0038] The target pattern 12a may include multiple target patterns 12a1. The multiple target patterns 12a1 are located in the array region R1, extending along direction D1 and arranged along direction D2.

[0039] Multiple target patterns 12c are located in the winding region R3. The multiple target patterns 12c include multiple target patterns 12c0 and 12c1, which extend along direction D2 respectively. Both target patterns 12c0 and 12c1 extend along direction D2 and are arranged along direction D1. Target patterns 12c0 and 12c1 are separated from each other and arranged in a row along direction D2. The width of target pattern 12c is, for example, 4 to 6 times the width W1 of target pattern 12a1.

[0040] Target pattern 12b is located between multiple target patterns 12a1 and multiple target patterns 12c. Target pattern 12b is also called a dummy structure, for example, it is comb-shaped. Target pattern 12b includes a main body MP and multiple extensions EP. The main body MP is a solid block that extends along direction D2, is located in transition region R2, and is adjacent to target pattern 12c at a non-zero distance. The multiple extensions EP extend along direction D1, are arranged along direction D2, and are located in array region R1. The multiple extensions EP are connected to the main body MP, are adjacent to target pattern 12a1 at a non-zero distance d1, and are adjacent to target pattern 12c at a non-zero distance d2. The distance d1 between the extensions EP and the target pattern 12a1 is less than 114 nm, for example, between 30 nm and 114 nm.

[0041] The width W2 of the extension EP is greater than twice the width W1 of the target pattern, for example, it is 2.5 to 3.5 times the width W1 of the target pattern. The width W3 of the main body MP is greater than the width W2 of the extension EP, for example, it is 4 to 9 times the width W1 of the target pattern 12a1.

[0042] Please refer to Figure 1B The target pattern 12a may also include multiple target patterns 12a. 10 12a 11 Target pattern 12a 10 12a 11 Located on both sides of target pattern 12a1. Target pattern 12a 10 12a 11 Located in array region R1, extending along direction D1 and arranged along direction D2. Target pattern 12a 10 12a 11 The width is, for example, 4 to 6 times the width W1 of the target pattern 12a1.

[0043] Please refer to Figure 1A and Figure 1B In some embodiments, the target pattern 12a1 is a patterned stacked layer 110a including word lines WL1 (e.g., Figure 5H(As shown in a partially enlarged view). The patterned stacked layer 110a includes a tunneling dielectric layer 102, a patterned floating gate layer 104a, an inter-gate dielectric layer 106a, a control gate layer 108, a metal layer 112a, and a capping layer 114a. In some embodiments, the tunneling dielectric layer 102 may also be patterned. The aspect ratio of the patterned stacked layer 110a is, for example, 10 to 12. Target pattern 12a 10 12a 11 These include the selection line SG. 10 With SG 11 Patterned stacked layers. Target patterns 12c0 and 12c1 respectively include the landing pad LP as the letter line WL0. 01 And the landing pad LP for line WL2 20 A patterned stacked layer. Target pattern 12b is a patterned stacked layer including the dummy structure DS1.

[0044] While the above embodiments illustrate a series of patterning steps using flash memory as an example, the present invention is not limited thereto. In other embodiments, this patterning step can also be used to form dynamic random access memory (DRAM) or similar target layers / films.

[0045] In summary, the embodiments of the present invention, by setting a hard mask pattern (also known as a dummy pattern) used to form the dummy structure DS, can improve the loading effect during the etching process of forming word lines and landing pads, so that the center and ends of the array region have similar contours, avoiding bridging or defects. Moreover, in this case, the target layers in the array region and the winding region can be patterned simultaneously, thereby forming multiple stacked structures with different pattern densities in the array region and the winding region.

Claims

1. A storage component, characterized in that, include: Substrate; Multiple first word lines extend in a first direction, are arranged in a second direction, and are located on the substrate; Multiple landing pads extend in the second direction and are respectively connected to multiple second letter lines, wherein the multiple second letter lines extend in the first direction, are arranged in the second direction, and are located on the substrate; as well as A dummy structure, adjacent to the ends of the plurality of first word lines, is located on the substrate, wherein the dummy structure includes: The main body extends in the second direction; as well as Multiple extensions extend in the first direction and connect to the main body, and are located between the main body and the multiple first letter lines. The dummy structure is located between the plurality of landing pads and the plurality of first letter lines.

2. The storage component according to claim 1, wherein the dummy structure is comb-shaped.

3. The storage component according to claim 1, wherein the width of the main body portion of the dummy structure in the first direction is greater than the width of each extension portion in the second direction, and the width of each extension portion in the second direction is greater than the width of each first word line in the second direction.

4. The storage component according to claim 1, wherein the main body of the dummy structure is a solid block.

5. The storage component of claim 1 further includes two select gates located on both sides of the plurality of first word lines, wherein the length of the main body in the second direction is less than the distance between the two select gates.

6. A method of manufacturing a memory assembly, comprising: include: Provide substrate; A target layer and a hard mask layer are formed on the substrate; The hard mask layer is patterned to form a patterned hard mask layer, the patterned hard mask layer comprising: a plurality of first patterns, a second pattern and a plurality of third patterns, wherein the plurality of first patterns extend in a first direction and are arranged in a second direction, the second pattern is comb-shaped and located between the plurality of first patterns and the third patterns, and the plurality of third patterns extend in the second direction and are arranged in the first direction; as well as Using the patterned hard mask layer, the plurality of first patterns, second patterns, and third patterns are transferred to the target layer to form a plurality of letter lines, a comb-like dummy structure, and a plurality of landing pads, wherein the plurality of letter lines include a plurality of first letter lines and a plurality of second letter lines, and the plurality of landing pads are respectively connected to the plurality of second letter lines. The comb-shaped dummy structure is located between the plurality of landing pads and the plurality of first letter lines.

7. The method of manufacturing a storage component according to claim 6, wherein the second pattern includes a main body portion and a plurality of extension portions, the main body portion extending in a second direction, and the plurality of extension portions extending in a first direction and arranged in the second direction.

8. The method of manufacturing a storage component according to claim 7, wherein the width of the main body portion in the first direction is greater than the width of each extension portion in the second direction, and the width of each extension portion in the second direction is greater than the width of each first pattern in the second direction.

9. The method of manufacturing a memory assembly of claim 7, wherein the body portion is a solid block.

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