Display panel and manufacturing method thereof

Abstract

The embodiment of the application discloses a display panel and a manufacturing method thereof; the display panel comprises a driving wire layer, an electron transport layer, an electron injection layer and a cathode layer; the driving wire layer comprises a cathode voltage line; the electron transport layer is connected with the cathode voltage line; the cathode layer is connected with the electron injection layer; the patterns of the electron transport layer and the electron injection layer are the same as the pattern of the cathode layer; the display panel further comprises a resistance reduction layer between the cathode voltage line and the electron transport layer; the cathode layer, the electron injection layer and the electron transport layer are patterned simultaneously through one mask plate, the same pattern is formed, the resistance reduction layer is arranged between the cathode voltage line and the electron injection layer and the electron transport layer, the number of mask plates is reduced, the production process is simplified, the production cost is reduced, the contact resistance between the cathode layer, the electron injection layer, the electron transport layer and the cathode voltage line is reduced, the electrical conductivity of the cathode overlap is enhanced, and the display effect is improved.

Description

Technical Field

[0001] This invention relates to the field of displays, and more specifically to a display panel and its manufacturing method. Background Technology

[0002] In recent years, inkjet printing (IJP) has been able to reduce the production cost of OLED (Organic Light-Emitting Diode) display panels, making them more cost-competitive. Due to limitations in the development of inks for the electron transport layer and electron injection layer, vapor deposition / sputtering processes are often used to deposit the electron transport layer, electron injection layer, and cathode layer. The cathode layer needs to be connected to the cathode voltage lines of the driving wiring layer to achieve circuit-controlled light emission. Therefore, the film deposition area of ​​the electron transport layer and electron injection layer needs to be smaller than the film deposition area of ​​the cathode layer, so that the cathode layer can directly connect with the cathode voltage lines. Thus, two types of mask designs with different openings are required to achieve different film deposition areas, making the process complex and the related costs high.

[0003] Therefore, there is an urgent need for a display panel and its manufacturing method to solve the above-mentioned technical problems. Summary of the Invention

[0004] This invention provides a display panel and its manufacturing method, which can alleviate the technical problems of complex and costly processes in forming the cathode layer, electron injection layer and electron transport layer.

[0005] This invention provides a display panel, comprising:

[0006] Driven trace layers, including cathode voltage lines;

[0007] An electron transport layer is located on one side of the drive trace layer and is connected to the cathode voltage line;

[0008] An electron injection layer is located on the side of the electron transport layer away from the drive trace layer;

[0009] The cathode layer is located on the side of the electron injection layer away from the drive trace layer and is connected to the electron injection layer;

[0010] A resistance-reducing layer is located between the cathode voltage line and the electron transport layer;

[0011] The patterns of the electron transport layer and the electron injection layer are the same as the pattern of the cathode layer.

[0012] Preferably, the resistance-reducing layer includes at least a first metal oxide layer in contact with the electron transport layer.

[0013] Preferably, the display panel further includes an anode layer, the material and film stack of which are the same as those of the resistivity-reducing layer.

[0014] Preferably, the resistance-reducing layer further includes a second metal oxide layer in contact with the cathode voltage line, and a conductive functional layer located between the first metal oxide layer and the second metal oxide layer.

[0015] Preferably, the drive trace layer further includes a trace layer and an insulating planarization layer located between the trace layer and the anode layer; the insulating planarization layer includes a plurality of first vias, the first vias exposing the cathode voltage line, and the resistance reduction layer is connected to the cathode voltage line through the first vias.

[0016] Preferably, the resistance-reducing layer includes a first resistance-reducing sub-section and a second resistance-reducing sub-section located around and connected to the first resistance-reducing sub-section, wherein the second resistance-reducing sub-section is located on the sidewall of the insulating planar layer corresponding to the first via.

[0017] Preferably, the driving trace layer includes a circuit layer and an insulating planarization layer located between the circuit layer and the anode layer of the display panel; the resistivity reduction layer includes a first resistivity reduction sub-section and a third resistivity reduction sub-section located around and connected to the first resistivity reduction sub-section, the third resistivity reduction sub-section being located between the cathode voltage line and the insulating planarization layer; the insulating planarization layer includes a plurality of first vias, the first vias exposing the first resistivity reduction sub-section of the resistivity reduction layer, and the electron transport layer being connected to the first resistivity reduction sub-section through the first vias.

[0018] Preferably, the display panel includes a display area and a non-display area located around the display area, the non-display area including a cathode overlap area, and each of the first vias being located within the cathode overlap area; wherein the cathode layer, the electron injection layer, and the electron transport layer cover the display area and the cathode overlap area.

[0019] The present invention also provides a method for manufacturing a display panel, comprising:

[0020] Provide a substrate;

[0021] A cathode voltage line is formed on one side of the substrate;

[0022] A resistance-reducing layer is formed on the side of the cathode voltage line away from the substrate;

[0023] An insulating planarization layer is formed on the resistance-reducing layer;

[0024] The insulating planarization layer is patterned to form a plurality of first vias, the first vias exposing the resistance-reducing layer.

[0025] An electron transport material layer, an electron injection material layer, and a cathode material layer are formed on the side of the insulating planar layer away from the substrate;

[0026] The electron transport material layer, the electron injection material layer, and the cathode material layer are patterned using a mask to form the electron transport layer, the electron injection layer, and the cathode layer.

[0027] The present invention also provides a method for manufacturing a display panel, comprising:

[0028] Provide a substrate;

[0029] A cathode voltage line is formed on one side of the substrate;

[0030] An insulating planar layer comprising a plurality of first vias is formed on the side of the cathode voltage line away from the substrate, the first vias exposing the cathode voltage line;

[0031] An anode material layer is formed on the side of the insulating planar layer away from the substrate;

[0032] The anode material layer is patterned using a mask to form an anode layer and a resistance-reducing layer corresponding to the first via.

[0033] An electron transport material layer, an electron injection material layer, and a cathode material layer are formed on the side of the insulating planar layer away from the substrate;

[0034] The electron transport material layer, the electron injection material layer, and the cathode material layer are patterned using a mask to form the electron transport layer, the electron injection layer, and the cathode layer.

[0035] The beneficial effects of this invention are as follows: This invention uses a single mask to simultaneously pattern the cathode layer, electron injection layer, and electron transport layer to form the same pattern. At the same time, a resistance-reducing layer is set between the cathode voltage line and the electron injection layer and electron transport layer, which reduces the number of masks, simplifies the production process, and reduces production costs. At the same time, it reduces the contact resistance between the cathode layer, electron injection layer, electron transport layer, and cathode voltage line, enhances the electrical conductivity of the cathode connection, and improves the display effect. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1This is a schematic diagram of the first structure of the display panel provided in the embodiment of the present invention;

[0038] Figure 2 yes Figure 1 An enlarged schematic diagram of region D;

[0039] Figure 3 This is a schematic diagram of the second structure of the display panel provided in the embodiment of the present invention;

[0040] Figure 4 This is a schematic diagram of the third structure of the display panel provided in the embodiment of the present invention;

[0041] Figure 5 This is a top view schematic diagram of the fourth structure of the display panel provided in the embodiments of the present invention;

[0042] Figure 6 yes Figure 5 Schematic diagram of the structure of region E;

[0043] Figure 7 This is a flowchart of a method for manufacturing a display panel according to an embodiment of the present invention;

[0044] Figure 8 This is a flowchart of another method for manufacturing a display panel according to an embodiment of the present invention;

[0045] Figure 9 This is a schematic diagram of the structure of the display device provided in an embodiment of the present invention. Detailed Implementation

[0046] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Furthermore, it should be understood that the specific embodiments described herein are only for illustration and explanation of the present invention and are not intended to limit the present invention. In the present invention, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, specifically the drawing directions in the accompanying drawings; while "inner" and "outer" refer to the outline of the device.

[0047] In recent years, inkjet printing (IJP) has been able to reduce the production cost of OLED (Organic Light-Emitting Diode) display panels, making them more cost-competitive. Due to limitations in the development of inks for the electron transport layer and electron injection layer, vapor deposition / sputtering processes are often used to deposit the electron transport layer, electron injection layer, and cathode layer. The cathode layer needs to be connected to the cathode voltage lines of the driving wiring layer to achieve circuit-controlled light emission. Therefore, the film deposition area of ​​the electron injection layer and electron transport layer needs to be smaller than that of the cathode layer, so that the cathode layer can be directly connected to the cathode voltage lines. Thus, two types of mask designs with different openings are required to achieve different film deposition areas, making the process complex and the related costs high.

[0048] Please see Figures 1 to 6 This invention provides a display panel 100, comprising:

[0049] The driving trace layer 200 includes the cathode voltage line 210;

[0050] An electron transport layer 701 is located on one side of the drive trace layer 200 and is connected to the cathode voltage line 210;

[0051] An electron injection layer 702 is located on the side of the electron transport layer 701 away from the drive trace layer 200;

[0052] The cathode layer 800 is located on the side of the electron injection layer 702 away from the drive trace layer 200 and is connected to the electron injection layer 702;

[0053] A resistance-reducing layer 600 is located between the cathode voltage line 210 and the electron transport layer 701;

[0054] The patterns of the electron transport layer 701 and the electron injection layer 702 are the same as the pattern of the cathode layer 800.

[0055] This invention uses a single mask to pattern the cathode layer, electron injection layer, and electron transport layer into the same pattern. At the same time, a resistance-reducing layer is set between the cathode voltage line and the electron injection layer and electron transport layer. This reduces the number of masks, simplifies the production process, and lowers production costs. At the same time, it reduces the contact resistance between the cathode layer, electron injection layer, electron transport layer, and cathode voltage line, enhances the electrical conductivity of the cathode connection, and improves the display effect.

[0056] The technical solution of the present invention will now be described in conjunction with specific embodiments.

[0057] By using a single mask, the cathode layer 800, electron injection layer 702, and electron transport layer 701 are simultaneously patterned to form identical patterns, simplifying the mask patterning process and reducing the number of masks. For ease of description, the electron injection layer 702 and electron transport layer 701 can be represented as a composite layer 700 in the figure. For mass production lines, in terms of logistics design, only one main cavity needs to be designed (one main cavity includes a mask separation cavity, a mask alignment cavity, a vapor deposition / sputtering cavity, a mask rotation cavity, a buffer cavity, etc.), resulting in a shorter vapor deposition line and lower equipment investment costs.

[0058] However, there are electron injection layer 702 and electron transport layer 701 between the cathode layer 800 and the cathode voltage line 210. The electron injection layer 702 and electron transport layer 701 are generally organic materials with poor conductivity and high contact resistance, which affects the electrical connection between the cathode layer 800 and the cathode voltage line 210, thereby affecting the electrical performance of the display panel 100. Therefore, a resistance-reducing layer 600 is set between the cathode voltage line 210 and the electron transport layer 701 to reduce the contact resistance between the cathode layer 800, electron injection layer 702, electron transport layer 701 and cathode voltage line 210, enhance the electrical conductivity of the cathode connection and improve the display effect.

[0059] The resistance-reducing layer 600 is located between the cathode voltage line 210 and the electron transport layer 701, indicating that the resistance-reducing layer 600 is located between the film layer containing the cathode voltage line 210 and the film layer containing the electron transport layer 701.

[0060] The display panel 100 includes a display area A and a non-display area B located around the display area A. The patterns of the electron transport layer 701 and the electron injection layer 702 are the same as the pattern of the cathode layer 800. The electron transport layer 701, the electron injection layer 702 and the cathode layer 800 all cover the entire display area A and extend into the non-display area B. Through a mask, the cathode layer 800, the electron injection layer 702 and the electron transport layer 701 are patterned simultaneously. Therefore, the electron transport layer 701, the electron injection layer 702 and the cathode layer 800 are flush with the edge of the non-display area B.

[0061] In some embodiments, please refer to Figure 1 , Figure 2 The resistance-reducing layer 600 includes at least a first metal oxide layer 601 in contact with the electron transport layer 701.

[0062] The cathode voltage line 210 generally adopts a metal Mo, or a stacked metal structure such as Mo\Al\Mo, Mo\Ti\Cu, etc. Therefore, the electron transport layer 701 will be in direct contact with metals such as Mo and MoTi. However, the contact impedance between the electron transport layer 701 and Mo and MoTi is relatively large. By using metal materials with different work functions to contact the electron transport layer 701, it was found through film contact impedance testing that metal oxides, such as ITO, IZO, IGZO, ZnO, WoO, etc., have lower contact impedance with the electron transport layer 701. Therefore, the first metal oxide layer 601 can be used to contact the electron transport layer 701, which can reduce the contact resistance between the cathode layer 800, the electron injection layer 702, the electron transport layer 701, and the cathode voltage line 210, enhance the electrical conductivity of the cathode connection, and improve the display effect.

[0063] In some embodiments, the display panel 100 further includes an anode layer 120, the material and film stack of which are the same as those of the drag-reducing layer 600.

[0064] The anode layer 120 near the electron transport layer 701 can be made of a metal oxide material. When fabricating the anode layer 120, the same mask can be used to form both the anode layer 120 and the resistance-reducing layer 600. Therefore, the material and film stack of the resistance-reducing layer 600 are the same as those of the anode layer 120, which can save a mask, simplify the process, and reduce production costs.

[0065] In some embodiments, please refer to Figure 1 , Figure 2 The resistance-reducing layer 600 further includes a second metal oxide layer 602 in contact with the cathode voltage line 210, and a conductive functional layer 603 located between the first metal oxide layer 601 and the second metal oxide layer.

[0066] The material and film layer stack of the resistance-reducing layer 600 are the same as those of the anode layer 120. The anode layer 120 is also a stack of metal oxide-conductive function-metal oxide, such as ITO / Ag / ITO, IZO / Ag / IZO, etc. The upper and lower metal oxide layers are in contact with the cathode voltage line 210, electron injection layer 702, and electron transport layer 701, which can more directly reduce the contact resistance, enhance the electrical conductivity of the cathode connection, and improve the display effect.

[0067] In some embodiments, please refer to Figure 1The drive trace layer 200 further includes a circuit layer 400 and an insulating planarization layer 500 located between the circuit layer 400 and the anode layer 120; the insulating planarization layer 500 includes a plurality of first vias 501, the first vias 501 exposing the cathode voltage line 210, and the resistance reduction layer 600 is connected to the cathode voltage line 210 through the first vias 501.

[0068] The resistivity-reducing layer 600 and the anode layer 120 are fabricated in the same process using the same mask. The fabrication step of the anode layer 120 is after the fabrication step of the insulating planarization layer 500. The anode layer 120 and the resistivity-reducing layer 600 are fabricated after the first via 501 is drilled. The patterning of the resistivity-reducing layer 600 can be positioned according to the position of the first via 501 to facilitate the formation of a precise pattern, so as to cover the bottom of the first via 501, enhance the electrical conductivity of the cathode connection, and improve the display effect.

[0069] In some embodiments, please refer to Figure 3 The resistance-reducing layer 600 includes a first resistance-reducing sub-section 610 and a second resistance-reducing sub-section 620 located around and connected to the first resistance-reducing sub-section 610. The second resistance-reducing sub-section 620 is located on the sidewall of the first via 501 corresponding to the insulating planarization layer 500.

[0070] The second resistance-reducing sub-section 620 can further enhance the resistance-reducing effect. At the same time, the second resistance-reducing sub-section 620 extends to the side wall of the insulating planar layer 500 corresponding to the first via 501. When the display panel 100 is bent, the risk of the resistance-reducing layer 600 falling off the first via 501 is reduced, thus ensuring the resistance-reducing effect.

[0071] In some embodiments, please refer to Figure 4 The driving trace layer 200 includes a circuit layer 400 and an insulating planarization layer 500 located between the circuit layer 400 and the anode layer 120 of the display panel 100; the resistivity-reducing layer 600 includes a first resistivity-reducing sub-section 610 and a third resistivity-reducing sub-section 630 located around and connected to the first resistivity-reducing sub-section 610, the third resistivity-reducing sub-section 630 being located between the cathode voltage line 210 and the insulating planarization layer 500; the insulating planarization layer 500 includes a plurality of first vias 501, the first vias 501 exposing the first resistivity-reducing sub-section 610 of the resistivity-reducing layer 600, and the electron transport layer 701 being connected to the first resistivity-reducing sub-section 610 through the first vias 501.

[0072] The insulating planarization layer 500 presses against the third resistance-reducing sub-section 630 of the resistance-reducing layer 600. Therefore, the formation step of the resistance-reducing layer 600 is located before the formation step of the insulating planarization layer 500, which can improve the flatness of the overall film layer of the display panel 100. At the same time, the material of the resistance-reducing layer 600 can be selected from a wider range, and it does not have to be limited to the same material as the anode layer 120. This is more conducive to reducing the contact resistance between the cathode layer 800, the electron injection layer 702, the electron transport layer 701, and the cathode voltage line 210, enhancing the electrical conductivity of the cathode connection, and improving the display effect.

[0073] In some embodiments, please refer to Figure 5 The display panel 100 includes a display area A and a non-display area B located around the display area A. The non-display area B includes a cathode overlap area C, and each of the first vias 501 is located within the cathode overlap area C. The cathode layer 800, the electron injection layer 702, and the electron transport layer 701 cover the display area A and the cathode overlap area C.

[0074] The first via 501 is disposed in the cathode overlap area C within the non-display area B. The electron injection layer 702, the electron transport layer 701, and the cathode layer 800 are formed through a mask. The electron injection layer 702, the electron transport layer 701, and the cathode layer 800 have the same coverage area, all covering the display area A and the cathode overlap area C.

[0075] In some embodiments, please refer to Figure 1 The driving trace layer 200 includes a plurality of thin film transistors 201 and a light-shielding layer 230 located on the side of the thin film transistors 201 away from the cathode layer 800. The light-shielding layer 230 includes a plurality of light-shielding units 231 and a plurality of auxiliary traces 232. The cathode voltage line 210 is connected to the auxiliary traces 232 through vias.

[0076] The cathode voltage line 210 is connected to the auxiliary trace 232 in parallel to reduce the resistance of the cathode voltage line 210 and improve the electrical performance of the display panel 100.

[0077] The thin-film transistor 201 includes the light-shielding unit 231, an active semiconductor, a gate, source and drain electrodes 220, and corresponding insulating layers.

[0078] In some embodiments, please refer to Figure 1 The display panel 100 further includes a substrate 110, a pixel definition layer 130 located on the side of the insulating planarization layer 500 away from the thin film transistor 201, and an encapsulation layer 900 located on the side of the cathode layer 800 away from the thin film transistor 201.

[0079] The pixel definition layer 130 includes a plurality of pixel openings that expose the anode layer 120. Each pixel opening is filled with a light-emitting functional material. The light-emitting functional material includes a hole-functional material and a light-emitting material, wherein the light-emitting functional material is represented by a first stack 140. The pixel openings are also filled with the electron injection layer 702 and the electron transport layer 701.

[0080] In some embodiments, please refer to Figure 1 The pixel definition layer 130 includes a plurality of second vias 502, and the second vias 502 are correspondingly connected to the first vias 501.

[0081] In some embodiments, please refer to Figure 1 The cathode voltage line 210 is disposed in the same layer as the source and drain electrodes 220.

[0082] In some embodiments, the cathode voltage line 210 is made of the same material as the source and drain electrodes 220.

[0083] In some embodiments, please refer to Figure 5 , Figure 6 The cathode overlap area C includes multiple sub-areas E, and multiple first vias 501 correspond to one sub-area E. The cathode voltage line 210 in one sub-area E is connected to multiple cathode fan-out traces. In one sub-area E, the thickness of the first resistance-reducing sub-section 610 near the center of the sub-area E is less than the thickness of the first resistance-reducing sub-section 610 near the edge of the sub-area E.

[0084] Within a sub-region E, the length of the cathode fan-out trace near the center of the sub-region E is shorter, while the length of the cathode fan-out trace near the edge of the sub-region E is longer. Cathode fan-out traces of different lengths have different resistances, which leads to a decrease in the resistance uniformity of the cathode layer 800. By varying the thickness of the first resistance-reducing sub-section 610, the voltage uniformity within a sub-region E can be improved, thereby improving the voltage uniformity of the cathode layer 800 and enhancing the display effect.

[0085] In some embodiments, within a sub-region E, the orthogonal projection area of ​​the drag-reducing layer 600 near the center of the sub-region E on the substrate 110 is smaller than the orthogonal projection area of ​​the drag-reducing layer 600 near the edge of the sub-region E on the substrate 110.

[0086] By varying the area of ​​the resistance-reducing layer 600, the voltage uniformity within a sub-region E is improved, thereby enhancing the voltage uniformity of the cathode layer 800 and improving the display effect.

[0087] In some embodiments, the active semiconductor material may be metal oxide type or polycrystalline silicon type, without specific limitation.

[0088] In some embodiments, the materials of the first metal oxide layer 601 and the second metal oxide layer 602 can be any one of ITO, IZO, IGZO, ZnO, and WoO.

[0089] In some embodiments, please refer to Figure 1 The insulating planarization layer 500 includes an insulating passivation layer 510 and an organic planarization layer 520 near the side of the thin film transistor 201.

[0090] This invention uses a single mask to pattern the cathode layer, electron injection layer, and electron transport layer into the same pattern. At the same time, a resistance-reducing layer is set between the cathode voltage line and the electron injection layer and electron transport layer. This reduces the number of masks, simplifies the production process, and lowers production costs. At the same time, it reduces the contact resistance between the cathode layer, electron injection layer, electron transport layer, and cathode voltage line, enhances the electrical conductivity of the cathode connection, and improves the display effect.

[0091] Please see Figure 7 This invention also provides a method for manufacturing a display panel 100, comprising:

[0092] S100, providing a substrate 110.

[0093] S200, A cathode voltage line 210 is formed on one side of the substrate 110.

[0094] S300, a resistance-reducing layer 600 is formed on the side of the cathode voltage line 210 away from the substrate 110.

[0095] S400, An insulating planarization layer 500 is formed on the resistivity-reducing layer 600.

[0096] S500, the insulating planarization layer 500 is patterned to form a plurality of first vias 501, the first vias 501 exposing the resistance-reducing layer 600.

[0097] S600, an electron transport material layer, an electron injection material layer, and a cathode material layer are formed on the side of the insulating planarization layer 500 away from the substrate 110.

[0098] S700, The electron transport material layer, electron injection material layer and cathode material layer are patterned using a mask to form electron transport layer 701, electron injection layer 702 and cathode layer 800.

[0099] This invention uses a single mask to pattern the cathode layer, electron injection layer, and electron transport layer into the same pattern. At the same time, a resistance-reducing layer is set between the cathode voltage line and the electron injection layer and electron transport layer. This reduces the number of masks, simplifies the production process, and lowers production costs. At the same time, it reduces the contact resistance between the cathode layer, electron injection layer, electron transport layer, and cathode voltage line, enhances the electrical conductivity of the cathode connection, and improves the display effect.

[0100] In some embodiments, step S300 includes:

[0101] S310a, A resistance-reducing layer 600 including a first resistance-reducing sub-section 610 is formed on the side of the cathode voltage line 210 away from the substrate 110.

[0102] In some embodiments, step S300 includes:

[0103] S310b, A first resistor-reducing sub-part 610 and a third resistor-reducing sub-part 630, which are located around and connected to the first resistor-reducing sub-part 610, are formed on the side of the cathode voltage line 210 away from the substrate 110, to form a resistor-reducing layer 600.

[0104] In some embodiments, step S400 includes:

[0105] S410. The insulating planarization layer 500 is patterned to form a plurality of first vias 501, the first vias 501 exposing the first resistance-reducing sub-parts 610 of the resistance-reducing layer 600.

[0106] In some embodiments, please refer to Figure 4 The driving trace layer 200 includes a circuit layer 400 and an insulating planarization layer 500 located between the circuit layer 400 and the anode layer 120 of the display panel 100; the resistivity-reducing layer 600 further includes a third resistivity-reducing sub-section 630 located around and connected to the first resistivity-reducing sub-section 610, the third resistivity-reducing sub-section 630 being located between the cathode voltage line 210 and the insulating planarization layer 500; the insulating planarization layer 500 includes a plurality of first vias 501, the first vias 501 exposing the first resistivity-reducing sub-section 610 of the resistivity-reducing layer 600, and the electron transport layer 701 being connected to the first resistivity-reducing sub-section 610 through the first vias 501.

[0107] The insulating planarization layer 500 presses against the third resistance-reducing sub-section 630 of the resistance-reducing layer 600. Therefore, the formation step of the resistance-reducing layer 600 is located before the formation step of the insulating planarization layer 500, which can improve the flatness of the overall film layer of the display panel 100. At the same time, the material of the resistance-reducing layer 600 can be selected from a wider range, and it does not have to be limited to the same material as the anode layer 120. This is more conducive to reducing the contact resistance between the cathode layer 800, the electron injection layer 702, the electron transport layer 701, and the cathode voltage line 210, enhancing the electrical conductivity of the cathode connection, and improving the display effect.

[0108] Please see Figure 8 This invention also provides a method for manufacturing a display panel 100, comprising:

[0109] S100, providing a substrate 110.

[0110] S200, A cathode voltage line 210 is formed on one side of the substrate 110.

[0111] S300, an insulating planarization layer 500 including a plurality of first vias 501 is formed on the side of the cathode voltage line 210 away from the substrate 110, the first vias 501 exposing the cathode voltage line 210.

[0112] S400, an anode material layer is formed on the side of the insulating planar layer 500 away from the substrate 110.

[0113] S500, The anode material layer is patterned using a mask to form an anode layer 120 and a resistance-reducing layer 600 corresponding to the first via 501. The resistance-reducing layer 600 is connected to the cathode voltage line 210.

[0114] S600, an electron transport material layer, an electron injection material layer, and a cathode material layer are formed on the side of the insulating planarization layer 500 away from the substrate 110.

[0115] S700, The electron transport material layer, electron injection material layer and cathode material layer are patterned using a mask to form electron transport layer 701, electron injection layer 702 and cathode layer 800.

[0116] This invention uses a single mask to pattern the cathode layer, electron injection layer, and electron transport layer into the same pattern. At the same time, a resistance-reducing layer is set between the cathode voltage line and the electron injection layer and electron transport layer. This reduces the number of masks, simplifies the production process, and lowers production costs. At the same time, it reduces the contact resistance between the cathode layer, electron injection layer, electron transport layer, and cathode voltage line, enhances the electrical conductivity of the cathode connection, and improves the display effect.

[0117] In some embodiments, step S500 includes:

[0118] S510a, The anode material layer is patterned using a mask to form an anode layer 120 and a first resistance-reducing sub-section 610 corresponding to the first via 501, thereby forming a resistance-reducing layer 600. The first resistance-reducing sub-section 610 is connected to the cathode voltage line 210.

[0119] In some embodiments, step S500 includes:

[0120] S510b: The anode material layer is patterned using a mask to form an anode layer 120, and a first resistance-reducing sub-section 610 and a second resistance-reducing sub-section 620 corresponding to the first via 501, to form a resistance-reducing layer 600. The first resistance-reducing sub-section 610 is connected to the cathode voltage line 210.

[0121] In some embodiments, please refer to Figure 3 The resistance-reducing layer 600 includes a first resistance-reducing sub-section 610 and a second resistance-reducing sub-section 620 located around and connected to the first resistance-reducing sub-section 610. The second resistance-reducing sub-section 620 is located on the sidewall of the first via 501 corresponding to the insulating planarization layer 500.

[0122] The second resistance-reducing sub-section 620 can further enhance the resistance-reducing effect. At the same time, the second resistance-reducing sub-section 620 extends to the side wall of the insulating planar layer 500 corresponding to the first via 501. When the display panel 100 is bent, the risk of the resistance-reducing layer 600 falling off the first via 501 is reduced, thus ensuring the resistance-reducing effect.

[0123] In some embodiments, please refer to Figure 2 , Figure 3 The display panel 100 further includes an anode layer 120, the material and film stack of which are the same as those of the drag-reducing layer 600.

[0124] The anode layer 120 near the electron transport layer 701 can be made of a metal oxide material. When fabricating the anode layer 120, the same mask can be used to form both the anode layer 120 and the resistance-reducing layer 600. Therefore, the material and film stack of the resistance-reducing layer 600 are the same as those of the anode layer 120, which can save a mask, simplify the process, and reduce production costs.

[0125] In some embodiments, please refer to Figure 2 , Figure 3The resistance-reducing layer 600 further includes a second metal oxide layer 602 in contact with the cathode voltage line 210, and a conductive functional layer 603 located between the first metal oxide layer 601 and the second metal oxide layer.

[0126] The material and film layer stack of the resistance-reducing layer 600 are the same as those of the anode layer 120. The anode layer 120 is also a stack of metal oxide-conductive function-metal oxide, such as ITO / Ag / ITO, IZO / Ag / IZO, etc. The upper and lower metal oxide layers are in contact with the cathode voltage line 210 and the electron transport layer 701, which can more directly reduce the contact resistance, enhance the electrical conductivity of the cathode connection, and improve the display effect.

[0127] Please see Figure 9 The present invention also provides a display device 10, including a display panel 100 as described above.

[0128] For the specific structure of the display panel 100, please refer to any of the above-described embodiments of the display panel 100 and the accompanying drawings, which will not be repeated here.

[0129] In this embodiment, the display device 10 includes a device body 20, which is integrated with the display panel 100.

[0130] In this embodiment, the main body 20 of the device may include a middle frame, frame adhesive, etc., and the display device 10 may be a display terminal such as a mobile phone, tablet, or television, which is not limited here.

[0131] This invention discloses a display panel and its manufacturing method. The display panel includes a driving trace layer, an electron transport layer, an electron injection layer, and a cathode layer. The driving trace layer includes cathode voltage lines. The electron transport layer is connected to the cathode voltage lines, and the cathode layer is connected to the electron injection layer. The patterns of the electron transport layer and the electron injection layer are the same as the pattern of the cathode layer. The display panel also includes a resistance-reducing layer located between the cathode voltage lines and the electron transport layer. This invention uses a single mask to simultaneously pattern the cathode layer, the electron injection layer, and the electron transport layer to form the same pattern. At the same time, a resistance-reducing layer is set between the cathode voltage lines and the electron injection layer and the electron transport layer, reducing the number of masks, simplifying the manufacturing process, and reducing production costs. At the same time, it reduces the contact resistance between the cathode layer, the electron injection layer, the electron transport layer, and the cathode voltage lines, enhances the electrical conductivity of the cathode connection, and improves the display effect.

[0132] The above provides a detailed description of a display panel and its manufacturing method according to embodiments of the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A display panel, characterized by, include: The driving trace layer includes cathode voltage lines and multiple cathode fan-out traces; An electron transport layer is located on one side of the drive trace layer and is connected to the cathode voltage line; An electron injection layer is located on the side of the electron transport layer away from the drive trace layer; The cathode layer is located on the side of the electron injection layer away from the drive trace layer and is connected to the electron injection layer; A resistance-reducing layer is located between the cathode voltage line and the electron transport layer; The patterns of the electron transport layer and the electron injection layer are the same as the pattern of the cathode layer; The display panel includes a display area and a non-display area located around the display area. The non-display area includes a cathode overlap area, which includes multiple sub-areas. Multiple first vias correspond to one sub-area. The cathode voltage line in one sub-area is connected to multiple cathode fan-out traces. In one sub-area, the length of the cathode fan-out trace near the center of the sub-area is less than the length of the cathode fan-out trace near the edge of the sub-area. The thickness of the resistance-reducing layer near the center of the sub-area is less than the thickness of the resistance-reducing layer near the edge of the sub-area.

2. The display panel of claim 1, wherein, The drag-reducing layer includes at least a first metal oxide layer in contact with the electron transport layer.

3. The display panel according to claim 2, characterized in that, The display panel further includes an anode layer, the material and film stack of which are the same as those of the drag-reducing layer.

4. The display panel according to claim 3, characterized in that, The resistance-reducing layer further includes a second metal oxide layer in contact with the cathode voltage line, and a conductive functional layer located between the first metal oxide layer and the second metal oxide layer.

5. The display panel according to claim 3, characterized in that, The drive trace layer further includes a circuit layer and an insulating planarization layer located between the circuit layer and the anode layer; The insulating planarization layer includes a plurality of first vias, the first vias exposing the cathode voltage line, and the resistance-reducing layer is connected to the cathode voltage line through the first vias.

6. The display panel according to claim 5, characterized in that, The resistance-reducing layer includes a first resistance-reducing sub-section and a second resistance-reducing sub-section located around and connected to the first resistance-reducing sub-section. The second resistance-reducing sub-section is located on the sidewall of the insulating planar layer corresponding to the first via.

7. The display panel according to claim 1, characterized in that, The driving trace layer includes a circuit layer and an insulating planarization layer located between the circuit layer and the anode layer of the display panel; The resistance-reducing layer includes a first resistance-reducing sub-section and a third resistance-reducing sub-section located around and connected to the first resistance-reducing sub-section. The third resistance-reducing sub-section is located between the cathode voltage line and the insulating planarization layer. The insulating planarization layer includes a plurality of first vias, the first vias exposing the first resistance-reducing sub-section of the resistance-reducing layer, and the electron transport layer is connected to the first resistance-reducing sub-section through the first vias.

8. The display panel according to claim 5 or 7, characterized in that, The display panel includes a display area and a non-display area located around the display area. The non-display area includes a cathode overlap area, and each of the first vias is located within the cathode overlap area. The cathode layer, the electron injection layer, and the electron transport layer cover the display area and the cathode overlap area.

9. A method for manufacturing a display panel, characterized in that, include: Provide a substrate; A cathode voltage line is formed on one side of the substrate; A resistance-reducing layer is formed on the side of the cathode voltage line away from the substrate; An insulating planarization layer is formed on the resistance-reducing layer; The insulating planarization layer is patterned to form a plurality of first vias, the first vias exposing the resistance-reducing layer. An electron transport material layer, an electron injection material layer, and a cathode material layer are formed on the side of the insulating planar layer away from the substrate; The electron transport material layer, the electron injection material layer and the cathode material layer are patterned using a mask to form the electron transport layer, the electron injection layer and the cathode layer. The driving trace layer containing the cathode voltage line further includes multiple cathode fan-out traces. The display panel includes a display area and a non-display area located around the display area. The non-display area includes a cathode overlap area, which includes multiple sub-areas. Multiple first vias correspond to one sub-area. The cathode voltage line in one sub-area is connected to multiple cathode fan-out traces. In one sub-area, the length of the cathode fan-out trace near the center of the sub-area is less than the length of the cathode fan-out trace near the edge of the sub-area. The thickness of the resistance-reducing layer near the center of the sub-area is less than the thickness of the resistance-reducing layer near the edge of the sub-area.

10. A method for manufacturing a display panel, characterized in that, include: Provide a substrate; A cathode voltage line is formed on one side of the substrate; An insulating planar layer comprising a plurality of first vias is formed on the side of the cathode voltage line away from the substrate, the first vias exposing the cathode voltage line; An anode material layer is formed on the side of the insulating planar layer away from the substrate; The anode material layer is patterned using a mask to form an anode layer and a resistance-reducing layer corresponding to the first via. An electron transport material layer, an electron injection material layer, and a cathode material layer are formed on the side of the insulating planar layer away from the substrate; The electron transport material layer, the electron injection material layer and the cathode material layer are patterned using a mask to form the electron transport layer, the electron injection layer and the cathode layer. The driving trace layer containing the cathode voltage line further includes multiple cathode fan-out traces. The display panel includes a display area and a non-display area located around the display area. The non-display area includes a cathode overlap area, which includes multiple sub-areas. Multiple first vias correspond to one sub-area. The cathode voltage line in one sub-area is connected to multiple cathode fan-out traces. In one sub-area, the length of the cathode fan-out trace near the center of the sub-area is less than the length of the cathode fan-out trace near the edge of the sub-area. The thickness of the resistance-reducing layer near the center of the sub-area is less than the thickness of the resistance-reducing layer near the edge of the sub-area.

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