Heterojunction threshold selector and preparation method thereof

Abstract

The application discloses a heterojunction threshold selector and a preparation method thereof. The threshold selector comprises a substrate, a first electrode layer, a heterojunction material layer and a second electrode layer which are sequentially stacked on the substrate. The heterojunction material layer comprises n+1 first sub-layers and n second sub-layers, the n+1 first sub-layers and the n second sub-layers are alternately stacked, the first first sub-layer is arranged in adhesion with the first electrode layer, the n+1 first sub-layer is arranged in adhesion with the second electrode layer, and n is a positive integer. The material of the first sub-layer comprises M, and the material of the second sub-layer comprises M x Te 1‑x , M comprises one of B and Si, and 0≤x≤0.5. The threshold selector provided by the application has a lower off current, better cycle performance and reliability.

Description

Technical Field

[0001] This invention relates to the field of gate technology, and in particular to a heterojunction threshold gate and its fabrication method. Background Technology

[0002] Memory is an indispensable hardware component in the era of big data. The massive data throughput and data read / write speeds place higher demands on memory. Among them, phase-change memory (PCM) is recognized by the industry as the most promising memory due to its advantages such as fast operation speed, low power consumption, and high storage density.

[0003] Phase-change memories (PCMs) suffer from high shutdown current. When the gate current flows through a designated node cell, it may flow through other cells, leading to a decrease in device reliability. Therefore, a gate switch is needed on each memory cell to reduce the shutdown current. Since the phase-change material needs to provide a sufficiently large reset current from the gate to heat it to a certain temperature to transition from a crystalline to an amorphous state, the gate is also a crucial factor in achieving high-density PCM storage.

[0004] Currently, commonly used threshold gate materials are mainly multi-component tellurium-based and sulfur-based materials, such as Ge-As-Te-Si-N and Ge-Se-Te-As-Si. However, due to the large number of atomic types, multi-component materials are prone to component segregation under repeated electrical pulses, leading to reduced device cycle performance and reliability. Furthermore, the asperium (As) they contain is toxic and not environmentally friendly, thus necessitating the search for materials with fewer components and no asperium. Recent studies have found that single-element Te materials possess switching characteristics, but unlike traditional threshold gate materials, Te is in a high-resistivity state in its crystalline state at room temperature and a low-resistivity state in its liquid state. Therefore, Te-based devices operate at high temperatures when on, affecting the data stability of adjacent phase-change memory cells. Common binary threshold gate materials include B-Te, C-Te, and Si-Te. Threshold gates based on these binary materials exhibit fast switching speeds and large drive currents, but their high turn-off current and cycle performance still require further improvement.

[0005] Therefore, existing technologies still need to be improved and developed. Summary of the Invention

[0006] In view of the shortcomings of the prior art, the purpose of this invention is to provide a heterojunction threshold selector and its preparation method, which aims to solve the problems of large shut-off current and the need for further improvement in the cycling performance of existing threshold selectors based on binary threshold selector materials.

[0007] The technical solution of the present invention is as follows:

[0008] In a first aspect, the present invention provides a heterojunction threshold gate, comprising a substrate, and a first electrode layer, a heterojunction material layer, and a second electrode layer sequentially stacked on the substrate.

[0009] The heterojunction material layer includes n+1 first sublayers and n second sublayers, which are alternately stacked. The first first sublayer is attached to the first electrode layer, and the (n+1)th first sublayer is attached to the second electrode layer; where n is a positive integer.

[0010] The material of the first sublayer includes M, and the material of the second sublayer includes M. x Te 1-x M includes one of B and Si, and 0 ≤ x ≤ 0.5.

[0011] Optionally, the thickness of the first sublayer is 0.5–2 nm, and the thickness of the second sublayer is 4–6 nm.

[0012] Optionally, the thickness of the heterojunction material layer is less than or equal to 50 nm.

[0013] Optionally, n can take values ​​from 1 to 11.

[0014] Optionally, the materials of the first electrode layer and the second electrode layer are each independently one of an inert metal and an alloy containing an inert metal nitride.

[0015] Optionally, the inert metal includes at least one of W, Pt, Au, Ti, Al, Ag, Cu, and Ni; the alloy containing the inert metal nitride is an alloy containing at least one of W nitride, Pt nitride, Au nitride, Ti nitride, Al nitride, Ag nitride, Cu nitride, and Ni nitride.

[0016] In a second aspect, the present invention provides a method for fabricating a heterojunction threshold gate, comprising the steps of:

[0017] Provide substrate;

[0018] A first electrode layer is formed on the substrate;

[0019] A heterojunction material layer is formed on the first electrode layer;

[0020] A second electrode layer is formed on the heterojunction material layer;

[0021] The heterojunction material layer comprises n+1 first sublayers and n second sublayers, which are alternately stacked. The first first sublayer is attached to the first electrode layer, and the (n+1)th first sublayer is attached to the second electrode layer; where n is a positive integer.

[0022] The material of the first sublayer includes M, and the material of the second sublayer includes M. x Te 1-x M includes one of B and Si, and 0 ≤ x ≤ 0.5.

[0023] Optionally, a first electrode layer is formed on the substrate by one of sputtering, evaporation, physical vapor deposition, chemical vapor deposition, plasma-enhanced chemical vapor deposition, molecular beam epitaxy, atomic layer deposition, atomic vapor deposition, and metal compound vapor deposition.

[0024] And / or,

[0025] A second electrode layer is formed on the heterojunction material layer by one of the following methods: sputtering, evaporation, physical vapor deposition, chemical vapor deposition, plasma-enhanced chemical vapor deposition, molecular beam epitaxy, atomic layer deposition, atomic vapor deposition, and metal compound vapor deposition.

[0026] Optionally, the step of forming a heterojunction material layer on the first electrode layer specifically includes:

[0027] n+1 first sublayers and n second sublayers are sequentially and alternately deposited on the first electrode layer.

[0028] Optionally, the deposition method includes one of sputtering, evaporation, physical vapor deposition, chemical vapor deposition, plasma-enhanced chemical vapor deposition, molecular beam epitaxy, atomic layer deposition, atomic vapor deposition, and metal compound vapor deposition.

[0029] Beneficial effects: In this invention, the material of the first sublayer includes M, and the material of the second sublayer corresponds to M. x Te 1-x M is one of B and Si. The M in the first sublayer (including one of B and Si) has weak conductivity at room temperature, resulting in a low turn-off current for the threshold selector. When the device is turned on, the threshold selector material is at a higher temperature. At this temperature, the conductivity of M increases, effectively increasing the drive current. Furthermore, M and M... x Te 1-xAfter the heterojunction is formed, M has high thermal stability, which can suppress the diffusion of M in the second sublayer due to high temperature or M that has diffused into the second sublayer after multiple operations in the direction perpendicular to the heterojunction material layer. This compresses the material from three-dimensional threshold transition characteristics to two-dimensional, thereby reducing the generation of voids and improving the device's cycle performance and reliability. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of the heterojunction threshold selector in an embodiment of the present invention.

[0031] Figure 2 This is a schematic diagram of the structure of a heterojunction threshold selector in another embodiment of the present invention.

[0032] Figure 3 This is a schematic diagram of the structure of a heterojunction threshold selector in another embodiment of the present invention.

[0033] Figure 4 This is the current-voltage characteristic diagram of the heterojunction threshold selector in Embodiment 1 of the present invention.

[0034] Figure 5 This is a diagram showing the cyclic characteristics of the heterojunction threshold selector in Embodiment 1 of the present invention.

[0035] Figure 6 This is the current-voltage characteristic diagram of the heterojunction threshold selector in Embodiment 5 of the present invention.

[0036] Figure 7 This is a diagram showing the cyclic characteristics of the heterojunction threshold selector in Embodiment 5 of the present invention. Detailed Implementation

[0037] This invention provides a heterojunction threshold selector and its fabrication method. To make the objectives, technical solutions, and effects of this invention clearer and more explicit, the invention is further described in detail below. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

[0039] This invention provides a heterojunction threshold gate, wherein, as shown in the embodiments, Figure 1 As shown, it includes a substrate 110, and a first electrode layer 120, a heterojunction material layer 130 and a second electrode layer 140 sequentially stacked on the substrate 110.

[0040] The heterojunction material layer 130 includes n+1 first sublayers 131 and n second sublayers 132, which are alternately stacked. The first first sublayer 131 is attached to the first electrode layer 120, and the (n+1)th first sublayer 131 is attached to the second electrode layer 140; where n is a positive integer.

[0041] The material of the first sublayer includes M, and the material of the second sublayer includes M. x Te 1-x M includes either B or Si, and 0 ≤ x ≤ 0.5 (where x represents the percentage of atoms of element M in M). x Te 1-x The ratio of the total number of atoms, x to 1-x, is the ratio of the number of atoms of element M to element Te.

[0042] In this embodiment, a heterojunction is formed between the interfaces of adjacent first and second sublayers in the heterojunction material layer. The material of the first sublayer includes M, and the material of the second sublayer includes M... x Te 1-x In other words, when M is B, the material of the first sublayer includes B, and the material of the second sublayer includes B. x Te 1-x When M is Si, the material of the first sublayer includes Si, and the material of the second sublayer includes Si. x Te 1-x In this embodiment, M x Te 1-x It is an alloy material composed of M and Te.

[0043] In this embodiment, the M (including one of B and Si) in the first sublayer has weak conductivity at room temperature, resulting in a low turn-off current for the threshold selector. When the device is turned on, the threshold selector material is at a higher temperature, at which point the conductivity of M increases, effectively increasing the drive current. Furthermore, M and M... x Te 1-x After the heterojunction is formed, M has high thermal stability, which can suppress the diffusion of M in the second sublayer due to high temperature or M that has diffused into the second sublayer after multiple operations in the direction perpendicular to the heterojunction material layer. This compresses the material from three-dimensional threshold transition characteristics to two-dimensional, thereby reducing the generation of voids and improving the device's cycle performance and reliability.

[0044] In one embodiment, the thickness of the first sublayer is 0.5 to 2 nm, for example, it can be 0.5 nm, 0.8 nm, 1 nm, 1.5 nm or 2 nm.

[0045] In one embodiment, the thickness of the second sublayer is 4 to 6 nm, for example, it can be 4 nm, 4.5 nm, 5 nm, 5.5 nm or 6 nm.

[0046] The thickness of both the first and second sublayers is below 6nm, which gives the threshold gate good amorphous thermal stability.

[0047] In one embodiment, the thickness of the heterojunction material layer is less than or equal to 50 nm. Excessive thickness of the heterojunction material layer can reduce the driving current of the threshold selector, affecting the reversible phase transition of the phase-change memory device cells; therefore, the thickness of the heterojunction material layer is no greater than 50 nm.

[0048] In one implementation, n takes values ​​from 1 to 11, for example, n=1, n=2, n=3, n=4, n=5, n=8, n=10, or n=11, etc. As an example, when n=2, the structural schematic diagram of the heterojunction threshold selector is as follows... Figure 2 As shown; when n=3, the structural schematic diagram of the heterojunction threshold selector is as follows. Figure 3 As shown, n ranging from 1 to 11 ensures that the heterojunction material layer has a suitable thickness, allowing the threshold gate to have a large driving current.

[0049] In one embodiment, the materials of the first electrode layer and the second electrode layer are each independently an inert metal or an alloy containing inert metal nitrides. Since inert metals and alloys containing inert metal nitrides are difficult to combine with other elements, the fact that the materials of the first electrode layer and the second electrode layer are each independently an inert metal or an alloy containing inert metal nitrides can, on the one hand, effectively prevent the diffusion of active metal conductive particles from the heterojunction material layer into the electrode layer, improving the cycle characteristics of the device; on the other hand, it can also effectively prevent device failure caused by oxidation or corrosion of the electrode layer.

[0050] In one embodiment, the inert metal includes at least one of W, Pt, Au, Ti, Al, Ag, Cu, and Ni, but is not limited thereto; the alloy containing the inert metal nitride is an alloy containing at least one of W nitride, Pt nitride, Au nitride, Ti nitride, Al nitride, Ag nitride, Cu nitride, and Ni nitride.

[0051] This invention also provides a method for fabricating a heterojunction threshold selector, comprising the following steps:

[0052] S1, Provide a substrate;

[0053] S2. A first electrode layer is formed on the substrate;

[0054] S3. A heterojunction material layer is formed on the first electrode layer;

[0055] S4. A second electrode layer is formed on the heterojunction material layer;

[0056] The heterojunction material layer comprises n+1 first sublayers and n second sublayers, which are alternately stacked. The first first sublayer is attached to the first electrode layer, and the (n+1)th first sublayer is attached to the second electrode layer. Here, n is a positive integer.

[0057] The material of the first sublayer includes M, and the material of the second sublayer includes M. x Te 1-x M includes one of B and Si, and 0 ≤ x ≤ 0.5.

[0058] The fabrication method provided in this invention is simple. The first sublayer M (including one of B and Si) in the obtained heterojunction threshold selector exhibits weak conductivity at room temperature, resulting in a low turn-off current for the threshold selector. When the device is turned on, the threshold selector material is at a higher temperature, at which point the conductivity of M increases, effectively increasing the drive current. Furthermore, M and M... x Te 1-x After the heterojunction is formed, M has high thermal stability, which can suppress the diffusion of M in the second sublayer due to high temperature or M that has diffused into the second sublayer after multiple operations in the direction perpendicular to the heterojunction material layer. This compresses the material from three-dimensional threshold transition characteristics to two-dimensional, thereby reducing the generation of voids and improving the device's cycle performance and reliability.

[0059] In this embodiment, both the first electrode layer and the second electrode layer are in contact with the first sublayer (the material is M with weak conductivity), thereby further preventing M in the second sublayer material caused by high temperature or M that has diffused into the second sublayer after multiple operations from diffusing in the direction perpendicular to the heterojunction material layer. This compresses the material from three-dimensional threshold transition characteristics to two dimensions, thereby reducing the generation of voids and improving the device's cycle performance and reliability.

[0060] In step S1, the present invention does not limit the specific material of the substrate; any existing material suitable for use as a threshold selector is acceptable. For example, the substrate may be a Si substrate, a Si / SiO2 substrate (i.e., a Si substrate with a layer of SiO2 on its surface), etc. Specifically, a dense layer of silicon dioxide is grown on the surface of the Si substrate using plasma-enhanced chemical vapor deposition or atomic layer deposition to form a Si / SiO2 substrate, wherein the crystal orientation of the Si is [missing information]. <100> .

[0061] In step S2, a first electrode layer is formed on the substrate using one of the following methods: sputtering, evaporation, physical vapor deposition, chemical vapor deposition, plasma-enhanced chemical vapor deposition, molecular beam epitaxy, atomic layer deposition, atomic vapor deposition, and metal compound vapor deposition. Of course, this invention is not limited to these methods; other methods for preparing the electrode layer are also acceptable.

[0062] In step S3, in one embodiment, the step of forming a heterojunction material layer on the first electrode layer specifically includes:

[0063] n+1 first sublayers and n second sublayers are sequentially and alternately deposited on the first electrode layer.

[0064] In one embodiment, the deposition method includes, but is not limited to, sputtering, evaporation, physical vapor deposition, chemical vapor deposition, plasma-enhanced chemical vapor deposition, molecular beam epitaxy, atomic layer deposition, atomic vapor deposition, and metal compound vapor deposition.

[0065] The material and thickness of the first sublayer, the material and thickness of the second sublayer, and the thickness of the heterojunction material layer are described above, and the value of n will not be repeated here.

[0066] In step S4, in one embodiment, a second electrode layer is formed on the heterojunction material layer using one of the following methods: sputtering, evaporation, physical vapor deposition, chemical vapor deposition, plasma-enhanced chemical vapor deposition, molecular beam epitaxy, atomic layer deposition, atomic vapor deposition, and metal compound vapor deposition. Of course, this invention is not limited to these methods; other methods for preparing the electrode layer are also acceptable.

[0067] When using sputtering, the sputtering time can be controlled according to the growth rate of the thin film. For example, the sputtering time can be controlled to be 20-25 min, so that the total thickness of the heterojunction material layer is 50 nm.

[0068] The material and thickness of the second electrode layer are described above and will not be repeated here.

[0069] The following detailed description uses specific examples.

[0070] Example 1

[0071] This embodiment provides a heterojunction threshold selector, including a substrate, and a first electrode layer, a heterojunction material layer and a second electrode layer are sequentially stacked on the substrate;

[0072] The heterojunction material layer includes n+1 first sublayers and n second sublayers, which are alternately stacked. The first first sublayer is attached to the first electrode layer, and the (n+1)th first sublayer is attached to the second electrode layer; where n = 2.

[0073] In this embodiment, the substrate is a Si wafer with a SiO2 layer on its surface; the material of the first sublayer is B, and the thickness of the first sublayer is 1 nm; the material of the second sublayer is B. 0.3 Te 0.7 The thickness of the second sublayer is 5nm, the material of the first electrode layer is W, and the thickness of the first electrode layer is 100nm; the material of the second electrode layer is W, and the thickness of the second electrode layer is 100nm.

[0074] The method for fabricating the heterojunction-type threshold gate includes the following steps:

[0075] (1) The Si wafer (crystal orientation is...) <100> The wafer is placed in acetone and alcohol for ultrasonic cleaning for about ten minutes. After ultrasonic cleaning, the residual liquid on the surface is blown away and dried with a nitrogen gun. A dense SiO2 layer is grown on the silicon wafer using plasma-enhanced chemical vapor deposition.

[0076] (2) A 100 nm W layer is magnetron sputtered on the SiO2 layer to form the first electrode layer;

[0077] (3) Magnetron sputtering was used, with a base pressure of 1×10⁻⁶. -5 During sputtering, the Ar gas pressure was 0.2 Pa. Using a B elemental target (sputtering power of 170 W), a 1 nm thick B layer was first sputtered on the first electrode layer. Then, a 5 nm thick B layer was co-sputtered using a B elemental target (sputtering power of 170 W) and a Te elemental target (sputtering power of 8 W). 0.3 Te 0.7 Layer; repeat this process, alternately sputtering layer B and layer B. 0.3 Te 0.7 Layers, until you get 3 B layers, 2 B layers 0.3 Te 0.7 layer;

[0078] (4) A 100 nm W layer is magnetron sputtered on the B layer to form a second electrode layer.

[0079] In this embodiment, the material of the first sublayer is B, and the material of the second sublayer is B. 0.3 Te 0.7After the heterojunction is formed, due to the high thermal stability of B, it can suppress the diffusion of B in the second sublayer material in the direction perpendicular to the heterojunction material layer caused by high temperature, compressing the material from three-dimensional threshold transition characteristics to two-dimensional, thereby reducing the generation of voids and improving the cycle life and reliability of the device.

[0080] The current-voltage (IV) characteristic diagram of the heterojunction threshold selector provided in Example 1 is shown below. Figure 4 As shown, the shut-off current of this heterojunction threshold selector is 6 × 10⁻⁶. -11 A. Drive current 1×10 -4 A. The on / off ratio has seven orders of magnitude. Measurements show that, based on non-heterojunction amorphous B... 0.3 Te 0.7 The threshold gate for the material (this device differs from the heterojunction threshold gate in Example 1 only in that the material of the heterojunction material layer in Example 1 is replaced with B) 0.3 Te 0.7 The shut-off current is 1×10 -9 The switching ratio is 10. 5 (5 orders of magnitude).

[0081] The cyclic characteristic diagram of the heterojunction threshold gate provided in Example 1 is as follows: Figure 5 As shown, this heterojunction threshold gate has a performance of 1×10 9 After several cycles, it still did not fail. Furthermore, during the cycle operation, both the drive current and the shutdown current remained relatively stable, indicating that this heterojunction threshold selector exhibits good cycling characteristics and device stability. Measurements showed that based on a non-heterojunction amorphous B... 0.3 Te 0.7 Material threshold gate (This device differs from the heterojunction threshold gate in Example 1 only in that the material of the heterojunction material layer in Example 1 is replaced with B) 0.3 Te 0.7 ) Cycle 1×10 8 It becomes invalid after that.

[0082] Therefore, the heterojunction threshold selector provided by this invention (with a turn-off current of 6 × 10⁻⁶) -11 A. Switch ratio is 7 orders of magnitude, cycle 1×10 9 (No subsequent failure) compared to non-heterojunction amorphous B 0.3 Te 0.7 Material threshold gate (shutdown current is 1×10) -9 The switching ratio is 10. 5 , repeat 1×10 8 (Post-failure) features lower shutdown current, higher on / off ratio, better cycle performance, reliability, and amorphous thermal stability.

[0083] Example 2

[0084] This embodiment provides a heterojunction threshold gate, which differs from Embodiment 1 only in that n = 8.

[0085] The fabrication method of the heterojunction threshold selector differs from that of Example 1 only in that, in step (3), nine B layers with a thickness of 1 nm and eight B layers with a thickness of 5 nm are deposited alternately. 0.3 Te 0.7 layer.

[0086] Example 3

[0087] This embodiment provides a heterojunction threshold gate, which differs from Embodiment 1 only in that the material of the second sublayer is Te.

[0088] The method for preparing the heterojunction threshold selector differs from that in Example 1 only in that, in step (3), a B layer with a thickness of 1 nm is first sputtered on the first electrode layer using a B single-element target (sputtering power of 170 W), and then a Te layer with a thickness of 5 nm is sputtered using a Te single-element target (sputtering power of 8 W); this process is repeated to alternately sputter B and Te layers until three B layers with a thickness of 1 nm and two Te layers with a thickness of 5 nm are obtained.

[0089] In this embodiment, the first sublayer is made of B, and the second sublayer is made of Te. The material from the first sublayer diffuses into a portion of the interface of the second sublayer to form a heterojunction. B exhibits weak conductivity at room temperature, resulting in a lower turn-off current for the threshold selector, thus addressing the issue of high turn-off current with Te material. Furthermore, due to the high thermal stability of B, it can suppress the diffusion of B into the Te layer after multiple operations in the direction perpendicular to the heterojunction material layer, compressing the material's three-dimensional threshold transition characteristics to two dimensions. This reduces void formation and improves the device's cycle life and reliability.

[0090] Example 4

[0091] This embodiment provides a heterojunction threshold gate, which differs from Embodiment 3 only in that n = 8.

[0092] The method for preparing the heterojunction threshold selector differs from that in Example 1 only in that, in step (3), nine B layers with a thickness of 1 nm and eight Te layers with a thickness of 5 nm are sputtered alternately.

[0093] Example 5

[0094] This embodiment provides a heterojunction threshold gate, which differs from Embodiment 1 only in that the material of the first sublayer is Si, and the material of the second sublayer is Si. 0.4 Te0.6 ;

[0095] The fabrication method of the heterojunction threshold gate differs from that in Example 1 only in that:

[0096] In step (3), a 1 nm thick Si layer is first sputtered on the first electrode layer using a Si elemental target (sputtering power of 150 W), and then a 5 nm thick Si layer is co-sputtered on the Si layer using a Si elemental target (sputtering power of 150 W) and a Te elemental target (sputtering power of 8 W). 0.4 Te 0.6 Layer, repeat this process alternately sputtering Si layers and Si 0.4 Te 0.6 Layers were applied until three 1nm thick Si layers and two 5nm thick Si layers were obtained. 0.4 Te 0.6 layer.

[0097] In this embodiment, the material of the first sublayer is Si, and the material of the second sublayer is Si. 0.4 Te 0.6 After the heterojunction is formed, Si has high thermal stability, which can suppress the diffusion of Si in the second sublayer material in the direction of the heterojunction material layer caused by high temperature. This compresses the material from three-dimensional threshold transition characteristics to two-dimensional, thereby reducing the generation of voids and improving the cycle life and reliability of the device.

[0098] The current-voltage (IV) characteristic diagram of the heterojunction threshold selector provided in Example 5 is shown below. Figure 6 As shown, the shut-off current of this heterojunction threshold selector is 1 × 10⁻⁶. -11 A. Drive current 8×10 -4 A. The on / off ratio has seven orders of magnitude. Measurements show that this is based on non-heterojunction amorphous Si. 0.4 Te 0.6 The threshold gate for the material (this device differs from the heterojunction threshold gate in Example 5 only in that the material of the heterojunction material layer in Example 5 is replaced with Si) 0.4 Te 0.6 The shut-off current is 8 × 10 -10 A. Switch ratio is 10 6 (6 orders of magnitude).

[0099] The cyclic characteristic diagram of the heterojunction threshold selector provided in Example 5 is as follows: Figure 7 As shown, this heterojunction threshold gate has a performance of 1×10 6After several cycles, it still did not fail. Furthermore, during the cycle operation, both the drive current and the shutdown current remained relatively stable, indicating that this heterojunction threshold selector exhibits good cycling characteristics and device stability. Measurements showed that this is based on a non-heterojunction amorphous Si... 0.4 Te 0.6 Material threshold gate (This device differs from the heterojunction threshold gate in Example 5 only in that the material of the heterojunction material layer in Example 1 is replaced with Si). 0.4 Te 0.6 ) Repeat 5×10 5 It becomes invalid after that.

[0100] Therefore, the heterojunction threshold selector provided by this invention (with a turn-off current of 1×10⁻⁶) -11 A. The switching ratio has 7 orders of magnitude, and the cycle is 1×10. 6 (No subsequent failure) compared to non-heterojunction amorphous Si 0.4 Te 0.6 Material threshold selector (shutdown current is 8×10) -10 A. The switching ratio is on the order of 6, with 5 × 10 cycles. 5 (Failure after secondary failure) features lower shutdown current, higher on / off ratio, better cycle performance, reliability, and amorphous thermal stability.

[0101] Example 6

[0102] This embodiment provides a heterojunction threshold gate, which differs from Embodiment 5 only in that n = 8.

[0103] The fabrication method of the heterojunction threshold selector differs from that of Example 5 only in that, in step (3), nine 1 nm thick Si layers and eight 5 nm thick Si layers are alternately sputtered. 0.4 Te 0.6 layer.

[0104] Example 7

[0105] This embodiment provides a heterojunction threshold gate, which differs from Embodiment 5 only in that the material of the second sublayer is Te.

[0106] The difference between the preparation method of the heterojunction threshold selector and Example 5 is that, using a Si single-element target (sputtering power of 150W), a Si layer with a thickness of 1nm is first sputtered on the first electrode layer, and then a Te single-element target (sputtering power of 150W) is used to sputter a Te layer with a thickness of 5nm on the Si layer. This process is repeated to alternately sputter the Si layer and the Te layer until three Si layers with a thickness of 1nm and two Te layers with a thickness of 5nm are obtained.

[0107] In this embodiment, the first sublayer is made of Si, and the second sublayer is made of Te. The material from the first sublayer diffuses into the second sublayer to form a heterojunction. Si exhibits weak conductivity at room temperature, resulting in a lower turn-off current for the threshold selector, thus addressing the issue of high turn-off current with Te material. Furthermore, due to the high thermal stability of Si, it can suppress the diffusion of Si that has diffused into the Te layer after multiple operations along the heterojunction material layer direction, compressing the material's three-dimensional threshold transition characteristics to two dimensions. This reduces void formation and improves the device's cycle life and reliability.

[0108] Example 8

[0109] This embodiment provides a heterojunction threshold gate, which differs from Embodiment 7 only in that n = 8.

[0110] The method for preparing the heterojunction threshold selector differs from that in Example 7 only in that, in step (3), nine Si layers with a thickness of 1 nm and eight Te layers with a thickness of 5 nm are sputtered alternately.

[0111] In summary, this invention provides a heterojunction-type threshold selector and its fabrication method. The material of the first sublayer in this invention includes M, and the material of the second sublayer corresponds to M. x Te 1-x M is one of B and Si. The M in the first sublayer (including one of B and Si) has weak conductivity at room temperature, resulting in a low turn-off current for the threshold selector. When the device is turned on, the threshold selector material is at a higher temperature. At this temperature, the conductivity of M increases, effectively increasing the drive current. Furthermore, M and M... x Te 1-x After the heterojunction is formed, M has high thermal stability, which can suppress the diffusion of M in the second sublayer due to high temperature or M that has diffused into the second sublayer after multiple operations in the direction perpendicular to the heterojunction material layer. This compresses the material from three-dimensional threshold transition characteristics to two-dimensional, thereby reducing the generation of voids and improving the device's cycle performance and reliability.

[0112] It should be understood that the application of the present invention is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A heterojunction threshold selector, characterized in that, It includes a substrate, and a first electrode layer, a heterojunction material layer and a second electrode layer sequentially stacked on the substrate; The heterojunction material layer includes n+1 first sublayers and n second sublayers, which are alternately stacked. The first first sublayer is attached to the first electrode layer, and the (n+1)th first sublayer is attached to the second electrode layer; where n is a positive integer. The material of the first sublayer is M, and the material of the second sublayer is M. x Te 1-x Where M is one of B and Si, 0 <x≤0.5; The thickness of the first sublayer is 0.5~2 nm, and the thickness of the second sublayer is 4~6 nm; The thickness of the heterojunction material layer is less than or equal to 50 nm.

2. The heterojunction threshold selector according to claim 1, characterized in that, n can be 1 to 11.

3. The heterojunction threshold selector according to claim 1, characterized in that, The materials of the first electrode layer and the second electrode layer are each independently one of an inert metal or an alloy containing an inert metal nitride.

4. The heterojunction threshold selector according to claim 3, characterized in that, The inert metal includes at least one of W, Pt, Au, Ti, Al, Ag, Cu, and Ni; the alloy containing the inert metal nitride is an alloy containing at least one of the following: W nitride, Pt nitride, Au nitride, Ti nitride, Al nitride, Ag nitride, Cu nitride, and Ni nitride.

5. A method for fabricating a heterojunction threshold selector, characterized in that, Including the following steps: Provide substrate; A first electrode layer is formed on the substrate; A heterojunction material layer is formed on the first electrode layer; A second electrode layer is formed on the heterojunction material layer; The heterojunction material layer comprises n+1 first sublayers and n second sublayers, which are alternately stacked. The first first sublayer is attached to the first electrode layer, and the (n+1)th first sublayer is attached to the second electrode layer; where n is a positive integer. The material of the first sublayer is M, and the material of the second sublayer is M. x Te 1-x Where M is one of B and Si, 0 <x≤0.5; The thickness of the first sublayer is 0.5~2 nm, and the thickness of the second sublayer is 4~6 nm; The thickness of the heterojunction material layer is less than or equal to 50 nm.

6. The preparation method according to claim 5, characterized in that, A first electrode layer is formed on the substrate by one of physical vapor deposition and chemical vapor deposition, wherein the physical vapor deposition method is sputtering, evaporation or molecular beam epitaxy, and the chemical vapor deposition method is plasma-enhanced chemical vapor deposition, atomic layer deposition, atomic vapor deposition or metal compound vapor deposition. And / or, a second electrode layer is formed on the heterojunction material layer by one of physical vapor deposition and chemical vapor deposition, wherein the physical vapor deposition method is sputtering, evaporation or molecular beam epitaxy, and the chemical vapor deposition method is plasma-enhanced chemical vapor deposition, atomic layer deposition, atomic vapor deposition or metal compound vapor deposition.

7. The preparation method according to claim 5, characterized in that, The step of forming a heterojunction material layer on the first electrode layer specifically includes: n+1 first sublayers and n second sublayers are sequentially and alternately deposited on the first electrode layer.

8. The preparation method according to claim 7, characterized in that, The deposition method includes one of physical vapor deposition and chemical vapor deposition. The physical vapor deposition method is sputtering, evaporation or molecular beam epitaxy. The chemical vapor deposition method is plasma-enhanced chemical vapor deposition, atomic layer deposition, atomic vapor deposition or metal compound vapor deposition.

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