Row drive signal enhancement circuit, shift register unit, display panel

Abstract

A horizontal drive signal enhancement circuit (100), a shift register unit, and a display panel belong to the field of display technology. The horizontal drive signal enhancement circuit (100) includes a control unit (110), an inverting unit (120), a first output unit (130), and a second output unit (140). The control unit (110) has a first external control terminal (IN1) and a second external control terminal (IN2) respectively loaded with two inverted signals, and the input terminal is electrically connected to a first power supply lead; the first output unit (130) and the second output unit (140) each have two input terminals, and the two input terminals are electrically connected to the first power supply lead and the second power supply lead respectively; the output terminal of the control unit (110) is electrically connected to the control terminal of the first output unit (130) and / or the control terminal of the second output unit (140); one of the control terminals of the first output unit (130) and the second output unit (140) is electrically connected to the output terminal of the control unit (110) through the inverting unit (120). The horizontal drive signal enhancement circuit (100) can improve the driving capability of the scanning signal.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a line drive signal enhancement circuit, a shift register unit, and a display panel. Background Technology

[0002] In a display panel, a scan signal is applied to the pixel driving circuit via the gate lead. Due to the load and impedance on the gate lead, a certain delay and voltage drop often occur when the scan signal reaches the pixel driving circuit. In silicon-based OLED (organic light-emitting diode) displays, due to the large pixel resolution, the delay and voltage drop of the scan signal on the gate lead are significant. This results in different data voltages written by different pixel driving circuits, thereby reducing the display uniformity of the silicon-based OLED display.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] This disclosure provides a line drive signal enhancement circuit, a shift register unit, and a display panel to improve the driving capability of the scan signal.

[0005] To achieve the above-mentioned objectives, the present disclosure adopts the following technical solution: According to one aspect of this disclosure, a line drive signal enhancement circuit is provided, including a control unit, an inverting unit, a first output unit, and a second output unit; The control unit has a first external control terminal, a second external control terminal, an input terminal, and an output terminal. The input terminal of the control unit is electrically connected to a first power supply lead. The first external control terminal and the second external control terminal are used to load two inverted signals, respectively. The first output unit has a control terminal, a first total output terminal and two input terminals, and the two input terminals are electrically connected to the first power supply lead and the second power supply lead, respectively. The second output unit has a control terminal, a second total output terminal, and two input terminals, the two input terminals being electrically connected to the first power lead and the second power lead, respectively; The output terminal of the control unit is electrically connected to the control terminal of the first output unit, and / or the output terminal of the control unit is electrically connected to the control terminal of the second output unit; one of the control terminals of the first output unit and the second output unit is electrically connected to the output terminal of the control unit through the inverting unit; The input terminal of the control unit is electrically connected to the first power lead through at least two conductive materials.

[0006] According to one embodiment of this disclosure, the first power lead is used to apply a first power supply voltage; the second power lead is used to apply a second power supply voltage. The control unit is used to output the first power supply voltage to the first node or the second node under the control of the first external control terminal and the second external control terminal; The inverting unit is connected to the first node and the second node, and is used to output the second power supply voltage to the second node in response to the first power supply voltage applied to the first node, and to output the second power supply voltage to the first node in response to the first power supply voltage applied to the second node. The first output unit is connected to the first node and is used to output one of the first power supply voltage and the second power supply voltage to the first total output terminal under the control of the first node; The second output unit is connected to the second node and is used to output the other of the first power supply voltage and the second power supply voltage to the second total output terminal under the control of the second node.

[0007] According to one embodiment of this disclosure, the control unit includes: The first transistor has an input terminal loaded with the first power supply voltage, an output terminal connected to the first node, and a control terminal serving as the first external control terminal; the first transistor is used to output the first power supply voltage to the first node under the control of the control terminal of the first transistor. The second transistor has an input terminal loaded with the first power supply voltage, an output terminal connected to the second node, and a control terminal serving as the second external control terminal; the second transistor is used to output the first power supply voltage to the second node under the control of the control terminal of the second transistor. Both the first transistor and the second transistor are either N-type transistors or both are P-type transistors.

[0008] According to one embodiment of this disclosure, the inverting unit includes: The third transistor has a control terminal connected to the first node, an input terminal loaded with the second power supply voltage, and an output terminal connected to the second node; the third transistor is used to output the second power supply voltage to the second node under the control of the first power supply voltage loaded on the first node. The fourth transistor has a control terminal connected to the second node, an input terminal loaded with the second power supply voltage, and an output terminal connected to the first node; the fourth transistor is used to output the second power supply voltage to the first node under the control of the first power supply voltage loaded on the second node.

[0009] According to one embodiment of this disclosure, the first output unit includes: The fifth transistor has a control terminal connected to the first node, an input terminal loaded with the first power supply voltage, and an output terminal connected to the first total output terminal. The sixth transistor has a control terminal connected to the first node, an input terminal loaded with the second power supply voltage, and an output terminal connected to the first total output terminal; The second output unit includes: The seventh transistor has a control terminal connected to the second node, an input terminal loaded with the first power supply voltage, and an output terminal connected to the second total output terminal; The eighth transistor has a control terminal connected to the second node, an input terminal loaded with the second power supply voltage, and an output terminal connected to the second total output terminal; Wherein, the first terminal of the fifth transistor and the first terminal of the seventh transistor are used to load the first power supply voltage, and the first terminal of the sixth transistor and the first terminal of the eighth transistor are used to load the second power supply voltage; The fifth transistor and the seventh transistor are of the same type, the sixth transistor and the eighth transistor are of the same type, and the fifth transistor and the sixth transistor are of different types.

[0010] According to one aspect of this disclosure, a shift register unit is provided, including a shift register, an inverter, and the above-described row drive signal enhancement circuit; The shift register is used to output the initial scan signal to the input of the inverter and the first master control terminal of the row drive signal enhancement circuit; the output of the inverter is connected to the second master control terminal of the row drive signal enhancement circuit.

[0011] According to one aspect of this disclosure, a display panel is provided, including the shift register unit described above; wherein the display panel includes a display area and a peripheral area surrounding the display area, the shift register unit being located in the peripheral area; and the row drive signal enhancement circuit being located between the shift register and the display area.

[0012] According to one embodiment of this disclosure, the line drive signal enhancement circuit includes a first transistor to an eighth transistor; the first transistor, the second transistor, the fifth transistor, and the seventh transistor are N-type transistors; the third transistor, the fourth transistor, the sixth transistor, and the eighth transistor are P-type transistors.

[0013] According to one embodiment of the present disclosure, the peripheral region includes at least one row drive signal enhancement region provided with the first transistor to the eighth transistor; The row drive signal enhancement region includes a P-type substrate region and an N-type substrate region. The P-type substrate region is located on the side of the N-type substrate region away from the display area. The N-type transistor is formed in the P-type substrate region, and the P-type transistor is formed in the N-type substrate region.

[0014] According to one embodiment of the present disclosure, the display panel includes a semiconductor substrate; the semiconductor substrate has active regions of the first transistor to the eighth transistor formed thereon; The P-type substrate region includes a P-type auxiliary doped region and a first active region, a second active region, a fifth active region, and a seventh active region that are isolated from each other. The first active region and the fifth active region are arranged along a first direction, and the second active region and the seventh active region are arranged along the first direction; the first direction is parallel to the plane where the semiconductor substrate is located and perpendicular to the edge of the display area near the shift register unit; The fifth active region and the seventh active region are arranged along the second direction, and the first active region and the second active region are arranged along the second direction; the second direction is parallel to the plane of the semiconductor substrate and perpendicular to the first direction; The fifth active region and the seventh active region are respectively surrounded by the P-type auxiliary doped region; the first active region and the second active region are located on the side of the fifth active region and the seventh active region away from the display area; the first active region and the second active region are together surrounded by the P-type auxiliary doped region; The first transistor is located in the first active region, the second transistor is located in the second active region, the fifth transistor is located in the fifth active region, and the seventh transistor is located in the seventh active region.

[0015] According to one embodiment of this disclosure, the N-type substrate region includes an N-type auxiliary doped region and mutually isolated third, sixth, and eighth active regions; The sixth active region and the eighth active region are arranged along the second direction, and the N-type auxiliary doped region is surrounded by the sixth active region and the eighth active region, respectively; the third active region is located on the side of the sixth active region and the eighth active region away from the display area, and the N-type auxiliary doped region is surrounded by the third active region. The third transistor and the fourth transistor are located in the third active region, the sixth transistor is located in the sixth active region, and the eighth transistor is formed in the eighth active region.

[0016] According to one embodiment of the present disclosure, the active region of any one of the transistors includes a channel region, a source electrode and a drain electrode on both sides of the channel region; In the row drive signal enhancement region, the channel region of the transistor, the source of the transistor, and the drain of the transistor all extend in the direction toward the display area.

[0017] According to one embodiment of the present disclosure, the display panel further includes a gate insulating layer and a gate layer sequentially stacked on the semiconductor substrate; In the row drive signal enhancement region, the gate layer includes the gates of each of the transistors, and the gate of any one of the transistors includes an interconnected gate region and a lead region; the orthogonal projection of the gate region of any one of the transistors onto the semiconductor substrate overlaps with the channel region of the transistor.

[0018] According to one embodiment of the present disclosure, the display panel further includes a first dielectric layer and a first metal wiring layer sequentially stacked on the side of the gate layer away from the semiconductor substrate; In the row drive signal enhancement region, a first conductive pillar is provided in the first dielectric layer, which penetrates the first dielectric layer and is connected to the lead region of the gate of each transistor, and a second conductive pillar is provided, which penetrates the first dielectric layer and the gate insulating layer and is connected to the semiconductor substrate. In the row drive signal enhancement region, the first metal wiring layer includes a first connection lead to a third connection lead, and gate connection lines, source connection lines, and drain connection lines corresponding to the first transistor to the eighth transistor; any one of the drain connection lines includes a drain region and a connection region that are interconnected. In the row drive signal enhancement region, the gate connection line corresponding to any one of the transistors is electrically connected to the lead area of ​​the gate of the transistor through the first conductive post; the source connection line corresponding to any one of the transistors is connected to the source of the transistor through the second conductive post; the drain area of ​​the drain connection line corresponding to any one of the transistors is connected to the drain of the transistor through the second conductive post. Specifically, the source connection lines corresponding to the first transistor and the second transistor are connected to the first connection lead; the source connection lines corresponding to the fifth transistor and the seventh transistor are connected to the second connection lead; the source connection lines corresponding to the sixth transistor and the eighth transistor are connected to the third connection lead; the connection region of the drain connection line corresponding to the third transistor is connected to the gate connection line corresponding to the fourth transistor; and the connection region of the drain connection line corresponding to the fourth transistor is connected to the gate connection line corresponding to the third transistor.

[0019] According to one embodiment of this disclosure, in the row drive signal enhancement region, the first metal wiring layer further includes a fourth to a sixth, a sixteenth, and a seventeenth connection lead; the sixteenth connection lead is disposed along the routing direction of the P-type auxiliary doped region and is connected to the P-type auxiliary doped region through the second conductive post; the seventeenth connection lead is disposed along the routing direction of the N-type auxiliary doped region and is connected to the N-type auxiliary doped region through the second conductive post; the first connection lead extends along the second direction and is connected to the sixteenth connection lead at both ends; the second connection lead extends along the second direction and is connected to the sixteenth connection lead at both ends; the third connection lead extends along the second direction and is connected to the seventeenth connection lead at both ends; the fourth connection lead is connected to the gate connection line corresponding to the fifth transistor and extends along the second direction; the fifth connection lead is located between the P-type substrate region and the N-type substrate region and extends along the second direction; the sixth connection lead is connected to the connection region of the drain connection line corresponding to the fourth transistor and extends along the second direction.

[0020] According to one embodiment of the present disclosure, the display panel further includes a second dielectric layer and a second metal wiring layer sequentially stacked on the side of the first metal wiring layer away from the semiconductor substrate; The second dielectric layer is provided with a third conductive post that penetrates the second dielectric layer and is connected to the first metal wiring layer; the second metal wiring layer is connected to the first metal wiring layer through the third conductive post. In the row drive signal enhancement region, the second metal wiring layer includes a seventh to thirteenth connection lead, a first power supply lead, a second power supply lead, a first control lead, a second control lead, a first output lead, and a second output lead, and each lead extends along the first direction; the first control lead is connected to the gate connection line corresponding to the first transistor; the second control lead is connected to the gate connection line corresponding to the second transistor; the first power supply lead is connected to the first connection lead and the second connection lead; the second power supply lead is connected to the third connection lead; the seventh connection lead is connected to the connection area of ​​the drain connection line corresponding to the first transistor and the gate connection line corresponding to the fifth transistor; the eighth connection lead is connected to the connection area of ​​the drain connection line corresponding to the second transistor, the gate connection line corresponding to the fourth transistor, the gate connection line corresponding to the seventh transistor, and the eighth transistor. The gate connection lines corresponding to the transistors are connected; the ninth connection line is connected to the end of the fourth connection line away from the gate connection line corresponding to the fifth transistor, and to the gate connection line corresponding to the third transistor; the tenth connection line is connected to the connection area of ​​the drain connection line corresponding to the seventh transistor, and to the fifth connection line; the eleventh connection line is connected to the gate connection line corresponding to the sixth transistor, and to the end of the sixth connection line away from the gate connection line corresponding to the third transistor; the twelfth connection line is connected to the source connection line corresponding to the third transistor, and to the source connection line corresponding to the fourth transistor; the thirteenth connection line is connected to the connection area of ​​the drain connection line corresponding to the eighth transistor; the first output line is connected to the connection area of ​​the drain connection line corresponding to the fifth transistor, and to the connection area of ​​the drain connection line corresponding to the sixth transistor; the second output line is connected to the sixth connection line.

[0021] According to one embodiment of the present disclosure, the display panel further includes a third dielectric layer and a third metal wiring layer sequentially stacked on the side of the second metal wiring layer away from the semiconductor substrate; In the row drive signal enhancement region, the third dielectric layer is provided with a fourth conductive post that penetrates the third dielectric layer and is connected to the second metal wiring layer; the third metal wiring layer is connected to the second metal wiring layer through the fourth conductive post; the third metal wiring layer includes a fourteenth connection lead and a fifteenth connection lead; the fourteenth connection lead is connected to the second power supply lead and the twelfth connection lead; the fifteenth connection lead is connected to the thirteenth connection lead and the second output lead.

[0022] According to one embodiment of this disclosure, in the row drive signal enhancement region, the second metal wiring layer further includes an eighteenth connection lead extending along the first direction and a nineteenth connection lead extending along the first direction; the third metal wiring layer further includes a twentieth connection lead; the eighteenth connection lead is connected to the sixteenth connection lead and the twentieth connection lead; the nineteenth connection lead is connected to the seventeenth connection lead and the fourteenth connection lead; the orthographic projection of the twentieth connection lead on the semiconductor substrate covers the channel regions of the first transistor, the second transistor, the fifth transistor, and the seventh transistor; the orthographic projection of the fourteenth connection lead on the semiconductor substrate covers the channel regions of the third transistor, the fourth transistor, the sixth transistor, and the eighth transistor.

[0023] According to one embodiment of this disclosure, in the row drive signal enhancement region, the first power lead and the first connection lead are connected by an array of third conductive pillars; the first power lead and the second connection lead are connected by an array of third conductive pillars; the first power lead and the twelfth connection lead are connected by at least one group of fourth conductive pillars, and the at least one group of fourth conductive pillars includes an array of fourth conductive pillars; the second power lead and the third connection lead are connected by an array of third conductive pillars; the second power lead and the fourteenth connection lead are connected by an array of fourth conductive pillars.

[0024] According to one embodiment of this disclosure, the source of the third transistor and the source of the fourth transistor coincide; the source connection line of the third transistor and the source connection line of the fourth transistor are multiplexed as the same lead.

[0025] According to one embodiment of this disclosure, in the row drive signal enhancement region, the N-type substrate region further includes a fourth active region; the fourth active region and the third active region are arranged along the second direction; the third active region and the eighth active region are arranged along the first direction, and the fourth active region and the sixth active region are arranged along the first direction; the display panel has an auxiliary transistor disposed in the fourth active region; The active region of the auxiliary transistor is located in the fourth active region, the gate of the auxiliary transistor is located in the gate layer, the source connection line corresponding to the auxiliary transistor is located in the first metal wiring layer and connected to the source of the auxiliary transistor, the drain connection line corresponding to the auxiliary transistor is located in the first metal wiring layer and connected to the drain of the auxiliary transistor, and the gate connection line corresponding to the auxiliary transistor is located in the first metal wiring layer and connected to the gate of the auxiliary transistor; the source connection line, drain connection line and gate connection line corresponding to the auxiliary transistor are connected to the seventeenth connection lead.

[0026] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.

[0027] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0028] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0029] Figure 1 This is a schematic diagram of the structure of a line drive signal enhancement circuit according to one embodiment of the present disclosure.

[0030] Figure 2 This is a schematic diagram of the structure of a line drive signal enhancement circuit according to one embodiment of the present disclosure.

[0031] Figure 3 This is a timing diagram of the signals applied to the two control terminals of the horizontal drive signal enhancement circuit in one embodiment of this disclosure.

[0032] Figure 4 This is a schematic diagram of the structure of a display panel in one embodiment of the present disclosure.

[0033] Figure 5 This is a schematic diagram of the structure of a semiconductor substrate in one embodiment of the present disclosure.

[0034] Figure 6 This is a schematic diagram of a semiconductor substrate doped with N to form an N-well in one embodiment of the present disclosure.

[0035] Figure 7 This is a schematic diagram of the gate layer structure in one embodiment of the present disclosure.

[0036] Figure 8 This is a schematic diagram of an N-doped structure in one embodiment of the present disclosure.

[0037] Figure 9 This is a schematic diagram showing the location of the N-doped region on a semiconductor substrate in one embodiment of this disclosure.

[0038] Figure 10 This is a schematic diagram of a structure with P doping in one embodiment of the present disclosure.

[0039] Figure 11 This is a schematic diagram showing the location of the P-doped region on a semiconductor substrate in one embodiment of this disclosure.

[0040] Figure 12 This is a schematic diagram showing the positions of each crystal in the updrive signal enhancement region according to one embodiment of this disclosure.

[0041] Figure 13 This is a schematic diagram showing the positions of each first conductive post in one embodiment of this disclosure.

[0042] Figure 14 This is a schematic diagram showing the positional relationship between each first conductive post and each transistor in one embodiment of this disclosure.

[0043] Figure 15 This is a schematic diagram of the structure of the first metal wiring layer in one embodiment of this disclosure.

[0044] Figure 16 This is a schematic diagram showing the positions of the first metal wiring layer and each transistor in one embodiment of this disclosure.

[0045] Figure 17 This is a schematic diagram showing the positions of each of the second conductive pillars in one embodiment of this disclosure.

[0046] Figure 18 This is a schematic diagram showing the positional relationship between each second conductive post and each transistor in one embodiment of this disclosure.

[0047] Figure 19 This is a schematic diagram of the structure of the second metal wiring layer in one embodiment of this disclosure.

[0048] Figure 20 This is a schematic diagram showing the positions of the second metal wiring layer and each transistor in one embodiment of this disclosure.

[0049] Figure 21 This is a schematic diagram of the structure of the third metal wiring layer in one embodiment of this disclosure.

[0050] Figure 22 This is a schematic diagram showing the positions of the third metal wiring layer and each transistor in one embodiment of this disclosure.

[0051] Figure 23 for Figure 22 A schematic diagram of the structure cut along the MM' direction.

[0052] The reference numerals used in the accompanying drawings mainly include: 100. Horizontal drive signal enhancement circuit; 110. Control unit; IN1. First total control terminal; IN2. Second total control terminal; 120. Inverting unit; 130. First output unit; OUT1. First total output terminal; 140. Second output unit; OUT2. Second total output terminal; A. First node; B. Second node; M1. First transistor; M2. Second transistor; M3. Third transistor; M4. Fourth transistor; M5. Fifth transistor; M6. Sixth transistor; M7. Seventh transistor; M8. Eighth transistor; 210. Shift register; 220. Inverter; 300. Pixel driving circuit; 310. Data writing unit; M01. First switching transistor; M02. Second switching transistor; Cst, storage capacitor; M03, driving transistor; F, third node; 400, semiconductor substrate; 401, first region; 402, second region; 410, P-type substrate region; 411, P-type auxiliary doped region; 420, N-type substrate region; 421, N-type auxiliary doped region; 431, first active region; 432, second active region; 433, third active region; 434, fourth active region; 435, fifth active region; 436, sixth active region; 437, seventh active region; 438, eighth active region; 4411, source of the first transistor; 4412, drain of the first transistor; 4413, channel region of the first transistor; 4414, gate of the first transistor; 4421, source of the second transistor; 4 422. Drain of the second transistor; 4423. Channel region of the second transistor; 4424. Gate of the second transistor; 4431. Source of the third transistor; 4432. Drain of the third transistor; 4433. Channel region of the third transistor; 4434. Gate of the third transistor; 4441. Source of the fourth transistor; 4442. Drain of the fourth transistor; 4443. Channel region of the fourth transistor; 4444. Gate of the fourth transistor; 4451. Source of the fifth transistor; 4452. Drain of the fifth transistor; 4453. Channel region of the fifth transistor; 4454. Gate of the fifth transistor; 4461. Source of the sixth transistor; 4462. Drain of the sixth transistor; 4463. Sixth transistor 4464. Channel region of the transistor; 4471. Gate of the sixth transistor; 4472. Source of the seventh transistor; 4473. Drain of the seventh transistor; 4474. Channel region of the seventh transistor; 4475. Gate of the seventh transistor; 4481. Source of the eighth transistor; 4482. Drain of the eighth transistor; 4483. Channel region of the eighth transistor; 4484. Gate of the eighth transistor; 510. Gate insulating layer; 520. Gate layer; 530. Insulating dielectric layer; 531. First dielectric layer; 5311. First conductive pillar; 532. Second dielectric layer; 5321. Second conductive pillar; 533. Third dielectric layer; 5331. Third conductive pillar; 540. Metal wiring layer; 541. First metal wiring layer;542. Second metal wiring layer; 543. Third metal wiring layer; 6011. First power supply lead; 6012. Second power supply lead; 6021. First control lead; 6022. Second control lead; 6031. First output lead; 6032. Second output lead; 611. Source connection line corresponding to the first transistor; 612. Drain connection line corresponding to the first transistor; 613. Gate connection line corresponding to the first transistor; 621. Source connection line corresponding to the second transistor; 622. Drain connection line corresponding to the second transistor; 623. Gate connection line corresponding to the second transistor. Wiring; 631, Source connection line corresponding to the third transistor; 632, Drain connection line corresponding to the third transistor; 633, Gate connection line corresponding to the third transistor; 641, Source connection line corresponding to the fourth transistor; 642, Drain connection line corresponding to the fourth transistor; 643, Gate connection line corresponding to the fourth transistor; 651, Source connection line corresponding to the fifth transistor; 652, Drain connection line corresponding to the fifth transistor; 653, Gate connection line corresponding to the fifth transistor; 661, Source connection line corresponding to the sixth transistor; 662, Drain connection line corresponding to the sixth transistor; 671. Source connection line corresponding to the seventh transistor; 672. Drain connection line corresponding to the seventh transistor; 673. Gate connection line corresponding to the seventh transistor; 681. Source connection line corresponding to the eighth transistor; 682. Drain connection line corresponding to the eighth transistor; 683. Gate connection line corresponding to the eighth transistor; 701. First connection lead; 702. Second connection lead; 703. Third connection lead; 704. Fourth connection lead; 705. Fifth connection lead; 706. Sixth connection lead; 707. Seventh Connecting leads; 708, Eighth connecting lead; 709, Ninth connecting lead; 710, Tenth connecting lead; 711, Eleventh connecting lead; 712, Twelfth connecting lead; 713, Thirteenth connecting lead; 714, Fourteenth connecting lead; 715, Fifteenth connecting lead; 716, Sixteenth connecting lead; 717, Seventeenth connecting lead; 718, Eighteenth connecting lead; 719, Nineteenth connecting lead; 720, Twentieth connecting lead; C, Display area; D, Peripheral area; E, Horizontal drive signal enhancement area. Detailed Implementation

[0053] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this disclosure more comprehensive and complete, and to fully convey the concept of the example embodiments to those skilled in the art. The described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a full understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced with one or more of the specific details omitted, or other methods, components, apparatus, steps, etc., can be employed. In other instances, well-known technical solutions are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0054] Furthermore, the accompanying drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0055] The terms “a,” “one,” “the,” and “the” are used to indicate the existence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first” and “second” are used only as markers and are not a limitation on the number of objects.

[0056] See Figure 1 This disclosure provides a line drive signal enhancement circuit 100, including a control unit 110, an inverting unit 120, a first output unit 130, and a second output unit 140; The control unit 110 has a first external control terminal IN1, a second external control terminal IN2, an input terminal, and an output terminal. The input terminal of the control unit is electrically connected to a first power supply lead. The first external control terminal IN1 and the second external control terminal IN2 are used to load two inverted signals respectively. The first output unit 130 has a control terminal, a first total output terminal OUT1 and two input terminals, which are electrically connected to the first power supply lead and the second power supply lead, respectively. The second output unit 140 has a control terminal, a second total output terminal OUT2, and two input terminals, which are electrically connected to the first power lead and the second power lead, respectively. The output terminal of the control unit 110 is electrically connected to the control terminal of the first output unit 130, and / or the output terminal of the control unit 110 is electrically connected to the control terminal of the second output unit 140; one of the control terminals of the first output unit 130 and the second output unit 140 is electrically connected to the output terminal of the control unit 110 through the inverting unit 120. The input terminal of the control unit 110 is electrically connected to the first power supply lead through at least two conductive materials.

[0057] In some implementations, the first power lead is used to apply a first power supply voltage; the second power lead is used to apply a second power supply voltage. See also Figure 1 The control unit 110 has two output terminals, which are respectively connected to the first node and the second node. In this embodiment: The control unit 110 has a first general control terminal IN1 and a second general control terminal IN2, and is used to output a first power supply voltage V1 to the first node A or the second node B under the control of the first general control terminal IN1 and the second general control terminal IN2. The inverting unit 120 is connected to the first node A and the second node B, and is used to output the second power supply voltage V2 to the second node B in response to the first power supply voltage V1 applied to the first node A, and to output the second power supply voltage V2 to the first node A in response to the first power supply voltage V1 applied to the second node B. The first output unit 130 is connected to the first node A and the first total output terminal OUT1, and is used to output one of the first power supply voltage V1 and the second power supply voltage V2 to the first total output terminal OUT1 under the control of the first node A. The second output unit 140 is connected to the second node B and the second total output terminal OUT2, and is used to output the other of the first power supply voltage V1 and the second power supply voltage V2 to the second total output terminal OUT2 under the control of the second node B.

[0058] See Figure 4The line drive signal enhancement circuit 100 provided in this disclosure can form a shift register unit with a shift register 210 and an inverter 220. The shift register 210 outputs an initial scan signal (i.e., a first initial scan signal) to the input of the inverter 220 and the first general control terminal IN1 of the line drive signal enhancement circuit 100. The output of the inverter 220 is connected to the second general control terminal IN2 of the line drive signal enhancement circuit 100 to generate a second initial scan signal that is opposite to the first initial scan signal. Thus, the shift register 210 and the inverter 220 can input two opposite initial scan signals (a first initial scan signal and a second initial scan signal) to the two control terminals (the first general control terminal IN1 and the second general control terminal IN2) of the control unit 110 of the line drive signal enhancement circuit 100, respectively. The row drive signal enhancement circuit 100 can, based on two opposite initial scan signals loaded on the first total control terminal IN1 and the second total control terminal IN2, cause the first output unit 130 and the second output unit 140 to output two different power supply voltages (first power supply voltage V1 and second power supply voltage V2) as scan signals for the display panel, that is, output scan signals formed by the first power supply voltage V1 and the second power supply voltage V2. The scan signals formed by these two power supply voltages can replace the initial scan signals generated by the shift register 210 and the inverter 220 to control the data writing unit 310 of the pixel drive circuit 300.

[0059] Therefore, the line drive signal enhancement circuit 100 provided in this disclosure can transform the initial scan signal with weak driving capability into a scan signal with stronger driving capability formed by the power supply voltage. This can overcome the problem of large delay and voltage loss when the initial scan signal arrives at the pixel drive circuit 300, and can improve the display uniformity of the display panel, especially the display uniformity of silicon-based OLED displays.

[0060] The structure, principle, and effect of the line drive signal enhancement circuit 100 of this disclosure will be further explained and illustrated below with reference to the accompanying drawings.

[0061] The horizontal drive signal enhancement circuit 100 disclosed herein is used to improve the horizontal drive capability of a display panel, particularly for silicon-based OLED displays. This horizontal drive signal enhancement circuit 100 can generate two scan signals based on two initial scan signals of the display panel. These two scan signals have different power supply voltages, resulting in a smaller voltage drop during transmission on the scan leads and a greater signal transmission capability to meet the needs of various loads on the scan leads, thus reducing the turn-on delay of each data writing unit 310. Therefore, the scan signals generated by this horizontal drive signal enhancement circuit 100 have stronger driving capability.

[0062] Optionally, in the line drive signal enhancement circuit 100, the first output unit 130 further includes a first input terminal and a second input terminal. The first input terminal of the first output unit 130 is electrically connected to the first power supply lead, and the second input terminal of the first output unit 130 is electrically connected to the second power supply lead. Thus, the first output unit 130 can directly output either the applied first power supply voltage V1 or the second power supply voltage V2 to the first total output terminal OUT1, without needing to generate the first power supply voltage V1 and the second power supply voltage V2 through voltage regulation. This ensures that the signal output from the first total output terminal OUT1 is not only the first power supply voltage V1 or the second power supply voltage V2 in terms of voltage, but also that the scan signal output from the first total output terminal OUT1 has stronger driving capability, meeting the needs of each load on each scan lead.

[0063] The second output unit 140 also includes a first input terminal and a second input terminal. The first input terminal of the second output unit 140 is electrically connected to the first power supply lead, and the second input terminal of the second output unit 140 is electrically connected to the second power supply lead. Thus, the second output unit 140 can directly output either the applied first power supply voltage V1 or the second power supply voltage V2 to the second total output terminal OUT2, without needing to generate the first power supply voltage V1 and the second power supply voltage V2 through voltage regulation. This ensures that the signal output from the second total output terminal OUT2 is not only the first power supply voltage V1 or the second power supply voltage V2 in terms of voltage, but also that the scanning signal output from the second total output terminal OUT2 has stronger driving capability, meeting the needs of each load on each scanning lead.

[0064] Optionally, the inverting unit 120 may have a maximum of two transistors. In this way, the number of transistors in the horizontal drive signal enhancement circuit 100 can be reduced while ensuring the functionality of the horizontal drive signal enhancement circuit 100, thereby reducing the power consumption and area ratio of the horizontal drive signal enhancement circuit 100, and consequently reducing the power consumption and size of the display panel.

[0065] Optionally, see Figure 2 The control unit 110 includes: The first transistor M1 has an input terminal loaded with a first power supply voltage V1 (electrically connected to a first power supply lead), an output terminal connected to the first node A, and a control terminal serving as a first overall control terminal IN1; the first transistor M1 is used to output the first power supply voltage V1 to the first node A under the control of the control terminal of the first transistor M1. The second transistor M2 has an input terminal loaded with a first power supply voltage V1 (electrically connected to the first power supply lead), an output terminal connected to the second node B, and a control terminal serving as the second overall control terminal IN2; the second transistor M2 is used to output the first power supply voltage V1 to the second node B under the control of the control terminal of the second transistor M2. The first transistor M1 and the second transistor M2 are either both N-type transistors or both P-type transistors.

[0066] See Figure 3 When the row drive signal enhancement circuit 100 of this disclosure is in operation, the first total control terminal IN1 and the second total control terminal IN2 of the control unit 110 are respectively loaded with two opposite initial scan signals. Therefore, the control terminals of the first transistor M1 and the second transistor M2 are respectively loaded with two opposite initial scan signals. Since the first transistor M1 and the second transistor M2 are of the same type, both being N-type transistors or both being P-type transistors, this not only facilitates the fabrication of transistors, but also allows the first transistor M1 and the second transistor M2 to be selectively turned on, so that the control unit 110 selectively outputs the first power supply voltage V1 to the first node A or the second node B.

[0067] The following describes the operation of the control unit 110, taking the example that both the first transistor M1 and the second transistor M2 are N-type transistors, and taking the first initial scan signal output by the shift register unit as a high-level signal.

[0068] Figure 3 This is a timing diagram of the two initial scan signals applied to the first master control terminal IN1 and the second master control terminal IN2. (See also...) Figure 3 The first master control terminal IN1 is loaded with a low base voltage during stages T1 and T3, and with a high first initial scan signal during stage T2. The second master control terminal IN2 is loaded with a high base voltage during stages T1 and T3, and with a low second initial scan signal during stage T2. Therefore, the signals on the first master control terminal IN1 and the second master control terminal IN2 are opposite; when one is high, the other is low.

[0069] During stages T1 and T3, a low-level signal is applied to the first master control terminal IN1 and a high-level signal is applied to the second master control terminal IN2, causing the second transistor M2 to turn on and the first transistor M1 to turn off. The control unit 110 outputs the first power supply voltage V1 to the second node B. During stage T2, a high-level signal is applied to the first master control terminal IN1 and a low-level signal is applied to the second master control terminal IN2, causing the first transistor M1 to turn on and the second transistor M2 to turn off. The control unit 110 outputs the first power supply voltage V1 to the first node A.

[0070] Optionally, see Figure 2 The inverting unit 120 includes: The third transistor M3 has a control terminal connected to the first node A, an input terminal loaded with the second power supply voltage V2 (electrically connected to the second power supply lead), and an output terminal connected to the second node B; the third transistor M3 is used to output the second power supply voltage V2 to the second node B under the control of the first power supply voltage V1 loaded on the first node A. The fourth transistor M4 has a control terminal connected to the second node B, an input terminal loaded with the second power supply voltage V2 (electrically connected to the second power supply lead), and an output terminal connected to the first node A; the fourth transistor M4 is used to output the second power supply voltage V2 to the first node A under the control of the first power supply voltage V1 loaded on the second node B.

[0071] Furthermore, if the first power supply voltage V1 is lower than the second power supply voltage V2, then the third transistor M3 and the fourth transistor M4 are P-type transistors; or, if the first power supply voltage V1 is higher than the second power supply voltage V2, then the third transistor M3 and the fourth transistor M4 are N-type transistors. In other words, when the control terminals of the third transistor M3 and the fourth transistor M4 are supplied with the first power supply voltage V1, the third transistor M3 and the fourth transistor M4 can conduct; when the control terminals of the third transistor M3 and the fourth transistor M4 are supplied with the second power supply voltage V2, the third transistor M3 and the fourth transistor M4 can be turned off.

[0072] The following explanation illustrates the operation of the inverting unit 120, assuming that the first power supply voltage V1 is lower than the second power supply voltage V2, and that the third transistor M3 and the fourth transistor M4 are P-type transistors. When the control unit 110 applies the first power supply voltage V1 to the first node A, it does not apply voltage to the second node B. Under the control of the first node A, the third transistor M3 conducts and outputs the second power supply voltage V2 to the second node B. Thus, the first power supply voltage V1 is applied to the first node A, and the second power supply voltage V2 is applied to the second node B. Conversely, when the control unit 110 applies the first power supply voltage V1 to the second node B, it does not apply voltage to the first node A. Under the control of the second node B, the third transistor M3 conducts and outputs the second power supply voltage V2 to the first node A. Thus, the first power supply voltage V1 is applied to the second node B, and the second power supply voltage V2 is applied to the first node A. Therefore, regardless of the operating state of the control unit 110 and the inverting unit 120, two different power supply voltages are applied to the first node A and the second node B.

[0073] Similarly, when the first power supply voltage V1 is higher than the second power supply voltage V2, and the third transistor M3 and the fourth transistor M4 are N-type transistors, it is also possible to apply two different power supply voltages to the first node A and the second node B. The principle and process of this disclosure will not be described in detail here.

[0074] Optionally, see Figure 2 The first output unit 130 includes: The fifth transistor M5 has a control terminal connected to the first node A, an input terminal loaded with the first power supply voltage V1 (electrically connected to the first power supply lead), and an output terminal connected to the first total output terminal OUT1. The sixth transistor M6 has a control terminal connected to the first node A, an input terminal loaded with the second power supply voltage V2 (electrically connected to the second power supply lead), and an output terminal connected to the first total output terminal OUT1; One of the fifth transistor M5 and the sixth transistor M6 is an N-type transistor, and the other is a P-type transistor. In other words, one of the fifth transistor M5 and the sixth transistor M6 can be turned on in response to the first power supply voltage V1 applied to the control terminal, and turned off in response to the second power supply voltage V2 applied to the control terminal; the other of the fifth transistor M5 and the sixth transistor M6 can be turned off in response to the first power supply voltage V1 applied to the control terminal, and turned on in response to the second power supply voltage V2 applied to the control terminal.

[0075] In this disclosure, since the fifth transistor M5 and the sixth transistor M6 are of opposite types, the fifth transistor M5 and the sixth transistor M6 can be selectively turned on regardless of whether the first power supply voltage V1 or the second power supply voltage V2 is applied to the first total output terminal OUT1, so that the first power supply voltage V1 or the second power supply voltage V2 is applied to the first total output terminal OUT1.

[0076] Further, see Figure 2 The second output unit 140 includes: The seventh transistor M7 has a control terminal connected to the second node B, an input terminal loaded with the first power supply voltage V1 (electrically connected to the first power supply lead), and an output terminal connected to the second total output terminal OUT2. The eighth transistor M8 has a control terminal connected to the second node B, an input terminal loaded with the second power supply voltage V2 (electrically connected to the second power supply lead), and an output terminal connected to the second total output terminal OUT2.

[0077] Among them, the fifth transistor M5 and the seventh transistor M7 are either N-type transistors or P-type transistors, and the sixth transistor M6 and the eighth transistor M8 are either N-type transistors or P-type transistors.

[0078] Thus, one of the seventh transistor M7 and the eighth transistor M8 can be turned on in response to the first power supply voltage V1 applied to the control terminal and turned off in response to the second power supply voltage V2 applied to the control terminal; the other of the seventh transistor M7 and the eighth transistor M8 can be turned off in response to the first power supply voltage V1 applied to the control terminal and turned on in response to the second power supply voltage V2 applied to the control terminal. Since the seventh transistor M7 and the eighth transistor M8 are of opposite types, regardless of whether the second node B is supplied with the first power supply voltage V1 or the second power supply voltage V2, the seventh transistor M7 and the eighth transistor M8 can be selectively turned on, so that the second total output terminal OUT2 is supplied with either the first power supply voltage V1 or the second power supply voltage V2.

[0079] The fifth transistor M5 and the seventh transistor M7 are of the same type, meaning that both transistors M5 and M7 can turn on in response to the first power supply voltage V1 applied to the control terminal, or both can turn on in response to the second power supply voltage V2 applied to the control terminal. Since the power supply voltages at the first node A and the second node B are different—one is the first power supply voltage V1 and the other is the second power supply voltage V2—the first total output terminal OUT1 and the second total output terminal OUT2 output the first power supply voltage V1 and the second power supply voltage V2, respectively.

[0080] Optionally, the first transistor M1 to the eighth transistor M8 are MOS (Metal Oxide Semiconductor) transistors.

[0081] The following is an exemplary description of a line drive signal enhancement circuit 100 and its operation process, in order to further explain and illustrate the principle, structure and effect of the line drive signal enhancement circuit 100 of this disclosure.

[0082] See Figure 2 The exemplary line drive signal enhancement circuit 100 includes a control unit 110, an inverting unit 120, a first output unit 130, and a second output unit 140.

[0083] The control unit 110 includes a first transistor M1 and a second transistor M2; the first transistor M1 has an input terminal loaded with a first power supply voltage V1, an output terminal connected to the first node A, and a control terminal serving as a first overall control terminal IN1; the second transistor M2 has an input terminal loaded with the first power supply voltage V1, an output terminal connected to the second node B, and a control terminal serving as a second overall control terminal IN2. The inverting unit 120 includes a third transistor M3 and a fourth transistor M4; the third transistor M3 has a control terminal connected to the first node A, an input terminal loaded with a second power supply voltage V2, and an output terminal connected to the second node B; the fourth transistor M4 has a control terminal connected to the second node B, an input terminal loaded with the second power supply voltage V2, and an output terminal connected to the first node A.

[0084] The first output unit 130 includes a fifth transistor M5 and a sixth transistor M6. The fifth transistor M5 has a control terminal connected to the first node A, an input terminal loaded with a first power supply voltage V1, and an output terminal connected to the first total output terminal OUT1. The sixth transistor M6 has a control terminal connected to the first node A, an input terminal loaded with a second power supply voltage V2, and an output terminal connected to the first total output terminal OUT1. The second output unit 140 includes a seventh transistor M7 and an eighth transistor M8. The seventh transistor M7 has a control terminal connected to the second node B, an input terminal loaded with the first power supply voltage V1, and an output terminal connected to the second total output terminal OUT2. The eighth transistor M8 has a control terminal connected to the second node B, an input terminal loaded with the second power supply voltage V2, and an output terminal connected to the second total output terminal OUT2.

[0085] In this configuration, transistors M1, M2, M5, and M7 are N-type transistors; transistors M3, M4, M6, and M8 are P-type transistors. The first power supply voltage V1 is lower than the second power supply voltage V2. Any N-type transistor can turn on in response to the second power supply voltage V2 applied to its control terminal and can turn off in response to the first power supply voltage V1 applied to its control terminal. Any P-type transistor can turn on in response to the first power supply voltage V1 applied to its control terminal and can turn off in response to the second power supply voltage V2 applied to its control terminal.

[0086] See Figure 3The timing sequence is shown below. In stage T1, the first total control terminal IN1 is loaded with a low-level signal and the second total control terminal IN2 is loaded with a high-level signal; therefore, the first transistor M1 is turned off, and the second transistor M2 is turned on, causing the second node B to be loaded with the first power supply voltage V1. Under the control of the second node B, the fourth transistor M4 is turned on, outputting the second power supply voltage V2 to the first node A; under the control of the first node A, the third transistor M3 is turned off. Thus, the first node A is loaded with the second power supply voltage V2, and the second node B is loaded with the first power supply voltage V1. Under the control of the first node A, the fifth transistor M5 is turned on, and the sixth transistor M6 is turned off, causing the first power supply voltage V1 to be loaded to the first total output terminal OUT1; under the control of the second node B, the eighth transistor M8 is turned on, and the seventh transistor M7 is turned off, causing the second power supply voltage V2 to be loaded to the second total output terminal OUT2.

[0087] In phase T2, the first total control terminal IN1 is loaded with a high-level signal and the second total control terminal IN2 is loaded with a low-level signal; therefore, the second transistor M2 is turned off, and the first transistor M1 is turned on, causing the first node A to be loaded with the first power supply voltage V1. Under the control of the first node A, the third transistor M3 is turned on, outputting the second power supply voltage V2 to the second node B, and the fourth transistor M4 is turned off under the control of the first node A. Thus, the first node A is loaded with the first power supply voltage V1, and the second node B is loaded with the second power supply voltage V2. Under the control of the first node A, the sixth transistor M6 is turned on, and the fifth transistor M5 is turned off, causing the second power supply voltage V2 to be loaded to the first total output terminal OUT1; under the control of the second node B, the seventh transistor M7 is turned on, and the eighth transistor M8 is turned off, causing the first power supply voltage V1 to be loaded to the second total output terminal OUT2.

[0088] Correspondingly, in stage T3, the first total output terminal OUT1 is loaded with the first power supply voltage V1, and the second total output terminal OUT2 is loaded with the second power supply voltage V2.

[0089] Optionally, in some embodiments, one of the first power supply voltage V1 and the second power supply voltage V2 can be ground voltage (GND), and the other can be the voltage (VDD) applied by the pixel driving circuit 300 to the source of the driving transistor M03 during the light-emitting stage. Preferably, the first power supply voltage V1 is ground voltage (GND).

[0090] This disclosure also provides a shift register unit, see [link to previous document]. Figure 4The shift register unit includes any of the line drive signal enhancement circuits 100 described in the above-described embodiments, and includes a shift register 210 and an inverter 220. The shift register 210 outputs an initial scan signal to the input of the inverter 220 and the first overall control terminal IN1 of the line drive signal enhancement circuit 100; the output of the inverter 220 is connected to the second overall control terminal IN2 of the line drive signal enhancement circuit 100. This shift register unit can generate an initial scan signal and then convert it into a scan signal using the power supply voltage. The scan voltage and base voltage of this scan signal are different power supply voltages, thereby improving the driving capability of the scan signal and overcoming the defects of large delay and large voltage drop on the scan leads.

[0091] Since the shift register unit has any of the row drive signal enhancement circuits 100 described in the above-described embodiments of the row drive signal enhancement circuit 100, it has the same beneficial effects, which will not be repeated here.

[0092] This disclosure also provides a display panel that includes any of the shift register units described in the above-described shift register unit embodiments. The display panel can be an OLED (Organic Light Emitting Diode) display panel, a liquid crystal display panel, a Micro LED (Micro Light Emitting Diode) display panel, or other types of display panels, particularly a silicon-based OLED display panel or a silicon-based liquid crystal display panel. Since this display panel has any of the shift register units described in the above-described shift register unit embodiments, it has the same beneficial effects, which will not be repeated here.

[0093] In one embodiment of this disclosure, the display panel includes a display area and a peripheral area surrounding the display area, with a shift register unit located in the peripheral area; and a row drive signal enhancement circuit located between the shift register and the display area.

[0094] In some embodiments, the display panel may include a driving backplane and a display layer stacked on the driving backplane. See also... Figure 23 The driving backplane includes a semiconductor substrate 400, a gate insulating layer 510, a gate layer 520, an insulating dielectric layer 530, and a metal wiring layer 540, which are sequentially stacked. See also... Figure 4 The display panel includes a display area C and a peripheral area D surrounding the display area C, and a plurality of horizontal drive signal enhancement areas E are provided in the peripheral area D; in any one of the horizontal drive signal enhancement areas E, the display panel is provided with a horizontal drive signal enhancement circuit 100 including a first transistor M1 to an eighth transistor M8.

[0095] Figure 5This is a schematic diagram of the structure of the row drive signal enhancement region E on the semiconductor substrate 400. Figure 5 The diagram only shows the location of the active regions of each transistor, and does not show the location of the N-type doped region and P-type doped region, etc., of the drive signal enhancement region E in that row.

[0096] See Figure 5 The semiconductor substrate 400 has active regions formed for transistors M1 to M8, where the active region of any transistor includes a channel region, a source, and a drain on both sides of the channel region. Specifically, transistors M1 and M2 are both N-type transistors (or P-type transistors). Transistors M5 and M7 are both N-type transistors (or P-type transistors). Transistors M6 and M8 are both N-type transistors (or P-type transistors), with one of M5 and M6 being an N-type transistor and the other a P-type transistor. Transistors M3 and M4 are both N-type transistors (or P-type transistors).

[0097] Preferably, the semiconductor substrate 400 can be a silicon-based semiconductor substrate, especially a single-crystal silicon semiconductor substrate.

[0098] See Figure 7 , Figure 12 and Figure 23 The gate layer 520 is formed with the gates of the first transistor M1 to the eighth transistor M8, and the gate insulating layer 510 isolates the gate and channel region of any one transistor.

[0099] See Figure 23 The insulating dielectric layer 530 covers the gate layer 520.

[0100] See Figures 13-22The metal wiring layer 540 includes connection leads, a first power supply lead 6011, a second power supply lead 6012, a first control lead 6021, a second control lead 6022, a first output lead 6031, and a second output lead 6032. The connection leads are electrically connected to the source, drain, and gate of each transistor via conductive pillars located in the insulating dielectric layer 530. The connecting leads electrically connect the source 4411 of the first transistor M1, the source 4421 of the second transistor M2, the source 4451 of the fifth transistor M5, and the source 4471 of the seventh transistor M7 to the first power supply lead 6011, and electrically connect the source 4431 of the third transistor M3, the source 4441 of the fourth transistor M4, the source 4461 of the sixth transistor M6, and the source 4481 of the eighth transistor M8 to the second power supply lead 6012, and electrically connect the drain 4412 of the first transistor M1, the drain 4442 of the fourth transistor M4, the gate 4434 of the third transistor M3, the gate 4454 of the fifth transistor M5, and the gate 4464 of the sixth transistor M6 to each other. The drain 4422 of the second transistor M2, the drain 4432 of the third transistor M3, the gate 4444 of the fourth transistor M4, the gate 4474 of the seventh transistor M7, and the gate 4484 of the eighth transistor M8 are electrically connected to each other. The gate 4414 of the first transistor M1 is electrically connected to the first control lead 6021. The gate 4424 of the second transistor M2 is electrically connected to the second control lead 6022. The drain 4452 of the fifth transistor M5 and the drain 4462 of the sixth transistor M6 are electrically connected to the first output lead 6031. The drain 4472 of the seventh transistor M7 and the drain 4482 of the eighth transistor M8 are electrically connected to the first output lead 6031.

[0101] Thus, in the display panel of this disclosure, the equivalent circuit of the horizontal drive signal enhancement circuit 100 is as follows: Figure 2 As shown. The working process and effect of the line drive signal enhancement circuit 100 have been described in detail in the above-described embodiment of the line drive signal enhancement circuit 100, and will not be repeated here. The display panel is provided with the line drive signal enhancement circuit 100, thus improving the line drive capability of the display panel and improving the uniformity of the display.

[0102] In the display panel provided in this disclosure, the first power lead 6011 can be loaded with a first power supply voltage V1, and the second power lead 6012 can be loaded with a second power supply voltage V2. The first control lead 6021 can serve as the first total control terminal IN1 of the horizontal drive signal enhancement circuit 100, and the second control lead 6022 can serve as the second total control terminal IN2 of the horizontal drive signal enhancement circuit 100. The first output lead 6031 can serve as the first total output terminal OUT1 of the horizontal drive signal enhancement circuit 100, and the second output lead 6032 can serve as the second total output terminal OUT2 of the horizontal drive signal enhancement circuit 100.

[0103] In one embodiment of this disclosure, the first transistor M1, the second transistor M2, the fifth transistor M5, and the seventh transistor M7 are N-type transistors; the third transistor M3, the fourth transistor M4, the sixth transistor M6, and the eighth transistor M8 are P-type transistors. Thus, each transistor can be formed using CMOS (Complementary Metal Oxide Semiconductor) technology, eliminating the need for additional processes that would increase the cost of the display panel.

[0104] Optionally, see Figure 5 Any row drive signal enhancement region E includes a P-type substrate region 410 and an N-type substrate region 420. The P-type substrate region 410 is located on the side of the N-type substrate region 420 away from the display region C; N-type transistors are formed in the P-type substrate region 410, and P-type transistors are formed in the N-type substrate region 420.

[0105] Further optional, see Figure 5 The P-type substrate region 410 includes a P-type auxiliary doped region 411 and mutually isolated first active regions 431, second active regions 432, fifth active regions 435, and seventh active regions 437. The fifth active regions 435 and seventh active regions 437 are arranged in a direction parallel to the edge of the display region C (especially along the column edge of the display region C), and are surrounded by P-type auxiliary doped regions 411. The first active regions 431 and second active regions 432 are arranged in a direction parallel to the edge of the display region C and are located on the side of the fifth active regions 435 and seventh active regions 437 away from the display region C. The first active regions 431 and second active regions 432 are together surrounded by the P-type auxiliary doped regions 411, meaning there is no P-type auxiliary doped region 411 between the first active regions 431 and second active regions 432. The first transistor M1 is located in the first active region 431, the second transistor M2 is located in the second active region 432, the fifth transistor M5 is located in the fifth active region 435, and the seventh transistor M7 is located in the seventh active region 437.

[0106] Thus, this transistor arrangement improves the compactness of the transistor arrangement, reduces the area ratio of the horizontal drive signal enhancement circuit 100, and reduces the length of the connecting leads, thereby reducing the power consumption of the horizontal drive signal enhancement circuit 100. Furthermore, the P-type auxiliary doped region 411 can reduce the leakage current of each transistor, further reducing the power consumption of the horizontal drive signal enhancement circuit 100.

[0107] Optionally, see Figure 5 The N-type substrate region 420 includes an N-type auxiliary doped region 421 and mutually isolated third active regions 433, sixth active regions 436, and eighth active regions 438. The sixth active regions 436 and eighth active regions 438 are arranged along a direction extending parallel to the edge of the display region C, and are surrounded by N-type auxiliary doped regions 421. The third active region 433 is located on the side of the sixth active regions 436 and eighth active regions 438 away from the display region C, and is surrounded by N-type auxiliary doped regions 421. Third transistor M3 and fourth transistor M4 are located in the third active region 433, sixth transistor M6 is located in the sixth active region 436, and eighth transistor M8 is formed in the eighth active region 438.

[0108] Thus, this transistor arrangement improves the compactness of the transistor layout, reduces the area ratio of the horizontal drive signal enhancement circuit 100, and reduces the length of the connecting leads, thereby reducing the power consumption of the horizontal drive signal enhancement circuit 100. Furthermore, the N-type auxiliary doped region 421 can reduce the leakage current of each transistor, further reducing the power consumption of the horizontal drive signal enhancement circuit 100.

[0109] Furthermore, the third transistor M3 and the fourth transistor M4 can share the same source. This avoids the need for a connecting wire between the source 4431 of the third transistor M3 and the source 4441 of the fourth transistor M4, further improving the compactness of the horizontal drive signal enhancement circuit 100. Even further, the N-type substrate region 420 may also include a fourth active region 434, which is adjacent to the third active region 433 and surrounded together by an N-type auxiliary doped region 421. An auxiliary transistor is formed within this fourth active region 434 to improve the uniformity of the fabrication process of the horizontal drive signal enhancement circuit 100. Preferably, within the fourth active region 434, the source 4491, drain 4492, and gate 4494 of the auxiliary transistor are electrically connected to each other, wherein the gate 4494 of the auxiliary transistor at least partially overlaps with the channel region 4493 of the auxiliary transistor.

[0110] For example, in one embodiment of this disclosure, in any one of the line drive signal enhancement regions E, the sixth transistor M6, the auxiliary transistor, the fifth transistor M5 and the first transistor M1 are arranged in a straight line away from the display area C, the eighth transistor M8, the third transistor M3 and the fourth transistor M4 are arranged as a whole, and the seventh transistor M7 and the second transistor M2 are arranged in a straight line away from the display area C.

[0111] The individual transistors can be fabricated using CMOS technology. For example, the individual transistors of the row drive signal enhancement circuit 100 can be formed in the row drive signal enhancement region E using the following method.

[0112] See Figure 6 A P-type semiconductor substrate 400 can be provided first. The P-type semiconductor substrate 400 has a first region 401 and a second region 402 in the row drive signal enhancement region E. The first region 401 can serve as a P-type substrate region 410, which has a P-well. N-type ions can be implanted into the second region 402 to form an N-well, serving as an N-type substrate region 420.

[0113] Then, see Figure 7 A gate insulating layer 510 can be formed. Figure 7 (not shown in the image) and gate layer 520, see [reference] Figure 12 This allows the gate insulating layer 510 and gate layer 520 to cover the channel regions of each transistor and expose the source and drain of each transistor. The gate insulating layer 510 can be made of inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. The gate layer 520 can be made of polysilicon.

[0114] See Figure 8 and Figure 9 N-type ion implantation can be performed on each active region of the P-type substrate region 410 and the N-type auxiliary doped region 421 of the N-type substrate region 420. In this way, the source and drain of each transistor in the P-type substrate region 410 are transformed into N-type doped, thereby forming each N-type transistor in the P-type substrate region 410; the doping concentration of the N-type auxiliary doped region 421 is increased, which has a better leakage current prevention effect.

[0115] See Figure 10 and Figure 11 P-type ion implantation can be performed on each active region of the N-type substrate region 420 and the P-type auxiliary doped region 411 of the P-type substrate region 410. In this way, the source and drain of each transistor in the N-type substrate region 420 are transformed into P-type doped, thereby forming each P-type transistor in the N-type substrate region 420; the doping concentration of the P-type auxiliary doped region 411 is increased, which has a better leakage current prevention effect.

[0116] Optionally, see Figure 23 The insulating dielectric layer 530 includes a first dielectric layer 531, a second dielectric layer 532, and a third dielectric layer 533 sequentially stacked on the gate layer 520. The metal wiring layer 540 includes a first metal wiring layer 541 located between the first dielectric layer 531 and the second dielectric layer 532, a second metal wiring layer 542 located between the second dielectric layer 532 and the third dielectric layer 533, and a third metal wiring layer 543 located on the surface of the third dielectric layer 533 away from the semiconductor substrate 400. The insulating dielectric layer 530 has conductive pillars for electrical connection. Exemplarily, a first conductive pillar 5311 penetrating the first dielectric layer 531 is provided in the first dielectric layer 531; a second conductive pillar 5321 penetrating the second dielectric layer 532 is provided in the second dielectric layer 532; and a third conductive pillar 5331 penetrating the third dielectric layer 533 is provided in the third dielectric layer 533. The material of each conductive pillar can be a metal or an alloy material, such as tungsten. Optionally, any type of conductive pillar can be fabricated using deposition and planarization methods. For example, in fabricating the first conductive pillar 5311, a first dielectric material layer can be deposited first, and then the first dielectric material layer can be patterned to form contact holes penetrating the first dielectric material layer, thus obtaining the first dielectric layer. Then, tungsten metal is deposited, filling the contact holes and covering the first dielectric layer. Then, CMP process is used for planarization to obtain the first dielectric layer in which the first conductive pillar 5311 (tungsten pillar in this example) is embedded.

[0117] See Figure 13 and Figure 14 The first dielectric layer 531 is provided with a first conductive post 5311, which is used to connect the semiconductor substrate 400 and the gate layer to the first metal wiring layer 541. See also Figure 15 and Figure 16 The first metal wiring layer 541 includes a portion of connection leads; the connection leads located in the first metal wiring layer 541 include first connection leads 701 to sixth connection leads 706, and also include gate connection lines, source connection lines, and drain connection lines corresponding to the first transistor M1 to the eighth transistor M8. The gate connection line corresponding to any transistor is connected to the gate of the transistor through a first conductive post 5311. For example, the gate connection line 663 corresponding to the sixth transistor M6 is connected to the gate of the sixth transistor M6 through the first conductive post 5311; the source connection line corresponding to any transistor is connected to the source of the transistor through the first conductive post 5311; and the drain connection line corresponding to any transistor is connected to the drain of the transistor through the first conductive post 5311.

[0118] See Figure 15The source connection line 611 corresponding to the first transistor M1 and the source connection line 621 corresponding to the second transistor M2 are connected to the first connection lead 701. The source connection line 651 corresponding to the fifth transistor M5 and the source connection line 671 corresponding to the seventh transistor M7 are connected to the second connection lead 702. The source connection line 661 corresponding to the sixth transistor M6 and the source connection line 681 corresponding to the eighth transistor M8 are connected to the third connection lead 703. The gate connection line 653 corresponding to the fifth transistor M5 is connected to the fourth connection lead 704. The gate connection line 633 corresponding to the third transistor M3 and the drain connection line 642 corresponding to the fourth transistor M4 are connected to the sixth connection lead 706. The drain connection line 632 corresponding to the third transistor M3 and the gate connection line 643 corresponding to the fourth transistor M4 are connected.

[0119] See Figure 17 and Figure 18 The second dielectric layer 532 is provided with a second conductive post 5321, which is used to connect the first metal wiring layer 541 to the second metal wiring layer 542. See also Figure 19 and Figure 20The second metal wiring layer 542 includes a first power lead 6011, a second power lead 6012, a first control lead 6021, a second control lead 6022, a first output lead 6031, a second output lead 6032, and some connection leads. The connection leads located in the second metal wiring layer 542 include seventh connection leads 707 to thirteenth connection leads 713. The first control lead 6021 is connected to the gate connection line 613 corresponding to the first transistor M1 via a second conductive post 5321. The second control lead 6022 is connected to the gate connection line 623 corresponding to the second transistor M2 via a second conductive post 5321. The first power lead 6011 is connected to the first connection lead 701 and the second connection lead 702 via the second conductive post 5321. The second power lead 6012 is connected to the third connection lead 703 via the second conductive post 5321. The seventh connecting lead 707 connects to the drain connection line 612 of the first transistor M1 and the gate connection line 653 of the fifth transistor M5 via the second conductive post 5321. The eighth connecting lead 708 connects to the drain connection line 622 of the second transistor M2, the gate connection line 643 of the fourth transistor M4, the gate connection line 673 of the seventh transistor M7, and the gate connection line 683 of the eighth transistor M8 via the second conductive post 5321. The ninth connecting lead 709 connects to the fourth connecting lead 704 and the gate connection line 633 of the third transistor M3 via the second conductive post 5321. The tenth connecting lead 710 connects to the drain connection line 672 of the seventh transistor M7 and the fifth connecting lead 705 via the second conductive post 5321. The eleventh connecting lead 711 connects to the drain connection line 662 of the sixth transistor M6 and the sixth connecting lead 706 via the second conductive post 5321. The twelfth connecting lead 712 is connected via the second conductive post 5321 to the source connection line 631 corresponding to the third transistor M3 and the source connection line 641 corresponding to the fourth transistor M4. The thirteenth connecting lead 713 is connected via the second conductive post 5321 to the drain connection line 682 corresponding to the eighth transistor M8. The first output lead 6031 is connected via the second conductive post 5321 to the drain connection line 652 corresponding to the fifth transistor M5 and the drain connection line 662 corresponding to the sixth transistor M6. The second output lead 6032 is connected via the second conductive post 5321 to the sixth connecting lead 706 and the thirteenth connecting lead 713.

[0120] The third dielectric layer 533 is provided with a third conductive post 5331, which is used to connect the second metal wiring layer 542 to the third metal wiring layer 543. See also Figure 21 and Figure 22The third metal wiring layer 543 includes a portion of connection leads, and the connection leads located in the third metal wiring layer 543 include a fourteenth connection lead 714 and a fifteenth connection lead 715; wherein, the fourteenth connection lead 714 is connected to the twelfth connection lead 712 and the second power supply lead 6012 through the third conductive post 5331; the fifteenth connection lead 715 is connected to the twelfth connection lead 712 and the second output lead 6032 through the third conductive post 5331.

[0121] Thus, in the line drive signal enhancement region E, the metal wiring layer 540 can interconnect the individual transistors to form the line drive signal enhancement circuit 100.

[0122] Optionally, see Figure 5 The source 4431 of the third transistor M3 and the source 4441 of the fourth transistor M4 coincide. See also Figure 15 The source connection line 631 corresponding to the third transistor M3 and the source connection line 641 corresponding to the fourth transistor M4 are multiplexed into the same connection lead. In this way, the compactness of the horizontal drive signal enhancement circuit 100 can be improved and the number of connection leads can be reduced, thereby reducing the area and power consumption of the horizontal drive signal enhancement circuit 100.

[0123] Further, see Figure 15 and Figure 19 The connecting leads also include a sixteenth connecting lead 716 and a seventeenth connecting lead 717 located in the first metal wiring layer 541. The sixteenth connecting lead 716 is arranged along the routing direction of the P-type auxiliary doped region 411 and is connected to the P-type auxiliary doped region 411 via a first conductive post 5311 and to the first power supply lead 6011 via a second conductive post 5321. The seventeenth connecting lead 717 is arranged along the routing direction of the N-type auxiliary doped region 421 and is connected to the N-type auxiliary doped region 421 via a first conductive post 5311 and to the second power supply lead 6012 via a second conductive post 5321.

[0124] Thus, the P-type auxiliary doped region 411 can be loaded with a first power supply voltage V1, further reducing the leakage current of each N-type transistor. The N-type auxiliary doped region 421 can be loaded with a second power supply voltage V2, further reducing the leakage current of each P-type transistor.

[0125] Further, see Figure 15 , Figure 19 and Figure 21The connecting leads also include an eighteenth connecting lead 718 and a nineteenth connecting lead 719 located on the second metal wiring layer 542, and a twentieth connecting lead 720 located on the third metal wiring layer 543. The eighteenth connecting lead 718 is connected to the sixteenth connecting lead 716 via a second conductive post 5321; the nineteenth connecting lead 719 is connected to the seventeenth connecting lead 717 via a second conductive post 5321, and to the fourteenth connecting lead 714 via a third conductive post 5331; the twentieth connecting lead 720 is connected to the eighteenth connecting lead 718 and the first power supply lead 6011 via the third conductive post 5331. This reduces the impedance between the first power supply lead 6011 and the P-type auxiliary doped region 411, ensuring that the first power supply voltage V1 can be effectively and uniformly applied to the P-type auxiliary doped region 411. Furthermore, it can reduce the impedance between the second power supply lead 6012 and the N-type auxiliary doped region 421, ensuring that the second power supply voltage V2 can be effectively and uniformly applied to the N-type auxiliary doped region 421.

[0126] Preferably, see Figure 21 and Figure 6 The twentieth connecting lead 720 covers the channel region 4413 of the first transistor M1, the channel region 4423 of the second transistor M2, the channel region 4453 of the fifth transistor M5, and the channel region 4473 of the seventh transistor M7; the fourteenth connecting lead 714 covers the channel region 4433 of the third transistor M3, the channel region 4443 of the fourth transistor M4, the channel region 4463 of the sixth transistor M6, and the channel region 4483 of the eighth transistor M8. Thus, the twentieth connecting lead 720 can shield the first transistor M1, the second transistor M2, the fifth transistor M5, and the seventh transistor M7 from electromagnetic interference from external signals; and the fourteenth connecting lead 714 can shield the third transistor M3, the fourth transistor M4, the sixth transistor M6, and the eighth transistor M8 from electromagnetic interference from external signals.

[0127] In one embodiment of this disclosure, see Figure 4The display panel also includes a pixel driving circuit 300 in the display area C. The pixel driving circuit 300 includes a data writing unit 310, a storage capacitor Cst, and a driving transistor M03. The data writing unit 310 has a first control terminal and a second control terminal. The first control terminal of the data writing unit 310 is connected to a first output lead 6031, and the second control terminal is connected to a second output lead 6032. The input terminal of the data writing unit 310 is connected to the data line of the display panel, and the output terminal is connected to a third node F. The first electrode plate of the storage capacitor Cst is connected to the third node F, and the second electrode plate of the storage capacitor Cst is loaded with a first driving voltage. The control terminal of the driving transistor M03 is connected to the third node F, the output terminal of the driving transistor M03 is connected to the light-emitting element (e.g., OLED) of the display panel, and the input terminal of the driving transistor M03 can be loaded with a second driving voltage.

[0128] Thus, the row drive signal enhancement circuit 100 can output a scan signal to control the on or off state of the data writing unit 310. When the data writing unit 310 is on, the data voltage Vdata applied to the input terminal of the data writing unit 310 can be applied to the third node F.

[0129] Preferably, the data writing unit 310 may include a first switching transistor M01 and a second switching transistor M02. One of the first switching transistor M01 and the second switching transistor M02 is a P-type transistor, and the other is an N-type transistor. The P-type transistor is turned on in response to a first power supply voltage V1 applied to its control terminal, and the N-type transistor is turned on in response to a second power supply voltage V2 applied to its control terminal. Thus, the control terminal of the first switching transistor M01 can serve as the first control terminal of the data writing unit 310, and the control terminal of the second switching transistor M02 can serve as the second control terminal of the data writing unit 310. When a scan signal is applied to the first and second control terminals of the data writing unit 310, both the first switching transistor M01 and the second switching transistor M02 are turned on; when a non-scan signal is applied to the first and second control terminals of the data writing unit 310, for example, when the base voltage on the first total output terminal OUT1 and the second total output terminal OUT2 of the row drive signal enhancement circuit 100 is applied to the first and second control terminals of the data writing unit 310, both are turned off.

[0130] For example, if the base voltage output by the first total output terminal OUT1 of the horizontal drive signal enhancement circuit 100 is the first power supply voltage V1 and the voltage of the scan signal is the second power supply voltage V2, then the base voltage output by the second total output terminal OUT2 of the horizontal drive signal enhancement circuit 100 is the second power supply voltage V2 and the voltage of the scan signal is the first power supply voltage V1. In this case, the first switching transistor M01 can be an N-type transistor, and the second switching transistor M02 can be a P-type transistor.

[0131] Further, see Figure 4 The display area C is provided with a first gate lead and a second gate lead. The first control terminal of the data writing unit 310 is connected to the first gate lead, and the second control terminal of the data writing unit 310 is connected to the second gate lead. The first output lead 6031 of the horizontal drive signal enhancement circuit 100 is connected to the first gate lead, and the second output lead 6032 of the horizontal drive signal enhancement circuit 100 is connected to the second gate lead.

[0132] Furthermore, the first power supply lead 6011 is used to apply the first driving voltage; the second power supply lead 6012 is used to apply the second driving voltage. Thus, the row drive signal enhancement circuit 100 provided in this disclosure has a power supply voltage specification that is consistent with the power supply voltage specification of the display area C, which not only simplifies the power supply specification setting and power distribution setting of the display panel, but also significantly improves the driving capability of the scanning signal.

[0133] Optionally, see Figure 4 The display panel also has multiple shift registers 210 and multiple inverters 220 in the peripheral area D, each corresponding to one of the horizontal drive signal enhancement circuits 100. In the corresponding horizontal drive signal enhancement circuits 100, shift registers 210 and inverters 220, the output terminal of shift register 210 is connected to the input terminal of inverter 220 and the first control lead 6021 of horizontal drive signal enhancement circuit 100, and the output terminal of inverter 220 is connected to the second control lead 6022 of horizontal drive signal enhancement circuit 100.

[0134] Thus, shift register 210 can output a first initial scan signal, which can be loaded onto the first overall control terminal IN1 of the row drive signal enhancement circuit 100. Inverter 220 can generate an opposite second initial scan signal based on the first initial scan signal, which can be loaded onto the second overall control terminal IN2 of the row drive signal enhancement circuit 100. Therefore, the two control terminals of the row drive signal enhancement circuit 100 are loaded with two different initial scan signals, and under the control of these two different initial scan signals, output a first scan signal and a second scan signal to scan the pixel drive circuit 300. In this way, the row drive signal enhancement circuit 100 can generate two opposite scan signals formed by the first power supply voltage V1 and the second power supply voltage V2 based on the first initial scan signal output by shift register 210, thereby improving the driving capability of the scan signal.

[0135] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A horizontal drive signal enhancement circuit, comprising a control unit, an inverting unit, a first output unit, and a second output unit; The control unit has a first external control terminal, a second external control terminal, an input terminal, and an output terminal. The input terminal of the control unit is electrically connected to a first power supply lead. The first external control terminal and the second external control terminal are used to load two inverted signals, respectively. The first output unit has a control terminal, a first total output terminal and two input terminals, and the two input terminals are electrically connected to the first power supply lead and the second power supply lead, respectively. The second output unit has a control terminal, a second total output terminal, and two input terminals, the two input terminals being electrically connected to the first power lead and the second power lead, respectively; The output terminal of the control unit is electrically connected to the control terminal of the first output unit, and / or the output terminal of the control unit is electrically connected to the control terminal of the second output unit; one of the control terminals of the first output unit and the second output unit is electrically connected to the output terminal of the control unit through the inverting unit; The input terminal of the control unit is electrically connected to the first power lead through at least two conductive materials.

2. The line drive signal enhancement circuit according to claim 1, wherein, The first power lead is used to apply a first power supply voltage; the second power lead is used to apply a second power supply voltage. The control unit is used to output the first power supply voltage to the first node or the second node under the control of the first external control terminal and the second external control terminal; The inverting unit is connected to the first node and the second node, and is used to output the second power supply voltage to the second node in response to the first power supply voltage applied to the first node, and to output the second power supply voltage to the first node in response to the first power supply voltage applied to the second node. The first output unit is connected to the first node and is used to output one of the first power supply voltage and the second power supply voltage to the first total output terminal under the control of the first node; The second output unit is connected to the second node and is used to output the first power supply voltage and the other of the second power supply voltage to the second total output terminal under the control of the second node.

3. The line drive signal enhancement circuit according to claim 2, wherein, The control unit includes: The first transistor has an input terminal loaded with the first power supply voltage, an output terminal connected to the first node, and a control terminal serving as the first external control terminal; the first transistor is used to output the first power supply voltage to the first node under the control of the control terminal of the first transistor. The second transistor has an input terminal loaded with the first power supply voltage, an output terminal connected to the second node, and a control terminal serving as the second external control terminal; the second transistor is used to output the first power supply voltage to the second node under the control of the control terminal of the second transistor. Both the first transistor and the second transistor are either N-type transistors or both are P-type transistors.

4. The line drive signal enhancement circuit according to claim 2, wherein, The inverting unit includes: The third transistor has a control terminal connected to the first node, an input terminal loaded with the second power supply voltage, and an output terminal connected to the second node; the third transistor is used to output the second power supply voltage to the second node under the control of the first power supply voltage loaded on the first node. The fourth transistor has a control terminal connected to the second node, an input terminal loaded with the second power supply voltage, and an output terminal connected to the first node; the fourth transistor is used to output the second power supply voltage to the first node under the control of the first power supply voltage loaded on the second node.

5. The line drive signal enhancement circuit according to claim 2, wherein, The first output unit includes: The fifth transistor has a control terminal connected to the first node, an input terminal loaded with the first power supply voltage, and an output terminal connected to the first total output terminal. The sixth transistor has a control terminal connected to the first node, an input terminal loaded with the second power supply voltage, and an output terminal connected to the first total output terminal; The second output unit includes: The seventh transistor has a control terminal connected to the second node, an input terminal loaded with the first power supply voltage, and an output terminal connected to the second total output terminal; The eighth transistor has a control terminal connected to the second node, an input terminal loaded with the second power supply voltage, and an output terminal connected to the second total output terminal; Wherein, the first terminal of the fifth transistor and the first terminal of the seventh transistor are used to load the first power supply voltage, and the first terminal of the sixth transistor and the first terminal of the eighth transistor are used to load the second power supply voltage; The fifth transistor and the seventh transistor are of the same type, the sixth transistor and the eighth transistor are of the same type, and the fifth transistor and the sixth transistor are of different types.

6. A shift register unit, comprising a shift register, an inverter, and the row drive signal enhancement circuit according to any one of claims 1 to 5; in, The shift register is used to output the initial scan signal to the input of the inverter and the first master control terminal of the row drive signal enhancement circuit; The output of the inverter is connected to the second master control terminal of the row drive signal enhancement circuit.

7. A display panel comprising the shift register unit of claim 6; wherein, The display panel includes a display area and a peripheral area surrounding the display area, with the shift register unit located in the peripheral area; the row drive signal enhancement circuit is located between the shift register and the display area.

8. The display panel according to claim 7, wherein, The line drive signal enhancement circuit includes a first transistor to an eighth transistor; the first transistor, the second transistor, the fifth transistor, and the seventh transistor are N-type transistors; the third transistor, the fourth transistor, the sixth transistor, and the eighth transistor are P-type transistors.

9. The display panel according to claim 8, wherein, The peripheral region includes at least one row drive signal enhancement region provided with the first transistor to the eighth transistor; The row drive signal enhancement region includes a P-type substrate region and an N-type substrate region. The P-type substrate region is located on the side of the N-type substrate region away from the display area. The N-type transistor is formed in the P-type substrate region, and the P-type transistor is formed in the N-type substrate region.

10. The display panel according to claim 9, wherein, The display panel includes a semiconductor substrate; the semiconductor substrate has active regions formed on the first transistor to the eighth transistor; The P-type substrate region includes a P-type auxiliary doped region and a first active region, a second active region, a fifth active region, and a seventh active region that are isolated from each other. The first active region and the fifth active region are arranged along a first direction, and the second active region and the seventh active region are arranged along the first direction; the first direction is parallel to the plane where the semiconductor substrate is located and perpendicular to the edge of the display area near the shift register unit; The fifth active region and the seventh active region are arranged along the second direction, and the first active region and the second active region are arranged along the second direction; the second direction is parallel to the plane of the semiconductor substrate and perpendicular to the first direction; The fifth active region and the seventh active region are respectively surrounded by the P-type auxiliary doped region; the first active region and the second active region are located on the side of the fifth active region and the seventh active region away from the display area; the first active region and the second active region are together surrounded by the P-type auxiliary doped region; The first transistor is located in the first active region, the second transistor is located in the second active region, the fifth transistor is located in the fifth active region, and the seventh transistor is located in the seventh active region.

11. The display panel according to claim 10, wherein, The N-type substrate region includes an N-type auxiliary doped region and mutually isolated third, sixth, and eighth active regions; The sixth active region and the eighth active region are arranged along the second direction, and the N-type auxiliary doped region is surrounded by the sixth active region and the eighth active region, respectively; the third active region is located on the side of the sixth active region and the eighth active region away from the display area, and the N-type auxiliary doped region is surrounded by the third active region. The third transistor and the fourth transistor are located in the third active region, the sixth transistor is located in the sixth active region, and the eighth transistor is formed in the eighth active region.

12. The display panel according to claim 11, wherein, The active region of any one of the transistors includes a channel region, a source on one side of the channel region, and a drain on the other side. In the row drive signal enhancement region, the channel region of the transistor, the source of the transistor, and the drain of the transistor all extend in the direction toward the display area.

13. The display panel according to claim 12, wherein, The display panel further includes a gate insulating layer and a gate layer sequentially stacked on the semiconductor substrate; In the row drive signal enhancement region, the gate layer includes the gates of each of the transistors, and the gate of any one of the transistors includes an interconnected gate region and a lead region; the orthogonal projection of the gate region of any one of the transistors onto the semiconductor substrate overlaps with the channel region of the transistor.

14. The display panel according to claim 13, wherein, The display panel further includes a first dielectric layer and a first metal wiring layer sequentially stacked on the side of the gate layer away from the semiconductor substrate; In the row drive signal enhancement region, a first conductive pillar is provided in the first dielectric layer, which penetrates the first dielectric layer and is connected to the lead region of the gate of each transistor, and a second conductive pillar is provided, which penetrates the first dielectric layer and the gate insulating layer and is connected to the semiconductor substrate. In the row drive signal enhancement region, the first metal wiring layer includes a first connection lead to a third connection lead, and gate connection lines, source connection lines, and drain connection lines corresponding to the first transistor to the eighth transistor; any one of the drain connection lines includes a drain region and a connection region that are interconnected. In the row drive signal enhancement region, the gate connection line corresponding to any one of the transistors is electrically connected to the lead area of ​​the gate of the transistor through the first conductive post; the source connection line corresponding to any one of the transistors is connected to the source of the transistor through the second conductive post; the drain area of ​​the drain connection line corresponding to any one of the transistors is connected to the drain of the transistor through the second conductive post. Specifically, the source connection lines corresponding to the first transistor and the second transistor are connected to the first connection lead; the source connection lines corresponding to the fifth transistor and the seventh transistor are connected to the second connection lead; the source connection lines corresponding to the sixth transistor and the eighth transistor are connected to the third connection lead; the connection region of the drain connection line corresponding to the third transistor is connected to the gate connection line corresponding to the fourth transistor; and the connection region of the drain connection line corresponding to the fourth transistor is connected to the gate connection line corresponding to the third transistor.

15. The display panel according to claim 14, wherein, In the row drive signal enhancement region, the first metal wiring layer further includes a fourth to a sixth, a sixteenth, and a seventeenth connection lead; the sixteenth connection lead is disposed along the routing direction of the P-type auxiliary doped region and is connected to the P-type auxiliary doped region through the second conductive post; the seventeenth connection lead is disposed along the routing direction of the N-type auxiliary doped region and is connected to the N-type auxiliary doped region through the second conductive post; the first connection lead extends along the second direction and is connected to the sixteenth connection lead at both ends; the second connection lead extends along the second direction and is connected to the sixteenth connection lead at both ends; the third connection lead extends along the second direction and is connected to the seventeenth connection lead at both ends; the fourth connection lead is connected to the gate connection line corresponding to the fifth transistor and extends along the second direction; the fifth connection lead is located between the P-type substrate region and the N-type substrate region and extends along the second direction; the sixth connection lead is connected to the connection region of the drain connection line corresponding to the fourth transistor and extends along the second direction.

16. The display panel according to claim 15, wherein, The display panel further includes a second dielectric layer and a second metal wiring layer sequentially stacked on the side of the first metal wiring layer away from the semiconductor substrate; The second dielectric layer is provided with a third conductive post that penetrates the second dielectric layer and is connected to the first metal wiring layer; the second metal wiring layer is connected to the first metal wiring layer through the third conductive post. In the row drive signal enhancement region, the second metal wiring layer includes a seventh to thirteenth connection lead, a first power supply lead, a second power supply lead, a first control lead, a second control lead, a first output lead, and a second output lead, and each lead extends along the first direction; the first control lead is connected to the gate connection line corresponding to the first transistor; the second control lead is connected to the gate connection line corresponding to the second transistor; the first power supply lead is connected to the first connection lead and the second connection lead; the second power supply lead is connected to the third connection lead; the seventh connection lead is connected to the connection area of ​​the drain connection line corresponding to the first transistor and the gate connection line corresponding to the fifth transistor; the eighth connection lead is connected to the connection area of ​​the drain connection line corresponding to the second transistor, the gate connection line corresponding to the fourth transistor, the gate connection line corresponding to the seventh transistor, and the eighth transistor. The gate connection lines corresponding to the transistors are connected; the ninth connection line is connected to the end of the fourth connection line away from the gate connection line corresponding to the fifth transistor, and to the gate connection line corresponding to the third transistor; the tenth connection line is connected to the connection area of ​​the drain connection line corresponding to the seventh transistor, and to the fifth connection line; the eleventh connection line is connected to the gate connection line corresponding to the sixth transistor, and to the end of the sixth connection line away from the gate connection line corresponding to the third transistor; the twelfth connection line is connected to the source connection line corresponding to the third transistor, and to the source connection line corresponding to the fourth transistor; the thirteenth connection line is connected to the connection area of ​​the drain connection line corresponding to the eighth transistor; the first output line is connected to the connection area of ​​the drain connection line corresponding to the fifth transistor, and to the connection area of ​​the drain connection line corresponding to the sixth transistor; the second output line is connected to the sixth connection line.

17. The display panel according to claim 16, wherein, The display panel further includes a third dielectric layer and a third metal wiring layer stacked sequentially on the side of the second metal wiring layer away from the semiconductor substrate; In the row drive signal enhancement region, the third dielectric layer is provided with a fourth conductive post that penetrates the third dielectric layer and is connected to the second metal wiring layer; the third metal wiring layer is connected to the second metal wiring layer through the fourth conductive post; the third metal wiring layer includes a fourteenth connection lead and a fifteenth connection lead; the fourteenth connection lead is connected to the second power supply lead and the twelfth connection lead; the fifteenth connection lead is connected to the thirteenth connection lead and the second output lead.

18. The display panel according to claim 17, wherein, In the row drive signal enhancement region, the second metal wiring layer further includes an eighteenth connection lead extending along the first direction and a nineteenth connection lead extending along the first direction; the third metal wiring layer further includes a twentieth connection lead; the eighteenth connection lead is connected to the sixteenth connection lead and the twentieth connection lead; the nineteenth connection lead is connected to the seventeenth connection lead and the fourteenth connection lead; the orthographic projection of the twentieth connection lead on the semiconductor substrate covers the channel regions of the first transistor, the second transistor, the fifth transistor, and the seventh transistor; the orthographic projection of the fourteenth connection lead on the semiconductor substrate covers the channel regions of the third transistor, the fourth transistor, the sixth transistor, and the eighth transistor.

19. The display panel according to claim 18, wherein, In the row drive signal enhancement region, the first power lead and the first connection lead are connected by an array of third conductive pillars; the first power lead and the second connection lead are connected by an array of third conductive pillars; the first power lead and the twelfth connection lead are connected by at least one group of fourth conductive pillars, and the at least one group of fourth conductive pillars includes an array of fourth conductive pillars; the second power lead and the third connection lead are connected by an array of third conductive pillars; the second power lead and the fourteenth connection lead are connected by an array of fourth conductive pillars.

20. The display panel according to claim 15, wherein, The source of the third transistor coincides with the source of the fourth transistor; the source connection line of the third transistor and the source connection line of the fourth transistor are multiplexed as the same lead.

21. The display panel according to claim 15, wherein, In the row drive signal enhancement region, the N-type substrate region further includes a fourth active region; the fourth active region and the third active region are arranged along the second direction; the third active region and the eighth active region are arranged along the first direction; the fourth active region and the sixth active region are arranged along the first direction; the display panel has an auxiliary transistor disposed in the fourth active region; The active region of the auxiliary transistor is located in the fourth active region, the gate of the auxiliary transistor is located in the gate layer, the source connection line corresponding to the auxiliary transistor is located in the first metal wiring layer and connected to the source of the auxiliary transistor, the drain connection line corresponding to the auxiliary transistor is located in the first metal wiring layer and connected to the drain of the auxiliary transistor, and the gate connection line corresponding to the auxiliary transistor is located in the first metal wiring layer and connected to the gate of the auxiliary transistor; the source connection line, drain connection line and gate connection line corresponding to the auxiliary transistor are connected to the seventeenth connection lead.

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