Methods of forming microelectronic devices, and related microelectronic devices and electronic systems

Abstract

The present application relates to methods of forming microelectronic devices, and to related microelectronic devices and electronic systems. A method of forming a microelectronic device includes forming a microelectronic device structure including a base structure, a doped semiconductor material overlying the base structure, a stack structure overlying the doped semiconductor material, a cell pillar structure extending vertically through the stack structure and the doped semiconductor material and into the base structure, and a digit line structure vertically overlying the stack structure. An additional microelectronic device structure including a control logic device is formed. The microelectronic device structure is attached to the additional microelectronic device structure to form a microelectronic device structure assembly. Portions of the base structure and the cell pillar structure extending vertically into the base structure are removed to expose the doped semiconductor material. The doped semiconductor material is then patterned to form at least one source structure over the stack structure and coupled to the cell pillar structure.

Description

Cross-reference of related applications

[0001] This application is a national phase project of international patent application PCT / US2021 / 033361, filed on May 20, 2021, designating the People's Republic of China, and published in English as International Patent Publication WO 2021 / 257238 A1 on December 23, 2021. It claims the benefit of U.S. Patent Application No. 16 / 905,698, filed June 18, 2020, pursuant to Article VIII of the Patent Cooperation Treaty. This U.S. Patent Application No. 16 / 905,385, filed June 18, 2020, concerning “Microelectronic Devices, and Relatted Methods, Memory Devices, and Electronic Systems,” listing Kunal R. Parekh as the inventor. This application also relates to U.S. Patent Application No. 16 / 905,452, filed June 18, 2020, entitled "Methods of Forming Microelectronic Devices, and Related Microelectronic Devices, Memory Devices, Electronic Systems, and Additional Methods," listing Kunal Parek as the inventor. This application also relates to U.S. Patent Application No. 16 / 905,747, filed June 18, 2020, entitled "Microelectronic Devices Including Source Structures Overlying Stack Structures, and Related Electronic Systems," listing Kunal Parek as the inventor. This application also relates to U.S. Patent Application No. 16 / 905,763, filed June 18, 2020, entitled “Methods of Forming Microelectronic Devices, and Related Microelectronic Devices and Electronic Systems,” listing Kunal Parek as the inventor, and now U.S. Patent No. 11,335,602, published May 17, 2022.This application also relates to U.S. Patent Application No. 16 / 905,734, filed June 18, 2020, listing Kunal Parrick as the inventor, and U.S. Patent No. 11,380,669, published July 5, 2022. The disclosure of each of the foregoing documents is incorporated herein by reference in its entirety. Technical Field

[0002] In various embodiments, this disclosure generally relates to the field of microelectronic device design and fabrication. More specifically, this disclosure relates to methods of forming microelectronic devices, and to related microelectronic devices and electronic systems. Background Technology

[0003] Microelectronic device designers often need to increase the integration or density of features within a microelectronic device by reducing the size of individual features and by reducing the spacing between adjacent features. Furthermore, microelectronic device designers often need to design architectures that are not only compact but also offer performance advantages, and that are simplified, easier, and cheaper to manufacture.

[0004] An example of a microelectronic device is a memory device. Memory devices are typically provided as internal integrated circuits in computers or other electronic devices. Many types of memory devices exist, including, but not limited to, non-volatile memory devices (e.g., NAND flash memory devices). One way to increase memory density in non-volatile memory devices is to utilize a vertical memory array (also known as a "three-dimensional (3D) memory array") architecture. A conventional vertical memory array comprises vertical memory strings that extend through openings in one or more layers (e.g., a stacked structure) containing conductive structures and dielectric materials. Each vertical memory string may contain at least one select device that is coupled in series to a series combination of vertically stacked memory cells. Compared to structures with a conventional flat (e.g., two-dimensional) transistor arrangement, this configuration allows a larger number of switching devices (e.g., transistors) to be positioned within a unit die area (i.e., the length and width of the occupied active surface) by building an array upwards (e.g., vertically) on the die.

[0005] Control logic devices within the basic control logic structure of a memory array underlying a memory device (e.g., a non-volatile memory device) are used to control operations performed on the memory cells of the memory device (e.g., access operations, read operations, write operations). Assemblies of control logic devices can provide electrical communication with the memory cells of the memory array via wiring and interconnect structures. However, the processing conditions (e.g., temperature, pressure, materials) used to form the memory array above the basic control logic structure can limit the configuration and performance of the control logic devices within the basic control logic structure. Furthermore, the number, size, and arrangement of different control logic devices employed within the basic control logic structure may unduly hinder reductions in the size (e.g., horizontal footprint) of the memory device and / or improvements in its performance (e.g., faster memory cell turn-on / off speeds, lower threshold voltage requirements, faster data transfer rates, lower power consumption). Summary of the Invention

[0006] In some embodiments, a method of forming a microelectronic device includes forming a microelectronic device structure. The microelectronic device structure includes a base structure, a doped semiconductor material overlying the base structure, a stacked structure overlying the doped semiconductor material and including a vertically alternating sequence of conductive and insulating structures, a cell pillar structure extending vertically through the stacked structure and the doped semiconductor material and into the base structure, and a digital line structure vertically overlying the stacked structure. An additional microelectronic device structure including control logic devices is formed. The microelectronic device structure is attached to the additional microelectronic device structure to form a microelectronic device structure assembly. The digital line structure is vertically inserted within the microelectronic device structure assembly between the stacked structure and the control logic devices. A portion of the base structure and the cell pillar structure extending vertically into the base structure is removed to expose the doped semiconductor material. After removing portions of the base structure and the cell pillar structure, the doped semiconductor material is patterned to form at least one source structure above the stacked structure and coupled to the cell pillar structure.

[0007] In an additional embodiment, the microelectronic device includes a memory array region, a control logic region, a first interconnect region, and a second interconnect region. The memory array region includes: a stacked structure comprising a vertically alternating sequence of conductive and insulating structures; a source structure vertically overlying the stacked structure and including a doped semiconductor material; a cell pillar structure vertically extending completely through the stacked structure and at least partially through the source structure; and a digital line structure vertically lying beneath the stacked structure and electrically connected to the cell pillar structure. The control logic region vertically lies beneath the memory array region and includes control logic devices. The first interconnect region is vertically inserted between the memory array region and the control logic region and includes additional conductive structures coupling the digital line structure of the memory array region to the control logic devices of the control logic region. The second interconnect region vertically overlying the memory array region includes other conductive structures electrically connected to the source structure.

[0008] In another additional embodiment, an electronic system includes an input device, an output device, a processor device operatively coupled to the input and output devices, and a memory device operatively coupled to the processor device. The memory device includes a stacked structure, a source structure, a digital line structure, a cell pillar structure, a conductive wiring structure, a control logic device, and additional conductive wiring structures. The stacked structure includes layers, each layer including a conductive structure and an insulating structure vertically adjacent to the conductive structure. The source structure is overlaid on the stacked structure. The digital line structure lies beneath the stacked structure. The cell pillar structure is coupled to the digital line structure and extends vertically and completely through the stacked structure and into the source structure. The conductive wiring structure lies vertically beneath the digital line structure and is coupled to the digital line structure. The control logic device is coupled to the conductive wiring structure and at least partially lies vertically beneath the conductive wiring structure. The additional conductive wiring structure is coupled to the source structure and vertically overlaid on the source structure. Attached Figure Description

[0009] Figures 1A to 1F This is a simplified partial cross-sectional view illustrating a method for forming a microelectronic device structure according to an embodiment of the present disclosure.

[0010] Figures 2A to 2H This illustrates the use of embodiments according to this disclosure by reference. Figures 1A to 1F A simplified cross-sectional view of the method for forming a microelectronic device structure.

[0011] Figure 3 This is a schematic block diagram of an electronic system according to an embodiment of the present disclosure. Detailed Implementation

[0012] The following description provides specific details, such as material composition, shape, and size, to provide a sufficient description of embodiments of this disclosure. However, those skilled in the art will understand that embodiments of this disclosure can be practiced without these specific details. In fact, embodiments of this disclosure can be combined with conventional microelectronic device manufacturing practices used in the industry. Furthermore, the description provided below does not form a complete process flow for manufacturing microelectronic devices (e.g., memory devices, such as 3D NAND flash memory devices). The structures described below do not form a complete microelectronic device. Only those process actions and structures necessary for understanding embodiments of this disclosure are described in detail below. Additional actions can be performed using conventional manufacturing techniques to form a complete microelectronic device according to the structure.

[0013] The drawings presented herein are for illustrative purposes only and are not intended to be actual views of any particular material, component, structure, device, or system. The shapes illustrated are intended to vary due to, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as limited to the specific shapes or areas shown, but rather include shape deviations due to, for example, manufacturing processes. For instance, an area illustrated or described as box-shaped may have rough and / or non-linear characteristics, and an area illustrated or described as circular may contain some rough and / or linear characteristics. Furthermore, acute angles illustrated may be rounded, and vice versa. Therefore, the areas illustrated in the drawings are schematic in nature, and their shapes are not intended to show the precise shape of the areas and do not limit the scope of the claims. The drawings are not necessarily drawn to scale. Additionally, common elements between the drawings may retain the same numerical designation.

[0014] As used herein, “memory device” means and includes, but is not limited to, microelectronic devices that exhibit memory functionality. In other words, and only as a non-limiting example, the term “memory device” includes not only conventional memory (e.g., conventional volatile memory, such as conventional dynamic random access memory (DRAM); conventional non-volatile memory, such as conventional NAND memory), but also application-specific integrated circuits (ASICs) (e.g., system-on-a-chip (SoC)), microelectronic devices combining logic and memory, and graphics processing units (GPUs) incorporating memory.

[0015] As used herein, the term “configured” refers to the size, shape, material composition, orientation, and arrangement of one or more of at least one structure and at least one device in a predetermined manner to facilitate the operation of one or more of the structure and device.

[0016] As used herein, the terms “vertical,” “longitudinal,” “horizontal,” and “lateral” refer to the principal plane of the structure and are not necessarily defined by the Earth’s gravitational field. A “horizontal” or “lateral” direction is generally parallel to the principal plane of the structure, while a “vertical” or “longitudinal” direction is generally perpendicular to the principal plane of the structure. The principal plane of the structure is defined by the surface of the structure that has a relatively large area compared to the other surfaces of the structure. Referring to the diagram, a “horizontal” or “lateral” direction may be perpendicular to the indicated “Z” axis and parallel to the indicated “X” axis and / or parallel to the indicated “Y” axis; and a “vertical” or “longitudinal” direction may be parallel to the indicated “Z” axis, perpendicular to the indicated “X” axis, and perpendicular to the indicated “Y” axis.

[0017] As used herein, a feature described as “adjacent” to each other (e.g., area, structure, device) means and includes the feature of the disclosed identifier (or identifiers) located closest to each other (e.g., closest to each other). Additional features (e.g., additional areas, additional structures, additional devices) of the disclosed identifier (or identifiers) that do not match “adjacent” features may be positioned between “adjacent” features. In other words, “adjacent” features may be directly positioned to be adjacent to each other such that no other features intervene between the “adjacent” features; or “adjacent” features may be indirectly positioned to be adjacent to each other such that at least one feature having an identifier other than the identifier associated with at least one “adjacent” feature is positioned between the “adjacent” features. Thus, a feature described as “vertically adjacent” to each other means and includes the feature of the disclosed identifier (or identifiers) located closest to each other vertically (e.g., vertically closest to each other). Furthermore, a feature described as “horizontally adjacent” to each other means and includes the feature of the disclosed identifier (or identifiers) located closest to each other horizontally (e.g., horizontally closest to each other).

[0018] As used herein, spatially relative terms such as “below,” “under,” “lower,” “bottom,” “above,” “upper,” “top,” “front,” “back,” “left,” and “right” are readily descriptive and can be used to describe the relationship of one element or feature to another element(s) shown in the diagram. Unless otherwise specified, spatially relative terms are intended to cover different orientations of material, in addition to those depicted in the diagram. For example, if material in the diagram is reversed, then an element described as “below other elements or features,” “below other elements or features,” “under other elements or features,” or “at the bottom of other elements or features” would then be oriented as “above other elements or features” or “on top of other elements or features.” Thus, the term “below” can encompass both above and below orientations, depending on the context in which the term is used, and will be obvious to a person skilled in the art. Material may be oriented in other ways (e.g., rotated 90 degrees, reversed, flipped), and the spatially relative descriptors used herein will be interpreted accordingly.

[0019] As used herein, unless the context clearly indicates otherwise, the singular forms “a / an” and “the” are expected to also include the plural forms.

[0020] As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0021] As used herein, the phrase “coupled to” means that structures are operatively connected to each other, for example, via a direct ohmic connection or via an indirect connection (e.g., by means of another structure) electrical connection.

[0022] As used herein, the term "generally" in relation to a given parameter, characteristic, or condition means and includes, to a degree that a person skilled in the art would understand to some extent, that the given parameter, characteristic, or condition conforms to a certain degree of variation, such as within acceptable tolerances. By way of example, depending on the specific parameter, characteristic, or condition that is generally satisfied, the parameter, characteristic, or condition may satisfy at least 90.0%, at least 95.0%, at least 99.0%, at least 99.9%, or even 100.0%.

[0023] As used herein, the term "about" or "approximately" with respect to a particular parameter includes the value, and the degree of variation of the value should be understood by one of ordinary skill in the art to be within the acceptable tolerances of the particular parameter. For example, "about" or "approximately" with respect to a value may include additional values ​​within the range of 90.0% to 110.0% of the value, such as within the range of 95.0% to 105.0%, 97.5% to 102.5%, 99.0% to 101.0%, 99.5% to 100.5%, or 99.9% to 100.1%.

[0024] As used herein, “conductive material” means and includes materials that conduct electricity, such as metals (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pa), platinum (Pt), copper (Cu), silver (Ag), gold (Au), and aluminum (Al), alloys (e.g., Co-based alloys, Fe-based alloys, Ni-based alloys, Fe and Ni-based alloys, C Materials containing conductive metals (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides), and conductive doped semiconductor materials (e.g., conductive doped polysilicon, conductive doped germanium (Ge), conductive doped silicon germanium (SiGe)) are included in the category of one or more of the following: Ni-based alloys, Fe- and Co-based alloys, Co-, Ni- and Fe-based alloys, Al-based alloys, Cu-based alloys, Magnesium (Mg)-based alloys, Ti-based alloys, steel, low-carbon steel, stainless steel), and conductive materials containing conductive metals (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides), and conductive doped semiconductor materials (e.g., conductive doped polycrystalline silicon, conductive doped germanium (Ge), conductive doped silicon germanium (SiGe)). Furthermore, "conductive structure" means and includes structures formed of conductive materials and containing conductive materials.

[0025] As used herein, “insulating material” means and includes electrically insulating materials, such as one or more of the following: at least one dielectric oxide material (e.g., silicon oxide (SiO2)). x Phosphorus silicate glass, borosilicate glass, borosilicate-phosphorus silicate glass, fluorosilicate glass, alumina (AlO) x ), hafnium oxide (HfO) x ), niobium oxide (NbO) x Titanium oxide (TiO) x Zirconium oxide (ZrO) x ), tantalum oxide (TaO) x ) and magnesium oxide (MgO) x One or more of the following), at least one dielectric nitride material (e.g., silicon nitride (SiN) y()), at least one dielectric oxide nitride material (e.g., silicon oxynitride (SiO) x N y ()), at least one dielectric carbon oxide material (e.g., silicon oxycarbonate (SiO) x C y ()), and at least one hydrogenated dielectric carbon oxide material (e.g., hydrogenated silicon carbide (SiC) x O y H z and at least one dielectric carbonitride material (e.g., silicon carbonitride (SiO2)). x C z N y This document contains the chemical formula of one or more of the following: "x", "y", and "z" (e.g., SiO2). x AlO x HfO x NbO x TiO x SiN y SiO x N y SiO x C y SiC x O y H z SiO x C z N y A chemical formula (e.g., Si, Al, Hf, Nb, Ti) represents a material containing an average ratio of "x" atoms of one element, "y" atoms of another element, and "z" atoms of an additional element (if present) for each atom of the other element. Since a chemical formula represents a relative atomic ratio rather than a precise chemical structure, an insulating material may include one or more stoichiometric compounds and / or one or more non-stoichiometric compounds, and the values ​​of "x", "y", and "z" (if present) may be integers or non-integers. As used herein, the term "non-stoichiometric compound" means and includes compounds composed of elements having ratios that cannot be expressed as well-defined natural numbers and violate the law of definite proportions. Additionally, "insulating structure" means and includes structures formed from and containing insulating materials.

[0026] Unless the context otherwise indicates, the materials described herein can be formed by any suitable technique, including but not limited to spin coating, blanket coating, chemical vapor deposition (“CVD”), atomic layer deposition (“ALD”), plasma-enhanced ALD, physical vapor deposition (“PVD”) (e.g., sputtering), or epitaxial growth. Depending on the specific material to be formed, the technique used for depositing or growing the material may be selected by one of ordinary skill in the art. Additionally, unless the context otherwise indicates, the removal of the material described herein can be achieved by any suitable technique, including but not limited to etching (e.g., dry etching, wet etching, vapor phase etching), ion milling, planarization, or other known methods.

[0027] Figures 1A to 1F This is a simplified partial cross-sectional view illustrating an embodiment of a method for forming a microelectronic device structure (e.g., a memory device structure), such as a 3D NAND flash memory device. From the description provided below, it will be apparent to those skilled in the art that the methods described herein can be used in a variety of applications. In other words, the methods of this disclosure can be used whenever it is necessary to form a microelectronic device.

[0028] See Figure 1A The microelectronic device structure 100 may be formed to include a base structure 102 and a doped semiconductor material 104 in, on, or above the base structure 102. For example... Figure 1A As shown, in some embodiments, a doped semiconductor material 104 is formed on the upper surface of the base structure 102. In additional embodiments, at least one material (e.g., at least one insulating material) is formed between the base structure 102 and the doped semiconductor material 104. As a non-limiting example, a dielectric oxide material (e.g., SiO2) may be used. x For example, silicon dioxide (SiO2) may be formed between the base structure 102 and the doped semiconductor material 104 (e.g., vertically formed therebetween). In other embodiments, the doped semiconductor material 104 may also be formed on or above one or more additional surfaces of the base structure 102. As a non-limiting example, a first portion of the doped semiconductor material 104 may be formed on or above the upper surface of the base structure 102, and a second portion of the doped semiconductor material 104 may be formed below (e.g., formed below and in contact with) the lower surface of the base structure 102.

[0029] The base structure 102 of the microelectronic device structure 100 includes a substrate material or construction on which additional features (e.g., materials, structures, devices) of the microelectronic device structure 100 are formed. The base structure 102 may be formed from and include one or more of the following: semiconductor materials (e.g., one or more of silicon materials, such as monocrystalline silicon or polycrystalline silicon (also referred to herein as "polysilicon")); silicon germanium; germanium; gallium arsenide; gallium nitride; gallium phosphide; indium phosphide; indium gallium nitride; and aluminum gallium nitride); substrate semiconductor materials on the support structure; glass materials (e.g., one or more of borosilicate glass (BSP), phosphosilicate glass (PSG), fluorosilicate glass (FSG), borosilicate glass (BPSG), aluminosilicate glass, alkaline earth borosilicate glass, quartz, titania silicate glass, and soda-lime glass); and ceramic materials (e.g., one or more of aluminum polynitride (p-AlN), aluminum polynitride on silicon (SOPAN), aluminum nitride (AlN), aluminum oxide (e.g., sapphire; α-Al2O3), and silicon carbide). The base structure 102 can be configured to facilitate the safe disposal of the microelectronic device structure 100 for subsequent attachment to at least one additional microelectronic device structure, as described in further detail below.

[0030] The doped semiconductor material 104 may be formed of and comprise at least one semiconductor material, said at least one semiconductor material being doped with at least one conductive dopant (e.g., at least one n-type dopant, such as one or more of phosphorus (P), arsenic (Ar), antimony (Sb), and bismuth (Bi); at least one p-type dopant, such as one or more of boron (B), aluminum (Al), and gallium (Ga)). In some embodiments, the doped semiconductor material 104 may be formed of and comprise at least one of the following: silicon material, such as monocrystalline silicon or polycrystalline silicon; silicon-germanium material; germanium material; gallium arsenide material; gallium nitride material; and indium phosphide material. As a non-limiting example, the doped semiconductor material 104 may be formed of and comprise epitaxial silicon (e.g., monocrystalline silicon formed via epitaxial growth) doped with at least one conductive dopant (e.g., at least one n-type dopant and at least one p-type dopant). As another non-limiting example, the doped semiconductor material 104 may be formed from and comprise polysilicon doped with at least one conductive dopant (e.g., at least one n-type dopant, at least one p-type dopant).

[0031] Next, see Figure 1B The initial stacked structure 106 can be formed on or above the doped semiconductor material 104. For example... Figure 1BAs shown, the initial stack structure 106 comprises a vertically alternating (e.g., in the Z direction) sequence of insulating structures 108 and sacrificial structures 110 arranged in layers 112. Each of the layers 112 of the initial stack structure 106 may include at least one of the sacrificial structures 110 vertically adjacent to at least one of the insulating structures 108. The initial stack structure 106 may be formed to include any desired number of layers 112, for example, more than or equal to sixteen (16) layers 112, more than or equal to thirty-two (32) layers 112, more than or equal to sixty-four (64) layers 112, more than or equal to one hundred and twenty-eight (128) layers 112, or more than or equal to two hundred and fifty-six (256) layers 112.

[0032] The insulating structure 108 of the layer 112 of the preliminary stacked structure 106 may be formed of and contain at least one insulating material, such as at least one dielectric oxide material (e.g., SiO2). x Phosphorosilicate glass, borosilicate glass, borophosphorosilicate glass, fluorosilicate glass, AlO x HfO x NbO x TiO x ZrO x TaO x and MgO x One or more of them), at least one dielectric nitride material (e.g., SiN). y ), and at least one dielectric oxide nitride material (e.g., SiO2). x N y and at least one dielectric carbonitride material (e.g., SiO2) x C z N y One or more of the insulating structures 108. Each of the insulating structures 108 may be generally homogeneous, or may be generally heterogeneous. As used herein, the term "homogeneous" means that the amount of material does not change throughout different parts of the structure (e.g., different horizontal parts, different vertical parts). Conversely, as used herein, the term "heterogeneous" means that the amount of material varies throughout different parts of the structure. In some embodiments, each of the insulating structures 108 is generally homogeneous. In other embodiments, at least one of the insulating structures 108 is generally heterogeneous. One or more of the insulating structures 108 may be formed, for example, by and comprise a stack (e.g., a laminate) of at least two different insulating materials (e.g., at least two different dielectric materials). In some embodiments, each of the insulating structures 108 is made of, for example, SiO2. xThe insulating structure 108 is formed and comprises a dielectric oxide material (e.g., SiO2). Each insulating structure 108 may be substantially flat and may individually exhibit the desired thickness (e.g., vertical height in the Z direction). Furthermore, each of the insulating structures 108 may be substantially the same as each other (e.g., having substantially the same material composition, material distribution, size, and shape), or at least one of the insulating structures 108 may differ from at least one of the other insulating structures 108 (e.g., having one or more of different material compositions, different material distributions, different sizes, and different shapes). In some embodiments, each of the insulating structures 108 is substantially the same as each other.

[0033] The sacrificial structure 110 of the initial stacked structure 106 at level 112 may be formed of and comprise at least one material (e.g., at least one insulating material) that is selectively removable relative to the insulating material of the insulating structure 108. The material composition of the sacrificial structure 110 differs from that of the insulating structure 108. The sacrificial structure 110 may be selectively etched relative to the insulating structure 108 during common (e.g., collectively, mutually) exposure to a first etchant, and the insulating structure 108 may be selectively etched relative to the sacrificial structure 110 during common exposure to different second etchants. As used herein, if a material exhibits an etch rate at least about five times (5×) that of another material, such as about ten times (10×), about twenty times (20×), or about forty times (40×), then the material is “selectively etchable” relative to the other material. As a non-limiting example, the sacrificial structure 110 may be formed of and comprise an additional insulating material, such as at least one dielectric oxide material (e.g., SiO₂). x Phosphorosilicate glass, borosilicate glass, borophosphorosilicate glass, fluorosilicate glass, AlO x HfO x NbO x TiO x ZrO x TaO x and MgO x One or more of them), at least one dielectric nitride material (e.g., SiN). y ), and at least one dielectric oxide nitride material (e.g., SiO2). x N y and at least one dielectric carbonitride material (e.g., SiO2) x C z N y One or more of the following. In some embodiments, each of the sacrificial structures 110 is formed of and contains a dielectric nitride material, such as SiN. y(e.g., Si3N4). Each of the sacrificial structures 110 may be individually substantially homogeneous or substantially heterogeneous. In some embodiments, each of the sacrificial structures 110 of the initial stacked structure 106 is substantially homogeneous. In additional embodiments, at least one of the sacrificial structures 110 of the initial stacked structure 106 is substantially heterogeneous. Each of the sacrificial structures 110 may be substantially flat and may each individually exhibit the desired thickness (e.g., vertical height in the Z direction). Additionally, each of the sacrificial structures 110 may be substantially the same as each other (e.g., exhibiting substantially the same material composition, material distribution, size, and shape), or at least one of the sacrificial structures 110 may be different from at least one of the other sacrificial structures 110 (e.g., exhibiting one or more of different material compositions, different material distributions, different sizes, and different shapes). In some embodiments, each of the sacrificial structures 110 is substantially the same as each other.

[0034] Next, see Figure 1C An opening 114 (e.g., a aperture, a via) may be formed to extend vertically (e.g., in the Z direction) through each of the initial stacked structure 106 and the doped semiconductor material 104 and into the base structure 102. Figure 1C As shown, each of the openings 114 can extend vertically from the uppermost surface of the initial stacked structure 106 to a vertical position between the uppermost and lowermost surfaces of the base structure 102. The openings 114 can be used to form cell pillar structures for forming vertically extending strings of memory cells, as described in further detail below.

[0035] The openings 114 may be individually formed to exhibit a geometry (e.g., size, shape) and spacing. The geometry and spacing of the openings 114 may be selected at least in part based on the configuration and location of other features of the microelectronic device structure 100. For example, the size, shape, and spacing of the openings 114 may be set to facilitate the desired geometry and spacing of additional features (e.g., additional structures, additional materials) subsequently formed therein. In some embodiments, each opening 114 is formed with a generally circular horizontal cross-sectional shape. In additional embodiments, one or more of the openings 114 (e.g., each one) are formed with different (e.g., non-circular) horizontal cross-sectional shapes, such as a quadrilateral horizontal cross-sectional shape (e.g., a square horizontal cross-sectional shape), an oval horizontal cross-sectional shape, an elliptical horizontal cross-sectional shape, a triangular horizontal cross-sectional shape, or one or more of another horizontal cross-sectional shape. Each of the openings 114 may be formed to exhibit substantially the same geometric configuration (e.g., same size and same shape) and horizontal spacing (e.g., in the X direction and in the Y direction) as each of the other openings 114, or at least some of the openings 114 may be formed to exhibit a different geometric configuration (e.g., one or more different sizes, different shapes) and / or different horizontal spacing than at least some of the other openings 114.

[0036] Next, see Figure 1D The unit column structure 116 can be formed in the opening 114 ( Figure 1C The unit column structure 116 can at least partially (e.g., substantially) fill the opening 114. Figure 1C The unit pillar structure 116 may extend vertically (e.g., in the Z direction) through each of the initial stack structure 106 and the doped semiconductor material 104 and into the base structure 102. Figure 1D As shown, each of the unit column structures 116 can extend vertically from the uppermost surface of the initial stacked structure 106 to a vertical position between the uppermost and lowermost surfaces of the base structure 102. The uppermost surface of the unit column structure 116 can be substantially coplanar with the uppermost surface of the initial stacked structure 106, and the lower surface of the unit column structure 116 can lie vertically beneath the uppermost surface of the base structure 102.

[0037] Each of the cell pillar structures 116 may be individually formed from and comprise a stack of materials that facilitates the use of the cell pillar structure 116 to form a vertically extending string of memory cells after subsequent processing operations, as described in further detail below. As a non-limiting example, each of the cell pillar structures 116 may be formed to comprise a first dielectric oxide material 118 (e.g., SiO2). x For example, SiO2; AlO x(e.g., Al2O3), dielectric nitride material 120 (e.g., SiN) y (e.g., Si3N4), second oxide dielectric material 122 (e.g., SiO) x The first dielectric oxide material 118 may be present in the opening 114 (e.g., SiO2), semiconductor material 124 (e.g., Si, such as polycrystalline Si), and dielectric filling material 125 (e.g., dielectric oxide, dielectric nitride, air). Figure 1C The dielectric nitride material 120 may be formed at the boundary (e.g., horizontal boundary, lower vertical boundary) on or above the surface of the microelectronic device structure 100 (e.g., the surface of the initial stacked structure 106, the doped semiconductor material 104, and the base structure 102). The dielectric nitride material 120 may be formed at the opening 114 (…). Figure 1C The second oxide dielectric material 122 may be formed on or above the surface of the first dielectric oxide material 118 within the opening 114. Figure 1C The dielectric nitride material 120 is formed on or above the opening 114. Semiconductor material 124 may be formed in or above the opening 114. Figure 1C The second oxide dielectric material 122 is located on or above the surface of the second oxide dielectric material 122 within the opening. The dielectric filling material 125 may occupy (e.g., fill) the opening 114. Figure 1C The central portion of the unit column structure 116 is not occupied by other features of the unit column structure 116 (e.g., first dielectric oxide material 118, dielectric nitride material 120, second oxide dielectric material 122, semiconductor material 124).

[0038] Next, see Figure 1E The microelectronic device structure 100 can undergo a so-called "replacement gate" or "post-gate" processing operation to at least partially replace the initial stacked structure 106 with a conductive structure 130. Figure 1D The sacrificial structure 110 ( Figure 1D And form a stacked structure 126. For example... Figure 1E As shown, the stacked structure 126 includes a vertically alternating (e.g., in the Z direction) sequence of additional insulating structures 128 and conductive structures 130 arranged in layers 132. After the "gate replacement" processing operation, the additional insulating structure 128 may correspond to the initial stacked structure 106 ( Figure 1D The insulation structure 108 ( Figure 1D The remainder (e.g., remaining portion, unremoved portion). Each of the layers 132 of the stacked structure 126 includes at least one of the conductive structures 130 that are vertically adjacent to at least one of the additional insulating structures 128. Additionally, as Figure 1EAs shown, the deep contact structure 134 may be formed to extend vertically through the stacked structure 126 and into or into the doped semiconductor material 104. The deep contact structure 134 may be electrically isolated from the conductive structure 130 of the layers 132 of the stacked structure 126 by means of an insulating liner structure 136 formed as a horizontal intervening structure between the deep contact structure 134 and the stacked structure 126.

[0039] The conductive structure 130 of the layer 132 of the stacked structure 126 may be formed of and contain a conductive material. By way of a non-limiting example, each of the conductive structures 130 may be individually formed of and contain a metallic material, including one or more of the following: at least one metal, at least one alloy, and at least one material containing a conductive metal (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide). In some embodiments, the conductive structure 130 is formed of and contains W. Each of the conductive structures 130 may be individually substantially homogeneous, or one or more of the conductive structures 130 may be individually substantially heterogeneous. In some embodiments, each of the conductive structures 130 is formed substantially homogeneous. In additional embodiments, each of the conductive structures 130 is formed heterogeneous. Each conductive structure 130 may, for example, be formed of and contain a stack of at least two different conductive materials.

[0040] See also Figure 1E One or more liner materials (e.g., insulating liner materials, conductive liner materials) may be formed around the conductive structure 130. The one or more liner materials may be formed from, for example, one or more of, and include one or more of, the following: metals (e.g., titanium, tantalum), alloys, metal nitrides (e.g., tungsten nitride, titanium nitride, tantalum nitride), and metal oxides (e.g., aluminum oxide). In some embodiments, the liner material includes at least one conductive material used as a seed material for forming the conductive structure 130. In some such embodiments, the liner material includes titanium nitride. In additional embodiments, the liner material further includes aluminum oxide. As a non-limiting example, aluminum oxide may be formed directly adjacent to the additional insulating structure 128, titanium nitride may be formed directly adjacent to aluminum oxide, and tungsten may be formed directly adjacent to titanium nitride. For the purpose of clarity and ease of understanding, Figure 1E One or more lining materials are not shown, but it should be understood that one or more lining materials may be arranged around the conductive structure 130.

[0041] To form the stacked structure 126 through a "gate replacement" process, slots (e.g., slits, trenches) may be formed to extend vertically through the initial stacked structure 106. Figure 1D To form discrete blocks. Subsequently, the initial stacked structure 106 ( Figure 1D The sacrificial structure 110 ( Figure 1D The portion of the conductive structure 130 can be selectively removed via a trench (e.g., selective etching and excavation) and replaced with a conductive material to form a conductive structure 130. Some conductive structures 130 can serve as access line structures (e.g., word line structures) for microelectronic devices (e.g., memory devices, such as 3D NAND flash memory devices) subsequently formed using the microelectronic device structure 100, and other conductive structures 130 can serve as select gate structures for the subsequently formed microelectronic devices. After forming the conductive structure 130, the trench can be filled with at least one dielectric material.

[0042] Continue to refer to Figure 1E The intersection of the conductive structure 130 of the unit pillar structure 116 and the layer 132 of the stacked structure 126 may define a series of vertically extending memory cells 138 coupled in series with each other within the stacked structure 126. In some embodiments, the memory cells 138 formed at the intersection of the conductive structure 130 and the unit pillar structure 116 within the layer 132 of the stacked structure 126 include so-called "MONOS" (metal-oxide-nitride-oxide-semiconductor) memory cells. In additional embodiments, the memory cells 138 include so-called "TANOS" (tantalum nitride-aluminum oxide-nitride-oxide-semiconductor) memory cells or so-called "BETANOS" (band / barrier engineered TANOS) memory cells, each of which is a subset of MONOS memory cells. In other embodiments, the memory cells 138 include so-called "floating gate" memory cells, which include a floating gate (e.g., a metal floating gate) as a charge storage structure. The floating gate can be horizontally inserted between the central structure of the unit column structure 116 and the conductive structures 130 of different levels 132 of the stacked structure 126.

[0043] The deep contact structure 134 can be configured and positioned to electrically connect one or more features subsequently formed above the stacked structure 126 to one or more other features underlying the stacked structure 126 (e.g., doped semiconductor material 104, additional features to be subsequently formed and coupled to the doped semiconductor material 104). The deep contact structure 134 may be formed of and contain a conductive material. In some embodiments, the deep contact structure 134 is formed of and contains W. In additional embodiments, the deep contact structure 134 is formed of and contains conductive doped polysilicon.

[0044] The insulating liner structure 136 extends continuously above and substantially covers the side surface of the deep contact structure 134. The insulating liner structure 136 may be formed over and comprise at least one insulating material, such as at least one dielectric oxide material (e.g., SiO2). xPhosphorosilicate glass, borosilicate glass, borophosphorosilicate glass, fluorosilicate glass, AlO x HfO x NbO x TiO x ZrO x TaO x and MgO x One or more of them), at least one dielectric nitride material (e.g., SiN). y ), and at least one dielectric oxide nitride material (e.g., SiO2). x N y and at least one dielectric carbonitride material (e.g., SiO2) x C z N y One or more of the insulating liner structures 136. In some embodiments, each of the insulating liner structures 136 is made of at least one dielectric oxide material (e.g., SiO2). x Formed with at least one dielectric oxide material (e.g., SiO2) and containing at least one dielectric oxide material (e.g., SiO2). x (e.g., SiO2).

[0045] Next, see Figure 1F Digital line structures 139 (e.g., data line structures, bit line structures), insulating line structures 140, digital line contact structures 142, bonding pads 144, and insulating material 146 may be formed on or above the stacked structure 126. Digital line structures 139 may be vertically formed above and electrically connected to vertically extending memory cells 138 and deep contact structures 134 strings. Insulating line structures 140 may be formed on or above digital line structures 139. Digital line contact structures 142 may extend vertically through insulating line structures 140 and may contact digital line structures 139. For each digital line contact structure 142, a first portion 142A may vertically cover one of the insulating line structures 140, and a second portion 142B may extend vertically through insulating line structures 140 and contact (e.g., physical contact, electrical contact) one of the digital line structures 139. Bonding pads 144 may be formed on or above digital line contact structures 142. The insulating material 146 may cover and surround portions of the stacked structure 126, the digital line structure 139, the insulating line structure 140, the digital line contact structure 142, and the bonding pad 144.

[0046] Digital line structures 139 may exhibit a horizontally elongated shape extending parallel to a first horizontal direction (e.g., the Y direction). As used herein, the term "parallel" means substantially parallel. Digital line structures 139 may each exhibit substantially the same dimensions (e.g., width in the X direction, length in the Y direction, height in the Z direction), shape, and spacing (e.g., in the X direction). In additional embodiments, one or more of the digital line structures 139 may exhibit at least one or more different dimensions (e.g., different lengths, different widths, different heights) and different shapes compared to one or more other digital line structures 139, and / or the spacing between at least two horizontally adjacent digital line structures 139 (e.g., in the X direction) may differ from the spacing between at least two other horizontally adjacent digital line structures 139.

[0047] The digital line structure 139 may be formed of and contain a conductive material. By way of non-limiting examples, the digital line structure 139 may each be individually formed of and contain a metallic material, said metallic material including one or more of the following: at least one metal, at least one alloy, and at least one material containing a conductive metal (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide). In some embodiments, the digital line structures 139 are each individually formed of and contain W. Each of the digital line structures 139 may be individually substantially homogeneous, or one or more of the digital line structures 139 may be individually substantially heterogeneous. If the digital line structure 139 is heterogeneous, then the amount of one or more elements contained in the digital line structure 139 may change gradually (e.g., abruptly) or continuously (e.g., gradually, such as linearly, parabolically). In some embodiments, each of the digital line structures 139 is substantially homogeneous. In an additional embodiment, each of the digital line structures 139 is heterogeneous. Each digital line structure 139 may be formed, for example, by and comprise a stack of at least two different conductive materials.

[0048] The insulated wire structure 140 may serve as an insulating cap structure (e.g., a dielectric cap structure) for the digital line structure 139. The insulated wire structure 140 may have a horizontally elongated shape extending parallel to a first horizontal direction (e.g., the Y direction). The horizontal dimensions, horizontal path, and horizontal spacing of the insulated wire structure 140 may be substantially the same as those of the digital line structure 139.

[0049] The insulated wire structure 140 may be formed of and contain an insulating material. By way of a non-limiting example, the insulated wire structure 140 may each be individually made of, for example, SiN. yThe insulating wire structure 140 is formed and comprises a dielectric nitride material (e.g., Si3N4). Each of the insulating wire structures 140 may be substantially homogeneous, or one or more of the insulating wire structures 140 may be heterogeneous. If the insulating wire structure 140 is heterogeneous, the amount of one or more elements contained in the insulating wire structure 140 may change gradually (e.g., abruptly) or continuously (e.g., gradually, such as linearly, parabolically). In some embodiments, each of the insulating wire structures 140 is substantially homogeneous. In additional embodiments, each of the insulating wire structures 140 is heterogeneous. Each insulating wire structure 140 may be formed and comprises, for example, a stack of at least two different dielectric materials.

[0050] See also Figure 1F Individual digital line contact structures 142 may be at least partially (e.g., substantially) horizontally aligned in the X direction with individual insulating line structures 140 (and therefore with individual digital line structures 139). For example, the horizontal centerline of the digital line contact structure 142 in the X direction may be substantially aligned with the horizontal centerline of the insulating line structure 140 in the X direction. Additionally, the digital line contact structures 142 may be formed at desired locations along the Y direction of the insulating line structure 140 (and therefore along the digital line structure 139). In some embodiments, at least some of the digital line contact structures 142 are disposed at different locations relative to each other in the Y direction. For example, the first digital line contact structure 142 may be disposed at different locations along the length of the first insulating line structure 140 in the Y direction relative to the location of the second digital line contact structure 142 along the length of the second insulating line structure 140 in the Y direction. In other words, at least some (e.g., all) of the digital line contact structures 142 may be horizontally offset relative to each other in the Y direction. In an additional embodiment, two or more of the digital line contact structures 142 are horizontally aligned with each other in the Y direction. In some embodiments, the digital line contact structures 142 serve as digital line contact structures (e.g., data line contact structures, bit line contact structures) for a microelectronic device (e.g., a memory device) formed from the microelectronic device structure 100 to be used, as described in further detail below.

[0051] The digital line contact structure 142 can be formed to represent a desired geometric configuration (e.g., desired size, desired shape). Figure 1FAs shown, in some embodiments, a first portion 142A (e.g., an upper portion) of an individual digital line contact structure 142 is formed to be wider than a second portion 142B (e.g., a lower portion) of the digital line contact structure 142. The side surfaces of the insulating material 146 may define the horizontal boundaries of the digital line contact structure 142. The digital line contact structure 142 may extend vertically (e.g., in the Z direction) from the lower vertical boundary (e.g., the lower surface) of the engagement pad 144 to the upper vertical boundary (e.g., the upper surface) of the digital line structure 139.

[0052] The digital line contact structure 142 may each be individually formed of and contain a conductive material. By means of non-limiting examples, the digital line contact structure 142 may be formed of and contain one or more of the following: at least one metal, at least one alloy, and at least one material containing a conductive metal (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide). In some embodiments, the digital line contact structure 142 is formed of Cu and contains Cu. In additional embodiments, the digital line contact structure 142 is formed of W and contains W.

[0053] Bonding pads 144 may be formed on or above the upper surface of the digital line contact structure 142. Bonding pads 144 may be formed to extend horizontally over the plurality of insulated line structures 140 (and therefore over the plurality of digital line structures 139). Individual bonding pads 144 may be coupled to individual digital line contact structures 142. Bonding pads 144 may be used to couple digital line contact structures 142 to additional bonding pads and additional conductive contact structures, as described in further detail below.

[0054] The bonding pads 144 may each be individually formed of and contain a conductive material. By way of non-limiting examples, the bonding pads 144 may be formed of and contain one or more of the following: at least one metal, at least one alloy, and at least one material containing a conductive metal (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide). The material composition of the bonding pads 144 may be substantially the same as that of the digital line contact structure 142, or the material composition of the bonding pads 144 may be different from that of the digital line contact structure 142. In some embodiments, the bonding pads 144 are formed of and contain Cu.

[0055] See also Figure 1F The insulating material 146 may be formed of and contain at least one insulating material. By way of non-limiting examples, the insulating material 146 may be formed of and contain one or more of the following: at least one dielectric oxide material (e.g., SiO2). xPhosphorosilicate glass, borosilicate glass, borophosphorosilicate glass, fluorosilicate glass, AlO x HfO x NbO x and TiO x One or more of them), at least one dielectric nitride material (e.g., SiN). y ), and at least one dielectric oxide nitride material (e.g., SiO2). x N y and at least one dielectric carbonitride material (e.g., SiO2) x C z N y In some embodiments, the insulating material 146 is made of SiO2. x (For example, SiO2) is formed and contains SiO x (e.g., SiO2). The insulating material 146 may be substantially homogeneous or heterogeneous. If the insulating material 146 is heterogeneous, the amount of one or more elements contained in the insulating material 146 may vary gradually (e.g., abruptly) or continuously (e.g., gradually, such as linearly or parabolically). In some embodiments, the insulating material 146 is substantially homogeneous. In additional embodiments, the insulating material 146 is heterogeneous. The insulating material 146 may be formed, for example, from and comprise a stack of at least two different dielectric materials.

[0056] In previous reference Figure 1F Following the described process stages, the microelectronic device structure 100 can be used to form the microelectronic device of this disclosure (e.g., a memory device, such as a 3D NAND flash memory device). By way of non-limiting examples, Figures 2A to 2H This is a simplified partial cross-sectional view illustrating a method for forming a microelectronic device according to an embodiment of the present disclosure. From the description provided below, it will be apparent to those skilled in the art that the methods and structures described herein can be used to form various devices and electronic systems.

[0057] See Figure 2A This can form the structure 100 to be subsequently attached to the microelectronic device. Figure 1F Additional microelectronic device structure 200. Additional microelectronic device structure 200 may be formed to include semiconductor substrate structure 202, gate structure 204, first wiring structure 206, first contact structure 208, second contact structure 210, additional bonding pad 212, and additional isolation material 214. Additional microelectronic device structure 200 may be formed subsequently used with microelectronic device structure 100. Figure 1FThe control logic region 216 of the microelectronic device formed by the additional microelectronic device structure 200 is described in further detail below. Various control logic devices 218 that form the control logic region 216 in portions of the semiconductor base structure 202, gate structure 204, first wiring structure 206, and first contact structure 208 of the additional microelectronic device structure 200 are also described in further detail below.

[0058] The semiconductor substrate structure 202 (e.g., a semiconductor wafer) of the additional microelectronic device structure 200 includes a substrate material or construction on which additional features (e.g., materials, structures, devices) of the additional microelectronic device structure 200 are formed. The semiconductor substrate structure 202 may include a semiconductor structure (e.g., a semiconductor wafer) or a substrate semiconductor material on a support structure. For example, the semiconductor substrate structure 202 may include a conventional silicon substrate (e.g., a conventional silicon wafer) or another bulk substrate comprising semiconductor material. In some embodiments, the semiconductor substrate structure 202 includes a silicon wafer. Additionally, the semiconductor substrate structure 202 may include one or more layers, structures, and / or regions formed therein and / or on it. For example, the semiconductor substrate structure 202 may include conductive doped regions and undoped regions. The conductive doped regions may, for example, serve as source and drain regions of transistors in the control logic device 218 of the control logic region 216; and the undoped regions may, for example, serve as channel regions of transistors in the control logic device 218.

[0059] like Figure 2A As shown, the gate structure 204 of the control logic region 216 of the additional microelectronic device structure 200 may vertically overlay (e.g., in the Z direction) a portion of the semiconductor substrate structure 202. The gate structure 204 may individually extend horizontally between and be used by the transistors of the control logic devices 218 within the control logic region 216 of the additional microelectronic device structure 200. The gate structure 204 may be formed of and contain a conductive material. A gate dielectric material (e.g., dielectric oxide) may vertically intersect (e.g., in the Z direction) between the gate structure 204 and the channel region of the transistor (e.g., within the semiconductor substrate structure 202).

[0060] The first wiring structure 206 may be vertically superimposed (e.g., in the Z direction) on the semiconductor base structure 202 and may be electrically connected to the semiconductor base structure 202 by means of the first contact structure 208. The first wiring structure 206 may serve as a subsequent additional microelectronic device structure 200 and microelectronic device structure 100. Figure 1FThis refers to the local wiring structure of a microelectronic device. A first group 208A of the first contact structures 208 may extend vertically between regions (e.g., conductive doped regions, such as source and drain regions) of the semiconductor substrate structure 202 and couple these regions to one or more of the first wiring structures 206. Additionally, a second group 208B of the first contact structures 208 may extend vertically between some of the first wiring structures 206 and couple these regions to each other.

[0061] The first wiring structure 206 may each be individually formed of and contain a conductive material. By means of non-limiting examples, the first wiring structure 206 may be formed of and contain one or more of the following: at least one metal, at least one alloy, and at least one material containing a conductive metal (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide). In some embodiments, the first wiring structure 206 is formed of Cu and contains Cu. In additional embodiments, the first wiring structure 206 is formed of W and contains W.

[0062] The first contact structure 208 (including its first group 208A and second group 208B) may each be individually formed of and contain a conductive material. By means of non-limiting examples, the first wiring structure 206 may be formed of and contain one or more of the following: at least one metal, at least one alloy, and at least one material containing a conductive metal (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide). In some embodiments, the first contact structure 208 is formed of Cu and contains Cu. In additional embodiments, the first contact structure 208 is formed of W and contains W. In other embodiments, the first contact structure 208 in the first group 208A of the first contact structure 208 is formed of and contains a first conductive material (e.g., W); and the first contact structure 208 in the second group 208B of the first contact structure 208 is formed of and contains a different second conductive material (e.g., Cu).

[0063] As previously mentioned, portions of the semiconductor base structure 202 (e.g., conductive doped regions acting as source and drain regions, and undoped regions acting as channel regions), the gate structure 204, the first wiring structure 206, and the first contact structure 208 form various control logic devices 218 of the control logic region 216. In some embodiments, the control logic device 218 includes a complementary metal-oxide-semiconductor (CMOS) circuit system. The control logic device 218 may be configured to control various operations of other components (e.g., memory cells) of a microelectronic device (e.g., a memory device) subsequently formed using the additional microelectronic device structure 200 and the microelectronic device structure 100 (FIG. 1G). As a non-limiting example, the control logic device 218 may include one or more (or each) of the following: a charge pump (e.g., V0) CCP Charge pump, V NEGWL Charge pumps, DVC2 charge pumps), delay-locked loop (DLL) circuit systems (e.g., ring oscillators), V dd Adjusters, drivers (e.g., string drivers), page buffers, decoders (e.g., layer decoders, row decoders, column decoders), sense amplifiers (e.g., equalization (EQ) amplifiers, isolation (ISO) amplifiers, NMOS sense amplifiers (NSA), PMOS sense amplifiers (PSA)), maintenance circuitry (e.g., column maintenance circuitry, row maintenance circuitry), I / O devices (e.g., local I / O devices), memory test devices, array multiplexers (MUX), error checking and correction (ECC) devices, self-refresh / loss equalization devices, and other chip / layer control circuitry systems.

[0064] Continue to refer to Figure 2A The second contact structure 210 of the additional microelectronic device structure 200 may vertically overlay and couple to some of the first wiring structures 206 of the control logic region 216. In some embodiments, the second contact structure 210 includes a conductive filled via extending vertically through a portion of additional insulating material 214 inserted between the additional bonding pad 212 and the first wiring structure 206. The second contact structure 210 may be formed of and contain a conductive material. By way of non-limiting examples, the second contact structure 210 may be formed of and contain one or more of the following: at least one metal, at least one alloy, and at least one material containing a conductive metal (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide). In some embodiments, each of the second contact structures 210 is formed of and contains Cu.

[0065] An additional bonding pad 212 of the additional microelectronic device structure 200 may be vertically overlaid on and coupled to the second contact structure 210. The second contact structure 210 may extend vertically from and between the additional bonding pad 212 and some of the first wiring structures 206. The additional bonding pad 212 may be configured and positioned to attach to the microelectronic device structure ( Figure 1F ) joint liner 144 ( Figure 1F The additional bonding pad 212 is formed to form the connected bonding pad, as described in further detail below. The additional bonding pad 212 may be formed of and contain a conductive material. By means of non-limiting examples, the additional bonding pad 212 may be formed of and contain one or more of the following: at least one metal, at least one alloy, and at least one material containing a conductive metal (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide). In some embodiments, each of the additional bonding pads 212 is formed of and contains Cu.

[0066] See also Figure 2A Additional insulating material 214 may cover and surround at least a portion of the first wiring structure 206, the second contact structure 210, and the additional bonding pad 212. In the use of microelectronic device structure 100 ( Figure 1F In the process of forming a microelectronic device (e.g., a memory device) and additional microelectronic device structure 200, additional insulating material 214 may subsequently be attached to the microelectronic device structure 100. Figure 1F ) isolation material 146 ( Figure 1F The material composition of the additional insulating material 214 may be the same as that of the insulating material 146, as described in further detail below. Figure 1F The material composition of the additional insulating material 214 is generally the same as that of the insulating material 146, or the material composition of the additional insulating material 214 may be different from that of the insulating material 146. Figure 1F The additional insulating material 214 is composed of at least one material, such as SiO2. x The dielectric oxide material (e.g., SiO2) is formed and comprises the dielectric oxide material. In an additional embodiment, the additional insulating material 214 is formed and comprises at least one low-k dielectric material, such as SiO2. x C y SiO x N y SiC x O y H z and SiO x C z N yOne or more of the following. The additional insulating material 214 may be substantially homogeneous or heterogeneous. In some embodiments, the additional insulating material 214 is substantially homogeneous. In additional embodiments, the additional insulating material 214 is heterogeneous. The additional insulating material 214 may be formed, for example, from and comprise a stack of at least two different dielectric materials.

[0067] Next, see Figure 2B After forming the microelectronic device structure 100 and separately forming the additional microelectronic device structure 200, the microelectronic device structure 100 can be vertically reversed (e.g., flipped in the Z direction) and attached (e.g., bonded) to the additional microelectronic device structure 200 to form a microelectronic device structure assembly 220. Alternatively, the additional microelectronic device structure 200 can be vertically reversed (e.g., flipped in the Z direction) and attached to the microelectronic device structure 100 to form the microelectronic device structure assembly 220. The attachment of the microelectronic device structure 100 to the additional microelectronic device structure 200 may attach the bonding pad 144 of the microelectronic device structure 100 to the additional bonding pad 212 of the additional microelectronic device structure 200 to form a connected bonding pad 222. Additionally, the attachment of the microelectronic device structure 100 to the additional microelectronic device structure 200 may also attach the insulating material 146 of the microelectronic device structure 100 to the additional insulating material 214 of the additional microelectronic device structure 200. Figure 2B As shown, the attachment of microelectronic device structure 100 to additional microelectronic device structure 200 can form a first interconnect region 224 of a microelectronic device (e.g., a memory device, such as a 3D NAND flash memory device) subsequently formed using microelectronic device structure assembly 220. Figure 2B In the diagram, before the microelectronic device structure 100 is attached to the additional microelectronic device structure 200 to form the microelectronic device structure assembly 220, the vertical boundary of the microelectronic device structure 100 relative to the additional microelectronic device structure 200 is depicted by a dashed line AA. The microelectronic device structure 100 can be attached to the additional microelectronic device structure 200 without bonding wires.

[0068] like Figure 2BAs shown, the bonding pads 222 of the first interconnect region 224 extend vertically from and between the digital line contact structure 142 of the microelectronic device structure 100 and the second contact structure 210 of the additional microelectronic device structure 200. Additional bonding pads 212 of the bonded bonding pads 222 extend vertically from and between the second contact structure 210 and the bonding pads 144 of the bonded bonding pads 222; and the bonding pads 144 of the bonded bonding pads 222 extend vertically from and between the digital line contact structure 142 and the additional bonding pads 212 of the bonded bonding pads 222. Figure 2B In this design, the additional coupling pads 212 and 144 in each connected coupling pad 222 are distinguished from each other by dashed lines. The additional coupling pads 212 and 144 can be integral and continuous with each other. In other words, each connected coupling pad 222 can be generally a monolithic structure, comprising an additional coupling pad 212 as its first region and a coupling pad 144 as its second region. For each connected coupling pad 222, its additional coupling pad 212 can be attached to its coupling pad 144 without a coupling line.

[0069] Next, see Figure 2C In the microelectronic device structure 100 ( Figure 2B After being attached to the additional microelectronic device structure 200, the base structure 102 can be removed (e.g., by conventional disassembly and / or conventional polishing processes). Figure 2B The material removal process may expose (e.g., expose) the doped semiconductor material 104 and a portion of the unit pillar structure 116. In some embodiments, the material removal process also exposes the remaining (e.g., unremoved) portion of the unit pillar structure 116. The upper surfaces of the doped semiconductor material 104 and the unit pillar structure 116 may be substantially coplanar with each other after the material removal process, or the upper surfaces of the doped semiconductor material 104 and the unit pillar structure 116 may be vertically offset from each other after the material removal process. Additionally, optionally, during the removal of the base structure 102 ( Figure 2BSubsequently, an additional amount (e.g., additional volume) of doped semiconductor material (e.g., doped polysilicon) may be formed on the doped semiconductor material 104. If formed, the additional amount of doped semiconductor material may have a material composition substantially the same as that of the doped semiconductor material 104, or may have a material composition different from that of the doped semiconductor material 104. Additionally, optionally, a bridging material 226 may be optionally formed on or above the doped semiconductor material 104. Before and / or after the formation of the bridging material 226 (if present), the doped semiconductor material 104 (and the additional amount of doped semiconductor material (if present)) may optionally be annealed (e.g., thermally annealed). For example, annealing the doped semiconductor material 104 may promote or enhance the activation of the dopant within the doped semiconductor material 104.

[0070] If formed, the bridging material 226 may be formed of and contain a conductive material. By way of a non-limiting example, the bridging material 226 (if present) may be formed of and contain a metallic material, said metallic material including one or more of the following: at least one metal, at least one alloy, and at least one material containing a conductive metal (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide). In some embodiments, the bridging material 226 is made of tungsten silicide (WSi). x ) formed and containing tungsten silicide (WSi) x In an additional embodiment, the bridging material 226 is composed of W and tungsten nitride (WN). x One or more of W and tungsten nitride (e.g., stacked) are formed and include one or more of W and tungsten nitride (e.g., stacked).

[0071] Next, see Figure 2D After removing the base structure 102 ( Figure 2B After that, a portion of the doped semiconductor material 104 (and an additional amount of doped semiconductor material (if present)) Figure 2C ) and bridging material 226 ( Figure 2C (If present) can be removed (e.g., etched) from the doped semiconductor material 104 ( Figure 2C ) forming one or more source structures 228 and one or more contact pads 230, and from the bridging material 226 ( Figure 2C (If present) Forms a bridging structure 232. For example... Figure 2DAs shown, forming one or more source structures 228 and one or more contact pads 230 can form a memory array region 237 of a microelectronic device (e.g., a memory device) subsequently formed using the microelectronic device structure assembly 220. The memory array region 237 may include a stacked structure 126; a cell pillar structure 116; a deep contact structure 134; a digital line structure 139; an insulated wire structure 140; and a portion of a digital line contact structure 142 (e.g., a second portion 142B). Figure 1F )); and source layer 235, which includes one or more source structures 228, one or more contact pads 230 and bridging structure 232 (if present).

[0072] Within the source hierarchy 235 of memory array region 237, one or more source structures 228 and one or more contact pads 230 may be horizontally adjacent to each other (e.g., in the X direction and in the Y direction). The one or more source structures 228 may be electrically isolated from the one or more contact pads 230 and may be positioned at substantially the same vertical location as the one or more contact pads 230 (e.g., in the Z direction). The one or more source structures 228 may be coupled to a vertically extending string of memory cells 138. The one or more contact pads 230 may be coupled to additional conductive features within the stacked structure 126, such as one or more of the deep contact structures 134.

[0073] The above text is about Figures 1A to 1F as well as Figures 2A to 2C The described processing actions occur after (e.g., subsequently, thereafter) other features of the memory array region 237 and within the microelectronic device structure 100. Figure 2B After being attached to the additional microelectronic device structure 200, one or more source structures 228, one or more contact pads 230, and bridging structures 232 (if present) are formed.

[0074] Next, see Figure 2E A third contact structure 234 may be formed above and electrically connected to one or more source structures 228 and one or more contact pads 230, and a second wiring structure 236 may be formed above and electrically connected to the third contact structure 234. The third contact structure 234 may be formed to extend between the second wiring structure 236 and one or more source structures 228 and one or more contact pads 230 of the source layer 235. If present, a bridging structure 232 may be vertically inserted between the third contact structure 234 and one or more source structures 228 and one or more contact pads 230. The third contact structure 234 may, for example, be formed on the upper surface of the bridging structure 232. Additionally, as... Figure 2EAs shown, at least one insulating material 238 may be formed to cover and surround the third contact structure 234 and the second wiring structure 236. At least one insulating material 238 may also be formed to cover and surround portions of one or more source structures 228 and one or more contact pads 230.

[0075] The third contact structure 234 and the second wiring structure 236 may each be formed of and contain a conductive material. By means of non-limiting examples, the third contact structure 234 and the second wiring structure 236 may each be individually formed of and contain one or more of the following: at least one metal, at least one alloy, and at least one material containing a conductive metal (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide). In some embodiments, the third contact structure 234 and the second wiring structure 236 are each formed of and contain Cu. In additional embodiments, the third contact structure 234 is formed of and contains W, and the second wiring structure 236 is formed of and contains Cu.

[0076] See also Figure 2E In some embodiments, the insulating material 238 is composed of at least one, such as SiO2. x The dielectric oxide material (e.g., SiO2) is formed and comprises the dielectric oxide material. In an additional embodiment, the insulating material 238 is formed and comprises at least one low-k dielectric material, such as SiO2. x C y SiO x N y SiC x O y H z and SiO x C z N y One or more of the elements. The insulating material 238 may be substantially homogeneous or heterogeneous. If the insulating material 238 is heterogeneous, the amount of one or more elements contained in the insulating material 238 may vary gradually (e.g., abruptly) or continuously (e.g., gradually, such as linearly or parabolically). In some embodiments, the insulating material 238 is substantially homogeneous. In additional embodiments, the insulating material 238 is heterogeneous. The insulating material 238 may be formed, for example, by and comprise a stack of at least two different dielectric materials.

[0077] In an additional embodiment, one or more capacitors (e.g., one or more metal-insulator-metal (MIM) capacitors; one or more metal-insulator-semiconductor (MIS) capacitors) may be formed in the above-referenced document. Figure 2EThe described processing stage. Using non-restricted instances, Figure 2F and 2G This is a simplified partial cross-sectional view illustrating an embodiment of the present disclosure, wherein a capacitor is formed in the previously referenced... Figure 2D The source level described is above 235. Figure 2F An embodiment of this disclosure is shown, wherein one or more MIM capacitors are formed above source layer 235. Figure 2G An embodiment of this disclosure is shown, wherein one or more MIS capacitors are formed above source layer 235.

[0078] See Figure 2F In some embodiments, one or more MIM capacitors 240 are formed above the source layer 235. Each MIM capacitor 240 may include a portion of a portion of a portion of a bridging structure 232, an insulating structure 242 on or above the bridging structure 232, and a portion of a third contact structure 234 on or above the insulating structure 242. The portion of the bridging structure 232 may serve as a first metal structure of the MIM capacitor 240, the third contact structure 234 may serve as a second metal structure of the MIM capacitor 240, and the insulating structure 242 may be interposed between the bridging structure 232 and the third contact structure 234. Figure 2F As shown, for an individual MIM capacitor 240, its insulating structure 242 may be positioned directly adjacent to the lower and side surfaces of the third contact structure 234. The insulating structure 242 may be inserted between the lower surface of the third contact structure 234 and the upper surface of the bridging structure 232 associated with the MIM capacitor 240, and may also be inserted between the side surface of the third contact structure 234 and the side surface of the insulating material 238 horizontally surrounding the third contact structure 234. In an additional embodiment, a metal structure (e.g., a metal structure, an alloy structure) is formed between the bridging structure 232 and the insulating structure 242, and serves as the first metal structure of the MIM capacitor 240.

[0079] The insulating structure 242 of an individual MIM capacitor 240 may be formed of and contain an insulating material. For example, the insulating structure 242 may be formed of and contain at least one dielectric oxide material, such as one or more SiO2 materials. x Phosphosilicate glass; Borosilicate glass; Borophosphosilicate glass, fluorosilicate glass; AlO x ; and high k-value oxides, such as HfO x NbO x and TiO x One or more of them. In some embodiments, the insulating structure 242 is made of at least one high-k oxide (e.g., HfO). x NbO x and TiO xIt is formed by one or more of the above and includes at least one high-k oxide. In an additional embodiment, the insulating structure 242 is made of SiO2. x (For example, SiO2) is formed and contains SiO x (For example, SiO2).

[0080] The MIM capacitor 240 can be formed using conventional processes (e.g., conventional material deposition processes, conventional material removal processes, such as conventional etching processes) and conventional processing equipment, which are not described in detail herein. One or more photomasks (e.g., one or more i-line photomasks) can be used to protect the insulating material (e.g., high-k oxide) of one or more insulating structures 242 during the patterning and etching processes used to form one or more MIM capacitors 240.

[0081] Next, see Figure 2G In an additional embodiment, one or more MIS capacitors 244 are formed above the source layer 235. Each MIS capacitor 244 may include a portion of a particular source structure 228, an insulating structure 246 on or above the source structure 228, and a metal structure 248 on or above the insulating structure 246. The metal structure 248 may serve as the metal structure of the MIS capacitor 244, a portion of the source structure 228 may serve as the semiconductor structure (e.g., a conductive doped semiconductor structure) of the MIS capacitor 244, and the insulating structure 246 may be interposed between the source structure 228 and the metal structure 248. Figure 2G As shown, for an individual MIS capacitor 244, its insulating structure 246 can be inserted between the lower surface of the metal structure 248 and the upper surface of the source structure 228 associated with the MIS capacitor 244. Figure 2G As shown, the bridging structure 232 ( Figure 2E The bridging structure 232 may not be vertically positioned between and in contact with the insulating structure 246 of the source structure 228 and the MIS capacitor 244. In some such embodiments, the bridging structure 232 is omitted (e.g., omitted) from the upper surface of one or more source structures 228 and one or more contact pads 230 of the source layer 235. In additional embodiments, the bridging structure 232 is formed above a portion of the upper surface of one or more source structures 228 and one or more contact pads 230 outside the horizontal boundary of one or more MIS capacitors 244, but omitted from other portions of the upper surface of one or more source structures 228 within the horizontal boundary of one or more MIS capacitors 244.

[0082] The insulating structure 246 of an individual MIS capacitor 244 may be formed of and contain an insulating material. For example, the insulating structure 246 may be formed of and contain at least one dielectric oxide material, such as one or more SiO2 materials. xPhosphosilicate glass; Borosilicate glass; Borophosphosilicate glass, fluorosilicate glass; AlO x ; and high k-value oxides, such as HfO x NbO x and TiO x One or more of them. In some embodiments, the insulating structure 246 is made of at least one high-k oxide (e.g., HfO). x NbO x and TiO x It is formed by one or more of the above and includes at least one high-k oxide. In an additional embodiment, the insulating structure 246 is made of SiO2. x (For example, SiO2) is formed and contains SiO x (For example, SiO2).

[0083] See also Figure 2G The metal structure 248 of an individual MIS capacitor 244 may be formed of and contain a metal material, which includes one or more of the following: at least one metal, at least one alloy, and at least one material containing a conductive metal (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide). In some embodiments, the metal structure 248 of one or more MIS capacitors 244 is formed of and contains W.

[0084] One or more MIS capacitors 244 can be formed using conventional processes (e.g., conventional material deposition processes, conventional material removal processes, such as conventional etching processes) and conventional processing equipment, the processes of which are not described in detail herein. One or more photomasks (e.g., one or more i-line photomasks) can be used to protect the insulating material (e.g., high k-value oxide) of one or more insulating structures 246 during the patterning and etching processes used to form one or more MIS capacitors 244.

[0085] Return to view Figure 2E After the second wiring structure 236 is formed, the microelectronic device structure assembly 220 may undergo additional processing to couple additional features to the second wiring structure 236. For example, see... Figure 2H A fourth contact structure 250 may be formed above and electrically connected to the second wiring structure 236, and a conductive pad 252 may be formed above and electrically connected to the fourth contact structure 250. The fourth contact structure 250 may be formed to extend between the second wiring structure 236 and the conductive pad 252. The fourth contact structure 250 may, for example, be formed on the upper surface of the second wiring structure 236, and the conductive pad 252 may be formed on the upper surface of the fourth contact structure 250. Additionally, as... Figure 2HAs shown, at least one additional insulating material 254 may be formed to cover and surround the fourth contact structure 250 and the conductive pad 252. At least one additional insulating material 254 may also be formed to cover and surround portions of the second wiring structure 236 and the insulating material 238.

[0086] The fourth contact structure 250 and the conductive pad 252 may each be formed of and contain a conductive material. By means of non-limiting examples, the fourth contact structure 250 and the conductive pad 252 may each be formed of and contain one or more of the following: at least one metal, at least one alloy, and at least one material containing a conductive metal (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide). In some embodiments, the fourth contact structure 250 is formed of and contains W, and the conductive pad 252 is formed of and contains Al.

[0087] See also Figure 2H The material composition of the additional insulating material 254 may be substantially the same as that of the insulating material 238, or the material composition of the additional insulating material 254 may be different from that of the insulating material 238. In some embodiments, the additional insulating material 254 is composed of at least one, for example, SiO2. x The dielectric oxide material (e.g., SiO2) is formed and comprises the dielectric oxide material. In an additional embodiment, the additional insulating material 254 is formed of and comprises at least one low-k dielectric material, such as SiO2. x C y SiO x N y SiC x O y H z and SiO x C z N y One or more of the elements. The additional insulating material 254 may be substantially homogeneous or heterogeneous. If the additional insulating material 254 is heterogeneous, the amount of one or more elements contained in the additional insulating material 254 may vary gradually (e.g., abruptly) or continuously (e.g., gradually, such as linearly or parabolically) throughout different portions of the additional insulating material 254. In some embodiments, the additional insulating material 254 is substantially homogeneous. In additional embodiments, the additional insulating material 254 is heterogeneous. The additional insulating material 254 is formed, for example, by and includes a stack of at least two different dielectric materials.

[0088] like Figure 2HAs shown, forming a fourth contact structure 250, a conductive pad 252, and additional insulating material 254 can form a second interconnect region 256. The second interconnect region 256 may include a third contact structure 234, a second wiring structure 236, insulating material 238, a fourth contact structure 250, conductive pad 252, and additional insulating material 254. Furthermore, the formation of the second interconnect region 256 enables the formation of a microelectronic device 258 (e.g., a memory device, such as a 3D NAND flash memory device). The microelectronic device 258 may include a control logic region 216, a first interconnect region 224, a memory array region 237, and the second interconnect region 256. At least the second wiring structure 236 and the conductive pad 252 of the second interconnect region 256 can serve as the global wiring structure of the microelectronic device 258. The second wiring structure 236 and the conductive pad 252 may, for example, be configured to receive global signals from an external bus and transfer global signals to other components (e.g., structures, devices) of the microelectronic device 258.

[0089] Therefore, according to embodiments of this disclosure, a method of forming a microelectronic device includes forming a microelectronic device structure. The microelectronic device structure includes a base structure, a doped semiconductor material overlying the base structure, a stacked structure overlying the doped semiconductor material and including a vertically alternating sequence of electrical and insulating structures, a cell pillar structure extending vertically through the stacked structure and the doped semiconductor material and extending into the base structure, and a digital line structure vertically overlying the stacked structure. An additional microelectronic device structure including control logic devices is formed. The microelectronic device structure is attached to the additional microelectronic device structure to form a microelectronic device structure assembly. The digital line structure is vertically inserted within the microelectronic device structure assembly between the stacked structure and the control logic devices. A portion of the base structure and the cell pillar structure extending vertically into the base structure is removed to expose the doped semiconductor material. After removing portions of the base structure and the cell pillar structure, the doped semiconductor material is patterned to form at least one source structure above the stacked structure and coupled to the cell pillar structure.

[0090] Furthermore, according to embodiments of this disclosure, the microelectronic device includes a memory array region, a control logic region, a first interconnect region, and a second interconnect region. The memory array region includes: a stacked structure comprising a vertically alternating sequence of conductive and insulating structures; a source structure vertically overlying the stacked structure and including a doped semiconductor material; a cell pillar structure vertically extending completely through the stacked structure and at least partially through the source structure; and a digital line structure vertically lying on the stacked structure and electrically connected to the cell pillar structure. The control logic region vertically lies on the memory array region and includes control logic devices. The first interconnect region is vertically inserted between the memory array region and the control logic region and includes additional conductive structures coupling the digital line structure of the memory array region to the control logic devices of the control logic region. The second interconnect region vertically overlying the memory array region includes other conductive structures electrically connected to the source structure.

[0091] Microelectronic devices according to embodiments of the present disclosure (e.g., microelectronic device 258) Figure 2H This can be used in embodiments of the electronic systems disclosed herein. For example, Figure 3 This is a block diagram of an illustrative electronic system 300 according to embodiments of the present disclosure. For example, electronic system 300 may include a computer or computer hardware component, a server or other network-connected hardware component, a cellular phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, a tablet computer with Wi-Fi or cellular capabilities (e.g., an iPad® or SURFACE® tablet computer), an e-book, a navigation device, etc. Electronic system 300 includes at least one memory device 302. Memory device 302 may include, for example, a microelectronic device as previously described herein (e.g., microelectronic device 258). Figure 2H The electronic system 300 may further include at least one electronic signal processor device 304 (often referred to as a “microprocessor”). The electronic signal processor device 304 may optionally include the microelectronic devices described earlier herein (e.g., microelectronic device 258). Figure 2H Although in Figure 2A The memory device 302 and the electronic signal processor device 304 are depicted as two (2) separate devices, but in additional embodiments, a single (e.g., only one) memory / processor device having the functions of both memory device 302 and electronic signal processor device 304 is included in the electronic system 300. In such embodiments, the memory / processor device may include the microelectronic device described earlier herein (e.g., microelectronic device 258). Figure 2HThe electronic system 300 may further include one or more input devices 306 for inputting information to the electronic system 300 by a user, such as a mouse or other pointing device, keyboard, touchpad, button, or control panel. The electronic system 300 may further include one or more output devices 308 for outputting information (e.g., visual or audio output) to the user, such as a monitor, display, printer, audio output jack, speaker, etc. In some embodiments, the input device 306 and output device 308 may include a single touchscreen device available for inputting information to the electronic system 300 and outputting visual information to the user. The input device 306 and output device 308 may be in electrical communication with one or more of the memory device 302 and the electronic signal processor device 304.

[0092] Therefore, according to embodiments of this disclosure, an electronic system includes an input device, an output device, a processor device operatively coupled to the input device and the output device, and a memory device operatively coupled to the processor device. The memory device includes a stacked structure, a source structure, a digital line structure, a cell pillar structure, a conductive wiring structure, a control logic device, and additional conductive wiring structures. The stacked structure includes layers, each layer including a conductive structure and an insulating structure vertically adjacent to the conductive structure. The source structure is overlaid on the stacked structure. The digital line structure lies beneath the stacked structure. The cell pillar structure is coupled to the digital line structure and extends vertically and completely through the stacked structure and into the source structure. The conductive wiring structure lies vertically beneath the digital line structure and is coupled to the digital line structure. The control logic device is coupled to the conductive wiring structure and at least partially lies vertically beneath the conductive wiring structure. The additional conductive wiring structure is coupled to the source structure and vertically overlaid on the source structure.

[0093] Compared to conventional structures, devices, and methods, the structures, devices, and methods of this disclosure advantageously promote one or more of the following: improved microelectronic device performance; reduced costs (e.g., manufacturing costs, material costs); increased component miniaturization; and greater packaging density. Compared to conventional structures, devices, and methods, the structures, devices, and methods of this disclosure also improve scalability, efficiency, and simplicity.

[0094] Non-limiting examples and embodiments of this disclosure include:

[0095] Example 1: A method of forming a microelectronic device, comprising: forming a microelectronic device structure, the microelectronic device structure including: a base structure; a doped semiconductor material above the base structure; a stacked structure consisting of a vertically alternating sequence of conductive and insulating structures overlying the doped semiconductor material; a unit pillar structure extending vertically through the stacked structure and the doped semiconductor material and into the base structure; and a digital line structure vertically overlying the stacked structure; forming an additional microelectronic device structure including control logic devices; attaching the microelectronic device structure to the additional microelectronic device structure to form a microelectronic device structure assembly, the digital line structure being vertically inserted within the microelectronic device structure assembly between the stacked structure and the control logic devices; removing portions of the base structure and the unit pillar structure extending vertically into the base structure to expose the doped semiconductor material; and patterning the doped semiconductor material after removing portions of the base structure and the unit pillar structure to form at least one source structure over the stacked structure and coupled to the unit pillar structure.

[0096] Example 2: According to the method of Example 1, forming a microelectronic device structure includes forming a microelectronic device structure to further include a conductive contact structure that extends vertically through the stacked structure and into the doped semiconductor material.

[0097] Example 3: The method according to one of Examples 1 and 2, wherein forming a microelectronic device structure includes: forming a preliminary stacked structure over a doped semiconductor material, the preliminary stacked structure including a vertically alternating sequence of a first insulating structure and a second insulating structure; forming an opening extending vertically through the preliminary stacked structure and the doped semiconductor material and into a base structure; forming a unit pillar structure within the opening; forming a groove extending through the preliminary stacked structure; using the groove to at least partially replace the second insulating structure with a conductive structure to form a stacked structure, the insulating structure of the stacked structure including the remainder of the first insulating structure; and a digital line structure formed above and electrically connected to the unit pillar structure.

[0098] Example 4: The method according to any one of Examples 1 to 3, wherein forming a microelectronic device structure includes forming a microelectronic device structure to further include: an insulating wire structure on a digital line structure; a digital line contact structure extending through a portion of the insulating wire structure and contacting the digital line structure; and a conductive pad structure on the digital line contact structure.

[0099] Example 5: According to the method of Example 4, forming an additional microelectronic device structure includes forming a microelectronic device structure to further include an additional conductive pad structure above the control logic device.

[0100] Example 6: According to the method of Example 5, attaching a microelectronic device structure to an additional microelectronic device structure includes: vertically reversing one of the microelectronic device structure and the additional microelectronic device structure; and bonding a conductive pad structure of the microelectronic device structure to an additional conductive pad structure of the additional microelectronic device structure.

[0101] Example 7: The method according to any one of Examples 1 to 6, wherein portions of the base structure and the unit pillar structure extending vertically into the base structure are removed to expose the upper boundary of the doped semiconductor material, including the remaining portion forming the unit pillar structure, to be substantially coplanar with the upper boundary of the doped semiconductor material.

[0102] Example 8: The method according to any one of Examples 1 to 7 further includes forming at least one metal bridging material over the doped semiconductor material before patterning the doped semiconductor material.

[0103] Example 9: The method according to any one of Examples 1 to 8 further includes: a conductive wiring structure formed above and electrically connected to at least one source structure; and a conductive pad structure formed above and electrically connected to the conductive wiring structure.

[0104] Example 10: The method according to Example 9 further includes forming at least one metal-insulator-metal (MIM) capacitor vertically above at least one source structure and vertically below the conductive wiring structure.

[0105] Example 11: The method according to Example 9 further includes forming at least one metal-insulator-semiconductor (MIS) capacitor vertically below the conductive wiring structure and at least partially vertically above at least one source structure.

[0106] Example 12: A microelectronic device comprising: a memory array region including: a stacked structure comprising a vertically alternating sequence of conductive and insulating structures; a source structure vertically overlying the stacked structure and including a doped semiconductor material; a cell pillar structure vertically extending completely through the stacked structure and at least partially through the source structure; and a digital line structure vertically lying on the stacked structure and electrically connected to the cell pillar structure; a control logic region vertically lying on the memory array region and including control logic devices; a first interconnect region vertically inserted between the memory array region and the control logic region, and including additional conductive structures coupling the digital line structure of the memory array region to the control logic devices of the control logic region; and a second interconnect region vertically overlying the memory array region and including other conductive structures electrically connected to the source structure.

[0107] Example 13: The microelectronic device according to Example 12 further includes: a contact pad horizontally adjacent to and substantially vertically aligned with the source structure, the contact pad comprising a doped semiconductor material; and a conductive contact structure coupled to the contact pad and extending vertically and completely through the stacked structure.

[0108] Example 14: A microelectronic device according to one of Examples 12 and 13, further comprising a metal bridging structure vertically inserted between the source structure and other conductive structures and electrically connected to the source structure and the other conductive structures.

[0109] Example 15: A microelectronic device according to any of Examples 12 to 14, wherein the upper boundary of the unit pillar structure is substantially coplanar with the upper boundary of the source structure.

[0110] Example 16: A microelectronic device according to any one of Examples 12 to 14, wherein the upper boundary of the unit pillar structure is vertically below the upper boundary of the source structure.

[0111] Example 17: A microelectronic device according to any one of Examples 12 to 16, wherein other conductive structures include: a conductive wiring structure above the source structure; a conductive contact extending between and coupling the conductive wiring structure and the source structure; a conductive pad structure above the conductive wiring structure; and an additional conductive contact extending between and coupling the conductive wiring structure and the conductive pad structure.

[0112] Example 18: A microelectronic device according to any of Examples 12 to 17, further comprising a metal-insulator-metal (MIM) capacitor located at least partially vertically between the source structure and other conductive structures.

[0113] Example 19: A microelectronic device according to any of Examples 12 to 18, further comprising a metal-insulator-semiconductor (MIS) capacitor at least partially vertically positioned between the source structure and other conductive structures.

[0114] Example 20: An electronic system comprising: an input device; an output device; a processor device operatively coupled to the input device and the output device; and a memory device operatively coupled to the processor device, comprising: a stacked structure including layers each comprising a conductive structure and an insulating structure vertically adjacent to the conductive structure; a source structure overlying the stacked structure; a digital line structure underlying the stacked structure; a cell pillar structure coupled to the digital line structure and extending vertically through the stacked structure and into the source structure; a conductive wiring structure vertically underlying the digital line structure and coupled to the digital line structure; a control logic device coupled to the conductive wiring structure and at least partially vertically underlying the conductive wiring structure; and an additional conductive wiring structure coupled to the source structure and vertically overlying the source structure.

[0115] While this disclosure is susceptible to various modifications and alternatives, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, this disclosure is not limited to the specific forms disclosed. Rather, this disclosure is intended to cover all modifications, equivalents, and alternatives falling within the scope of the following appended claims and their legal equivalents. For example, elements and features disclosed with respect to one embodiment may be combined with elements and features disclosed with respect to other embodiments of this disclosure.

Claims

1. A method for forming a microelectronic device, comprising: The structure of a microelectronic device includes: Base structure; The doped semiconductor material above the base structure; A stacked structure, which is covered by the doped semiconductor material and includes a vertically alternating sequence of conductive and insulating structures; A unit column structure that extends vertically through the stacked structure and the doped semiconductor material and into the base structure; A conductive contact structure extending vertically through the stacked structure and into the doped semiconductor material; and A digital line structure, which is vertically superimposed on the stacked structure; Forming an additional microelectronic device structure that includes control logic devices; The microelectronic device structure is attached to the additional microelectronic device structure to form a microelectronic device structure assembly, wherein the digital line structure is vertically inserted within the microelectronic device structure assembly between the stacked structure and the control logic device; Remove portions of the base structure and the unit pillar structures extending vertically into the base structure to expose the doped semiconductor material; and After removing the portions of the base structure and the unit pillar structure, the doped semiconductor material is patterned to form at least one source structure above the stacked structure and coupled to the unit pillar structure, and at least one contact pad, the at least one contact pad being electrically isolated from the at least one source structure and coupled to the conductive contact structure.

2. The method of claim 1, wherein patterning the doped semiconductor material comprises forming the at least one source structure and the at least one contact pad substantially simultaneously on the doped semiconductor material.

3. The method of claim 1, wherein forming the microelectronic device structure comprises: A preliminary stacked structure is formed on the doped semiconductor material, the preliminary stacked structure comprising a vertically alternating sequence of a first insulating structure and a second insulating structure; An opening is formed, which extends vertically through the initial stacked structure and the doped semiconductor material and into the base structure; The unit column structure is formed within the opening; Forming grooves that extend through the initial stacked structure; The groove is used to at least partially replace the second insulating structure with the conductive structure to form the stacked structure, the insulating structure of the stacked structure including the remaining portion of the first insulating structure; as well as The digital line structure is formed above and electrically connected to the unit column structure.

4. The method according to any one of claims 1 to 3, wherein forming the microelectronic device structure comprises forming the microelectronic device structure to further include: The insulating wire structure on the digital line structure; A digital line contact structure that extends through a portion of the insulating wire structure and contacts the digital line structure; as well as The conductive pad structure on the digital line contact structure.

5. The method of claim 4, wherein forming the additional microelectronic device structure comprises: The microelectronic device structure is formed to further include an additional conductive pad structure above the control logic device.

6. The method of claim 5, wherein attaching the microelectronic device structure to the additional microelectronic device structure comprises: One of the microelectronic device structure and the additional microelectronic device structure is vertically reversed; as well as The conductive pad structure of the microelectronic device structure is bonded to the additional conductive pad structure of the additional microelectronic device structure.

7. The method according to any one of claims 1 to 3, wherein removing portions of the base structure and the unit pillar structure extending vertically into the base structure to expose the doped semiconductor material comprises: The upper boundary of the remaining portion of the unit pillar structure is formed to be substantially coplanar with the upper boundary of the doped semiconductor material.

8. The method according to any one of claims 1 to 3, further comprising forming at least one metal bridging material over the doped semiconductor material prior to patterning the doped semiconductor material.

9. The method according to any one of claims 1 to 3, further comprising: A conductive wiring structure formed above and electrically connected to the at least one source structure; as well as A conductive pad structure formed above and electrically connected to the conductive wiring structure.

10. The method of claim 9, further comprising forming at least one metal-insulator-metal (MIM) capacitor vertically above the at least one source structure and vertically below the conductive wiring structure.

11. The method of claim 9, further comprising forming at least one metal-insulator-semiconductor (MIS) capacitor vertically below the conductive wiring structure and at least partially above the at least one source structure.

12. A microelectronic device comprising: The memory array region includes: A stacked structure comprising a vertically alternating sequence of conductive and insulating structures; A source structure, which is vertically superimposed on the stacked structure and includes a doped semiconductor material; A unit column structure that extends vertically and completely through the stacked structure and at least partially through the source structure; A digital line structure, which lies vertically beneath the stacked structure and is electrically connected to the unit column structure; A contact pad, horizontally adjacent to and substantially vertically aligned with the source structure, electrically isolated from the source structure, and comprising the doped semiconductor material; and A conductive contact structure coupled to the contact pad and extending vertically and completely through the stacked structure; A control logic area, which lies vertically beneath the memory array area and includes control logic devices; A first interconnect region, vertically inserted between the memory array region and the control logic region, includes an additional conductive structure coupling the digital line structure of the memory array region to the control logic device of the control logic region; and The second interconnect region is vertically superimposed on the memory array region and includes other conductive structures electrically connected to the source structure.

13. The microelectronic device of claim 12, wherein the conductive contact structure is electrically isolated from the conductive structure of the stacked structure by an insulating liner structure.

14. The microelectronic device of claim 12, further comprising a metal bridging structure vertically inserted between the source structure and the other conductive structure and electrically connected to both the source structure and the other conductive structure.

15. The microelectronic device according to any one of claims 12 to 14, wherein the upper boundary of the unit pillar structure is substantially coplanar with the upper boundary of the source structure.

16. The microelectronic device according to any one of claims 12 to 14, wherein the upper boundary of the unit pillar structure is vertically below the upper boundary of the source structure.

17. The microelectronic device according to any one of claims 12 to 14, wherein the other conductive structure comprises: The conductive wiring structure above the source structure; A conductive contact that extends between the conductive wiring structure and the source structure and couples the conductive wiring structure and the source structure; The conductive pad structure above the conductive wiring structure; as well as An additional conductive contact extends between and couples the conductive wiring structure and the conductive pad structure.

18. The microelectronic device according to any one of claims 12 to 14, further comprising a metal-insulator-metal (MIM) capacitor at least partially vertically positioned between the source structure and the other conductive structure.

19. The microelectronic device according to any one of claims 12 to 14, further comprising a metal-insulator-semiconductor (MIS) capacitor at least partially vertically positioned between the source structure and the other conductive structure.

20. An electronic system comprising: Input device; Output device; A processor device operatively coupled to the input device and the output device; as well as A memory device operatively coupled to the processor device and comprising: A stacked structure comprising layers, each including a conductive structure and an insulating structure vertically adjacent to the conductive structure; A source structure, which is overlaid on the stacked structure; A contact pad is located at a vertical position of the source structure and is electrically isolated from the source structure, and the contact pad has the same material composition as the source structure; A conductive contact structure coupled to the contact pad and extending vertically and completely through the stacked structure; A digital line structure resting beneath the stacked structure; a unit column structure coupled to the digital line structure and extending vertically and completely through the stacked structure and into the source structure; A conductive wiring structure, which lies vertically beneath and is coupled to the digital line structure; A control logic device coupled to and at least partially vertically resting on the conductive wiring structure; and An additional conductive wiring structure is coupled to the source structure and vertically overlaid on the source structure.

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