Power semiconductor device

Abstract

The invention provides a power semiconductor device (1) comprising: a semiconductor substrate (2) comprising: a base layer (5) selectively provided at a first side of the semiconductor substrate and wherein the base layer has a first conductivity type; a collector layer (3) provided at a second side of the semiconductor substrate, wherein the second side is opposite to the first side, and wherein the collector layer has the first conductivity type; and a drift layer (4) having a second conductivity type opposite to the first conductivity type, wherein the drift layer (2) is arranged between the collector layer (3) and the base layer (5); an active cell (15) provided in the semiconductor substrate (2), wherein the active cell (5) comprises an emitter region (7) having the second conductivity type and an active base region (5-i) being part of the base layer (5); and an insulating trench (17) provided in the semiconductor substrate (2) and adjacent to the active cell (15), wherein: the insulating trench (17) extends along a first direction from a surface (16) of the first side of the semiconductor substrate (2) into the drift layer (4); the insulating trench (17) comprises a gate electrode (9) and a dielectric material (11, 10) provided therein; and the gate electrode (9) is configured to control a conduction / blocking state of a current channel within the active cell (15); wherein the active cell (15) has a first length L1 along a second direction X perpendicular to the first direction Y, and the insulating trench (17) has a second length L2 along the second direction Y, and the first length L1 and the second length L2 further satisfy a relation of 0.5 ≤ L2 / L1 ≤ 2.

Description

Technical Field

[0001] This disclosure relates to power semiconductor devices. More specifically, but not exclusively, this disclosure relates to trench-gate power semiconductor devices having insulating trenches. Background Technology

[0002] Power semiconductor devices (e.g., insulated-gate bipolar transistors (IGBTs)) are widely used as power switches in a variety of power applications. Important operating parameters of IGBTs typically include the on-state voltage drop between the collector and emitter (Vf). CE,sat ), switching loss (E) SW ) and Safe Work Area (SOA). V CE,sat and E SW SOA represents the efficiency of the IGBT, while SOA represents the reliability of the IGBT.

[0003] Generally, there are two common IGBT structures. One type is called a planar gate IGBT, where the gate electrode is provided on the surface of the wafer. The other type is called a trench gate IGBT, where a trench structure is formed in the wafer, and the gate electrode is buried in the trench structure. Trench gate IGBTs have MOS channels perpendicular to the wafer surface, and the vertical MOS channels effectively eliminate the JFET effect in planar gate structures. Simultaneously, since the density of MOS channels is not limited by the chip surface area, the channel density can be greatly increased. In this way, compared to planar gate IGBTs, trench gate IGBTs can provide increased channel density and correspondingly reduce the on-state voltage drop Von. CE,sat However, trench gate IGBTs exhibit poor short-circuit current capability or poor short-circuit SOA (SCSOA) due to their high saturation collector current density. Therefore, in recent trench gate technologies, dummy regions are employed to optimize Vo. CE,sat A trade-off between performance and SCSOA without sacrificing reverse blocking voltage.

[0004] Dummy regions (including dummy trenches and dummy wells between them) introduce additional parasitic capacitance and more space to store free electron-hole carriers that need to be removed or flooded in when the device is off or on. Dummy trenches have been reported to be electrically connected to the active gate electrode of a trench-gate IGBT, but this type of connection will result in increased gate-collector capacitance (C0). GC This leads to large switching losses. It is also known that a dummy trench can be electrically connected to the emitter electrode of the IGBT, but this type of connection will increase the switching speed (expressed by the rate of change of collector current di / dt) and by changing the gate resistor R. g,on This leads to uncontrollable di / dt.

[0005] Therefore, it is often necessary to compromise one operating parameter of the IGBT to improve another. Similar problems exist for other types of power semiconductor devices.

[0006] It is generally desirable to provide a power semiconductor device with improved device efficiency and improved reliability. Summary of the Invention

[0007] One of the purposes of this disclosure is to provide an improved power semiconductor device that addresses the problems associated with known structures, both herein and elsewhere.

[0008] According to a first aspect of this disclosure, a power semiconductor device is provided, comprising:

[0009] Semiconductor substrate, comprising:

[0010] A base layer, selectively disposed on a first side of a semiconductor substrate, wherein the base layer has a first conductivity type;

[0011] A collector layer is disposed on a second side of a semiconductor substrate, wherein the second side is opposite to the first side, and wherein the collector layer has a first conductivity type; and

[0012] A drift layer having a second conductivity type opposite to the first conductivity type, wherein the drift layer is disposed between the collector layer and the base layer;

[0013] An active cell disposed in a semiconductor substrate, wherein the active cell includes an emitter region having a second conductivity type and an active base region as part of a base layer; and

[0014] An insulating trench is disposed in a semiconductor substrate and adjacent to an active cell, wherein: the insulating trench extends along a first direction from a surface of a first side of the semiconductor substrate into a drift layer; the insulating trench includes a gate electrode and a dielectric material disposed therein; and the gate electrode is configured to control the on / off state of a current path within the active cell;

[0015] The active unit has a first length L1 along a second direction perpendicular to the first direction, and the insulating trench has a second length L2 along the second direction. The first length L1 and the second length L2 also satisfy the relationship 0.5≤L2 / L1≤2.

[0016] Compared to existing designs of power semiconductor devices (e.g., IGBTs) where adjacent active cells provide dummy semiconductor regions, using an insulating trench to replace at least a portion of the dummy semiconductor region is advantageous for improving SOA and switching controllability, as well as reducing switching losses and EMI noise in power semiconductor devices, while providing similar levels of current density. The length L1 of the active cell and the length L2 of the insulating trench follow the design rule 0.5 ≤ L2 / L1 ≤ 2, which is useful for maintaining a uniform electric field distribution on the front side of the chip (thus improving device reliability) and maintaining process uniformity and controllability. L2 / L1 refers to the ratio of the second length L2 to the first length L1.

[0017] It should be understood that an active cell refers to the smallest repeating unit capable of conducting current throughout a power semiconductor device, and an active cell is configured to provide at least one current path during the on-state of the power semiconductor device. Since the gate electrode can control the on / off state of the current path within the active cell, it is an active gate electrode. It should be understood that the gate electrode is arranged adjacent to the emitter region to control the on / off state of the current path provided by the active cell.

[0018] The gate electrode can extend from the surface of a first side of the semiconductor substrate into the semiconductor substrate along a first direction.

[0019] The current path provided by the active unit can be approximately along the first direction.

[0020] A portion of the dielectric material can act as a gate insulating layer between the emitter region and the gate electrode.

[0021] The emitter region can be selectively disposed on the first side of the semiconductor substrate. Preferably, the first length L1 and the second length L2 can also satisfy the relationship L2 / L1≤1.7. More preferably, the first length L1 and the second length L2 can also satisfy the relationship L2 / L1≤1.5. By ensuring that L2 / L1 is not greater than 2, preferably not greater than 1.7, and most preferably not greater than 1.5, when the device is reverse biased, the electric field under the insulating trench can be prevented from reaching an excessively high level, thereby protecting the device from damage.

[0022] Preferably, the first length L1 and the second length L2 can also satisfy the relationship L2 / L1≥1. By ensuring that L2 / L1 is not less than 0.5, and more preferably not less than 1, the risk of the device being subjected to high short-circuit current is reduced, thereby allowing the device to have acceptable SCSOA performance.

[0023] The active cell may also include a first implantation region disposed between the active base region and the drift layer. The first implantation region may be of a second conductivity type and have a higher doping concentration than the drift layer.

[0024] Advantageously, the first injection region improves conductivity modulation in the power semiconductor device by enhancing carrier distribution in the drift layer during the on-state, thereby reducing the Vt of the power semiconductor device. CE,sat .

[0025] The power semiconductor device may include another insulating trench adjacent to the active cell. This other insulating trench may extend along a first direction from the surface of the semiconductor substrate into the drift layer and may include a gate electrode and a dielectric material disposed therein. The gate electrode of the other insulating trench may be configured to control the on / off state of another current path within the active cell.

[0026] The current path and another current path can be arranged on opposite sides of the active unit.

[0027] The gate electrode may be a first gate electrode, and the insulating trench may include a second gate electrode. The first gate electrode and the second gate electrode may be disposed on opposite sides of the insulating trench.

[0028] The second gate electrode can be an active gate electrode or a dummy gate electrode.

[0029] The active cell may also include a dummy gate trench, which includes a dummy gate insulating layer and a dummy gate electrode disposed therein.

[0030] Insulating trenches and dummy gate trenches can have substantially the same depth along the first direction.

[0031] An active cell may include multiple dummy gate trenches.

[0032] The current path of the active cell and another current path can be located on opposite sides of a dummy gate trench or multiple dummy gate trenches.

[0033] The dummy gate trench can be arranged along the second direction in the middle of the active cell.

[0034] The power semiconductor device may also include an emitter electrode. The emitter electrode may include an emitter contact trench extending along a first direction into the base layer. The emitter contact trench may be electrically connected to the emitter region and the dummy gate electrode.

[0035] Emitter contact trenches advantageously simplify the electrical connection between the dummy gate electrode and the emitter electrode, and allow for a reduction in the minimum distance between the gate electrode and the dummy gate trench, thereby improving the current density and on-state voltage drop of power semiconductor devices. Emitter contact trenches also help improve the hole collection capability of the emitter electrode, thus enhancing the SOA performance of the device.

[0036] In the case where the active cell includes multiple dummy gate trenches, the emitter contact trench can be electrically connected to the dummy gate electrode in each dummy gate trench.

[0037] The gate electrode of the insulating trench can have a longer length along the first direction than the dummy gate electrode. In other words, the dummy gate trench can be etched to form the emitter contact trench.

[0038] The emitter contact trench can have a longer length along the second direction than the dummy gate trench.

[0039] In the case where the active cell includes multiple dummy gate trenches, the emitter contact trench can have a longer length along the second direction than the multiple dummy gate trenches.

[0040] The emitter contact trench can be arranged along the second direction in the middle of the active cell.

[0041] The power semiconductor device may also include a second injection region between an insulating trench and a drift layer, the second injection region having a first conductivity type.

[0042] Specifically, the second injection region can be located between the gate electrode and the drift layer of the insulating trench.

[0043] Advantageously, during the on-state of the power semiconductor device, the second injection region protects the gate electrode and its associated gate insulating layer (provided by the dielectric layer) from the blocking holes injected by the collector layer, and thus protects the gate electrode and gate insulating layer from the trapping of holes blocked on the collector layer. As a result, the second injection region improves the reliability of the power semiconductor device. Furthermore, the second injection region provides better blocking capability for the power semiconductor device.

[0044] The second injection region can be electrically connected to the emitter electrode or floated.

[0045] The second injection region can also be located within the active cell between the dummy gate trench and the drift layer.

[0046] Advantageously, the second injection region between the dummy gate trench and the drift layer provides better blocking capability for power semiconductor devices and can be electrically connected to the emitter electrode or floated.

[0047] The second direction can be parallel to the surface of the semiconductor substrate.

[0048] Power semiconductor devices may also include dummy cells. Dummy cells may include dummy base regions that are part of the base layer.

[0049] It should be understood that during the on-state of a power semiconductor device, the dummy cell does not provide any current path.

[0050] A dummy cell may not include any emitter region formed within the dummy base region.

[0051] The dummy cell may also include a dummy gate trench, which includes a dummy gate insulating layer and a dummy gate electrode disposed therein.

[0052] A dummy cell may include multiple dummy gate trenches.

[0053] Active cells and dummy cells can include the same number of dummy gate trenches. The length of the dummy cell along the second direction can be equal to the first length L1.

[0054] The first injection region can also be set in a virtual cell between the virtual base region and the drift layer.

[0055] The second injection region can also be set in the dummy cell between the dummy gate trench and the drift layer.

[0056] Advantageously, the second injection region between the dummy gate trench and the drift layer provides better blocking capability for power semiconductor devices and can be electrically connected to the emitter electrode.

[0057] The power semiconductor device may include multiple active cells and multiple insulating trenches, with each active cell disposed adjacent to each other between two insulating trenches along a second direction.

[0058] "Closely adjacent" means that there is no other structure between the two insulating trenches.

[0059] The power semiconductor device may also include a plurality of dummy cells, wherein at least one dummy cell and at least two insulating trenches are disposed between adjacent active cells along a second direction.

[0060] The insulating trench can be disposed along the second direction between the dummy unit and the active unit, or between two dummy units.

[0061] The power semiconductor device may also include a buffer layer having a second conductivity type, wherein the buffer layer is disposed between the drift layer and the collector layer and has a higher doping concentration than the drift layer.

[0062] The buffer layer helps reduce the on-state voltage drop V of power semiconductor devices. CE,sat It is useful.

[0063] Power semiconductor devices may include insulated gate bipolar transistors (IGBTs).

[0064] According to a second aspect of this disclosure, a method for manufacturing a power semiconductor device is provided, the method comprising:

[0065] A semiconductor substrate is provided, comprising:

[0066] A base layer disposed on a first side of a semiconductor substrate, wherein the base layer has a first conductivity type; and

[0067] A drift layer having a second conductivity type opposite to the first conductivity type;

[0068] Selectively etch the base layer and drift layer to form insulating trenches within the semiconductor substrate;

[0069] A gate electrode is formed in an insulating trench, and the insulating trench is filled with a dielectric material.

[0070] An emitter region having a second conductivity type is selectively formed within the base layer on a first side of the semiconductor substrate, wherein the emitter region and a portion of the base layer in which the emitter region is disposed provide an active cell, and wherein the insulating trench is adjacent to the active cell, and a gate electrode is configured to control the on / off state of a current path within the active cell; and

[0071] A collector layer is formed on the second side of a semiconductor substrate. The collector layer has a first conductivity type, wherein the second side is opposite to the first side, and a drift layer is disposed between the collector layer and the base layer.

[0072] in:

[0073] An insulating trench is configured to extend along a first direction from the surface of a first side of the semiconductor substrate into the drift layer;

[0074] The active unit has a first length L1 along a second direction perpendicular to the first direction, and the insulating trench has a second length L2 along the second direction; and

[0075] The first length L1 and the second length L2 satisfy the relationship 0.5≤L2 / L1≤2.

[0076] Where appropriate, any optional features described above with respect to the first aspect of this disclosure may be applied to the second aspect of this disclosure.

[0077] It is understood that the various ranges of L2 / L1 described above allow for a degree of variability in the specified values ​​of the range endpoints, such as ±10%. For example, the specified limit of 2 can be any number between 2*(1-10%) and 2*(1+10%). Furthermore, values ​​expressed in range format should be interpreted flexibly to include not only the values ​​explicitly listed as range endpoints, but also all individual values ​​or subranges contained within that range, as if each value and subrange were explicitly listed. Attached Figure Description

[0078] To better understand this disclosure, several embodiments of the disclosure will now be described by way of example with reference to the accompanying drawings, in which:

[0079] Figure 1 This is a schematic cross-sectional view of a power semiconductor device according to the first embodiment of the present disclosure;

[0080] Figure 2 This is a schematic cross-sectional view of a power semiconductor device according to a second embodiment of the present disclosure;

[0081] Figure 3 This is a schematic cross-sectional view of a power semiconductor device according to a third embodiment of the present disclosure;

[0082] Figure 4 This is a schematic cross-sectional view of a power semiconductor device according to the fourth embodiment of the present disclosure;

[0083] Figure 5 This is a schematic cross-sectional view of a power semiconductor device according to the fifth embodiment of this disclosure;

[0084] Figures 6-1 to 6-8 A method for manufacturing a power semiconductor device according to a third embodiment is shown.

[0085] In the accompanying drawings, the same parts are indicated by the same reference numerals.

[0086] It should be understood that the accompanying drawings are for illustrative purposes only and are not drawn to scale. Detailed Implementation

[0087] Hereinafter, with reference to the accompanying drawings, a detailed description of preferred embodiments of the power semiconductor device according to the present disclosure will be given. In the description and drawings, layers or regions prefixed with N or P signify that electrons or holes are respectively the majority carriers. Furthermore, a "+" or "-" added to N or P indicates a higher or lower impurity concentration than a layer or region without a "+" or "-". Doped regions having the same relative doping concentration do not necessarily have the same absolute doping concentration. For example, two different "N" doped regions may have the same or different absolute doping concentrations. In the following description and drawings, the same reference numerals are given the same configuration, and redundant descriptions are omitted.

[0088] Figure 1 A schematic cross-sectional view of a power semiconductor device 1 according to a first embodiment of the present disclosure is shown. Figure 1In the provided example, the power semiconductor device is implemented as a trench gate IGBT. IGBT 1 is formed on a semiconductor substrate 2. The semiconductor substrate 2 includes a P-type base layer 5 disposed on a first side (e.g., the top side) of the substrate, a P+ type collector layer 3 disposed on a second opposite side (e.g., the bottom side) of the substrate, an N-type drift layer 4 located between the collector layer 3 and the base layer 5, and an N-type buffer layer 6 located between the P+ type collector layer 3 and the N-type drift layer 4. The semiconductor substrate 2 has a first surface 16 (e.g., the top surface) on the first side and a second surface 14 (e.g., the bottom surface) on the second side. The second surface 14 is the surface of the P+ type collector layer 3. The first surface 16 is the surface of the P-type base layer 5.

[0089] Multiple active cells 15 and multiple insulating trenches 17 are formed within the semiconductor substrate 2. For example... Figure 1 As shown, active cells 15 and insulating trenches 17 are arranged alternately along the X-axis. In other words, an insulating trench 17 is disposed adjacent to two adjacent active cells 15. No other structures are located between adjacent active cells. The X-axis is typically parallel to the first surface 16 or the second surface 14 of the substrate 2. Each active cell 15 refers to the smallest repeating cell capable of conducting current in the IGBT 1. Although Figure 1 The diagram shows IGBT 1 with four active cells 15, but this is for illustrative purposes only, and in reality, IGBTs can typically have at least hundreds to thousands of active cells. The active cells 15 are designed to have nearly identical dimensions and construction. The term "active cell" means that the cell will provide at least one current path during the on-state of IGBT 1.

[0090] like Figure 1 As shown, each insulating trench 17 extends along the Y-axis from the first surface 16 of the substrate 2 into the N-type drift layer 4. The Y-axis is typically perpendicular to either the first surface 16 or the second surface 14. The Y-axis may also be referred to as the "first direction" or depth direction of the substrate 2, and the X-axis may be referred to as the "second direction" or lateral direction of the substrate 2. Each insulating trench includes two gate electrodes 9 disposed on opposite sides of the respective insulating trench. The two gate electrodes 9 are respectively configured to be adjacent to two active cells adjacent to the insulating trench. Each gate electrode 9 also extends along the Y-axis. Figure 1 As shown, the gate electrode 9 of the insulating trench 17 is aligned along the X-axis. The gate electrode 9 can be formed using any material commonly used in the art, such as doped polysilicon.

[0091] Each insulating trench also includes at least one dielectric material disposed therein. The dielectric material provides two gate insulating layers 11 for each of the two gate electrodes 9. The gate insulating layers 11 are disposed between the gate electrodes 9 and the active cells adjacent to the insulating trench. The dielectric material also provides an isolation structure 10 between the two gate electrodes 9. The isolation structure 10 differs from the gate insulating layer 11 by being formed as a trench insulation that is thicker than the gate insulating layer 11. The gate insulating layer 11 and the isolation structure 10 can be made of the same dielectric material or different types of dielectric materials. The gate insulating layer 11 can be formed using any materials and techniques commonly used in the art. For example, the gate insulating layer 11 can be a gate oxide, such as silicon dioxide, and can be produced by deposition or thermal growth. Thick isolation structures 10 can be deposited.

[0092] like Figure 1 As shown, the P-type base layer 5 is divided into multiple isolated P-type base regions 5-i by insulating trenches 17. Each active cell 15 includes one of the P-type base regions 5-i. The P-type active base region 5-i can also be referred to as an active P-well. As described in more detail below, during the on-state of the IGBT 1, at least one current conduction path is formed within the P-type base region 5-i. Therefore, the P-type base region 5-i of the active cell 15 can also be referred to as a P-type active base region. Continuing as... Figure 1 As shown, a first implantation region 13 is located between each active base region 5-i and the N-drift layer 4. The first implantation region is N-type. As the name suggests, the first implantation region 13 is formed by implantation. Therefore, all first implantation regions 13 can be formed simultaneously in the substrate 2. Each active cell 15 also includes two N+ type emitter regions 7. The emitter regions 7 are adjacent to the first surface 16 of the substrate 2 along the Y-axis and adjacent to the gate electrode 9 of the adjacent insulating trench 17 along the X-axis.

[0093] IGBT 1 also includes a collector electrode 19 electrically connected to the P+ type collector layer 3 and an emitter electrode 21 electrically connected to each emitter region 7. The emitter electrode 21 may include a barrier layer, for example, made of titanium nitride, tantalum nitride, titanium, or tantalum. The main layer of the emitter electrode 21 may be made of, for example, tungsten or a tungsten-based metal, aluminum, copper, or an alloy of aluminum and copper. The collector electrode 19 may include aluminum, copper, an alloy of aluminum or copper, or a multilayer metal, such as Al / Ti / Ni / Ag or Al / Ni / Ag. Although the electrical connection between the gate electrodes 9 of the insulating trench 17 is not in... Figure 1 The provided cross-sectional perspective view clearly shows this, but the gate electrode 9 can be relative to... Figure 1 They are shorted together in the third dimension of the cross-sectional plane.

[0094] Interlayer dielectric 23 covers the upper portion of the active cell 15. Therefore, interlayer dielectric 23 electrically isolates the active gate electrode 10 from the emitter electrode 21. The emitter electrode 21 includes an emitter contact via 22 extending through the interlayer dielectric 23 to form an electrical connection with the emitter region 7 and the P-type active base region 5-i. A heavily doped P+ type region 8 is also provided at the interface between each emitter contact via 22 and the corresponding P-type active base region 5-i to reduce the contact resistance between the via 22 and the active base region 5-i. The reduced contact resistance is useful because it allows excess holes injected from the P+ type collector layer 3 into the N-drift layer 4 during the on-state of the IGBT 1 to easily flow to the emitter electrode 21.

[0095] To switch IGBT 1 from the off state to the on state, a positive gate-emitter voltage V is applied between the gate electrode 9 and the emitter electrode 21. GE When V GE When the voltage exceeds the gate-emit threshold voltage, a portion of the P-type active base region 5-i, spanning the gate insulating layer 11 and opposite the gate electrode 9, is inverted to N-type, thereby forming a channel region. Therefore, electrons emitted from the emitter region 7 can flow through the N-type channel region and the N-type first injection region 13 to the N-type drift layer 4 and the N-type buffer layer 6 before being collected by the P+ type collector layer 3. Figure 1 In the example, during the on-state of IGBT 1, each active cell 15 is able to provide two current paths (or conduction paths) on opposite sides of the respective active cell. Furthermore, the two gate electrodes 9 contained within the insulating trench 17 are control electrodes that control the on / off state of the current paths of adjacent active cells 15. In this sense, both gate electrodes 9 of each insulating trench 17 are active gate electrodes.

[0096] In IGBT 1, any gate electrode 9 and its associated gate insulating layer 11 can be considered a trench gate. The semiconductor region between two adjacent active trench gates is typically referred to as a mesa region or mesa portion. Figure 1 In the example shown, each mesa region includes an active base region 5-i and a first injection region 13. Generally, the center-to-center distance (i.e., spacing) between adjacent mesa regions determines the channel density, which in turn determines the on-state resistance of the IGBT.

[0097] like Figure 1 As shown, each active unit has a first length L1 along the X-axis, and each insulating trench has a second length L2 along the X-axis. The first length L1 can also be referred to as the length of the mesa area. Lengths L1 and L2 satisfy the design rule 0.5 ≤ L2 / L1 ≤ 2. More preferably, lengths L1 and L2 satisfy the design rule L2 / L1 ≤ 1.7, or most preferably L2 / L1 ≤ 1.5 and / or L2 / L1 ≥ 1.

[0098] The specific design rules between L1 and L2 help maintain a uniform electric field distribution on the front side of the chip and correspondingly improve the reliability of IGBT 1. The front side of the chip refers to the top surface of the wafer on which IGBT 1 is fabricated. If L2 is too long relative to L1, then when IGBT 1 is reverse biased (i.e., when V...),... GE =0 and V CE When the voltage is positive, the bottom of the insulating trench 17 may experience a higher electric field, thereby reducing the breakdown voltage of IGBT 1. On the other hand, if L2 is too short relative to L1, IGBT 1 may experience a higher short-circuit current, thereby degrading the SCSOA performance of IGBT 1.

[0099] Furthermore, specific design rules are useful for maintaining process uniformity and controllability. As described in more detail below, the semiconductor substrate can be etched in a single dry etching step to simultaneously provide the insulating trench 17. Since L2 is no longer than twice the length of L1, the lengths L1 and L2 have comparable dimensions. In this way, the etching depth of the semiconductor substrate can be kept uniform across the chip area. This means that the insulating trench 17 will have substantially the same depth along the Y-axis. Furthermore, if L2 is too long relative to L1, it may be difficult to control the process of filling the insulating trench 17 with dielectric material.

[0100] Furthermore, as described in more detail below, the insulating trench 17 is formed by selectively etching the P-type base layer 5 and the N-drift layer 4. The sidewalls of the insulating trench 17 are parallel to the vertical Y-axis, as shown below. Figure 1 As shown. This can be achieved by anisotropic dry etching. It should be understood that the sidewalls of the insulating trench 17 can form a small angle (e.g., less than 5°) relative to the Y-axis. In this case, taking into account the length variation along the Y-axis, the first length L1 can be the average length of the active cell 15. Similarly, taking into account the length variation along the Y-axis, the second length L2 can be the average length of a single insulating trench 17.

[0101] By adjusting the second length L2 of the insulating trench 17, the current density of the IGBT 1 can be adjusted to meet predetermined performance requirements. For example, it may be necessary for the IGBT to deliver 200A of current within a 1cm x 1cm chip area. The required current density can be achieved by adjusting the ratio between the second length L2 and the first length L1.

[0102] In existing IGBT designs, dummy semiconductor regions (also known as dummy areas) are typically provided between adjacent active cells. Known dummy areas typically include a P-type dummy base region (which is similar to a portion of the P-type base layer 5 of IGBT 1 and may also be referred to as a dummy P-well). The dummy base region is typically kept floating, meaning it is not electrically connected to any electrode and therefore has a floating potential. For example, in Figure 9 of US Patent 9478614B2, an example of a dummy region is shown as P-region 13. Alternatively, the dummy base region may be grounded or partially grounded. Known dummy regions may also include one or more dummy gate trenches within the dummy base region. In Figure 9 of US Patent 9478614B2, an example of a dummy gate trench is shown as trench 65.

[0103] Compared to known dummy regions, using insulating trenches 17 between adjacent active cells 15 is advantageous for improving the SOA of IGBT 1. This will be explained in more detail below.

[0104] During the on-state of IGBT 1, the P+ type collector layer 3 injects a large amount of excess holes into the N-drift layer 4. Therefore, the carrier concentration in the high-resistivity N-drift layer increases, leading to a decrease in its resistivity. This temporary increase in conductivity (i.e., a decrease in resistivity) during conduction is called conductivity modulation. When IGBT 1 switches from the on-state to the off-state, the excess holes in the N-drift layer 4 either flow into the emitter electrode 21 or are annihilated by excess electrons due to recombination. However, in existing designs of IGBTs that provide a dummy base region between adjacent active cells, excess holes tend to accumulate within the dummy base region, leading to an increase in the potential of the dummy base region. The increased potential in the dummy base region can cause dynamic avalanche in the IGBT, thus limiting the SOA of the IGBT. By using insulating trenches 17 (specifically, isolation structure 10) instead of a dummy base region, the IGBT 1 of this disclosure significantly reduces the accumulation of excess holes in the substrate 2 when IGBT 1 switches from the on-state to the off-state. Therefore, IGBT 1 has reduced dynamic avalanche risk and improved SOA.

[0105] Using insulating trenches 17 between adjacent active units 15 is also beneficial for improving switch controllability and reducing switching losses and EMI noise of IGBT 1. This will be explained in more detail below.

[0106] The gate capacitance of an IGBT affects its switching losses and switching controllability. Gate capacitance includes the gate-emitter capacitance (C0). GE ) and Miller capacitance (C GC )

[0107] By providing an insulating trench 17 between adjacent active cells 15, the gate-emitter capacitance (C) of IGBT 1 is...GE This significantly reduces the amount by an amount equal to the gate-emitter capacitance (C) of the trench gate structure (active trench gate or dummy trench gate). GE Otherwise, it can be set at the location of the isolation structure 10 of the insulating trench 17.

[0108] Miller capacitance C GC Due to the internal structure of the IGBT, it exists and can be considered as comprising two separate capacitors arranged in series. The first capacitor is generated by the oxide layer of the gate (e.g., gate insulator 11) and has a constant value. The second capacitor represents the capacitive coupling between the collector and emitter. Figure 1 As shown, the isolation structure 10 of the insulating trench 17 provides a thick dielectric layer between the emitter electrode 21 and the P+ type collector layer 3. Therefore, the insulating trench 17 significantly reduces the capacitive coupling between the emitter electrode 20 and the collector electrode 19. Thus, the use of the insulating trench 17 is also beneficial for reducing the Miller capacitance of the IGBT.

[0109] The use of insulating trench 17 reduces the gate-emitter capacitance (C). GE ) and Miller capacitance (C GC Therefore, the gate capacitance of IGBT 1 can be charged and discharged at a faster rate than existing designs, resulting in reduced switching losses and improved switching controllability.

[0110] Furthermore, existing IGBT designs contain significant parasitic capacitances associated with the dummy base region and dummy gate trench, which cause oscillations and generate unpleasant noise during the on / off switching of IGBT 1. By replacing the dummy base region and dummy gate trench with insulating trench 17, the parasitic capacitance within the device is reduced, thus reducing the EMI noise generated by IGBT 1.

[0111] Therefore, compared to existing IGBT designs that provide dummy semiconductor regions between adjacent active cells, using insulating trench 17 instead of such dummy regions improves SOA and switching controllability, reduces switching losses and EMI noise of IGBT 1, and provides a similar level of current density. The length L2 of insulating trench 17 along the X-axis follows the design rule 0.5≤L2 / L1≤2 to maintain a uniform electric field distribution on the front side of the chip (thus improving the reliability of IGBT 1) and to maintain process uniformity and controllability.

[0112] Furthermore, the N-type first injection region 13 helps to improve the conductivity modulation in IGBT 1 by enhancing the carrier distribution in the N-type drift layer 4 during the on-state, thereby advantageously reducing the Vt of IGBT 1. CE,sat Therefore, the voltage drop V of IGBT 1 in the on state is...CE,sat Switching loss E SW It presents an improved performance trade-off between the safe operating area (SOA) and the performance of the secure operating area (SOA). Compared to existing IGBT designs, IGBT 1 offers improved efficiency and improved reliability.

[0113] Furthermore, compared to existing IGBT designs where active cells are adjacent to each other, the first injection region 13, together with the insulating trench 17, advantageously achieves VI of IGBT 1. CE,sat Simultaneous improvements to SOA. More specifically, by providing insulating trenches 17 between adjacent active cells 15, the IGBT 1 has a reduced channel density compared to typical IGBT designs. The reduced channel density results in improved SOA (particularly SCSOA). Typically, the reduced channel density also leads to improved V... CE,sat The increase. However, compared to existing designs, utilizing the first injection region 13 can increase V. CE,sat Keep it at the same level, or even reduce V. CE,sat .

[0114] The N-type buffer layer 6 can also be called a field barrier layer because it terminates the electric field within IGBT 1. Buffer layer 6 helps reduce the on-state voltage drop V of IGBT 1. CE,sat It is useful and makes IGBT 1 a punch-through (PT) IGBT. It should be understood that the N-type buffer layer 6 can be omitted. It should also be understood that the first injection region 13 can also be omitted.

[0115] It should also be understood that instead of having two gate electrodes 9, each insulating trench 17 may include a single gate electrode 9 on one side. In this way, each active cell will provide a single current path during the on-state of the IGBT 1. The single current path will be located on one side of the active cell, which spans the gate insulator 11 of the adjacent insulating trench 17 opposite to the gate electrode 9. The emitter region 7 formed on the other side of the active cell that is not adjacent to any gate electrode can be omitted. The IGBT modified in this way provides a lower current density, which is about half the current density achievable by the IGBT 1, and is useful for applications requiring lower current densities.

[0116] Figure 2 A cross-sectional view of a trench gate IGBT 1A according to a second embodiment of the present disclosure is schematically shown. Components of IGBT 1A that are identical to those of IGBT 1 are identified using the same markings. Components of IGBT 1A that correspond to but are different from those of IGBT 1 are marked with the same numbers but are distinguished by the letter "A". The features and advantages described above with reference to the first embodiment generally apply to the second embodiment.

[0117] The IGBT 1A includes a plurality of active cells 15A and a plurality of insulating trenches 17. Compared with Figure 1 the active cell 15 shown in the drawings, each active cell 15A further includes a dummy gate trench 12. The dummy gate trench 12 is located in the middle of the respective active cell 15A (or mesa region). The dummy gate trench 12 includes a gate insulating layer 20 and a dummy gate electrode 18. "Dummy gate electrode" and "dummy gate trench" mean that the corresponding gate electrode in the corresponding gate trench is not a control electrode and cannot be used to control the on / off switching of any current path of the IGBT 1A. The gate insulating layer 20 and the dummy gate electrode 18 may be made of the same material as the gate insulating layer 11 and the (active) gate electrode 9, respectively. In particular, the gate insulating layer may be a thin layer such as an oxide film, and the dummy gate electrode 18 may be made of polysilicon.

[0118] Compared with Figure 1 the active cell 15 shown in the drawings, the dummy gate trench 12 replaces a part of the active base region 5-i between the two emitter regions 7, and divides Figure 1 the active base region 5-i into two smaller active base regions 5-i. In this way, more than half of the active mesa regions in the IGBT 1A, which enhances electron injection from the emitter side to reduce V CE,sat . The dummy gate trench 12 also improves the electric field distribution in the mesa region, thereby providing an improved SOA.

[0119] During the on-state of the IGBT 1A, each active cell 15A provides two current paths (or conduction paths) on opposite sides of the corresponding active cell. This is similar to the active cell 15 described above. In addition, the two current paths are disposed on opposite sides of the dummy gate trench 12 within the corresponding active cell.

[0120] Although Figure 2 it is shown that each active cell 15A includes a single dummy gate trench 12, it should be understood that more than one dummy gate trench 12 may be provided within each active cell 15A. In this case, the two current paths of each active cell 15A are disposed on opposite sides of the more than one dummy gate trenches 12 as a group.

[0121] Although Figure 2 not shown in the drawings, all the dummy gate electrodes 18 may be electrically connected to the emitter electrode 21 which is normally grounded. The connection point between the dummy gate electrode 18 and the emitter electrode 21 may be located at both ends of the array of the active cells 15A.

[0122] In Figure 2In the provided example, each gate electrode 9 is shown as approximately half the size of each dummy gate electrode 18. It should be understood that this illustration is provided merely for conceptual clarity, and the relative dimensions of gate electrodes 9 and 18 may differ. Figure 3 A cross-sectional view of a trench gate IGBT 1B according to a third embodiment of the present disclosure is schematically shown. Elements of IGBT 1B that are identical to those of IGBT 1 or IGBT 1A are identified using the same notation. Elements of IGBT 1B that correspond to but are different from those of IGBT 1 or IGBT 1A are marked with the same numbers but distinguished by the letter "B". The features and advantages described above with reference to the first embodiment generally apply to the third embodiment.

[0123] IGBT 1B is similar to IGBT 1A. In IGBT 1A, the emitter electrode 21 includes two emitter contact vias 22 to form electrical connections with the two emitter regions 7 of the active cell 15A, respectively. However, in IGBT 1B, the emitter electrode 21B includes a single wide emitter contact trench 22B to simultaneously form electrical connections with both emitter regions 7 of the active cell 15B. Furthermore, the single emitter contact trench 22B is also electrically connected to the dummy gate electrode 18B of the same active cell 15B.

[0124] In this way, the dummy gate electrode 18B is electrically connected to the normally grounded emitter electrode 21B.

[0125] The length of the emitter contact trench 22B along the X-axis is greater than the length of the dummy gate trench 12B. To fabricate the emitter contact trench 22B, the P-type active base region 5-i and the dummy gate trench 12B between the two emitter regions 7 of the same active cell 15B are etched along the Y-axis, and emitter metal is deposited to fill the emitter contact trench 22B. Therefore, the dummy gate trench 12B is longer along the Y-axis than the active gate electrode 9 or the dummy gate trench 12 (e.g., ...). Figure 2 (As shown) is shorter. The combination of emitter contact trench 22B and dummy gate trench 12B can also be referred to as a recessed emitter trench (RET) gate. Therefore, IGBT 1B can be referred to as a RET-IGBT.

[0126] The heavily doped P+ type region 8B is further disposed at the interface between the emitter contact trench 22B on one side and the corresponding P-type active base region 5-i and the dummy gate electrode 18B on the other side. Similar to the P+ type region 8 used in IGBT 1 or 1A, the P+ type region 8B is useful for reducing the contact resistance between the metal and the semiconductor.

[0127] The use of the wide emitter contact trench 22B offers several advantages.

[0128] First, it electrically connects both the emitter region 7 and the dummy gate electrode 18B within the active cell 15B to the emitter electrode 21B. In this way, it is not necessary to provide a separate electrical connection to ground the dummy gate electrode 18B.

[0129] Secondly, compared to IGBT 1A, the use of a wide emitter contact trench 22B reduces the minimum distance between each active gate electrode and the dummy gate trench. In IGBT 1A, the emitter contact via 22 is arranged between the active gate electrode 9 and the dummy gate trench 12. The minimum distance along the X-axis between each active gate electrode 9 and the dummy gate trench 12 is the sum of (i) the length of one emitter region 7, (ii) the minimum length of the via 22, and (iii) the minimum spacing between the via 23 and the dummy gate trench 12. However, in IGBT 1B, since the wide emitter contact trench 22B extends continuously between the two emitter regions 7 and also contacts the dummy gate trench 12B, the minimum distance between each active gate electrode 9 and the dummy gate trench 22B is no longer limited by (ii) and (iii). In this way, the distance between the active gate electrode 9 and the dummy gate trench 12B can be significantly reduced, thereby improving the current density and VT of IGBT 1B. CE,sat Furthermore, forming the emitter contact via 22 might require a photolithography process capable of providing fine-geometric trench technology. In contrast, the wide emitter contact trench 22B relaxes this requirement imposed on the photolithography process.

[0130] Third, each emitter contact trench 22B provides a wide contact area between the emitter electrode 21B and the corresponding P-type active base region 5-i. This wide contact area effectively collects holes and allows them to flow out from the PN junction between the N+ type emitter region 7 and the P-type active base region 5-i. This allows the IGBT 1B to provide excellent SOA performance (particularly reverse bias (RB) SOA and SCSOA).

[0131] Although Figure 3 Each active cell 15B is shown to include a single dummy gate trench 12B; however, it should be understood that there may be more than one dummy gate trench 12B within each active cell 15B. In this case, each emitter contact trench 22B would be electrically connected to all dummy gate trenches within the same active cell.

[0132] Figure 4A cross-sectional view of a trench gate IGBT 1C according to a fourth embodiment of the present disclosure is schematically shown. Components of IGBT 1C that are identical to those of IGBTs 1, 1A, and 1B are identified using the same labels. Components of IGBT 1C that correspond to but are different from those of IGBTs 1, 1A, and 1B are marked with the same numbers but distinguished by the letter "C". The features and advantages described above with reference to the first embodiment generally apply to the fourth embodiment.

[0133] IGBT 1C and Figure 2 Similar to the IGBT 1A, but also includes multiple dummy cells 15C within the semiconductor substrate 2. For example... Figure 4 As shown, a single dummy cell 15C is provided between two adjacent active cells 15A along the X-axis. The dummy cell 15C is a semiconductor region formed in the substrate 2. A single insulating trench 17 is used to isolate any dummy cell 15C from the adjacent active cell 15A. In this way, the combination of two insulating trenches 17 and the dummy cell 15C is disposed adjacent to each other along the X-axis between two adjacent active cells 15A.

[0134] It should be understood that more than one dummy unit 15C can be provided between two adjacent active units 15A. In this case, an insulating trench 17 will be provided between each dummy unit 15C and its adjacent dummy unit or active unit to isolate the units (whether active or dummy) from each other. In other words, M dummy units 15C (M is an integer ≥ 2) and M+1 insulating trenches 17 can be arranged adjacent to each other along the X-axis between two adjacent active units 15A.

[0135] As described above, expressing "active cell" means that each cell will provide at least one conductive path during the IGBT's on-state. Conversely, expressing "dummy cell" means that each cell will not provide any conduction current path during the IGBT's on-state. Each dummy cell 15C includes a dummy gate trench 12C, which includes a gate insulating layer 20C and a dummy gate electrode 18C. The dummy gate trench 12C has the same dimensions and construction as the dummy gate trench 12 disposed in the active cell 15A.

[0136] Each dummy cell 15C also includes a P-type dummy base region 5-ii and a first implantation region 13 located on any side of its dummy gate trench 12. The first implantation region 13 is disposed between the P-type dummy base region 5-ii and the N-drift layer 4. All first implantation regions 13 within the active cell and the dummy cell can be formed simultaneously in the substrate 2 via a single implantation step. Similar to the active base region 5-i of the active cell 15A, the dummy base region 5-ii is part of the P-type base layer 5. The dummy base region 5-ii is designed to have the same size and the same doping concentration as the active base region 5-i. The dummy base region 5-ii can also be referred to as a dummy well.

[0137] There is no emitter region within any dummy base region 5-ii. Therefore, during the on-state of IGBT 1C, no current path flows through any dummy cell 15C. The gate electrode of the insulating trench 17 adjacent to the dummy cell 15C is referred to as the dummy gate electrode 9C. However, the dummy gate electrode 9C has the same dimensions as the active gate electrode 9. Furthermore, the dummy gate electrode 9C can be electrically connected to the active gate electrode 9. In this way, the dummy gate electrode 9C itself may be indistinguishable from the active gate electrode 9. Optionally, the dummy gate electrode 9C can be electrically connected to the normally grounded emitter electrode 21B.

[0138] like Figure 3 As shown, the length L1 of each dummy cell 15C along the X-axis is the same as the length L1 of the active cell 15A. The lengths L1 and L2 in IGBT 1B still satisfy the design rule 0.5 ≤ L2 / L1 ≤ 2. More preferably, the lengths L1 and L2 satisfy the design rule L2 / L1 ≤ 1.7, or most preferably L2 / L1 ≤ 1.5 and / or L2 / L1 ≥ 1. Since both the dummy cells 15C and the active cells 15A are semiconductor regions formed in the substrate 2 and are designed to have very similar structures and configurations, the specific design rules between L1 and L2 remain useful for maintaining a uniform electric field distribution on the front side of the chip and for maintaining process uniformity and controllability.

[0139] It should be understood that, with the same lengths L1 and L2, the IGBT 1C has a lower channel density than the IGBT 1 because the dummy cell 15C does not provide any conductive path during the on-state of the IGBT 1C. Therefore, the IGBT 1C typically provides a lower current density, approximately half that achievable with the IGBT 1A. Thus, the IGBT 1C is useful for applications requiring lower current densities.

[0140] As described above, IGBTs 1 and 1A use an insulating trench 17 instead of the entire dummy semiconductor region used in existing designs. (Go to...) Figure 4It is clear that the IGBT 1C uses its insulating trench 17 to replace most of the dummy semiconductor region used in existing designs (e.g., in...). Figure 4 (More than two-thirds of the examples provided). As a result, when IGBT 1C switches from the on state to the off state, IGBT 1C still has a reduction in the amount of excess holes accumulated in substrate 2 (especially in the dummy base region 5-ii). Therefore, IGBT 1C has a reduced dynamic avalanche risk and improved SOA. In addition, by using insulating trench 17 to replace most of the dummy semiconductor region used in the prior art, IGBT 1C has a reduced gate-emitter capacitance (C) compared to the prior art. GE and the reduced Miller capacitance C GC For reasons similar to those in the first embodiment described above, the insulating trench 17 is also beneficial for switch controllability and reducing switching losses and EMI noise in the IGBT 1C.

[0141] The dummy base region 5-ii can be electrically connected to the normally grounded emitter electrode 21. Additionally, the dummy gate electrode 18 can also be connected to the emitter electrode 21. The dummy gate electrode 18C can also be connected to the emitter electrode 21 or can remain floating.

[0142] Understandable. Figure 4 The dummy gate trenches 12 and 12C can be omitted. Furthermore, as... Figure 3 As shown, the emitter contact via 22 and dummy gate trench 12 of each active cell 15A can be replaced by a wide emitter contact trench 22B and an etched dummy gate trench 12B. Furthermore, the first injection region 13 can be omitted from the dummy cell 15C.

[0143] Figure 5 A cross-sectional view of a trench gate IGBT 1D according to a fifth embodiment of the present disclosure is schematically shown. The same labels are used to identify IGBT 1D elements that are identical to the elements of the IGBTs described above. IGBT 1D elements that correspond to but are different from the IGBT elements described above are marked with the same numbers but distinguished by the letter "D". The features and advantages described above with reference to the first embodiment generally apply to the fifth embodiment.

[0144] Compared to IGBT 1B, IGBT 1D has an additional second implantation region 25. The second implantation region 25 is P-type and is formed by implantation. Therefore, all second implantation regions 25 can be formed simultaneously in the substrate 2.

[0145] like Figure 5 As shown, some second injection zones 25 are disposed below the insulating trench 17, that is, between the insulating trench 17 and the N-drift layer 4.

[0146] The second injection regions 25 are useful because they protect the gate insulating layer 11 and the active gate electrode 9 from blocking holes injected by the P+ collector layer 3 during the on-state of the IGBT 1D. Therefore, the gate insulating layer 11 and the active gate electrode 9 are protected by the second injection regions 25 to prevent holes from being trapped from the collector layer 3. As a result, the second injection regions 25 below the insulating trench 17 (particularly below the gate electrode 9 and the gate insulating layer 11) improve the reliability of the IGBT 1D.

[0147] Furthermore, as a P-type, the second injection region 25 below the insulating trench 17 can also be used to deplete the N-drift layer 4 which is in a blocking state, thereby supporting the high breakdown voltage of the IGBT 1D.

[0148] like Figure 5 As further shown, the second injection region 25 is also disposed below the dummy gate trench 12B, that is, between the dummy gate trench 12B and the N-drift layer 4. Similarly, the second injection region 25 below the gate trenches 9, 9B provides better blocking capability.

[0149] The second injection region 25 may be electrically connected to the emitter electrode 21 (which is typically grounded) or may be floating (i.e., not electrically connected to any electrode of the IGBT 1D).

[0150] It should be understood that the second injection region 25 can be disposed within each of the aforementioned IGBTs 1A, 1B, and 1C. It should also be understood that the second injection region 25 below the dummy gate trench can be omitted, such that the second injection region 25 is formed only below the insulating trench 17.

[0151] All of the IGBTs mentioned above are N-channel IGBTs. It should be understood that the doping type of each region / layer can be changed to the opposite doping type to provide a P-channel IGBT.

[0152] Figures 6-1 to 6-8 A method for manufacturing the IGBT 1B according to the third embodiment is shown.

[0153] exist Figure 6-1 In the first step shown, a P-type dopant (e.g., boron) is implanted into the semiconductor substrate 2 to form a P-type base layer 5 on the top side of the substrate. The semiconductor substrate 2 is a lightly doped N-type substrate with a doping concentration corresponding to the doping concentration of the N-drift layer 4. The semiconductor substrate 2 is made of a single-crystal semiconductor material, which may be, for example, silicon (Si), silicon carbide (SiC), germanium (Ge), or silicon-germanium crystal (SiGe). The dimensions and doping concentrations given below refer, for example, to silicon IGBTs.

[0154] exist Figure 6-2In the second step shown, the top side of substrate 2 is selectively etched to form trenches in substrate 2. These trenches provide a dummy gate trench 12B and an insulating trench 17 in the finished product. Anisotropic dry etching can be used in this step to form the vertical sidewalls of the trenches. The etching depth can be between 3 micrometers (μm) and 7 micrometers. A gate oxide layer (e.g., silicon dioxide) is then thermally grown on the surface of substrate 2. The gate oxide layer provides gate insulating layers 11 and 20B. The thickness of the gate oxide layer can be... arrive Between. Optionally, the steps of growing and removing the sacrificial gate oxide layer can be performed before growing the gate oxide layer. The thickness of the sacrificial gate oxide layer can be between. to Between. It should be understood that during the thermal growth of the gate oxide layer and / or the sacrificial gate oxide layer, the dopant implanted in the first step will move to a deeper depth of the substrate 2 to form the active base region 5-i.

[0155] After the gate oxide layer is formed, another implantation step can be performed. Figure 6-2 (Not shown in the diagram) to provide the second implantation region 25 required for the IGBT 1D according to the fifth embodiment. Specifically, the P-type dopant (e.g., boron) can be in the form of 1 × 10⁻⁶... 12 Up to 1×10 14 ions / cm 2 The dose, ion energy of 50–400 keV and tilt angle of 0 degrees are selectively injected to form a P-type injection region 25 below the dummy gate trench 12B and the insulating trench 17.

[0156] exist Figure 6-3 In the third step shown, a polysilicon layer 30 is deposited on the top surface of the substrate 2 to fill the dummy gate trench 12B.

[0157] exist Figure 6-4 In the fourth step shown, the deposited polysilicon at the bottom of the insulating trench 17 is etched away. In this way, the remaining polysilicon forms the active gate electrode 9 and the dummy gate electrode 18B.

[0158] In addition, a thick dielectric material layer 32 (e.g., silicon dioxide) is deposited on the top surface of the substrate 2 to fill the insulating trench 17.

[0159] exist Figure 6-5 In the fifth step shown, the top surface of substrate 2 is polished using a chemical mechanical polishing (CMP) process, followed by wet cleaning. Subsequently, another dielectric material (e.g., silicon dioxide) is deposited on the top surface of substrate 2. The thickness of this layer can be... between.

[0160] Furthermore, an N-type dopant (e.g., phosphorus) is selectively implanted into the substrate 2 at a high ion energy (e.g., >2.0 MeV) to form a first implantation region 13 within the active cell 15B. Thermal annealing is then performed to activate the implanted N-type dopant. Due to the depth of the first implantation region 13 within the substrate 2, a high ion energy is required.

[0161] Furthermore, an N-type dopant (e.g., phosphorus) is selectively implanted into the substrate 2 at a high ion energy (e.g., >2.0 MeV) to form a first implantation region 13 within the active cell 15B. Thermal annealing is then performed to activate the implanted N-type dopant. Due to the depth of the first implantation region 13 within the substrate 2, a high ion energy is required.

[0162] exist Figure 6-6 In the sixth step shown, an N-type dopant (e.g., arsenic or phosphorus) is selectively implanted into the base layer 5 to form an N+ type emitter layer 34. The dielectric layer (e.g., silicon dioxide) previously deposited on the top surface of the substrate 2 is then cleaned. Another dielectric material layer (e.g., silicon dioxide) with an exemplary thickness greater than 0.6 μm is then deposited on the top surface of the substrate to form an interlayer dielectric 23.

[0163] exist Figure 6-7 In the seventh step shown, the interlayer dielectric 23, emitter layer 34, base layer 5, and dummy gate trench 12B are selectively etched along the Y-axis, for example, to a depth of 0.3-0.5 μm. The etching forms trench 36. The size and location of trench 36 correspond to the size and location of emitter contact trench 22B in the finished product. The etching further separates the N+ type emitter layer 34 into two emitter regions 7 within each active cell 15B. A P-type dopant (e.g., boron) is then implanted and thermally annealed to form a P+ type contact region 8B.

[0164] exist Figure 6-8 In the eighth step shown, metal is deposited on the top surface of substrate 2 to fill the emitter contact trench 22B and form the emitter electrode 21B. The bottom side of substrate 2 can be ground to the target wafer thickness as needed and then doped to form an N-type buffer layer 6 and a P+ type collector layer 3. Metal is further deposited on the bottom surface of substrate 2 to form the collector electrode 19. The processing performed on the bottom side of substrate 2 can be performed during or after the aforementioned processing steps on the top side.

[0165] Although the above paragraphs only describe the methods for manufacturing IGBT 1B and 1D, it should be understood that the described methods can be readily adapted (e.g., by modifying the masks used during the implantation and etching steps) to manufacture IGBTs of other embodiments.

[0166] Although the above embodiments only relate to IGBTs, it should be understood that this disclosure can be applied to other types of power semiconductor devices.

[0167] Those skilled in the art will understand that positional terms such as “top,” “bottom,” “below,” “side,” and “vertical” in the foregoing description and appended claims are made with reference to conceptual illustrations of power semiconductor devices, such as those showing standard cross-sectional views and those illustrated in the accompanying drawings. These terms are used for convenience of reference and are not intended to be restrictive. Therefore, these terms should be understood to refer to semiconductor structures when in the orientation shown in the accompanying drawings.

[0168] Although this disclosure has been described with reference to preferred embodiments as described above, it should be understood that these embodiments are merely illustrative and the claims are not limited to these embodiments. Those skilled in the art will be able to make modifications and substitutions in view of the disclosure which are expected to fall within the scope of the appended claims. Each feature disclosed or illustrated in this specification may be incorporated in this disclosure alone or in any suitable combination with any other feature disclosed or illustrated herein.

Claims

1. A power semiconductor device, comprising: Semiconductor substrate, comprising: A base layer, selectively disposed on a first side of the semiconductor substrate, wherein the base layer has a first conductivity type; A collector layer is disposed on a second side of the semiconductor substrate, wherein the second side is opposite to the first side, and wherein the collector layer has the first conductivity type; and A drift layer having a second conductivity type opposite to the first conductivity type, wherein the drift layer is disposed between the collector layer and the base layer; An active cell disposed in the semiconductor substrate, wherein the active cell includes an emitter region having the second conductivity type and an active base region as part of the base layer; and An insulating trench is disposed in the semiconductor substrate and adjacent to the active cell, wherein: the insulating trench extends along a first direction from the surface of a first side of the semiconductor substrate into the drift layer; the insulating trench includes a gate electrode and a dielectric material disposed therein; and the gate electrode is configured to control the on / off state of a current path within the active cell; Another insulating trench adjacent to the active cell, wherein the other insulating trench extends from the surface of the semiconductor substrate into the drift layer along the first direction and includes a gate electrode and a dielectric material disposed therein; wherein the gate electrode of the other insulating trench is configured to control the on / off state of another current channel within the active cell; The active unit includes a mesa region disposed between the insulating trench and the other insulating trench, and the mesa region includes an active base region. The active unit has a first length L1 along a second direction perpendicular to the first direction, and the insulating trench has a second length L2 along the second direction. The first length L1 and the second length L2 also satisfy the relationship 0.5 ≤ L2 / L1 ≤ 2. The active unit further includes a dummy gate trench, which includes a dummy gate insulating layer and a dummy gate electrode disposed therein, wherein the dummy gate trench is arranged along the second direction in the middle of the mesa region.

2. The power semiconductor device according to claim 1, wherein, The first length LI and the second length L2 also satisfy the relationship L2 / L1 ≤ 1.

7.

3. The power semiconductor device according to claim 1, wherein, The active unit further includes a first injection region disposed between the active base region and the drift layer, wherein the first injection region is of the second conductivity type and has a higher doping concentration than the drift layer.

4. The power semiconductor device according to claim 1, wherein, The current channel and the other current channel are arranged on opposite sides of the active unit.

5. The power semiconductor device according to claim 1, wherein, The gate electrode of the insulating trench is a first gate electrode, and the insulating trench includes a second gate electrode, wherein the first gate electrode and the second gate electrode are arranged on opposite sides of the insulating trench.

6. The power semiconductor device according to any one of claims 1 to 5, further comprising an emitter electrode, wherein, The emitter electrode includes an emitter contact trench extending along the first direction into the base layer, wherein the active cell corresponds to a single emitter contact trench, the emitter contact trench being electrically connected to the emitter region of the active cell and its dummy gate electrode.

7. The power semiconductor device according to claim 6, wherein, The emitter contact trench has a longer length along the second direction than the dummy gate trench.

8. The power semiconductor device according to claim 6, wherein, The emitter contact trench is arranged in the middle of the active cell along the second direction.

9. The power semiconductor device according to any one of claims 1 to 5, further comprising a second injection region between the insulating trench and the drift layer, the second injection region having the first conductivity type.

10. The power semiconductor device according to claim 9, wherein, The second injection region is also located within the active cell between the dummy gate trench and the drift layer.

11. The power semiconductor device according to any one of claims 1 to 5, wherein, The second direction is parallel to the surface of the semiconductor substrate.

12. The power semiconductor device according to any one of claims 1 to 5, further comprising a dummy unit, wherein, The dummy cell includes a dummy base region that is part of the base layer.

13. The power semiconductor device according to claim 12, wherein, The dummy cell also includes a dummy gate trench, which includes a dummy gate insulating layer and a dummy gate electrode disposed therein.

14. The power semiconductor device according to claim 12, wherein, The length of the dummy unit along the second direction is equal to the first length L1.

15. The power semiconductor device according to claim 3, further comprising a dummy unit, wherein, The dummy cell includes a dummy base region that is part of the base layer, wherein the first injection region is also disposed within the dummy cell between the dummy base region and the drift layer.

16. The power semiconductor device according to claim 9, further comprising a dummy unit, wherein, The dummy cell includes a dummy base region that is part of the base layer, wherein the second injection region is also disposed within the dummy cell between the dummy gate trench and the drift layer.

17. The power semiconductor device according to any one of claims 1 to 5, wherein, The power semiconductor device includes multiple active cells and multiple insulating trenches, with each active cell disposed adjacent to one another between two insulating trenches along the second direction.

18. The power semiconductor device according to claim 17, further comprising a plurality of dummy units, wherein, Each of the plurality of dummy cells includes a dummy base region as part of the base layer, and wherein at least one of the dummy cells and at least two of the insulating trenches are disposed between adjacent active cells in the active cell along the second direction.

19. The power semiconductor device according to claim 18, wherein, The insulating trench is disposed along the second direction between the dummy unit and the active unit, or between two dummy units.

20. The power semiconductor device according to any one of claims 1 to 5, further comprising a buffer layer having the second conductivity type, wherein, The buffer layer is disposed between the drift layer and the collector layer, and has a higher doping concentration than the drift layer.

21. The power semiconductor device according to any one of claims 1 to 5, wherein, This power semiconductor device includes an insulated-gate bipolar transistor.

22. A method for manufacturing a power semiconductor device, the method comprising: A semiconductor substrate is provided, comprising: A base layer disposed on a first side of the semiconductor substrate, wherein the base layer has a first conductivity type; and A drift layer having a second conductivity type opposite to the first conductivity type; The base layer and the drift layer are selectively etched to form an insulating trench and another insulating trench within the semiconductor substrate; A gate electrode is formed in each of the insulating trench and the other insulating trench, and each of the insulating trench and the other insulating trench is filled with a dielectric material; An emitter region having the second conductivity type is selectively formed within the base layer on the first side of the semiconductor substrate, wherein the emitter region and a portion of the base layer in which the emitter region is disposed provide a mesa region of an active cell, and wherein each of the insulating trench and the other insulating trench is adjacent to the active cell, and the gate electrode of the insulating trench is configured to control the on / off state of a current path within the active cell, and the gate electrode of the other insulating trench is configured to control the on / off state of another current path within the active cell, and wherein the mesa region is disposed between the insulating trench and the other insulating trench; and A collector layer is formed on a second side of the semiconductor substrate. The collector layer has a first conductivity type, wherein the second side is opposite to the first side, and the drift layer is disposed between the collector layer and the base layer. in: Each of the insulating trench and the other insulating trench is configured to extend along a first direction from the surface of a first side of the semiconductor substrate into the drift layer; The active unit has a first length L1 along a second direction perpendicular to the first direction, and the insulating trench has a second length L2 along the second direction; The first length L1 and the second length L2 satisfy the relationship 0.5 ≤ L2 / L1 ≤ 2; The active cell also includes a dummy gate trench, which includes a dummy gate insulating layer and a dummy gate electrode disposed therein; and The dummy gate trench is arranged along the second direction in the middle of the mesa region.

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