Circuit and method for entering test mode, chip, test device, electronic device

Abstract

The application discloses a circuit and method for entering a test mode, a chip, a test device and electronic equipment, and particularly relates to the technical field of circuit testing. The circuit for entering the test mode comprises a latch unit, which is used for receiving a start signal, obtaining an enable signal, latching the enable signal and obtaining a latched signal; and a signal processing unit, which is connected with the latch unit, is used for receiving the latched signal, entering a test mode, obtaining a test item of a to-be-tested chip in the test mode, and defining test content of the to-be-tested chip. The latch unit can receive the start signal, obtain the enable signal, latch the enable signal, obtain the latched signal, send the latched signal to the signal processing unit, the signal processing unit receives the latched signal, enters the test mode, obtains the test item of the to-be-tested chip in the test mode, and tests the to-be-tested chip according to the test item, so that the process of entering the chip test mode can be simplified.

Description

Technical Field

[0001] This application relates to the field of circuit testing technology, specifically to a circuit and method for entering a test mode, a chip, a test device, and an electronic device. Background Technology

[0002] Chip testing is a crucial step in the chip design process, and its cost is a significant component of the overall chip cost. Ideally, chip testing should cover and execute as many test items as possible without excessively increasing chip costs, while also ensuring that testers can easily and conveniently complete their testing tasks.

[0003] In current chip testing processes, entering chip test mode is often complex (e.g., requiring a dedicated test signal parsing module to analyze chip test signals), making it difficult for testers to enter test mode and thus affecting the chip's normal function. Furthermore, most chip circuits require reserving dedicated test pins to enter chip test mode. Such testing methods often increase chip area, waste additional I / O pin resources, and the process of entering chip test mode is also quite complex. Summary of the Invention

[0004] In view of this, embodiments of this application provide a circuit and method for entering a test mode, a chip, a test apparatus, and an electronic device to improve the problem of complex startup of existing chip test modes.

[0005] Firstly, this application provides a circuit for entering a test mode, comprising: A latching unit is used to receive a start signal, acquire an enable signal, latch the enable signal, and obtain a latch signal; A signal processing unit, connected to the latching unit, is used to receive the latching signal, enter a test mode, and acquire test items of the chip under test in the test mode. The test items are used to limit the test content of the chip under test.

[0006] Optionally, the start signal is received through a preset multiplexed port.

[0007] Optionally, the start signal includes a preset signal input from at least two multiplexed ports.

[0008] Optionally, the latching unit includes: a switching subunit for transmitting the start signal when it is turned on; a signal combining subunit connected to the switching subunit for acquiring the start signal, performing a preset combination based on the start signal, and outputting an enable signal; and a signal latching subunit connected to the signal combining subunit for acquiring the enable signal, latching the enable signal, and outputting the latched signal.

[0009] Optionally, the latching unit further includes: a signal shaping subunit, connected to the signal latching subunit, the switching subunit, and the signal combining subunit, for shaping the latched signal and outputting the shaped latched signal, and for shaping the start signal and providing the shaped start signal to the signal combining subunit.

[0010] Optionally, the switching subunit includes: a first switching transistor and a second switching transistor, wherein a first end of the first switching transistor and a first end of the second switching transistor are both connected to a signal input terminal, a second end of the first switching transistor and a second end of the second switching transistor are both grounded, and a third end of the first switching transistor and a third end of the second switching transistor are both connected to the signal combination subunit and a power supply.

[0011] Optionally, the signal combination subunit includes: a logic combination circuit, which is connected to the switch subunit and the signal latch subunit respectively, for acquiring the start signal, combining the start signal according to preset logic, and outputting the enable signal.

[0012] Optionally, when the start signal is a preset signal input to two multiplexed ports, the logic combination circuit includes a first delay, a first inverter, a first NAND gate, a second inverter, a second NAND gate, a third inverter, a third NAND gate, a fourth NAND gate, a second delay, and a fourth inverter; the first terminal of the first delay is connected to the first terminal of the first inverter, and the second terminal of the first inverter is used to receive a preset enable signal; the second terminal of the first delay is connected to the first terminal of the first NAND gate, and the second terminal and the third terminal of the first NAND gate are respectively used to receive the preset signal; the third terminal of the first delay is connected to the first terminal of the second inverter, and the second terminal of the second inverter is respectively used to receive the preset signal. The first terminal of the second NAND gate is connected to the first terminal of the third NAND gate, and the second terminal of the second NAND gate is connected to the first terminal of the third inverter. The second terminal of the third inverter is used to output the enable signal. The second terminal of the third NAND gate and the third terminal of the third NAND gate are respectively connected to the signal latch subunit, wherein the second terminal of the third NAND gate is used to receive a preset indication signal. The first terminal of the second delay is connected to the first terminal of the fourth NAND gate, and the second terminal of the fourth NAND gate and the third terminal of the fourth NAND gate are respectively used to receive the preset signal. The second terminal of the second delay is connected to the first terminal of the fourth inverter, and the second terminal of the fourth inverter is used to output the enable signal.

[0013] Optionally, the circuit for entering the test mode further includes an indicator unit connected to the signal processing unit, used to indicate that the current test mode is being entered according to the activation signal.

[0014] Optionally, the circuit for entering the test mode further includes: a data transmission unit connected to the signal processing unit, used to transmit the start signal and the control signal of the test item.

[0015] Optionally, the data transmission unit includes: a data input subunit connected to the signal processing unit, used to receive the indication signal of the test item and output the control signal of the test item.

[0016] Optionally, the data transmission unit includes a data output subunit connected to the chip under test, used to receive the test results of the chip under test and output the test results.

[0017] Optionally, the circuit for entering the test mode further includes: a start signal input port, which is connected to the latch unit, the data input subunit, and the data output subunit, respectively, for transmitting the start signal, the indicator signal of the test item, and the test result.

[0018] Secondly, this application provides a method for entering test mode, including: The enable signal is obtained from the start signal, and the enable signal is latched to obtain the latch signal; The circuit enters the test mode according to the latch signal to obtain the test items of the chip under test in the test mode, the test items being used to define the test content of the chip under test.

[0019] Thirdly, this application provides a chip that includes any of the above-mentioned circuits for entering a test mode, wherein the circuit for entering a test mode is used to execute the method for entering a test mode as described above.

[0020] Fourthly, this application provides a testing device comprising a housing, wherein the housing is provided with any of the aforementioned circuits for entering a test mode or any of the aforementioned chips, and the circuit for entering a test mode is used to execute the method for entering a test mode as described above.

[0021] Fifthly, this application provides an electronic device including any of the above-described circuits for entering a test mode, any of the above-described chips, or any of the above-described testing devices, wherein the circuit for entering a test mode is used to execute the method for entering a test mode as described above.

[0022] As can be seen from the above technical solution, the circuit for entering the test mode disclosed in this invention includes a latch unit that can receive a start signal, acquire an enable signal, latch the enable signal, obtain a latch signal, and send the latch signal to a signal processing unit. The signal processing unit is used to receive the latch signal and enter the test mode to acquire the test items of the chip under test in the test mode and test the chip under test according to the test items. This simplifies the process of entering the chip test mode and improves the test efficiency. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of the circuit for entering the test mode provided in an embodiment of the present invention.

[0025] Figure 2 This is a schematic diagram of the latch unit in the circuit for entering test mode provided in an embodiment of the present invention.

[0026] Figure 3 This is a schematic diagram of the circuit for entering the test mode provided in an embodiment of the present invention.

[0027] Figure 4 This is a schematic diagram of the circuit for entering the test mode provided in an embodiment of the present invention.

[0028] Figure 5 This is a schematic diagram of the circuit structure of the latch unit in the circuit for entering the test mode provided in an embodiment of the present invention.

[0029] Figure 6 The timing diagram for negative voltage latching of the circuit entering test mode provided in the embodiment of the present invention.

[0030] Figure 7 This is a timing diagram of the circuit for entering test mode provided in an embodiment of the present invention.

[0031] Figure 8 A flowchart illustrating the method for entering test mode provided in an embodiment of the present invention. Detailed Implementation

[0032] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application. Unless otherwise specified, the following embodiments and their technical features can be combined with each other.

[0033] To address the issue of complex startup procedures in existing chip test modes, embodiments of the present invention provide a circuit and method for entering test mode, a chip, a test device, and an electronic device.

[0034] See Figure 1 , Figure 1 This is a schematic diagram of a circuit for entering a test mode according to an embodiment of the present invention. The circuit for entering a test mode according to an embodiment of the present invention includes: a latch unit 10, used to receive a start signal, acquire an enable signal, latch the enable signal, and obtain a latch signal; and a signal processing unit 20, connected to the latch unit 10, used to receive the latch signal, enter a test mode, and acquire test items of a chip under test (not shown in the figure) in the test mode, wherein the test items are used to define the test content of the chip under test.

[0035] The circuit for entering the test mode provided in this embodiment can receive a start signal, acquire an enable signal, latch the enable signal, obtain a latch signal, and send the latch signal to the signal processing unit 20. After receiving the latch signal, the signal processing unit 20 enters the test mode to acquire the test items of the chip under test and control the chip under test to perform corresponding tests according to the test items. The whole process of entering the test mode is relatively simple and can simplify the start process of the chip test mode.

[0036] This invention provides a circuit for entering a test mode. Since the test mode startup process is complex in existing chip test modes, this embodiment simplifies the complexity by setting a latch unit 10. Based on the startup signal, an enable signal is acquired, and the enable signal is latched to generate a latch signal. The signal processing unit 20 then receives this latch signal to enter the test mode, begins acquiring test items for the chip under test, and executes the test work for the chip under test.

[0037] In one embodiment, to save chip port resources, the start signal can be received through the chip's multiplexed port.

[0038] In one example, the inventors further discovered that when the start signal is set to a single signal, the instability caused by the real-time transmission of a single signal can easily lead to the start signal being misjudged by the signal processing unit 20. To solve this problem, in this example, the start signal is set to a preset signal input from at least two multiplexed ports (e.g., the chip's PAD_EN port and PAD_A port). A stable start signal is obtained by detecting the two multiplexed ports.

[0039] Optionally, the preset signal provided in this example can be the same positive pressure signal, the same negative pressure signal, or a signal that can be set according to the user's own needs. For example, the preset signals received by the PAD_EN port and the PAD_A port are both negative pressure.

[0040] In one embodiment, the latch unit 10 may consist of a delay unit and a memory, or it may consist of a latch circuit, such as a latch. The latch unit 10 generates a latch signal by latching the input start signal, and sends the latch signal to the signal processing unit 20.

[0041] In one example, see Figure 2 As shown, Figure 2 This is a schematic diagram of the latch unit in the circuit for entering test mode provided in an embodiment of the present invention. Specifically, the latch unit 10 includes: The switching subunit 101 is used to transmit the start signal when it is turned on. The switching subunit 101 may include a field-effect transistor, such as a PMOS transistor or an NMOS transistor.

[0042] The signal combination subunit 102, connected to the switch subunit 101, is used to acquire a start signal, perform preset combinations based on the start signal, and output an enable signal. The output enable signal can be an enable signal provided to the signal processing unit or an enable signal provided by other control units. In this embodiment, outputting an enable signal is to ensure the circuit can operate normally.

[0043] The signal latch subunit 103, connected to the signal combination subunit 102, is used to acquire an enable signal, latch the enable signal, and output a latched signal. The signal latch subunit 103 may include a latch. In this embodiment, the use of a latch ensures the continuity of the enable signal, guaranteeing that the subsequent signal processing unit 20 can accurately identify the enable signal, thereby simplifying the startup method of existing chip test modes.

[0044] Optionally, the latch unit 10 further includes a signal shaping subunit 104, connected to the signal latch subunit 103, the switching subunit 101, and the signal combining subunit 102. This subunit shapes the latched signal, outputting the shaped latched signal, and shapes the start signal, providing a shaped start signal to the signal combining subunit 102. The signal shaping subunit 104 can be an inverter or a shaping unit circuit composed of discrete components. The signal shaping subunit 104 is provided to ensure that the output latched signal can be correctly recognized by the signal processing unit 20.

[0045] Optionally, the signal processing unit 20 can be a controller or control terminal, responsible for transmitting test item codes (such as test items) to determine and switch between test items. The signal processing unit may include at least one controller or control integrated circuit.

[0046] The circuit for entering test mode provided in this embodiment utilizes the signal transmission process of the latch unit 10 and the signal processing unit 20. When a user needs to test the chip, the user can first control the multiplexing of two chip pins, input a negative voltage to the two chip pins, and maintain it for a corresponding time to put the chip into test mode. The circuit for entering test mode provided in this embodiment realizes the multiplexing of chip pins, eliminates the need for storage devices, and prevents the user from easily entering other test modes (such as convenient test modes).

[0047] See Figure 3This is a schematic diagram of a circuit for entering a test mode according to an embodiment of the present invention. This embodiment provides a circuit for entering a test mode, which is used to enable a chip test mode. The circuit includes a latch unit 10, a signal processing unit 20, an indicator unit 30, a data transmission unit 40, and a start signal input port 50. It should also be noted that the start signal used in this embodiment is two negative voltage signals.

[0048] In this embodiment, the signal processing unit 20 is connected to the latching unit 10, the indicating unit 30, the data transmission unit 40, and the start signal input port 50, respectively. The latching unit 10 latches the input start signal and outputs a latched signal; the signal processing unit 20 receives the latched signal, determines based on the latched signal, and outputs the start signal and the control signal for the test item; the indicating unit 30 indicates the current test mode based on the start signal; the data transmission unit 40 transmits the start signal and / or the control signal for the test item; and the start signal input port 50 transmits the start signal and the indication signal for the test item. Optionally, the indication signal for the test item may include parameters or signals used to indicate the test process, and the signal processing unit 20 can generate the control signal for the test item based on the indication signal.

[0049] For example: Figure 4 As shown, Figure 4 This is a schematic diagram of an optional circuit structure for entering a test mode according to an embodiment of the present invention. The circuit for entering the test mode includes: a latch unit 10, a signal processing unit 20, an indicator unit 30, a data transmission unit 40, and a start signal input port 50. The data transmission unit 40 includes: a data input subunit 41 and a data output subunit 42. The data input subunit 41 is connected to the signal processing unit 20 and is used to receive the indicator signal of the test item and output the control signal of the test item; and / or, the data output subunit 42 is connected to the chip under test and is used to receive the test result of the chip under test and output the test result. The test result can be output via PAD_EN, which can be reused to further improve port utilization.

[0050] Optionally, the data input subunit 41 can be an I2C communication circuit or an I2C communication module.

[0051] In one example, the start signal input port 50 is connected to the latch unit 10, the data input subunit 41, and the data output subunit 42, respectively, for transmitting the start signal, the indicator signal of the test item, and the test result. Specifically, the start signal input port 50 is connected to the latch unit 10 for transmitting the start signal; the start signal input port 50 is connected to the data input subunit 41 for transmitting the indicator signal of the test item; and the start signal input port 50 is connected to the data output subunit 42 for transmitting the test result. This example can reuse the start signal input port 50, improving its utilization rate.

[0052] Optionally, the latch unit 10 is also connected to the signal processing unit 20, which in turn is connected to the indicator unit 30 and the data output subunit 42. Optionally, the signal processing unit 20 can also be connected to the chip under test (DUT), which is connected to the data output subunit 42. This allows the DUT to perform tests according to the test items transmitted by the signal processing unit 20 and send test results to the data output subunit 42, so that the data output subunit 42 outputs the corresponding test results.

[0053] Specifically, the user sends two negative voltage start signals to the start signal input port 50 (PAD_EN port, PAD_A port). The two negative voltage start signals are then transmitted to the input of the latch unit 10. The latch unit 10 receives the two negative voltage start signals and generates an enable signal based on them. After latching the enable signal, the latch unit 10 outputs a latch signal TM_EN to the signal processing unit 20. When the signal processing unit 20 receives the latch signal TM_EN (high level), it enters the test mode and obtains the corresponding test item from the data input subunit 41. After the corresponding test item is executed, the test item reset signal TM_RST can be set high to end the test of the corresponding test item and wait for other instructions from the user. In the test mode, the test item can be transmitted by the data input subunit 41.

[0054] In one embodiment of this application, the signal processing unit 20 receives a latch signal and enters a test mode. It can obtain test items from the data input subunit 41 and test the corresponding chip under test. The signal processing unit 20 can send a test mode start signal to the indication unit 30 to prompt the user that the current chip or device has entered the test mode; and / or, the signal processing unit 20 can send a test mode signal to the data output transmission subunit 42 and wait for the user to send the corresponding chip parameter test command or directly execute the corresponding preset chip parameter test.

[0055] Optional, such as Figure 5 As shown, Figure 5This is a schematic diagram of the circuit structure of the latch unit in the circuit for entering the test mode according to an embodiment of the present invention. The latch unit 10 includes: a switch subunit 101, a signal combination subunit 102, a signal latch subunit 103, and a signal shaping subunit 104. The switch subunit 101 includes a first switch transistor M1 and a second switch transistor M2. The first terminal of the first switch transistor M1 and the first terminal of the second switch transistor M2 are respectively used to receive a start signal. The second terminals of both the first switch transistor M1 and the second switch transistor M2 are grounded. The third terminals of both the first switch transistor M1 and the third terminals of the second switch transistor M2 are connected to the signal combination subunit 102 and the power supply.

[0056] Optionally, the signal combination subunit 102 includes a logic combination circuit, which is connected to the switch subunit 101 and the signal latch subunit 103 respectively, for acquiring a start signal, combining the start signal according to preset logic, and outputting an enable signal.

[0057] In one example, when the start signal is a preset signal input to two multiplexed ports, the logic combination circuit includes: a first delay unit Delay1, a first inverter N1, a first NAND gate P1, a second inverter N2, a second NAND gate P2, a third inverter N3, a third NAND gate P3, a fourth NAND gate P4, a second delay unit Delay2, a fourth inverter N4, an eighth inverter N8, and a tenth inverter N10.

[0058] The first terminal of the first delay unit Delay1 is connected to the first terminal of the first inverter N1, and the second terminal of the first inverter N1 is used to receive a preset enable signal. The second terminal of the first delay unit Delay1 is connected to the first terminal of the first NAND gate P1, the second terminal of the first NAND gate P1 is connected to the output terminal of the eighth inverter, the third terminal of the first NAND gate P1 is connected to the third terminal of the fourth NAND gate P4 and the output terminal of the tenth inverter, and the input terminals of the eighth inverter and the tenth inverter are both used to receive preset signals. The third terminal of the first delay unit Delay1 is connected to the first terminal of the second inverter N2, the second terminal of the second inverter N2 is connected to the first terminal of the second NAND gate P2 and the first terminal of the third NAND gate P3, the second terminal of the second NAND gate P2 is connected to the first terminal of the third inverter N3, and the second terminal of the third inverter N3 is used to output an enable signal. The second terminals of the third NAND gate P3 and the third terminal of the third NAND gate P3 are respectively connected to the signal latch subunit 103.

[0059] In this embodiment, the second terminal of the third NAND gate P3 is used to receive a preset indication signal; the first terminal of the second delay unit Delay2 is connected to the first terminal of the fourth NAND gate P4, and the second and third terminals of the fourth NAND gate P4 are respectively used to receive preset signals; the second terminal of the second delay unit Delay2 is connected to the first terminal of the fourth inverter N4, and the second terminal of the fourth inverter N4 is used to output an enable signal. In this embodiment, the preset enable signal and the preset signal are voltage values ​​predefined by the user through software.

[0060] The signal latch subunit 103 includes a latch, the first and second terminals of which are connected to the signal combination subunit 102, and the third terminal of which is connected to the signal shaping subunit 104. Specifically, the first terminal of the latch is connected to the second terminal of the third NAND gate M3, and the second terminal of the latch is connected to the third terminal of the third NAND gate M3.

[0061] The signal shaping subunit 104 includes: a fifth inverter N5, a sixth inverter N6, a seventh inverter N7, and a ninth inverter N9. The fifth inverter N5 and the sixth inverter N6 are connected in series, as are the seventh inverter N7 and the ninth inverter N9. The first terminal of the fifth inverter N5 is connected to the signal latching subunit 103, and the second terminal of the fifth inverter N5 is connected to the first terminal of the sixth inverter N6, which is used to output a latched signal. The first terminal of the seventh inverter N7 is connected to the third terminal of the first switch M1 and the power supply, and the second terminal of the seventh inverter N7 is connected to the first terminal of the eighth inverter N8 and the second terminal of the fourth NAND gate P4. The first terminal of the ninth inverter N9 is connected to the third terminal of the second switch M2 and the power supply, and the second terminal of the ninth inverter N9 is connected to the first terminal of the tenth inverter N10.

[0062] Optionally, the indicator unit 30 may be an LED indicator or a buzzer, used to provide voice or photoelectric prompts to the user.

[0063] In this embodiment, the switch subunit 101 acquires the start signal and conducts it when each port corresponding to the start signal meets certain conditions (such as all being negative voltage) to transmit the start signal; the signal combination subunit combines the start signal to ensure that it can be latched to the required chip test mode start signal, thereby ensuring that the chip test mode can be started normally.

[0064] In one example, such as Figure 4As shown, the signal processing unit 20 is the digital part of the chip, responsible for processing and transmitting test item codes to determine and switch between test items. After receiving the chip / device / equipment enable signal pin PAD_EN and another pin PAD_A continuously receiving negative voltage signals, the latch unit 10 latches the TM_EN signal high and uses this as the enable signal for the signal processing unit 20 to work. At the same time, the system enable signal (EN_SYSTEM) is kept at a high level to ensure that other modules of the chip can be enabled and work normally, thereby releasing the PAD_EN pin for testing.

[0065] Once the chip successfully enters the test mode, the signal processing unit 20 outputs a test mode start signal (TM_INI), causing the test status indicator circuit to have a detectable continuous pull-down current at the power supply VIN, which indicates that the chip has successfully entered the test mode.

[0066] The data input subunit 41 in the data transmission unit 40 communicates with the digital module via multiplexed pins, thereby controlling the switching of test items. The data output subunit 42 is used to transmit analog / digital test signals to the chip, and the selection of its transmission signal path is determined by the test item control signal (TM_MODE) output by the signal processing unit 20. After transmitting the specific test item code to the signal processing unit 20 via I2C communication, the signal processing unit 20 outputs a valid test item function signal (SDA_PD) to the data output subunit 42, and a detectable pull-down current appears at the start signal input port 50 to indicate that the chip has successfully entered the specific test item.

[0067] See Figure 6 and Figure 7 As shown, Figure 6 This is a timing diagram of the circuit entering test mode during negative voltage latching, provided in an embodiment of the present invention. Figure 7 This is a timing diagram of a circuit for entering test mode according to an embodiment of the present invention. The enable signal used in the circuit for entering test mode is as follows: Figure 6 , Figure 7 As shown, EN_SYSTEM is the enable control signal actually received by other modules, TM_EN is the enable latch signal, TM_RST is the test item reset signal, BG_OK is the bandgap reference voltage establishment completion indication signal generated by the bandgap reference circuit in the chip, and the BG_OK signal needs to be established after a certain delay time after being enabled. When the enable signal is invalid, the BG_OK signal also becomes low level. PAD_EN and PAD_A are the signal waveforms received by the chip's PAD_EN port and PAD_A port.

[0068] When the chip is operating normally, the start signal input to the PAD_EN port is high, and EN_SYSTEM is also high. To enter test mode, both the PAD_EN and PAD_A ports are pulled to negative voltage and held until the BG_OK signal is re-established. When the PAD_EN port receives a negative voltage, the BG_OK signal first drops low, and after a delay, point M goes high, followed by EN_SYSTEM. After another delay, the BG_OK signal is re-established, causing the latch output TM_EN to go high and latching it. At this point, the chip's required enable signal EN_SYSTEM is latched high, and the I / O pin PAD_EN can be released for testing. Simultaneously... Figure 5 The test status indicator circuit will show a detectable continuous pull-down current at the power supply VIN. By detecting this current, it can be determined whether the chip has successfully entered the test mode.

[0069] The timing of test mode operation is as follows Figure 7 As shown, after entering test mode, the required test item is selected via I2C communication. After communication is complete, the signal processing unit 20 outputs the control signal for the test item to the data output subunit 42. A detectable pull-down current appears at the start signal input port, the PAD_EN port, to indicate that the chip has successfully entered the specific test item. After the test item is completed, Figure 5 The start signal input port PAD_A is pulled to a negative voltage, making the TM_RST signal low. This signal is transmitted to the signal processing unit 20, causing it to exit the current test item (but not exit the test mode). Repeating the above operation can test all test items in the test mode. After the test is completed, power is turned off at the power supply VIN terminal to exit the test mode.

[0070] In this embodiment, the chip test mode is entered by simultaneously and continuously applying a negative voltage to two I / O pins. This eliminates the need for a dedicated test mode parsing circuit and reduces the likelihood of accidentally entering the test mode while the chip is operating normally. Furthermore, the I / O pins are reused, saving chip resources. A detectable current is provided as an indication signal upon successful entry into the test mode and upon successful entry into a specific test item.

[0071] See Figure 8 The present invention also provides a flowchart of a method for entering a test mode, which can be applied to the circuit for entering a test mode described in any of the above embodiments. Specifically, the method for entering a test mode includes: S1, Obtain the enable signal based on the start signal, latch the enable signal, and obtain the latch signal.

[0072] S2, a circuit that enters the test mode according to the latch signal, in order to obtain the test items of the chip under test in the test mode, the test items being used to define the test content of the chip under test.

[0073] The method for entering test mode provided in this embodiment uses a dual-pin negative voltage approach. This method is simple, requires no dedicated circuitry, and is less likely to be accidentally entered during normal chip operation, thus not affecting normal chip function. All test pins are multiplexed, eliminating the need for dedicated test pins and saving chip pin resources. Indicator signals identify the entry into test mode and the test item, making it easy to operate. Furthermore, the above method for entering test mode can be applied to the circuits described in any of the above embodiments, possessing all the beneficial effects of the circuits described in any of the above embodiments, and will not be elaborated further here.

[0074] This invention also provides a chip including the circuit for entering the test mode as described in any of the above embodiments, which can be used to execute the method for entering the test mode as described in any of the above embodiments.

[0075] This invention also provides a testing device, including a housing, within which is disposed a circuit for entering a test mode as described in any of the above embodiments or a chip as described in any of the above embodiments. The circuit or chip for the test mode can be used to execute the method for entering a test mode as described in any of the above embodiments.

[0076] This invention also provides an electronic device, including a circuit for entering a test mode as described in any of the above embodiments, a chip as described in any of the above embodiments, or a test device as described in any of the above embodiments. The circuit, chip, or test device for the test mode is used to execute the method for entering a test mode as described in any of the above embodiments.

[0077] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0078] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0079] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0080] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0081] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0082] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

Claims

1. A circuit for entering a test mode, characterized in that, include: A latching unit is used to receive a start signal, acquire an enable signal, latch the enable signal, and obtain a latch signal; A signal processing unit, connected to the latching unit, is used to receive the latching signal, enter a test mode, and acquire test items of the chip under test in the test mode. The test items are used to limit the test content of the chip under test. A data transmission unit, connected to the signal processing unit, is used to transmit the start signal and the control signal of the test item; The latching unit includes: a switching subunit for transmitting the start signal when it is turned on; a signal combining subunit connected to the switching subunit for acquiring the start signal, performing a preset combination based on the start signal, and outputting an enable signal; and a signal latching subunit connected to the signal combining subunit for acquiring the enable signal, latching the enable signal, and outputting the latching signal. The signal combination subunit includes a logic combination circuit, which is connected to the switch subunit and the signal latch subunit respectively, for acquiring the start signal, combining the start signal according to preset logic, and outputting the enable signal.

2. The circuit for entering the test mode according to claim 1, characterized in that, The start signal is received through a preset multiplexed port.

3. The circuit for entering the test mode according to claim 2, characterized in that, The start signal includes a preset signal input from at least two multiplexed ports.

4. The circuit for entering the test mode according to claim 1, characterized in that, The latch unit further includes: The signal shaping subunit is connected to the signal latching subunit, the switching subunit, and the signal combining subunit. It is used to shape the latched signal, output the shaped latched signal, and shape the start signal to provide the shaped start signal to the signal combining subunit.

5. The circuit for entering the test mode according to claim 1, characterized in that, The switching subunit includes: The first switch and the second switch are connected to the signal input terminal at their first and second ends, respectively. The second ends of the first and second switches are grounded, respectively. The third ends of the first and second switches are connected to the signal combination subunit and the power supply.

6. The circuit for entering the test mode according to claim 1, characterized in that, When the start signal is a preset signal input from two multiplexed ports, the logic combination circuit includes: First delay unit, first inverter, first NAND gate, second inverter, second NAND gate, third inverter, third NAND gate, fourth NAND gate, second delay unit and fourth inverter; The first terminal of the first delay is connected to the first terminal of the first inverter, and the second terminal of the first inverter is used to receive a preset enable signal; the second terminal of the first delay is connected to the first terminal of the first NAND gate, and the second and third terminals of the first NAND gate are respectively used to receive the preset signal; the third terminal of the first delay is connected to the first terminal of the second inverter, and the second terminal of the second inverter is connected to the first terminals of the second and third NAND gates respectively, the second terminal of the second NAND gate is connected to the first terminal of the third inverter, and the second terminal of the third inverter is used to output the enable signal; the second terminals of the third NAND gate and the third terminal of the third NAND gate are respectively connected to the signal latch subunit, wherein the second terminal of the third NAND gate is used to receive a preset indication signal; The first terminal of the second delay is connected to the first terminal of the fourth NAND gate, and the second and third terminals of the fourth NAND gate are respectively used to receive the preset signal; the second terminal of the second delay is connected to the first terminal of the fourth inverter, and the second terminal of the fourth inverter is used to output the enable signal.

7. The circuit for entering the test mode according to any one of claims 1 to 3, characterized in that, Also includes: An indicator unit, connected to the signal processing unit, is used to indicate that the current state is in test mode based on the start signal.

8. The circuit for entering the test mode according to claim 1, characterized in that, The data transmission unit includes: A data input subunit, connected to the signal processing unit, is used to receive the indication signal of the test item and output the control signal of the test item; and / or The data output subunit is connected to the chip under test and is used to receive the test results of the chip under test and output the test results.

9. The circuit for entering the test mode according to claim 8, characterized in that, Also includes: The start signal input port is connected to the latch unit, the data input subunit, and the data output subunit, respectively, and is used to transmit the start signal, the indicator signal of the test item, and the test result.

10. A method for entering test mode, characterized in that, The method for entering the test mode is applied to the circuit for entering the test mode according to any one of claims 1 to 9, comprising: The enable signal is obtained from the start signal, and the enable signal is latched to obtain the latch signal; The circuit enters the test mode according to the latch signal to obtain the test items of the chip under test in the test mode. The test items are used to define the test content of the chip under test.

11. A chip, characterized in that, The circuit includes the entry test mode as described in any one of claims 1-9, wherein the entry test mode circuit is used to perform the entry test mode method as described in claim 10.

12. A testing device, characterized in that, The device includes a housing, within which is disposed a circuit for entering a test mode as described in any one of claims 1-9 or a chip as described in claim 11, wherein the circuit for entering a test mode is used to perform the method for entering a test mode as described in claim 10.

13. An electronic device, characterized in that, Includes a circuit for entering a test mode as described in any one of claims 1-9, a chip as described in claim 11, or a test apparatus as described in claim 12, wherein the circuit for entering a test mode is used to perform the method for entering a test mode as described in claim 10.

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