Photonic IC chip

Abstract

The present disclosure relates to photonic IC chips. A photonic integrated circuit chip includes a vertical grating coupler defined in a first layer. A second insulating layer covers the vertical grating coupler and has an interconnect structure of metal levels embedded in the second insulating layer. A cavity extends through the second insulating layer in depth up to an intermediate level between the coupler and the metal level closest to the coupler. The cavity has lateral dimensions such that the cavity can accommodate a block for holding an array of optical fibers that are intended to be optically coupled to the coupler.

Description

[0001] Divisional Application Instructions

[0002] This application is a divisional application of Chinese patent application No. 202010232161.9, filed on March 25, 2020, entitled "Photonic IC Chip". Technical Field

[0003] This disclosure generally relates to photonic integrated circuits (optical and optoelectronic). Background Technology

[0004] During testing or operation of a photonic integrated circuit, optical signals are supplied to the circuit's optical inputs, and the corresponding optical signals can be observed or acquired at the circuit's optical output level. Optical fibers are used to transmit optical signals to the circuit's optical inputs, for example, optical signals supplied by one or more optical signal sources external to the circuit. Optical fibers can also be used to transmit optical signals acquired at the circuit's optical output level to external devices, such as optical signal analysis equipment.

[0005] Optical fibers used for exchanging optical signals with photonic integrated circuits are typically organized into fiber arrays, with the fibers held in place relative to each other within a holding block. The fibers are arranged in the holding block such that they all have a first end flush with the same surface of the holding block. The distribution of the first ends corresponds to the distribution of multiple optical inputs and / or outputs of the circuit. Therefore, when the first ends of the fibers in the fiber array are arranged opposite to such multiple optical inputs and / or outputs of the circuit, multiple optical signals can be exchanged with the circuit. Summary of the Invention

[0006] This disclosure generally relates to photonic integrated circuits (optical and optoelectronic). Specific embodiments relate to the exchange of optical signals with such circuits during test steps or during operation of such circuits.

[0007] The embodiments can overcome, for example, all or part of the disadvantages of known photonic integrated circuits, such as the manner in which the optical inputs and / or outputs of these circuits are optically coupled to optical fibers arranged in an optical fiber array within a holding block.

[0008] One embodiment provides a photonic integrated circuit chip including a plurality of couplers having vertical grating couplers defined in a first semiconductor or insulating layer, the first semiconductor or insulating layer having an interconnect structure on top of the first insulating layer including a plurality of metal levels embedded in a second insulating layer. A cavity extends downward in depth through the second insulating layer to an intermediate level between the couplers and the metal level closest to the couplers. The cavity has lateral dimensions such that the cavity can accommodate a block for holding an array of optical fibers intended to be optically coupled to the couplers.

[0009] According to one embodiment, the lateral dimension of the cavity is equal to the lateral dimension of the block plus the tolerance margin.

[0010] According to one embodiment, the tolerance margin is in the range of 10 μm to 200 μm, preferably in the range of 50 μm to 150 μm, and preferably substantially equal to 100 μm.

[0011] According to one embodiment, the first layer is a semiconductor layer of the semiconductor-on-insulator type, preferably made of silicon.

[0012] According to one embodiment, the first layer is an insulating layer made of silicon nitride.

[0013] According to one embodiment, the first layer is located on a third semiconductor layer of the semiconductor-on-insulator type, which is preferably made of silicon.

[0014] According to one embodiment, the bottom of the cavity is opposite to a plurality of couplers.

[0015] According to one embodiment, the chip also includes a protective ring surrounding the cavity on the upper surface of the interconnect structure, the protective ring being configured to prevent adhesive from flowing out of the ring when adhesive is disposed in the cavity and a block is inserted into the cavity.

[0016] According to one embodiment, the protective ring is formed by a plurality of metal micropillars regularly distributed along the circumference of the protective ring.

[0017] Another embodiment provides a component that includes a chip, as defined above, and a block for holding an array of optical fibers in an insertion cavity.

[0018] According to one embodiment, the assembly further includes an adhesive disposed in the cavity at least between the bottom of the cavity and the surface of the block, the adhesive preferably being an epoxy resin, the surface of the block being opposite the bottom of the cavity, the adhesive holding the block in place within the cavity.

[0019] Another embodiment provides a semiconductor wafer that includes a plurality of chips, such as those defined above, or a plurality of components, such as those defined above.

[0020] Another embodiment provides a method for implementation from a semiconductor wafer comprising a plurality of photonic circuit chips, each of the plurality of photonic circuit chips including a plurality of couplers having vertical grating couplers defined in a first semiconductor layer or a first insulating layer, the top of the first semiconductor layer or the first insulating layer having an interconnect structure including a plurality of metal levels embedded in a second insulating layer, the method comprising the steps of: etching a cavity from the upper surface of the interconnect structure, the cavity penetrating into the second layer up to an intermediate level between the coupler and the metal level closest to the coupler, the cavity having a lateral dimension such that the cavity can accommodate a block for holding an array of optical fibers, the array of optical fibers being intended to be optically coupled to the coupler.

[0021] According to one embodiment, the method further includes the step of sawing the wafer to individualize the chip.

[0022] According to one embodiment, for at least one chip, the method includes the following steps: distributing an adhesive, preferably epoxy resin, in a chip cavity; inserting and positioning a block in the cavity to optically couple the end of an optical fiber to a coupler; and preferably curing the adhesive by polymerization caused by exposure to light radiation, preferably ultraviolet light.

[0023] The foregoing and other features and advantages will be discussed in detail below in a non-limiting description of specific embodiments, taken in conjunction with the accompanying drawings. Attached Figure Description

[0024] Figure 1 A cross-sectional view schematically illustrates one embodiment of a photonic integrated circuit to which the described embodiments are applied, as an example.

[0025] Figure 2 includes Figure 2A and Figure 2B The two views in the middle, Figure 2A and Figure 2B The steps of one embodiment of the method are shown;

[0026] Figure 3 includes Figure 3A and Figure 3B The two views in the middle, Figure 3A and Figure 3B Another step of one embodiment of the method is shown;

[0027] Figure 4 A cross-sectional view is schematically shown, illustrating the steps of Figure 2 according to an alternative embodiment; and

[0028] Figure 5 includes Figure 5A and Figure 5B Two views, Figure 5A and Figure 5BAn alternative embodiment of the method described with respect to Figures 2 and 3 is shown. Detailed Implementation

[0029] In different figures, the same elements are represented by the same reference numerals. In particular, structural and / or functional elements common to different embodiments can be designated by the same reference numerals and can have the same structure, dimensions, and material properties.

[0030] For clarity, only steps and elements useful for understanding the described embodiments are shown and described in detail. In particular, the fabrication, operation, and testing (selection of optical and electrical input signals and interpretation of corresponding output signals) of the photonic integrated circuit are not described in detail, and the described embodiments are compatible with ordinary photonic integrated circuits.

[0031] Throughout this disclosure, the term "connection" (electrical or optical) is used to refer to a direct electrical or optical connection between circuit elements without any intermediate element other than an electrical conductor or optical waveguide, while the term "coupled" (electrical or optical) is used to refer to an electrical or optical connection between circuit elements, which may be direct or may be via one or more other elements. Furthermore, unless otherwise stated, when referring to optically coupled optical fibers and optical inputs or outputs, it means that the optical fibers and optical inputs or outputs are arranged such that an optical signal can be transmitted between the optical fiber and the optical input or output, rather than through evanescent coupling or near-field coupling, and the distance between such coupled optical fibers and optical inputs or outputs can be greater than one or several times the wavelength of the optical signal.

[0032] In the following description, unless otherwise stated, when referring to terms that define absolute position (such as the terms "front", "back", "top", "bottom", "left", "right", etc.) or terms that define relative position (such as the terms "above", "below", "up", "down", etc.) or terms that define direction (such as "horizontal", "vertical", etc.), refer to the orientation shown in the accompanying drawings.

[0033] The terms “about,” “approximately,” “substantially,” and “approximately” are used herein to indicate a tolerance of plus or minus 10%, preferably plus or minus 5%, for the value under discussion.

[0034] Figure 1 The following block diagram schematically illustrates one embodiment of a photonic integrated circuit chip 1000 to which the described embodiments are applied, as an example. It should be understood that the embodiments described below are not limited to this particular example of a chip or photonic integrated circuit.

[0035] Chip 1000 includes a semiconductor layer 10, preferably made of silicon, situated on an insulating layer 12 (BOX), preferably made of silicon dioxide, which itself rests on a support 14, such as a silicon substrate. Layer 10 is considered to be of the SOI (“semiconductor on insulator”) type, or simply a layer of an SOI device.

[0036] In this embodiment, various optical and / or optoelectronic components are defined inside and / or on top of layer 10. Specifically, waveguide 16 is defined in layer 10. Figure 1 A single waveguide 16 is shown. The optical inputs / or outputs 18 of the chip 1000, i.e., the optical inputs and / or outputs of the photonic integrated circuits included in the chip 1000, are arranged at the ends of the waveguide 16. Figure 1 A single optical input 18 is shown. In the described embodiment, the case is considered where these optical inputs and / or outputs are vertical grating couplers (VGCs). Like waveguide 16, coupler 18 is defined in layer 10. Figure 1 In the example, a phase modulator 20 is also defined in layer 10.

[0037] Layer 10 is covered by insulating layer 22. Layer 22 is in contact with layer 10. Layers 12 and 22 form an optical sheath with a refractive index lower than that of layer 10. Although the upper layer of layer 22 is located above the upper layer of layer 10 here, as a variant, the upper layer of layer 22 may be confounded with the upper layer of layer 10.

[0038] Despite Figure 1 Electronic components, such as transistors, may be defined inside and / or on top of layer 10, but are not shown in the diagram.

[0039] Interconnect structure 24 covers layer 22. Interconnect structure 24 includes a portion of metal layer 26 separated by insulating layers (28A and 28B in this example) and metal vias 30. Metal vias 30 pass through insulating layers 28A and 28B and may extend through a portion of the thickness of insulating layer 22 to electrically couple portions of metal layer 26 together and / or to components of chip 1000 defined inside and / or on top of layer 10, and / or to contact pads 32 at layers arranged on the upper surface of interconnect structure 24. Vias 32 and / or portions of metal layer 26 that are not electrically coupled to or connected to pads 32 or components of chip 1000 may be provided in interconnect structure 24.

[0040] The components of a portion of the metal layer 26 arranged at the same level in the interconnect structure 24 are called metal layers or metallization layers. In the example shown, the chip includes four consecutive metal layers M1, M2, M3 and M4, with metal layer M1 arranged on one side of layer 10, or in other words, the metal layer closest to layer 10.

[0041] exist Figure 1 In the example, each metal level M1, M2, M3, and M4 is arranged in layer 28B, which is preferably made of silicon dioxide, and the upper level of the metal level is flush with the upper surface of layer 28B in which the metal level is arranged. Furthermore, in Figure 1 In the example, layer 28A, preferably made of silicon nitride, is located on top of and preferably in contact with the upper surface of each component of the metal hierarchy and layer 28B, in which the metal hierarchy is disposed. This alternation of layers 28A and 28B is produced, for example, by a manufacturing method implemented to form interconnect structure 24. The described embodiment is not limited to this particular example of interconnect structure 24.

[0042] like Figure 1 As shown, one or more insulating layers (in this example, insulating layers 34A and 34B) may be arranged or inserted between the components of layers 10 and 22 and the interconnect structure 24. In this case, vias 30 of the interconnect structure 24 may pass through insulating layers 34A and 34B to electrically couple components formed inside and / or on top of layer 10 to the remainder of the interconnect structure. More specifically, in Figure 1 In one example, layer 34B, made of silicon dioxide, is inserted between layer 10 and interconnect structure 24. Preferably, as... Figure 1 As shown, layer 34A, preferably made of silicon nitride, is located on top of and in contact with layer 34B, and layer 34B is located on top of and in contact with another layer 34A, preferably made of silicon nitride.

[0043] In this embodiment, layer 38 is disposed within layer 34B. In this example, layer 38 is preferably made of silicon nitride, while layer 34B is made of silicon dioxide. Therefore, layer 34B covers layer 38 and has an interconnect structure 24 on top. A waveguide 36 is defined within layer 38. Figure 1 A single waveguide 36 is shown. Regarding waveguide 16, a vertical grating coupler 40 is disposed at the end of waveguide 36. Like waveguide 36, coupler 40 is defined in layer 38. Coupler 40 forms the optical input and / or output of chip 1000.

[0044] The operation of the vertical grating coupler is based on the phenomenon of diffraction. Couplers 18 and 40 of chip 1000 are configured to emit (optical output) or receive (optical input) a light beam (optical signal) propagating in a direction substantially orthogonal to the planes of layers 10 and 38, which are parallel to the upper surface of layer 12. As an example, couplers 18 and 40 are configured to emit or receive the light beam in a direction forming an angle α with the normal to the planes of layers 10 and 38, for example, in the range of 20 degrees to 5 degrees, such as approximately 8 degrees or 13 degrees. As an example, when the diameter of the received or emitted light beam is approximately 10 μm, the vertical grating coupler occupies a surface area of ​​approximately 20 μm by approximately 30 μm.

[0045] Despite Figure 1 Not shown, but chip 1000 includes at least one component of a plurality of couplers 18 intended for optical coupling to a first corresponding end of an optical fiber arranged in a holding block. Similarly, chip 1000 includes at least one component of a plurality of couplers 40 intended for optical coupling to a first corresponding end of an optical fiber arranged in a holding block.

[0046] Waveguides 16 and / or 36 and couplers 18 and / or 40 are preferably configured to operate at near-infrared wavelengths, i.e., wavelengths in the range of 1 μm to 2 μm, preferably equal to about 1.3 μm or about 1.55 μm, for example equal to 1.3 μm or 1.55 μm.

[0047] This document has shown one embodiment in which chip 1000 includes silicon coupler 18 and silicon nitride coupler 40. In an alternative embodiment not shown, coupler 18 may be omitted, and chip 1000 includes only coupler 40. In this variant, waveguide 16 may be omitted. Conversely, in another alternative embodiment, coupler 40 may be omitted, and chip 1000 includes only coupler 18. In this other variant, waveguide 36 may be omitted.

[0048] Furthermore, chip 1000 can be one of a plurality of identical chips 1000 manufactured from the same conductive wafer, or in other words, the semiconductor wafer can include a plurality of identical chips 1000. Chip 1000 can also be an individualized chip, i.e., one of the chips 1000 obtained after the step of sawing a semiconductor wafer comprising a plurality of identical chips 1000.

[0049] Figure 2 schematically shows two views ( Figure 2A and Figure 2B These two views illustrate the steps of an embodiment of a photonic integrated circuit chip manufacturing method. Figure 2A and Figure 2BThese are corresponding cross-sectional and top views of a portion of chip 1000 after this step has been implemented. More specifically, Figure 2A A portion of the chip 1000 shown corresponds to along Figure 2B A portion of the cross-sectional view of the cross-sectional plane AA.

[0050] In this embodiment, the chip 1000 includes a plurality of couplers 18 (six couplers 18 in this example) designed to optically couple to a first corresponding end of an optical fiber in an optical fiber array held in place in a holding block.

[0051] In the steps of Figure 2, chip 1000 is preferably formed as part of a semiconductor wafer comprising a plurality of identical chips 1000, and the steps described herein are performed simultaneously for all chips 1000 in the wafer.

[0052] In this step, the cavity 200 has been etched from the upper surface of the interconnect structure 24, that is, from the upper surface of the insulating layer 28A at the top of the structure 24 in this example. The cavity 200 is etched through the insulating layers 28A and 28B of the interconnect structure 24. The etching of the cavity 200 stops at an intermediate layer between the lower layer closest to the metal layer (here, metal layer M1) of the coupler 18 and the upper layer of the layer 10 that defines the coupler 18. In other words, etching is performed such that the bottom 201 of the cavity 200 is disposed at this intermediate layer. Preferably, the intermediate layer is above the upper layer of the layer 22 of the cover layer 10. In the example of FIG. 2, the etching stops in layer 34B.

[0053] It should be noted that, Figure 2B Although adjacent portions of couplers 18 and waveguides 16 are visible at the bottom of cavity 200, these couplers 18 and waveguide portions 16 are coated with at least one insulating layer, which in this example is a portion of the thickness of layer 22, lower layer 34A, and layer 34B. Furthermore, pads 32 are not shown in view B.

[0054] Furthermore, as can be seen from view B of Figure 2, the cavity 200 is completely surrounded by the interconnect structure 24. In other words, the cavity 200 is completely defined by the interconnect structure 24 in the lateral direction.

[0055] The lateral dimension of cavity 200 is determined by the dimensions of the fiber array holding block. Therefore, cavity 200 is capable of accommodating the fiber array holding block. In practice, the holding block is designed to be at least partially inserted into cavity 200 such that the first end of the fiber array is optically coupled to coupler 18. More specifically, the lateral dimension of cavity 200 is slightly larger than the corresponding lateral dimension of the fiber array holding block. Preferably, the lateral dimension of the cavity is equal to the corresponding lateral dimension of the holding block plus a tolerance margin. The tolerance margin is, for example, in the range of 10 μm to 200 μm, preferably in the range of 50 μm to 150 μm, and preferably substantially equal to 100 μm. Although manufacturing dispersion may occur during etching, such a tolerance margin allows it to be determined that the holding block can be inserted into the cavity. The tolerance margin also allows the orientation of the holding block in the cavity to be modified so that the first end of the fiber in the array and the coupler 18 are aligned, such alignment taking into account the possible angle α between the propagation directions of the beam between the first end of the fiber in the array and the corresponding coupler 18.

[0056] Furthermore, the position of cavity 200 is determined by the position of coupler 18, to which the first end of the optical fiber in the fiber array is intended to be coupled. More specifically, the position of cavity 200 is determined such that, when the fiber holding block of the fiber array is inserted into the cavity, the first end of the optical fiber in the fiber array is optically coupled to coupler 18, taking into account a possible angle α. Preferably, a step of fine alignment of the optical fiber and coupler 18 is implemented, during which the orientation of the block in cavity 200 and / or the depth of the block insertion into cavity 200 are modified to maximize the optical coupling between the first end of the optical fiber in the fiber array and coupler 18.

[0057] As an example of dimensions, the width of the block used to hold the optical fibers in an optical fiber array comprising six optical fibers is approximately a few millimeters, for example less than 3 mm, for example approximately 2 mm, and the length is also a few millimeters, for example shorter than 7 mm, for example approximately 5 mm.

[0058] Figure 3 schematically shows Figure 3A and Figure 3B , Figure 3A and Figure 3B Another step of one embodiment of the method is shown. After the implementation of this other step, Figure 3A and Figure 3B Corresponding to the corresponding Figure 2A and Figure 2B .

[0059] In this step, chip 1000 is preferably an individualized chip, although this step can be performed while chip 1000 is still part of a semiconductor chip comprising multiple identical chips 1000.

[0060] In this step, adhesive 300 has been disposed within cavity 200. For example, adhesive 300 fills cavity 200 and is flush with the exposed surface of interconnect structure 24, and adhesive 300 can also protrude above the exposed surface of interconnect structure 24 by, for example, about 2 μm. Adhesive 300 is selected such that optical signals transmitted between the optical fiber and coupler 18 in the fiber array can propagate within the adhesive. In other words, adhesive 300 is transparent to the wavelength of the optical signal in question. As an example, adhesive 300 is an epoxy resin adhesive, preferably an epoxy resin adhesive whose curing is caused by polymerization (e.g., by irradiating adhesive 300 with ultraviolet light).

[0061] Furthermore, in this step, a retaining block 302, for example made of glass, in which optical fibers 304 of the optical fiber array are arranged, has been inserted into the cavity 200. Figure 3A A single fiber optic cable (304) is visible in the image. Figure 3B In the image, optical fiber 304 is not shown, and although portions of coupler 18 and waveguide 16 are visually shown, they have an insulating layer and block 302 on top.

[0062] More specifically, block 302 is inserted such that the first end of optical fiber 304 is flush with the surface 306 of block 302 (i.e., Figure 3A The lower surface of block 302 in the cavity is opposite to the bottom 201 of cavity 200, and therefore opposite to coupler 18.

[0063] Therefore, adhesive 300 extends from the surface 306 of block 302 to the bottom 201 of cavity 200. Preferably, the amount of adhesive 300 disposed in cavity 200 is selected such that when block 302 is inserted into cavity 200, adhesive 300 creeps upward along the side surface of block 302 and at least partially fills the available space between the side surface of block 302 and the sidewall of cavity 200. This allows for increased stability or mechanical resistance of the assembly of chip 1000 and block 302 after adhesive 300 has hardened, compared to the case where adhesive 300 is only present between the bottom 201 of cavity 200 and the surface 306 of block 302. In the example shown, adhesive 300 completely fills the available space and overflows on the upper surface of interconnect structure 24.

[0064] The orientation of block 302 and the possible insertion depth of block 302 into cavity 200 are determined to optimize (i.e., maximize) the optical coupling between fiber optic 304 and coupler 18. The implementation of the step of maximizing or finely aligning the optical coupling between the fiber optic array holding the block and the vertical grating coupler of the integrated circuit chip is within the capabilities of those skilled in the art and will not be described in detail here. As an example, this step can be achieved by supplying an optical signal to coupler 18 via fiber optic 304 and modifying the orientation of block 302 and the possible insertion depth of block 302 into cavity 200 to maximize the output quantity of the chip, such as the amplitude of an electrical signal, which depends on the amount of light received by coupler 18 or the amount of light supplied by another coupler 18 optically coupled to the receiving coupler 18.

[0065] After block 302 is positioned in cavity 200, a curing step of adhesive 300 is performed. For example, adhesive 300 is cured by exposure to a light source, preferably ultraviolet light. According to another example, adhesive is cured by heating.

[0066] Instead of providing a cavity 200 for inserting block 302 therein, the cavity 200 can be designed to bond block 302 directly to the upper surface of interconnect structure 24, possibly after removing the last insulating layer of interconnect structure 24 (in this case 28A, which actually forms a passivation layer) at least where block 302 is bonded.

[0067] However, due to the larger number of insulating layers 28A and 28B that the optical signal will pass through between the optical fiber 304 and the coupler 18, the transmission loss between the first end of the optical fiber 304 of block 302 and the corresponding coupler 18 will be significantly greater than that shown in Figure 3. Such transmission loss will, for example, be in the range of 0.1 dB to 1 dB.

[0068] Furthermore, the adhesive used to bond block 302 to the upper surface of interconnect structure 24 will spread further on the upper surface than when adhesive 300 is initially arranged in cavity 200 as described in conjunction with FIG. 3. Moreover, such localized deposition of adhesive at the location where block 302 will be bonded will be more difficult to achieve compared to the case described with respect to FIG. 3. Therefore, taking chip 1000 as an example, this will result in the pads 32 being arranged further away from block 302 when bonding block 302 to the upper surface of interconnect structure 24, compared to the case where block 302 is at least partially inserted into cavity 200. In other words, the provision of cavity 200 makes it possible to increase the integration density of chip 1000, particularly with respect to the electrical connection elements formed at the layer level on the upper surface of interconnect structure 24.

[0069] Furthermore, contrary to the case described with respect to Figure 3, it would be difficult, or even impossible, to modify the height of block 302 relative to coupler 18 to maximize the optical coupling between fiber 304 and coupler 18.

[0070] Alternatively, a cavity can be provided above each coupler 18, or in other words, each coupler 18 can have its own cavity. This allows for a reduction in the transmission loss of the optical signal between the fiber 304 and the corresponding coupler 18.

[0071] However, the lateral dimension of each cavity will therefore be approximately the lateral dimension of the coupler 18 above which the cavity is positioned, for example, a width and length of approximately 50 μm, respectively (e.g., measured in a plane parallel to the plane of layer 10). In other words, the lateral dimension of each cavity above the corresponding coupler 18 will be much smaller than the lateral dimension of cavity 200, for example, by at least a factor of 5. Compared to the case of FIG. 3, in which adhesive 300 fills the space between the bottom 201 of cavity 200 and the surface 306 of block 302, it will be much more difficult to fill the available space between the bottom of the cavity and the surface 306 of block 302 with adhesive.

[0072] Furthermore, because at least a portion of block 302 is inserted into cavity 200, the height of the portion of block 302 protruding from the upper surface of interconnect structure 24 is less than if block 302 were directly bonded to that upper surface. This reduces the risk of block 302 tearing during the assembly of chip 1000 and block 302. The mechanical resistance of the chip 1000 assembly is even greater when adhesive 300 fills all or part of the available space between the sidewall of cavity 200 and the side surface of block 302. Such mechanical resistance cannot be achieved if block 302 were directly bonded to the upper surface of interconnect structure 24, and therefore if the adhesive were only disposed between surface 306 of block 302 and the upper surface of interconnect structure 24, and possibly along the lower portion of the side surface of block 302.

[0073] Because the cavity 200 is entirely defined laterally by the interconnect structure 24, the block 302 is held in place better when at least partially inserted into the cavity 200 compared to when the block 302 is positioned on the edge of the chip 1000 (e.g., on a shoulder disposed on that edge of the chip 1000). In fact, by placing the block 302 on the edge of the chip 1000, at least some of the side surfaces of the block 302 will not be opposite the wall of the cavity 200. Furthermore, placing the block 302 on the edge of the chip 1000 makes it difficult, if not impossible, to individualize the chip 1000 after the block 302 has been assembled with the chip 1000.

[0074] It can also be designed to use a block for holding the optical fibers in the fiber array, such that after being inserted into the cavity 200, the first end of the optical fiber in the array is flush with the same side surface of the holding block, such that the first end is directly attached to the corresponding end of the plurality of waveguides 16 (“butt coupling”), thus omitting the coupler 18.

[0075] In this case, the bottom of the cavity 200 should have a cross layer 10 defining the waveguide 16, which will reduce the number or surface area of ​​layers 10 that can be used to form components therein.

[0076] Furthermore, coupling by placing the fiber end directly against the end of waveguide 16 is less efficient than coupling to coupler 18. In fact, the size of waveguide 16 is much smaller than the core size of fiber 304, and the amount of light transmitted from the fiber to the waveguide will be less than in the case of coupler 18, which allows for the collection of a greater amount of light.

[0077] Furthermore, compared to the accuracy of aligning the end of the optical fiber 304 with the coupler 18 (alignment accuracy, for example, about 1 μm), when coupling is performed by placing the end of the optical fiber directly against the end of the waveguide 16, the alignment of the end of the optical fiber with the end of the waveguide 16 should be performed with higher accuracy (for example, about 0.1 μm).

[0078] Figure 4 A cross-sectional view is schematically shown, illustrating the steps of Figure 2 according to an alternative embodiment.

[0079] In this alternative embodiment, the chip 1000 includes a plurality of couplers (e.g., six couplers 40), a single coupler of which is shown in FIG3, which are intended to optically couple to a first corresponding end of an optical fiber 304 in an optical fiber array held in place in the holding block 302.

[0080] exist Figure 4 In the steps described herein, chip 1000 is preferably formed as part of a semiconductor wafer comprising a plurality of identical chips 1000, and the steps described herein are performed simultaneously for all chips 1000 in the wafer.

[0081] In this step, instead of etching the cavity 200 at the location determined by the position of the components of the coupler 18, the cavity 200 is etched at a location determined by the position of the first corresponding end of the fiber 304 in the fiber array held in block 302 to which the coupler 40 is coupled.

[0082] Similar to the description regarding Figure 2, in Figure 4The etching of the cavity, as shown, stops at an intermediate layer between the lower layer of the metal layer closest to the coupler 40 (here, metal layer M1) and the upper layer of the layer 36 having the coupler 40 defined therein. Preferably, this intermediate layer is above the upper layer of the cover layer 10, layer 34B. Figure 4 In the example, the etching stops in layer 28B, in which the metal layer M1 is arranged.

[0083] The lateral dimensions and / or position of cavity 200 are determined similarly to those described with respect to Figure 2, except that the coupler considered here is coupler 40 instead of coupler 18.

[0084] In the next step (not shown), similar to that described with respect to Figure 3, adhesive 300 is arranged in cavity 200, and then block 302 for holding optical fibers 304 in the array is inserted into cavity 200. Adapt the description of coupler 18 and waveguide 16 with respect to Figure 3 to that of coupler 40 and waveguide 36. Figure 4 The situation is within the capabilities of those skilled in the art.

[0085] Furthermore, all the advantages indicated above with respect to Figures 2 and 3 can be found in this alternative embodiment, which considers coupler 40, waveguide 36, and layer 38 instead of the corresponding coupler 18, waveguide 16, and layer 10.

[0086] Figure 5 schematically includes Figure 5A and Figure 5B , Figure 5A and Figure 5B Alternative embodiments of the methods described with respect to Figures 2 and 3 are shown. Figure 5A and Figure 5B Corresponding to Figure 3A and Figure 3B The corresponding view.

[0087] In this alternative embodiment, chip 1000 is provided as including a protective ring 500 surrounding cavity 200 on the upper surface of interconnect structure 24. The protective ring protrudes from the upper surface of interconnect structure 24. As shown in FIG5, the protective ring is configured to reduce or even prevent adhesive 300 from flowing out of the protective ring 500 when block 302 is inserted into cavity 200.

[0088] In this example, the protective ring 500 is formed by a plurality of metal micropillars 502 distributed on the circumference of the protective ring 500, the micropillars 502 extending in the height direction orthogonal to the upper surface of the interconnect structure 24. In other words, the micropillars 502 are arranged one after another along the circumference of the ring. Preferably, two consecutive micropillars 502 are separated by the same spacing, or in other words, the same distance. Preferably, the spacing is determined by the viscosity of the adhesive 300 used, such that when the adhesive 300 reaches the protective ring 500, the flow of the adhesive 300 on the upper surface of the interconnect structure 24 is reduced, or even prevented.

[0089] Preferably, the micropillar 502 is the same as the micropillar (not shown) for the electrical connection of chip 1000 to another integrated circuit chip, intermediate, or printed circuit. As an example, each micropillar 502 is located on top of and in contact with pad 32 at a layer disposed on the upper surface of interconnect structure 24. Thus, preferably, the pad 32 is not electrically connected to any component of chip 1000 through via 30 and the metal layers M1, M2, M3, and M4 of interconnect structure 24.

[0090] As an example of dimensions, each micropillar 502 has a height of approximately 10 μm, for example, a diameter of approximately 20 μm, and a space between two adjacent micropillars 502 is, for example, approximately 20 μm.

[0091] Compared to the case where block 302 is directly bonded to the upper surface of interconnect structure 24 and such a protective ring 500 is provided, this protective ring will be larger than in the case of FIG. 5, or in other words, it will be arranged at a greater distance from block 302 than in the case of FIG. 5. Therefore, this allows electrical connection elements (e.g., other micropillars, metal balls, pads 32, etc.) to be closer to block 302 than in the case where block 302 is directly bonded to the upper surface of interconnect structure 24.

[0092] Such alternative embodiments and their advantages are applicable to... Figure 4 The described alternative embodiments.

[0093] In the above about Figure 1 In the embodiments and variations depicted in Figure 5, no portion of the through-hole 30 and the metal layer 26 is provided at the location of cavity 200, or in other words, above coupler 18 and correspondingly above coupler 40. However, in Figure 1 In known chips of the type shown, it is already the case that the chip does not have a cavity 200 and the block 302 is intended to be directly bonded to the upper surface of the interconnect structure 24. In fact, in such known chips, the presence of the via 30 or a portion of the metal layer 26 will interfere with or even prevent the propagation of optical signals between the optical fiber 304 and the corresponding coupler 18 or 40. Therefore, regarding Figures 2 and 3... Figure 4The embodiments and variations described in Figure 5 are compatible with known photonic chips.

[0094] Furthermore, although the advantages of the above embodiments and variations have been indicated relative to the chip 1000 and the components of the block 302 for holding the optical fibers 304 in the optical fiber array, such advantages are inherent in the chip 1000 provided with the cavity 200, or in other words, are due to the provision of the cavity 200 in the chip 1000.

[0095] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations can be combined, and other variations will occur to those skilled in the art.

[0096] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variations is within the capabilities of those skilled in the art.

[0097] Such changes, modifications, and improvements are intended to be part of this disclosure and are intended to fall within the spirit and scope of the invention. Therefore, the foregoing description is by way of example only and is not intended to be limiting. The invention is defined solely by the appended claims and their equivalents.

Claims

1. A method for manufacturing a chip, comprising: Multiple vertical grating couplers are formed in the first layer of the semiconductor component, the first layer including a semiconductor layer or an insulating layer; Multiple second insulating layers are covered on the plurality of vertical grating couplers; An interconnect structure is formed, the interconnect structure including a plurality of metal layers and a plurality of metal vias embedded in the second insulating layer; One or more phase modulators are formed in the first layer, each phase modulator being coupled to a corresponding metal via. as well as An etched cavity extends in depth through the second insulating layer to an intermediate layer between the plurality of vertical grating couplers and the metal layer closest to the plurality of vertical grating couplers. The cavity has a lateral dimension such that it can accommodate a block for holding an array of optical fibers designed to be optically coupled to the plurality of vertical grating couplers.

2. The method according to claim 1, wherein, The lateral dimension of the cavity is equal to the lateral dimension of the block plus the tolerance margin.

3. The method according to claim 2, wherein, The tolerance margin is between 10 μm and 200 μm.

4. The method according to claim 2, wherein, The tolerance margin is between 50 μm and 150 μm.

5. The method according to claim 1, wherein, The first layer is the semiconductor layer of a semiconductor-on-insulator (SOI) device.

6. The method according to claim 1, wherein, The first layer is an insulating layer made of silicon nitride.

7. The method according to claim 6, wherein, The first layer is disposed on the semiconductor layer of the semiconductor-on-insulator device, and wherein the cavity has a bottom opposite the plurality of vertical grating couplers.

8. The method according to claim 1, wherein, It also includes a protective ring surrounding the cavity on the upper surface of the interconnect structure, wherein the protective ring is formed of a plurality of metal micropillars that are regularly distributed along the circumference of the protective ring.

9. A method comprising: Form the first insulating layer; Multiple vertical grating couplers are formed in the first insulating layer; Multiple second insulating layers are covered on the plurality of vertical grating couplers; An interconnect structure is formed, the interconnect structure including a plurality of metal layers and a plurality of metal vias embedded in the second insulating layer; One or more phase modulators are formed in the first insulating layer, and each phase modulator is coupled to a corresponding metal via. as well as An etched cavity is formed that extends in depth through the second insulating layer to an intermediate layer between the plurality of vertical grating couplers and the corresponding metal layers closest to the plurality of vertical grating couplers.

10. The method according to claim 9, wherein, The cavity includes a lateral dimension such that it can accommodate a block for holding an array of optical fibers, the array of optical fibers being optically coupled to the vertical grating coupler.

11. The method of claim 10, wherein the lateral dimension of the cavity is equal to the lateral dimension of the block plus a tolerance margin, and wherein the cavity has a bottom opposite the plurality of vertical grating couplers.

12. The method according to claim 9, wherein, The first insulating layer is disposed on the semiconductor layer of the insulator-on-semiconductor device.

13. The method according to claim 9, wherein, It also includes a protective ring on the upper surface of the interconnect structure surrounding the cavity, wherein the protective ring is formed of a plurality of metal micropillars that are regularly distributed along the circumference of the protective ring.

14. A method for realizing an individualized chip from a semiconductor wafer comprising a plurality of photonic integrated circuit chips, each of the plurality of photonic integrated circuit chips including a plurality of vertical grating couplers defined in a first layer, the first layer being located beneath an interconnect structure including a plurality of metal levels embedded in an insulating layer, the method comprising: A cavity is etched from the upper surface of the interconnect structure, penetrating downwards into the insulating layer until it reaches an intermediate level between the coupler and the metal level closest to the coupler. The cavity has a lateral dimension such that it can accommodate a block for holding an array of optical fibers designed to be optically coupled to the coupler.

15. The method of claim 14, further comprising dicing the wafer into a plurality of individual chips.

16. The method of claim 14, further comprising: Adhesive is disposed in the cavity of one of the chips; The block is inserted and positioned within the cavity to optically couple the end of the optical fiber to the coupler of one of the chips in the chip; and The adhesive is then allowed to harden.

17. The method of claim 16, wherein the adhesive comprises an epoxy resin.

18. The method of claim 16, wherein curing the adhesive comprises: The adhesive is hardened by polymerization caused by exposure to light radiation.

19. The method of claim 18, wherein the light radiation includes ultraviolet light radiation.

20. The method of claim 16, wherein one of the chips further comprises a protective ring surrounding the cavity on the upper surface of the interconnect structure, and wherein arranging the adhesive includes using the protective ring to prevent the adhesive from flowing beyond the protective ring.

21. A method for implementing a personalized chip, comprising: Multiple vertical grating couplers are formed in the first layer of the semiconductor component, the first layer including a semiconductor layer or an insulating layer; Multiple second insulating layers are covered on the plurality of vertical grating couplers; An interconnect structure is formed, the interconnect structure including a plurality of metal layers and a plurality of metal vias embedded in the second insulating layer; One or more phase modulators are formed in the first layer, each phase modulator being coupled to a corresponding metal via. as well as A cavity is etched from the upper surface of the interconnect structure, penetrating downwards through the second insulating layer to an intermediate level between the coupler and the metal level closest to the coupler. The cavity has a lateral dimension such that it can accommodate a block for holding an array of optical fibers designed to be optically coupled to the coupler.

22. The method of claim 21, wherein the method is implemented from a semiconductor wafer comprising a plurality of photonic integrated chips, wherein each photonic integrated chip comprises a corresponding vertical grating coupler among a plurality of vertical grating couplers.

23. The method of claim 22, further comprising dicing the semiconductor wafer into a plurality of individual photonic integrated chips.

24. The method of claim 22, further comprising: Adhesive is disposed in the cavity of one of the chips; The block is inserted and positioned within the cavity to optically couple the end of the optical fiber to the coupler of one of the chips in the chip; and The adhesive is then allowed to harden.

25. The method of claim 24, wherein curing the adhesive comprises: The adhesive is hardened by polymerization caused by exposure to light radiation.

26. The method of claim 24, wherein one of the chips further comprises a protective ring surrounding the cavity on the upper surface of the interconnect structure, and wherein arranging the adhesive includes using the protective ring to prevent the adhesive from flowing beyond the protective ring.

27. The method of claim 21, wherein the lateral dimension of the cavity is equal to the lateral dimension of the block plus a tolerance margin.

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