A real-time clock circuit with improved temperature compensation accuracy and reduced power consumption

Abstract

The present disclosure provides a real-time clock circuit with improved temperature compensation accuracy and reduced power consumption, comprising: a clock generation circuit configured to generate an oscillation signal and a multi-stage delay signal; a digital temperature sensing circuit configured to convert a real-time temperature into digital temperature information using the oscillation signal as a reference counting frequency; and a digital compensation circuit configured to compensate for an integer part and a decimal part of an absolute offset of the oscillation signal according to the digital temperature information to obtain a final clock signal. The clock has lower power consumption compared to a traditional temperature-compensated clock.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a real-time clock circuit with a quartz crystal or other MEMS resonator that improves temperature compensation accuracy and reduces power consumption. Background Technology

[0002] With the continuous evolution of IoT technology, especially for battery-powered IoT devices used outdoors, stringent requirements are placed on the power consumption and temperature stability of their internal real-time clock circuits. Real-time clock circuits based on quartz crystals or other MEMS resonant devices suffer from significant cumulative errors over long periods due to temperature-frequency drift of the resonant elements, necessitating correction at the circuit level.

[0003] Currently, there are generally two correction methods for real-time clock circuits based on quartz crystals or other MEMS resonant elements: one is to correct relative frequency deviations, and the other is to correct absolute frequency deviations. Relative frequency correction typically uses a fractional phase-locked loop (PLL) to compensate for temperature drift by dividing the clock circuit by a fractional value. Absolute frequency correction, on the other hand, is usually based on an integer divider to generate a fixed, lower-frequency compensated clock output.

[0004] While relative frequency deviation compensation can provide an output frequency equal to or higher than the input clock frequency, it greatly increases system power consumption due to the use of fractional phase-locked loops, making it unsuitable for ultra-low power applications such as the Internet of Things. On the other hand, absolute frequency deviation compensation, while having the advantage of low power consumption, typically produces an output signal with instantaneous jitter that is far below the oscillation frequency if higher compensation accuracy is required. Summary of the Invention

[0005] (a) Technical problems to be solved

[0006] To address the aforementioned issues, this disclosure provides a real-time clock circuit that improves temperature compensation accuracy and reduces power consumption, thereby alleviating the technical problems existing in the prior art.

[0007] (II) Technical Solution

[0008] This disclosure provides a real-time clock circuit that improves temperature compensation accuracy and reduces power consumption, comprising: a clock generation circuit configured to generate an oscillation signal and a multi-level delay signal; a digital temperature sensing circuit configured to use the oscillation signal as a reference counting frequency to convert real-time temperature into digital temperature information; and a digital compensation circuit configured to compensate for the integer and fractional parts of the absolute offset of the oscillation signal according to the digital temperature information to obtain the final clock signal.

[0009] According to an embodiment of this disclosure, the clock generating circuit includes: a resonator, with its input and output terminals connected to capacitors and then grounded; an oscillation circuit, with switches at both ends respectively connected to the input and output terminals of the resonator, used to inject energy into the resonator to increase the amplitude of the resonator's oscillation signal, thereby obtaining an initial oscillation signal; an amplitude detection circuit, used to detect the amplitude value of the obtained initial oscillation signal; a comparator, connected to the amplitude detection circuit, used to determine whether the amplitude value of the initial oscillation signal meets the requirements and output an enable signal accordingly; a preamplifier circuit, used to convert the sinusoidal initial oscillation signal into a square wave oscillation signal; a delay-locked loop, used to delay the oscillation signal by N stages to obtain a multi-stage delayed signal, where N is a multiple of 4; and a pulse generation unit, including a connected pulse generator and a driving circuit, the pulse generation unit being used to generate a pulse signal based on the first stage of the multi-stage delayed signal. Level delay signal and the first The N-level delayed signal generates an injection pulse signal and is input to the resonator.

[0010] According to an embodiment of this disclosure, a digital temperature sensing circuit includes: a temperature-to-frequency conversion circuit for converting real-time temperature into temperature frequency information; a digital circuit including: a first counter for obtaining a first count value based on the temperature frequency information; a second counter for obtaining a second count value based on an input oscillation signal as a reference counting frequency; and a conversion circuit connected to the first and second counters for obtaining digital temperature information based on the first and second count values.

[0011] According to an embodiment of this disclosure, the temperature-frequency conversion circuit includes a ring oscillator composed of four basic delay units connected end to end. The basic delay unit includes an inverter with a leakage current tail current source and a Schmitt trigger structure.

[0012] According to an embodiment of this disclosure, the digital compensation circuit includes: a polynomial correction module for obtaining an integer division ratio and a strobe signal for a fractional input based on the input digital temperature information; an integer divider for receiving an oscillation signal and an integer division ratio, and for obtaining the integer part of the current absolute frequency offset based on the integer division ratio; a multiplexer for receiving a multi-level delay signal and a strobe signal, and selecting one of the corresponding multi-level delay signals as a fractional delay output; a logic control unit for receiving the status information of the polynomial correction module, the integer divider, and the multiplexer to obtain corresponding control signals, output strobe signals, and output enable signals; and a two-way selector for receiving the integer part of the absolute frequency offset and the fractional delay output, and obtaining the compensated final clock signal under the action of the output strobe signal and the output enable signal.

[0013] According to an embodiment of this disclosure, the clock generating circuit includes an oscillation circuit and a capacitor. When the clock generating circuit reaches a stable state, the oscillation circuit will be disconnected.

[0014] According to an embodiment of this disclosure, the real-time clock circuit further includes a bias voltage generation circuit for providing a bias voltage. After stabilization, it operates periodically. Under clock control, it operates only in one of multiple cycles and remains off for the rest of the time. Subsequently, the bias voltage is held on a capacitor to save power consumption.

[0015] According to embodiments of this disclosure, the resonator type includes a quartz crystal or a MEMS resonator.

[0016] According to embodiments of this disclosure, the polynomial correction module uses a polynomial approximation digital compensation algorithm of arbitrary order that meets the accuracy requirements, while simultaneously performing linearization processing on the digital temperature information.

[0017] (III) Beneficial Effects

[0018] As can be seen from the above technical solution, the real-time clock circuit of this disclosure that improves temperature compensation accuracy and reduces power consumption has at least one or a part of the following beneficial effects:

[0019] (1) The clock generation circuit adopts a pulse-driven working mode, which has higher energy utilization efficiency under the same oscillation amplitude, thus having lower power consumption compared with the clock generation circuit of the traditional temperature-compensated clock.

[0020] (2) Compared with the traditional compensation method based on fractional frequency division, the power consumption is greatly reduced under the same compensation accuracy because the fractional phase-locked loop is avoided.

[0021] (3) By reusing the output of the multi-stage inverter chain of the delay-locked loop in the clock generation circuit, the accuracy is improved by N times compared with the traditional compensation method based on integer frequency division, at the same compensation frequency output.

[0022] (4) A temperature sensing circuit based on frequency counting is adopted, and the frequency output of the clock generation circuit is used as the reference input. Compared with the ADC sensing method used in the traditional temperature compensation real-time clock, it has lower power consumption.

[0023] (5) The pulse injection working mode can effectively suppress the noise injected into the resonator by the circuit, especially reducing the influence of low-frequency flicker noise, and can achieve better long-term stability. Attached Figure Description

[0024] Figure 1 A schematic diagram illustrating the system architecture of a real-time clock circuit according to an embodiment of the present disclosure is shown.

[0025] Figure 2 A schematic diagram illustrating the composition of a clock generation circuit according to an embodiment of the present disclosure is shown.

[0026] Figure 3 A schematic diagram illustrating the composition of a digital temperature sensing circuit according to an embodiment of the present disclosure is shown.

[0027] Figure 4 A schematic diagram of the temperature-frequency conversion circuit according to an embodiment of the present disclosure is shown.

[0028] Figure 5 A schematic diagram illustrating the composition of a digital compensation circuit according to an embodiment of the present disclosure is shown.

[0029] Figure 6 A waveform sequence diagram involving a clock generation circuit according to an embodiment of the present disclosure is illustrated schematically. Detailed Implementation

[0030] This disclosure provides a real-time clock circuit that improves temperature compensation accuracy and reduces power consumption. It aims to solve the problem that it is difficult to achieve a jitter-free, high-precision temperature compensation real-time clock circuit under the existing absolute deviation compensation method, and hopes to further reduce the power consumption of the overall circuit.

[0031] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0032] In this embodiment of the disclosure, a real-time clock circuit that improves temperature compensation accuracy and reduces power consumption is provided, such as... Figure 1 As shown, the real-time clock circuit includes: a clock generation circuit, a digital temperature sensing circuit, and a digital compensation circuit.

[0033] The clock generation circuit is configured to generate oscillation signals and multi-stage delayed signals;

[0034] The digital temperature sensing circuit is configured to use the oscillation signal as a reference counting frequency to convert real-time temperature into digital temperature information; and

[0035] The digital compensation circuit is configured to compensate for the integer and fractional parts of the absolute offset of the oscillation signal based on the digital temperature information to obtain the final clock signal.

[0036] According to embodiments of this disclosure, such as Figure 2 As shown, the clock generation circuit includes: a resonator, an oscillation circuit, an amplitude detection circuit, a comparator, a preamplifier circuit, a delay-locked loop, and a pulse generation unit.

[0037] The input and output terminals of the resonator are connected to capacitors and then grounded. The oscillation circuit has switches at both ends, connected to the input and output terminals of the resonator respectively, to inject energy into the resonator, increasing the amplitude of the resonator's oscillation signal to obtain the initial oscillation signal. An amplitude detection circuit detects the amplitude value of the initial oscillation signal. A comparator connected to the amplitude detection circuit determines whether the amplitude value of the initial oscillation signal meets the requirements and outputs an enable signal accordingly. A preamplifier circuit converts the sinusoidal initial oscillation signal into a square wave oscillation signal. A delay-locked loop performs N-stage delay on the oscillation signal to obtain a multi-stage delayed signal, where N is a multiple of 4. The pulse generation unit includes a connected pulse generator and a driving circuit. The pulse generation unit is used to generate the pulse signal based on the first pulse in the multi-stage delayed signal. Level delay signal and the first The N-stage delay signal generates an injection pulse signal and is input to the resonator. The clock generation circuit uses a pulse-driven oscillator based on a delay-locked loop to maximize energy utilization efficiency, reduce circuit power consumption, and suppress noise injection. The delay output of the N-stage voltage-controlled delay unit of the delay-locked loop in the clock generation circuit is brought out as the fractional delay input of the digital compensation circuit, which improves the minimum compensation accuracy by N times without increasing additional power consumption.

[0038] The working principle is as follows: the clock generation circuit generates the clock signal to be compensated and outputs an N-stage delay, which is divided into... A clock signal with one cycle is generated. At the same time, the temperature sensing circuit senses the current temperature and converts it into digital temperature information output (the bit width of the digital temperature value is N bits). The digital compensation circuit divides the signal to be compensated in the clock generation circuit into integers based on the digital temperature information from the temperature sensing circuit, and adds the decimal part after delay, and outputs the final compensated clock signal.

[0039] Oscillation start-up stage: The circuit works in the same way as a traditional oscillator. Except for the oscillation start-up circuit, other circuit modules do not work. The oscillation start-up circuit continuously injects energy into the resonant element, causing its oscillation signal amplitude to increase rapidly. When the amplitude of the oscillation signal is sufficient to drive the subsequent digital circuit, the circuit will enter the stable stage.

[0040] Stable Phase: The oscillation circuit will be disconnected from the circuit and will no longer consume power. At the same time, other circuit modules will start working: the delay-locked loop will delay the output of the voltage-controlled delay line by one cycle to align it with the input signal, thus deriving its delay. Period and The rising edges of the periodic signals are aligned with the peaks and troughs of the input sine wave, respectively. After passing through the pulse generation circuit and the drive circuit, these two signals are pulled up and pulled down once at the maximum and minimum amplitudes of the oscillation signal, respectively, to inject energy into the resonator and maintain oscillation.

[0041] The clock generation circuit produces two signal outputs: the oscillation output of the main oscillator and the delayed output of each stage of the N-stage voltage-controlled delay line in the delay-locked loop. It is also important to note that the DC bias generation circuit operates periodically, working only within one cycle of multiple cycles, after which its voltage is held across a capacitor to conserve DC power.

[0042] According to embodiments of this disclosure, the clock generating circuit includes an oscillation circuit and a capacitor. The oscillation circuit is disconnected when the clock generating circuit reaches a stable state. The oscillation circuit can be, but is not limited to, one or a modified version of, the following circuits: a Pierce oscillator, a Colpitts oscillator, a Santos oscillator, or a cross-coupled oscillator. In some embodiments, the temperature sensing circuit can be any temperature sensor implemented based on frequency counting.

[0043] According to embodiments of this disclosure, the resonator type includes a quartz crystal or a MEMS resonator.

[0044] According to embodiments of this disclosure, the oscillation circuit uses a Pierce oscillator circuit with an inverter structure. The resonator is a MEMS resonator of model WMRAG32K76CS4C00R0, with a resonant frequency of 32.768 kHz (±20 ppm), and an on-chip 6 pF load capacitor to ground is connected in parallel across the resonator. The preamplifier uses a self-biased inverter, such as... Figure 6 As shown, the initial oscillation signal of a standard sine wave is transformed into a square wave oscillation signal with a 50% duty cycle. The voltage-controlled delay line uses a 32-stage inverter chain with tail current sources, and the output of each stage is used as the input of a multiplexer within the temperature compensation unit. Specifically, the delayed outputs of stages 8 and 9, and stages 24 and 25, after logical operations, generate two control signals with a pulse width of 1 / 32 of a cycle, used to turn the subsequent drive circuit on or off. The drive circuit uses a simple NMOS and PMOS pair, which, under the control of the pulse signal, pulls the resonator up and down once at the peak and trough of the signal, respectively, to complete the energy injection.

[0045] According to embodiments of this disclosure, such as Figure 3 As shown, the digital temperature sensing circuit includes two main parts: a temperature-to-frequency conversion circuit and a digital circuit.

[0046] Temperature-to-frequency conversion circuits are used to convert real-time temperature into temperature-frequency information;

[0047] The digital circuit includes: a first counter, a second counter, and a conversion circuit.

[0048] The first counter is used to obtain a first count value based on the temperature frequency information; the second counter is used to obtain a second count value based on the input oscillation signal as a reference counting frequency; the conversion circuit, connected to the first and second counters, is used to obtain digital temperature information based on the first and second count values.

[0049] The digital circuit also includes a logic control unit, which controls the first counter, the second counter, and the conversion circuit to operate in a preset sequence.

[0050] The temperature-to-frequency conversion circuit in a temperature sensing circuit can be any oscillating circuit whose frequency changes with temperature, and whose operating frequency is close to that of the clock generator circuit. Digital temperature sensing circuits are implemented using a frequency-counting-based approach, reusing the oscillation output signal of the clock generator circuit as the reference counting frequency, thus reducing the power consumption of using an additional frequency reference source.

[0051] According to embodiments of this disclosure, such as Figure 4 As shown, the temperature-frequency conversion circuit includes a ring oscillator composed of four basic delay units connected end to end. The basic delay unit includes an inverter with a leakage current tail current source and a Schmitt trigger structure.

[0052] The specific working principle is similar to that of common temperature sensors that use frequency counting. By generating a frequency signal that is strongly correlated with temperature, counting the frequency of this signal with a reference signal, and then comparing the results, the temperature can be converted into a digital value. In this invention, the reference signal is the oscillation signal output from a clock generation circuit. Although this signal has a certain temperature drift, its temperature stability is still satisfactory compared to the frequency output signal that is strongly correlated with temperature.

[0053] According to embodiments of this disclosure, such as Figure 5 As shown, the digital compensation circuit includes: a polynomial correction module, an integer frequency divider, a multiplexer, a logic control unit, and a two-way selector.

[0054] The polynomial correction module is used to obtain the integer division ratio and the strobe signal of the fractional input based on the input digital temperature information; the integer divider receives the oscillation signal and the integer division ratio, and is used to obtain the integer part of the current absolute frequency offset based on the integer division ratio; the multiplexer is used to receive multi-level delay signals and strobe signals, and select one of the corresponding multi-level delay signals as the fractional delay output; the logic control unit is used to receive the status information of the polynomial correction module, the integer divider, and the multiplexer to obtain the corresponding control signals, output strobe signals, and output enable signals; the two-way selector is used to receive the integer part of the absolute frequency offset and the fractional delay output, and obtains the compensated final clock signal under the action of the output strobe signal and the output enable signal.

[0055] The polynomial correction module receives temperature information from the temperature sensing circuit and calculates the required integer division ratio and corresponding fractional strobe signal based on a preset polynomial correction algorithm. It also linearizes the digital temperature information. The integer divider compensates for the integer portion of the current absolute frequency offset; its input frequency is the oscillation signal output of the clock generator circuit. The multiplexer compensates for the fractional portion of the current absolute frequency offset; its input is the N-stage delay signal output of the clock generator circuit. Figure 5 As shown, the logic control unit is a finite state machine that receives state information from other units and controls the relevant units to complete corresponding functions. The specific working process of the circuit is as follows: ① The polynomial correction module obtains the required integer division ratio based on the current temperature information, sets the division ratio of the integer frequency divider to the corresponding value, sets the selection signal of the multiplexer, selects the corresponding input as the fractional output, and exchanges state information with the logic control unit after completing the operation; ② After the integer frequency divider overflows, it generates an overflow signal to the logic control unit, which enables the two multiplexers and outputs the compensated signal; ③ The logic control unit resets each unit to start the next compensation cycle, repeating ① and ②.

[0056] According to embodiments of this disclosure, such as Figure 4 As shown, the temperature-to-frequency conversion circuit of the temperature sensing circuit uses an inverter with a leakage current tail current source to form a ring oscillator whose output frequency changes exponentially with temperature. Its output frequency satisfies the formula:

[0057]

[0058] Among them, f clk It is a temperature frequency signal (CLK) out The frequency value is T, where T represents the current temperature, and a and b are constant coefficients.

[0059] In order to reduce the short-circuit power consumption of the inverter during the switching process, a feed-back gating Schmitt trigger structure is used in this temperature sensor. The Schmitt trigger with this structure has a short-circuit current for only a very short period of time near the turn-on moment, which greatly reduces the power consumption of the temperature sensor.

[0060] The polynomial correction circuit calculates the required integer division ratio and fractional input gating signal based on the digital temperature information from the digital temperature sensor circuit, according to a pre-set polynomial correction algorithm. Simultaneously, under the control of the state machine, the frequency divider starts counting. When the frequency divider reaches the corresponding count value, it enables the 32-channel selector and the 2-channel selector, outputting a compensated 1Hz signal. The accumulated fractional part is included in the next compensation cycle, and the circuit recalculates the corresponding control signal based on the temperature information, repeating this process. The polynomial correction circuit also linearizes the digital temperature information. Anyone skilled in the art can write the corresponding hardware description code based on the circuit block diagram and the above-described working process, and use relevant EDA tools to complete the compilation, synthesis, and physical implementation. The specific implementation process will not be discussed further here.

[0061] According to embodiments of this disclosure, the polynomial correction module uses a polynomial approximation digital compensation algorithm of arbitrary order that meets the accuracy requirements, while simultaneously performing linearization processing on the digital temperature information.

[0062] In the digital compensation circuit, integer compensation is achieved through a programmable integer divider, while fractional compensation is achieved through a multiplexer that dynamically selects the N-stage delay output in the clock generation circuit. The digital compensation algorithm can be an arbitrary-order polynomial approximation that meets the accuracy requirements. This algorithm unit can simultaneously perform linearization processing on the original digital temperature. Based on the temperature information from the temperature sensing circuit, the digital compensation circuit calculates the integer division ratio and fractional delay used for compensation using a predefined polynomial compensation algorithm, controlling the corresponding circuits to output a high-precision compensated low-frequency clock signal.

[0063] According to an embodiment of this disclosure, the real-time clock circuit further includes a bias voltage generation circuit for providing a bias voltage. After stabilization, it operates periodically. Under clock control, it operates only in one of multiple cycles and remains off for the rest of the time. Subsequently, the bias voltage is held on a capacitor to save power consumption.

[0064] The embodiments of this disclosure have been described in detail above with reference to the accompanying drawings. It should be noted that implementations not illustrated or described in the drawings or the main text of the specification are forms known to those skilled in the art and are not described in detail. Furthermore, the definitions of the various elements and methods described above are not limited to the specific structures, shapes, or methods mentioned in the embodiments, and those skilled in the art can easily modify or substitute them.

[0065] Based on the above description, those skilled in the art should have a clear understanding of the real-time clock circuit disclosed herein that improves temperature compensation accuracy and reduces power consumption.

[0066] In summary, this disclosure provides a real-time clock circuit that improves temperature compensation accuracy and reduces power consumption, exhibiting extremely low power consumption and high temperature compensation accuracy. The circuit mainly comprises three parts: a clock generation circuit, a digital temperature sensing circuit, and a digital compensation circuit. The clock generation circuit employs a pulse-driven oscillator based on a delay-locked loop to generate the signal to be compensated and a multi-stage delayed signal. The digital temperature sensing circuit uses a frequency counting method, utilizing the output of the clock generation circuit as a reference frequency. The digital compensation circuit compensates for the frequency offset by dividing it into integer and fractional parts according to a preset algorithm, and divides and combines the output signal of the clock generation circuit to produce a stable output.

[0067] It should also be noted that the above are different embodiments provided by this disclosure. These embodiments are used to illustrate the technical content of this disclosure and are not intended to limit the scope of protection of this disclosure. A feature of one embodiment can be applied to other embodiments through suitable modifications, substitutions, combinations, or separations.

[0068] It should be noted that, unless otherwise specified herein, having "a" element is not limited to having a single element, but may include one or more of the element.

[0069] Furthermore, unless otherwise specified, the ordinal numbers such as "first," "second," etc., used herein are merely for distinguishing multiple elements with the same name and do not indicate any hierarchy, order of execution, or process sequence among them. A "first" element and a "second" element may appear together in the same component or separately in different components. The presence of an element with a higher ordinal number does not necessarily indicate the presence of another element with a lower ordinal number.

[0070] In this document, unless otherwise specified, the term "characteristic A" or "and / or" and "characteristic B" means that A exists alone, B exists alone, or A and B exist simultaneously; the term "characteristic A" and "and" or "and" and "and" and "characteristic B" means that A and B exist simultaneously; the terms "including", "containing", "having", and "containing" refer to, but are not limited to, these.

[0071] Furthermore, in this document, terms such as "up," "down," "left," "right," "front," "back," or "between" are used only to describe the relative positions of multiple elements and can be extended to include translation, rotation, or mirroring. Additionally, unless otherwise specified, the statement "one element is on another element" or similar statements do not necessarily indicate that the element is in contact with the other element.

[0072] Furthermore, unless specifically described or required to occur in a specific order, the order of the above steps is not limited to those listed above and can be varied or rearranged according to the desired design. Moreover, the above embodiments can be used in combination with each other or with other embodiments based on design and reliability considerations; that is, technical features from different embodiments can be freely combined to form more embodiments.

[0073] The specific embodiments described above further illustrate the purpose, technical solutions, and beneficial effects of this disclosure. It should be understood that the above descriptions are merely specific embodiments of this disclosure and are not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A real-time clock circuit that improves temperature compensation accuracy and reduces power consumption, comprising: The clock generation circuit is configured to generate oscillation signals and multi-stage delayed signals; The digital temperature sensing circuit is configured to use the oscillation signal as a reference counting frequency to convert real-time temperature into digital temperature information. as well as A digital compensation circuit is configured to compensate for the integer and fractional parts of the absolute offset of the oscillation signal based on the digital temperature information to obtain the final clock signal. The digital temperature sensing circuit includes a temperature-frequency conversion circuit, a digital circuit, and a conversion circuit; the temperature-frequency conversion circuit is used to convert real-time temperature into temperature frequency information; the digital circuit includes a first counter and a second counter, the first counter being used to obtain a first count value based on the temperature frequency information; The second counter is used to obtain a second count value based on the input oscillation signal as a reference counting frequency; the conversion circuit is connected to the first and second counters and is used to obtain digital temperature information based on the first and second count values.

2. The real-time clock circuit according to claim 1, wherein the clock generating circuit comprises: The resonator has capacitors connected to its input and output terminals, which are then grounded. The oscillation circuit has switches at both ends, which are respectively connected to the input and output terminals of the resonator. It is used to inject energy into the resonator to increase the amplitude of the resonator's oscillation signal, thereby obtaining the initial oscillation signal. An amplitude detection circuit is used to detect the amplitude value of the initial oscillation signal; The comparator, connected to the amplitude detection circuit, is used to determine whether the amplitude value of the initial oscillation signal meets the requirements and outputs an enable signal accordingly. The preamplifier circuit is used to convert the initial sinusoidal oscillation signal into a square wave oscillation signal. A delay-locked loop is used to delay an oscillating signal by N stages to obtain a multi-stage delayed signal, where N is a multiple of 4. as well as The pulse generation unit includes a connected pulse generator and a driving circuit. The pulse generation unit is used to generate a pulse based on the first pulse in the multi-stage delayed signal. Level delay signal and the first The delayed signal generates an injection pulse signal and is input to the resonator.

3. The real-time clock circuit according to claim 1, wherein the temperature-frequency conversion circuit comprises a ring oscillator consisting of four basic delay units connected end to end, wherein the basic delay unit comprises an inverter of a leakage current tail current source and a Schmitt trigger structure.

4. The real-time clock circuit according to claim 1, wherein the digital compensation circuit comprises: The polynomial correction module is used to obtain the integer frequency division ratio and the strobe signal of the fractional input based on the input digital temperature information; An integer frequency divider receives an oscillation signal and an integer division ratio, and is used to obtain the integer part of the current absolute frequency offset based on the integer division ratio; A multiplexer is used to receive multi-stage delay signals and gating signals, and select one of the corresponding multi-stage delay signals as a fractional delay output. The logic control unit is used to receive the status information of the polynomial correction module, the integer frequency divider, and the multiplexer to obtain the corresponding control signals, output gating signals, and output enable signals. as well as A two-way selector is used to receive the integer part and fractional delay of the absolute frequency offset output, and obtains the compensated final clock signal under the action of the output strobe signal and the output enable signal.

5. The real-time clock circuit according to claim 2, wherein the clock generating circuit includes an oscillation circuit and a capacitor, and the oscillation circuit will be disconnected when the clock generating circuit reaches a stable state.

6. The real-time clock circuit according to claim 2 further includes a bias voltage generation circuit for providing a bias voltage, which operates periodically after stabilization, and under clock control, operates only in one cycle of multiple cycles and remains off for the rest of the time. Subsequently, the bias voltage is held on a capacitor to save power consumption.

7. The real-time clock circuit according to claim 2, wherein the resonator type includes a quartz crystal or a MEMS resonator.

8. In the real-time clock circuit according to claim 4, the polynomial correction module uses a polynomial approximation digital compensation algorithm of arbitrary order that meets the accuracy requirements, and simultaneously completes the linearization processing of digital temperature information.

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