Method and system for clock frequency compensation, electronic device, chip

Abstract

The application provides a clock frequency compensation method and system, an electronic device and a chip, wherein the clock frequency compensation method comprises the following steps: obtaining a time deviation value; calculating an error compensation value according to the time deviation value, a sampling rate of a terminal in a current mode and a sleep duration of the terminal in a previous mode, wherein the current mode is a normal working mode and the previous mode is a sleep mode to which the terminal is switched; determining a clock frequency compensation value of the terminal in a next mode by using the error compensation value and an automatic frequency control tracking value of the terminal in the current mode, wherein the next mode is the sleep mode; and compensating a clock frequency of the terminal in the next mode according to the clock frequency compensation value. The application can reduce the complexity and power consumption of a system of the terminal.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and in particular to a method, system, electronic device, and chip for clock frequency compensation. Background Technology

[0002] To save power, terminals typically enter sleep mode. In sleep mode, the terminal operates at low voltage. After transitioning from sleep mode to normal operating mode, the terminal operates at normal temperature and pressure. The clock used in sleep mode and normal operating mode are different.

[0003] Under normal circumstances, the terminal uses a 26MHz or 52MHz clock to synchronize and time with the base station in normal working mode, while in sleep mode, the terminal uses a 32KHz clock to maintain this synchronization and timing in order to save power.

[0004] However, when a terminal transitions from sleep mode to normal operating mode, it faces time and frequency deviations. Existing methods for compensating for these deviations typically only consider the fixed calibration relationship between the fast and slow clocks under normal temperature and pressure operating conditions, without taking into account the impact of the low-pressure operating state during sleep mode on the chip's 32kHz clock. This leads to a gradual increase in accumulated errors as the sleep time lengthens, resulting in a larger accumulated error when the terminal wakes up and resumes the 26MHz clock. This increases the overall system time deviation, forcing the system to require more frequent calibrations or other methods to maintain the accuracy of the system clock and timing. Furthermore, to restore the receiver time, the wake-up time needs to be advanced, reducing the time the terminal spends in sleep mode, increasing the system's time synchronization complexity, increasing the operating time in normal operating mode, and ultimately increasing the overall system power consumption.

[0005] Therefore, how to reduce the time synchronization complexity when the terminal switches from sleep mode to normal working mode, and further reduce the system complexity and power consumption of the terminal, has become an urgent problem to be solved. Summary of the Invention

[0006] To address the aforementioned issues, the present invention provides a clock frequency compensation method, system, electronic device, and chip. By using the error compensation value and the automatic frequency control tracking value of the terminal in the current mode, the clock frequency compensation value for the terminal to enter the next mode is determined. This allows for clock frequency compensation in the next mode, thereby reducing the time synchronization complexity when the terminal transitions from sleep mode to normal working mode in the next mode, and further reducing the system complexity and power consumption of the terminal.

[0007] In a first aspect, the present invention provides a clock frequency compensation method, characterized in that it includes:

[0008] Obtain the time deviation value; The error compensation value is calculated based on the time deviation value, the sampling rate of the terminal in the current mode, and the sleep duration of the terminal in the previous mode. The current mode is the normal working mode, and the previous mode is the terminal switching to sleep mode. The clock frequency compensation value for the terminal to enter the next mode is determined by the error compensation value and the automatic frequency control tracking value of the terminal in the current mode. The next mode is the sleep mode. The clock frequency of the terminal in the next mode is compensated based on the clock frequency compensation value.

[0009] Optionally, the step of calculating the error compensation value based on the time deviation value, the sampling rate of the terminal in the current mode, and the sleep duration of the terminal in the previous mode includes: The scaling factor is calculated by multiplying the sampling rate of the terminal in the current mode by the sleep duration of the terminal in the previous mode. The error compensation value is calculated by taking the reciprocal of the scaling factor and the time deviation value.

[0010] Optionally, the step of obtaining the time deviation value includes: The pre-synchronization strategy is determined based on the terminal's sleep duration in the previous mode; The time deviation value is calculated based on the pre-synchronization strategy.

[0011] Optionally, the pre-synchronization strategy includes: a cell search strategy and an observed arrival time difference strategy; The steps for determining the pre-synchronization strategy based on the terminal's sleep duration in the previous mode include: When the sleep duration in the previous mode exceeds the time threshold, the cell search strategy is selected as the pre-synchronization strategy. When the sleep duration in the previous mode is less than or equal to the time threshold, the observed arrival time difference strategy is selected as the pre-synchronization strategy.

[0012] Optionally, the step of determining the clock frequency compensation value for the terminal to enter the next mode by using the error compensation value and the automatic frequency control tracking value of the terminal in the current mode includes: Convert the clock frequency compensation value into a first increment or decrement value corresponding to the clock frequency in sleep mode; The automatic frequency control tracking value is converted into a second increment or decrement value corresponding to the clock frequency in sleep mode; The clock frequency compensation value is determined by the first increment / decrement value and the second increment / decrement value.

[0013] Optionally, after determining the clock frequency compensation value for the terminal to enter the next mode by using the error compensation value and the automatic frequency control tracking value of the terminal in the current mode, the method further includes: recording the error compensation value.

[0014] Optionally, the step of compensating the clock frequency of the terminal in the next mode based on the clock frequency compensation value includes: Before the terminal enters the next mode, the clock frequency of the terminal in the next mode is compensated according to the clock frequency compensation value.

[0015] In a second aspect, the present invention provides a clock frequency compensation system, comprising: The acquisition module is configured to acquire time deviation values. The calculation module is configured to calculate the error compensation value based on the time deviation value, the sampling rate of the terminal in the current mode, and the sleep duration of the terminal in the previous mode. The current mode is the normal working mode, and the previous mode is the terminal switching to sleep mode. The determination module is configured to determine the clock frequency compensation value for the terminal to enter the next mode by using the error compensation value and the automatic frequency control tracking value of the terminal in the current mode. The next mode is sleep mode. The compensation module is configured to compensate the clock frequency of the terminal in the next mode based on the clock frequency compensation value.

[0016] Optionally, the computing module includes: The first calculation submodule is configured to calculate the scaling factor by multiplying the sampling rate of the terminal in the current mode by the sleep duration of the terminal in the previous mode. The second calculation submodule is configured to calculate the error compensation value by using the reciprocal of the scaling factor and the time deviation value.

[0017] Optionally, the acquisition module includes: The determination submodule is configured to determine the pre-synchronization strategy based on the sleep duration of the terminal in the previous mode; The third calculation submodule is configured to calculate the time deviation value based on the pre-synchronization strategy.

[0018] Optionally, the pre-synchronization strategy includes: a cell search strategy and an observed arrival time difference strategy; The determination submodule is further configured to select the cell search strategy as the pre-synchronization strategy when the sleep duration in the previous mode is greater than the time threshold, and to select the observed arrival time difference strategy as the pre-synchronization strategy when the sleep duration in the previous mode is less than or equal to the time threshold.

[0019] Optionally, the determined module includes: The first conversion submodule is configured to convert the clock frequency compensation value into a first increment or decrement value corresponding to the clock frequency in sleep mode; The second conversion submodule is configured to convert the automatic frequency control tracking value into a second increment or decrement value corresponding to the clock frequency in sleep mode; The determination submodule is configured to determine the clock frequency compensation value by using a first increment / decrement value and a second increment / decrement value.

[0020] Optionally, the system also includes: The recording module is configured to record error compensation values.

[0021] Optionally, the compensation module is further configured to compensate the clock frequency of the terminal in the next mode according to the clock frequency compensation value before the terminal enters the next mode.

[0022] Thirdly, the present invention provides an electronic device, the electronic device comprising: At least one processor; and A memory that is communicatively connected to at least one processor; wherein, The memory stores instructions that can be executed by at least one processor, such that the at least one processor is able to perform any of the methods described above.

[0023] Fourthly, the present invention provides a chip, the chip comprising: At least one processor; and A memory that is communicatively connected to at least one processor; wherein, The memory stores instructions that can be executed by at least one processor, such that the at least one processor is able to perform any of the methods described above.

[0024] Fifthly, the present invention provides a chip module, which includes the aforementioned chip.

[0025] In a sixth aspect, the present invention provides a computer-readable storage medium storing computer instructions that, when executed by a processor, implement the method as described in any of the preceding claims.

[0026] The clock frequency compensation method, system, electronic device, and chip provided in this invention determine the clock frequency compensation value for the terminal to enter the next mode by using the error compensation value and the automatic frequency control tracking value of the terminal in the current mode. This can compensate for the clock frequency of the next mode, so that the frame interrupt time generated when the terminal switches from sleep mode to normal working mode in the next mode is closer to the previously synchronized time. This reduces the time synchronization complexity when the terminal switches from sleep mode to normal working mode in the next mode, and further reduces the system complexity and power consumption of the terminal. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a schematic flowchart illustrating a clock frequency compensation method according to an embodiment of this application; Figure 2 This is a schematic structural diagram of a clock frequency compensation system according to an embodiment of this application. Detailed Implementation

[0029] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0031] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, an element or feature described as “below,” “below,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0032] It should be noted that when an element is referred to as "fixedly connected" to another element, it can be directly on the other element or there may be an intervening element. When an element is considered to be "connected" to another element, it can be directly connected to the other element or there may be an intervening element. Conversely, when an element is referred to as being "directly on" another element, there is no intervening element. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.

[0033] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising,” “including,” or “having,” etc., specify the presence of the stated feature, whole, step, operation, component, part, or combination thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof.

[0034] Firstly, this embodiment provides a clock frequency compensation method, see [link to relevant documentation]. Figure 1 The method includes steps S101 to S102: Step S101: Obtain the time deviation value.

[0035] The time offset value can be estimated by the modem or dynamically selected through a presync strategy.

[0036] In this embodiment, the step of obtaining the time deviation value includes: determining a pre-synchronization strategy based on the sleep duration of the terminal in the previous mode; and calculating the time deviation value based on the pre-synchronization strategy. The pre-synchronization strategy includes at least one calculation strategy for calculating the time deviation value, and different calculation strategies will be used depending on the application system.

[0037] Furthermore, pre-synchronization strategies include, but are not limited to, cell search (CS) strategies and observed time difference of arrival (OTDOA) strategies.

[0038] The steps for determining the pre-synchronization strategy based on the sleep duration of the terminal in the previous mode include: when the sleep duration in the previous mode is greater than the time threshold, selecting the cell search strategy as the pre-synchronization strategy; when the sleep duration in the previous mode is less than or equal to the time threshold, selecting the observed arrival time difference strategy as the pre-synchronization strategy.

[0039] In this embodiment, the time threshold is 128 seconds, but it is not limited to this; at the same time, this embodiment does not further limit the specific method of calculating the time deviation value through cell search strategy or observation arrival time difference strategy.

[0040] In an alternative embodiment, the pre-synchronization strategy may also include: a cell search (CS) strategy and a DMRS (Demodulation Reference Signal) strategy.

[0041] The steps for determining the pre-synchronization strategy based on the sleep duration of the terminal in the previous mode include: when the sleep duration in the previous mode is greater than the time threshold, selecting the cell search strategy as the pre-synchronization strategy; when the sleep duration in the previous mode is less than or equal to the time threshold, selecting the observed arrival time difference strategy as the pre-synchronization strategy.

[0042] Step S102: Calculate the error compensation value based on the time deviation value, the sampling rate of the terminal in the current mode, and the sleep duration of the terminal in the previous mode.

[0043] The current mode is the normal working mode, and the previous mode was when the terminal switched to sleep mode.

[0044] Specifically, the terminal uses a clock frequency of 26MHz in normal working mode, but is not limited to 26MHz. In practical applications, a clock frequency of 52MHz can also be used. The terminal uses a clock frequency of 32KHz in sleep mode. In practical applications, a clock frequency of 32768Hz is used, but is not limited to 32KHz.

[0045] In this embodiment, the terminal uses a 26MHz clock for synchronization and timing with the base station in normal operating mode. In sleep mode, the terminal uses a 32kHz clock to maintain this synchronization and timing to save power. The principle of maintaining synchronization and timing with a 32kHz clock is as follows: the count value of the 32kHz clock is converted into a counter value for the 26MHz timing clock using a coefficient. The specific implementation method will not be elaborated in this embodiment.

[0046] In one optional embodiment, the step of calculating the error compensation value based on the time deviation value, the sampling rate of the terminal in the current mode, and the sleep duration of the terminal in the previous mode includes: calculating a scaling factor by multiplying the sampling rate of the terminal in the current mode by the sleep duration of the terminal in the previous mode; and calculating the error compensation value by dividing the reciprocal of the scaling factor by the time deviation value. Specifically, see Formula 1: Formula 1 Where ppm represents the error compensation value, fs is the sampling rate, and sleeptime is the sleep duration that causes time_offset, i.e., the sleep duration of the terminal in the previous mode.

[0047] In an optional embodiment, after calculating the error compensation value based on the time deviation value, the sampling rate of the terminal in the current mode, and the sleep duration of the terminal in the previous mode, the method further includes: recording the error compensation value.

[0048] Recording error compensation values ​​not only facilitates subsequent clock frequency compensation for the next mode, but also allows the error compensation values ​​to be applied to sleep modes in similar stages of other application scenarios. Furthermore, it enables users to optimize and adjust the error compensation values ​​through the operating system based on the compensation effect on the next mode. Step S103: Determine the clock frequency compensation value for the terminal to enter the next mode by using the error compensation value and the automatic frequency control tracking value of the terminal in the current mode.

[0049] The next mode is the hibernation mode.

[0050] In one optional embodiment, the step of determining the clock frequency compensation value for the terminal to enter the next mode by using the error compensation value and the automatic frequency control tracking value of the terminal in the current mode includes: converting the clock frequency compensation value into a first increment / decrement value corresponding to the clock frequency in the sleep mode; converting the automatic frequency control tracking value into a second increment / decrement value corresponding to the clock frequency in the sleep mode; and determining the error compensation value by using the first increment / decrement value and the second increment / decrement value.

[0051] Step S104: Compensate the clock frequency of the terminal in the next mode according to the clock frequency compensation value.

[0052] In one optional embodiment, the step of compensating the clock frequency of the terminal in the next mode according to the clock frequency compensation value includes: compensating the clock frequency of the terminal in the next mode according to the clock frequency compensation value before the terminal enters the next mode.

[0053] For example, the crystal in the terminal operates at a clock frequency (rate) of 32kHz in sleep mode, and the rate is 0x752f8bc. The value of -3374 ppm is converted to an increment / decrement of the rate, i.e., the first increment / decrement value, which is +0x19. Simultaneously, the AFC (automatic frequency control) tracking value of -28 in the current normal mode is also converted to an increment / decrement of the 32kHz clock frequency, i.e., the second increment / decrement value, which is -0x3. Then, before entering the next mode, i.e., before activating the 32kHz clock timing for the next mode, the actual clock frequency used by the terminal in the next mode is determined, i.e., the actual clock frequency rate used in the next sleep phase is 0x752f8d2. Where 0x752f8d2 = 0x752f8bc + 0x19 - 0x3.

[0054] This clock frequency compensation method determines the clock frequency compensation value for the terminal to enter the next mode by using the error compensation value and the automatic frequency control tracking value of the terminal in the current mode. It can compensate the clock frequency of the terminal before the terminal enters the next mode, that is, it pre-compensates the 32k crystal. This makes the frame interrupt time generated when the terminal switches from sleep mode to normal working mode in the next mode closer to the previously synchronized time. In this way, it can reduce the time synchronization complexity when the terminal switches from sleep mode to normal working mode in the next mode, further reducing the system complexity and power consumption of the terminal. At the same time, it can also reduce the power consumption of the corresponding chips, chip modules and system.

[0055] Secondly, based on the clock frequency compensation method in the first aspect, this embodiment provides a clock frequency compensation system 200, see [link to documentation]. Figure 2 The clock frequency compensation system 200 includes: Module 201 is configured to acquire time deviation values; The calculation module 202 is configured to calculate the error compensation value based on the time deviation value, the sampling rate of the terminal in the current mode, and the sleep duration of the terminal in the previous mode, wherein the current mode is the normal working mode and the previous mode is the terminal switching to sleep mode. The determination module 203 is configured to determine the clock frequency compensation value for the terminal to enter the next mode by using the error compensation value and the automatic frequency control tracking value of the terminal in the current mode. The next mode is the sleep mode. The compensation module 204 is configured to compensate the clock frequency of the terminal in the next mode according to the clock frequency compensation value.

[0056] In one optional embodiment, the computing module 202 includes: The first calculation submodule is configured to calculate the scaling factor by multiplying the sampling rate of the terminal in the current mode by the sleep duration of the terminal in the previous mode. The second calculation submodule is configured to calculate the error compensation value by using the reciprocal of the scaling factor and the time deviation value.

[0057] In one optional embodiment, the acquisition module 201 includes: The determination submodule is configured to determine the pre-synchronization strategy based on the sleep duration of the terminal in the previous mode; The third calculation submodule is configured to calculate the time deviation value based on the pre-synchronization strategy.

[0058] In one optional embodiment, the pre-synchronization strategy includes: a cell search strategy and an observed arrival time difference strategy; The determination submodule is further configured to select the cell search strategy as the pre-synchronization strategy when the sleep duration in the previous mode is greater than the time threshold, and to select the observed arrival time difference strategy as the pre-synchronization strategy when the sleep duration in the previous mode is less than or equal to the time threshold.

[0059] In one alternative embodiment, the determining module 203 includes: The first conversion submodule is configured to convert the clock frequency compensation value into a first increment or decrement value corresponding to the clock frequency in sleep mode; The second conversion submodule is configured to convert the automatic frequency control tracking value into a second increment or decrement value corresponding to the clock frequency in sleep mode; The determination submodule is configured to determine the clock frequency compensation value by using a first increment / decrement value and a second increment / decrement value.

[0060] In an optional embodiment, the clock frequency compensation system 200 further includes: The recording module is configured to record error compensation values.

[0061] In an optional embodiment, the compensation module 204 is further configured to compensate the clock frequency of the terminal in the next mode according to the clock frequency compensation value before the terminal enters the next mode.

[0062] Thirdly, this embodiment provides an electronic device, which includes: At least one processor; and A memory that is communicatively connected to at least one processor; wherein, The memory stores instructions that can be executed by at least one processor, such that the at least one processor is able to perform any of the methods described above.

[0063] Fourthly, this embodiment provides a chip, the chip comprising: At least one processor; and A memory that is communicatively connected to at least one processor; wherein, The memory stores instructions that can be executed by at least one processor, such that the at least one processor is able to perform any of the methods described above.

[0064] Fifthly, this embodiment provides a chip module, which includes the chip described above.

[0065] Sixthly, this embodiment provides a computer-readable storage medium storing computer instructions that, when executed by a processor, implement the method described in any of the preceding claims.

[0066] In the description of this specification, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0067] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0068] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for clock frequency compensation, characterized in that, include: Obtain the time deviation value; The step of obtaining the time deviation value includes: determining a pre-synchronization strategy based on the sleep duration of the terminal in the previous mode; and calculating the time deviation value based on the pre-synchronization strategy. An error compensation value is calculated based on the time deviation value, the sampling rate of the terminal in the current mode, and the sleep duration of the terminal in the previous mode, wherein the current mode is the normal working mode, and the previous mode is the terminal switching to sleep mode; the step of calculating the error compensation value based on the time deviation value, the sampling rate of the terminal in the current mode, and the sleep duration of the terminal in the previous mode includes: calculating a scaling factor by multiplying the sampling rate of the terminal in the current mode by the sleep duration of the terminal in the previous mode; and calculating the error compensation value by dividing the reciprocal of the scaling factor by the time deviation value; The clock frequency compensation value for the terminal to enter the next mode is determined by using the error compensation value and the automatic frequency control tracking value of the terminal in the current mode, wherein the next mode is a sleep mode; the step of determining the clock frequency compensation value for the terminal to enter the next mode by using the error compensation value and the automatic frequency control tracking value of the terminal in the current mode includes: converting the clock frequency compensation value into a first increment / decrement value corresponding to the clock frequency in the sleep mode; converting the automatic frequency control tracking value into a second increment / decrement value corresponding to the clock frequency in the sleep mode; and determining the clock frequency compensation value by using the first increment / decrement value and the second increment / decrement value; The clock frequency of the terminal in the next mode is compensated according to the clock frequency compensation value.

2. The method according to claim 1, characterized in that, The pre-synchronization strategy includes: a cell search strategy and an observed arrival time difference strategy; The step of determining the pre-synchronization strategy based on the terminal's sleep duration in the previous mode includes: When the sleep duration in the previous mode exceeds the time threshold, the cell search strategy is selected as the pre-synchronization strategy. When the sleep duration in the previous mode is less than or equal to the time threshold, the observed arrival time difference strategy is selected as the pre-synchronization strategy.

3. The method according to any one of claims 1 to 2, characterized in that, After the step of determining the clock frequency compensation value for the terminal to enter the next mode by using the error compensation value and the automatic frequency control tracking value of the terminal in the current mode, the method further includes: recording the error compensation value.

4. The method according to any one of claims 1 to 2, characterized in that, The step of compensating the clock frequency of the terminal in the next mode according to the clock frequency compensation value includes: Before the terminal enters the next mode, the clock frequency of the terminal in the next mode is compensated according to the clock frequency compensation value.

5. A clock frequency compensation system, characterized in that, include: The acquisition module is configured to acquire time deviation values. The acquisition module includes: a determination submodule, configured to determine a pre-synchronization strategy based on the sleep duration of the terminal in the previous mode; and a third calculation submodule, configured to calculate the time deviation value based on the pre-synchronization strategy. The calculation module is configured to calculate an error compensation value based on the time deviation value, the sampling rate of the terminal in the current mode, and the sleep duration of the terminal in the previous mode, wherein the current mode is the normal working mode, and the previous mode is the terminal switching to sleep mode; the calculation module includes: a first calculation submodule, configured to calculate a scaling factor by multiplying the sampling rate of the terminal in the current mode by the sleep duration of the terminal in the previous mode; and a second calculation submodule, configured to calculate the error compensation value by dividing the reciprocal of the scaling factor by the time deviation value; A determining module is configured to determine the clock frequency compensation value for the terminal to enter the next mode, wherein the next mode is a sleep mode, based on the error compensation value and the automatic frequency control tracking value of the terminal in the current mode. The determining module includes: a first conversion submodule configured to convert the clock frequency compensation value into a first increment / decrement value corresponding to the clock frequency in the sleep mode; a second conversion submodule configured to convert the automatic frequency control tracking value into a second increment / decrement value corresponding to the clock frequency in the sleep mode; and a determining submodule configured to determine the clock frequency compensation value based on the first increment / decrement value and the second increment / decrement value. The compensation module is configured to compensate the clock frequency of the terminal in the next mode according to the clock frequency compensation value.

6. The system according to claim 5, characterized in that, The pre-synchronization strategy includes: a cell search strategy and an observed arrival time difference strategy; The determining submodule is further configured to select the cell search strategy as the pre-synchronization strategy when the sleep duration in the previous mode is greater than the time threshold, and to select the observed arrival time difference strategy as the pre-synchronization strategy when the sleep duration in the previous mode is less than or equal to the time threshold.

7. The system according to any one of claims 5 to 6, characterized in that, The system also includes: The recording module is configured to record the error compensation value.

8. The system according to any one of claims 5 to 6, characterized in that, The compensation module is further configured to compensate the clock frequency of the terminal in the next mode according to the clock frequency compensation value before the terminal enters the next mode.

9. An electronic device, characterized in that, The electronic device includes: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1 to 4.

10. A chip, characterized in that, The chip includes: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1 to 4.

11. A chip module, characterized in that, The chip module includes the chip described in claim 10.

12. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that, when executed by a processor, implement the method as described in any one of claims 1 to 4.

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