Memory access control

Abstract

The memory access controls described herein can utilize persistent memory to store data that would normally be stored in non-persistent memory. An example method for memory access control can include receiving, by control circuitry residing on a memory device, a memory access request targeting an address of a volatile (e.g., non-persistent) memory component of the memory device and determining a characteristic of data associated with the target address. The method can further include accessing data at the target address of the volatile memory component in response to determining that the characteristic of the data satisfies a first criterion and accessing data at another address of a non-volatile memory component in response to determining that the characteristic of the data satisfies a second criterion.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor memories and methods, and more specifically, to memory access control. Background Technology

[0002] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic systems. Many different types of memory exist, including volatile and non-volatile memory. Volatile memory requires power to maintain its data (e.g., host data, error data, etc.) and includes Random Access Memory (RAM), Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), and Synchronous Dynamic Random Access Memory (SDRAM). Non-volatile memory provides persistent data by retaining the stored data when no power is supplied and includes NAND flash memory, NOR flash memory, and resistive variable memory, such as Phase-Change Random Access Memory (PCRAM), Resistive Random Access Memory (RRAM), and Magnetoresistive Random Access Memory (MRAM), such as Spin Torque Transfer Random Access Memory (STT RAM).

[0003] A memory device may be coupled to a host computer (e.g., a host computing device) to store data, commands, and / or instructions for use by the host computer or electronic system during operation. For example, data, commands, and / or instructions may be transferred between the host computer and the memory device during the operation of a computing or other electronic system. Summary of the Invention

[0004] On one hand, this application relates to a method comprising: receiving, by a control circuitry system residing on a memory device, a memory access request targeting an address of a volatile memory component of the memory device; determining, by the control circuitry system, characteristics of data associated with the target address; accessing the data at the target address of the volatile memory component in response to determining that the characteristics of the data satisfy a first criterion; and accessing data at another address of a non-volatile memory component in response to determining that the characteristics of the data satisfy a second criterion.

[0005] In another aspect, this application relates to an apparatus comprising: a volatile memory component; a non-volatile memory component coupled to the volatile memory component; a network interface card (NIC); and a control circuitry coupled to the NIC, the volatile memory component, and the non-volatile memory component, wherein the control circuitry is configured to: receive a plurality of memory access requests from the NIC; analyze the memory access requests to determine characteristics associated with data corresponding to a memory access request among the plurality of memory access requests; access the data associated with a particular memory access request in response to determining that the characteristic associated with the data is below a threshold data characteristic value; and access the data associated with the particular memory access request using the non-volatile memory component in response to determining that the characteristic associated with the data is above the threshold data characteristic value.

[0006] In another aspect, this application relates to an apparatus comprising: a non-persistent memory component; a persistent memory component coupled to the non-persistent memory component; an input / output (I / O) device; and a control circuitry coupled to the I / O device, the non-persistent memory component, and the persistent memory component, wherein the I / O device is configured to: receive a command to access data previously intended to be written to the non-persistent memory component; and transmit the command to access the data to the control circuitry, wherein the control circuitry is configured to: determine, based on characteristics of the data, that the data has been written to the persistent memory component; notify the I / O device that the execution of the command to access the data will take an amount of time greater than the time associated with the execution of a deterministic read operation; after notifying the I / O device that the execution of the command to access the data will take an amount of time greater than the time associated with the execution of the deterministic read operation, transfer the data from the persistent memory component to the non-persistent memory component; and transfer the data from the non-persistent memory component to the I / O device.

[0007] In another aspect, this application relates to a system comprising: a virtual machine (VM); a memory device communicatively coupled to the VM and including: a non-persistent memory component; a persistent memory component coupled to the non-persistent memory component; an input / output (I / O) device configured to: receive a memory access request from the VM for the non-persistent memory component; and append I / O device data to the memory access request; and a control circuitry coupled to the I / O device, the non-persistent memory component, and the persistent memory component, wherein the control circuitry is configured to: receive the memory access request containing the I / O device data; determine characteristics of data associated with the memory access request containing the I / O device data; execute the memory access request using the non-persistent memory component in response to determining that the characteristics of the data satisfy a first criterion; and execute the memory access request using the persistent memory component in response to determining that the characteristics of the data satisfy a second criterion. Attached Figure Description

[0008] Figure 1 This is a functional block diagram of a computing system including a host and a memory device, according to several embodiments of the present disclosure.

[0009] Figure 2 This is a functional block diagram of a memory device according to several embodiments of the present disclosure.

[0010] Figure 3 This is a functional block diagram of a memory device coupled to multiple virtual machines according to several embodiments of the present disclosure.

[0011] Figure 4 This is a flowchart illustrating an example method for memory access control according to several embodiments of the present disclosure. Detailed Implementation

[0012] This document describes systems, apparatus, and methods related to memory access control. The memory access control described herein can utilize non-volatile and / or persistent memory to store data typically stored in volatile and / or non-persistent memory. An example method for memory access control may include receiving a memory access request targeting an address of a volatile (e.g., non-persistent) memory component of the memory device by a control circuitry system residing on the memory device and determining characteristics of data associated with the target address. The method may further include accessing data at the target address of the volatile memory component in response to determining that the characteristics of the data satisfy a first criterion, and accessing data at another address of the non-volatile (e.g., persistent) memory component in response to determining that the characteristics of the data satisfy a second criterion.

[0013] Computing systems utilize various types of memory resources during operation. For example, a computing system may utilize a combination of volatile (e.g., random access memory) memory resources and non-volatile (e.g., storage) memory resources during operation. Generally, volatile memory resources can operate much faster than non-volatile memory resources and can have a longer lifespan; however, volatile memory resources are typically more expensive than non-volatile memory resources. Generally, as used herein, and for the context of this disclosure, volatile memory resources may alternatively be referred to as “non-persistent” or “non-persistent memory devices,” while non-volatile memory resources may alternatively be referred to as “persistent” or “persistent memory devices.”

[0014] The terms "non-persistent memory device" and "persistent memory device" are used interchangeably, in particular, with the terms "non-persistent memory component" and "persistent memory component" to clearly distinguish between the terms "memory device" and non-persistent and persistent memory components described herein. For example, in some parts of this disclosure, "memory device" may refer to a collection of hardware components including non-persistent memory devices, persistent memory devices, control circuitry systems, communication channels, etc. In such cases, the terms "non-persistent memory component" and "persistent memory component" are used to avoid confusion with the entire memory device.

[0015] However, persistent memory devices can refer more broadly to the ability to access data persistently. As an example, in the context of persistent memory, a memory device can store multiple logical-to-physical mappings or translated data and / or lookup tables in a memory array to track the location of data within the memory device, regardless of whether the memory is non-volatile. Furthermore, persistent memory devices can refer to the non-volatility of memory and the ability to utilize this non-volatility through the inclusion of service commands for sequential processes (e.g., using logical-to-physical mappings, lookup tables, etc.).

[0016] These different characteristics of persistent and non-persistent memory devices need to be balanced in computing systems to supply sufficient resources to function in response to the growing demands of consumers and computing resource providers. For example, in multi-user computing networks (such as cloud-based computing deployments, software-defined data centers, etc.), a relatively large amount of volatile memory can be provided to supply virtual machines running in the multi-user network. However, as is common in some approaches, relying on volatile memory to supply memory resources to multi-user networks increases the costs associated with supplying memory resources to the network, especially as network users need to make increasingly larger sets of computing resources available.

[0017] Furthermore, in methods that rely on volatile memory to provide memory resources for provisioning virtual machines in a multi-user network, once the volatile memory resources are exhausted (e.g., once the volatile memory resources are allocated to users in the multi-user network), additional users cannot be added to the multi-user network until additional volatile memory resources become available or are added. This can result in potential users being turned away, potentially leading to a loss of revenue that could have been generated when additional memory resources became available in the multi-user network.

[0018] For example, volatile memory resources like Dynamic Random Access Memory (DRAM) tend to operate in a deterministic manner, while non-volatile memory resources like storage-type memory (such as NAND flash memory devices, solid-state drives, and variable resistance memory devices) tend to operate in a non-deterministic manner. For instance, due to error correction operations, encryption operations, RAID operations, etc., performed on data retrieved from storage-type memory devices, the time between requesting data from the storage-type memory device and the availability of data can vary depending on the read operation, thus making data retrieval from the storage-type memory device uncertain. In contrast, the time between requesting data from a volatile memory device and the availability of data can remain constant from the time of read to the time of read, thus making data retrieval from a DRAM device deterministic.

[0019] Furthermore, due to the difference between the deterministic behavior of volatile memory resources and the determinate behavior of non-volatile memory resources, data transferred to and from memory resources typically traverses specific interfaces (e.g., buses) associated with the type of memory used. For example, data transferred to and from DRAM devices typically travels via a Double Data Rate (DDR) bus, while data transferred to and from NAND devices typically travels via a Peripheral Component Interconnect High Speed ​​(PCI-e) bus. However, it should be understood that instances of data being transferred to and from volatile and non-volatile memory resources via their interfaces are not limited to these specific examples.

[0020] Due to the different behaviors of non-volatile and volatile memory devices, some methods choose to store specific types of data in either volatile or non-volatile memory. This can mitigate problems that can arise from the deterministic behavior of, for example, volatile memory devices, compared to the uncertain behavior of non-volatile memory devices. For instance, in some methods, a computing system stores a small amount of data that is periodically accessed during the operation of the computing system in volatile memory devices, while storing larger or less frequently accessed data in non-volatile memory devices. However, in multi-user network deployments, the vast majority of data can be stored in volatile memory devices. This can become problematic due to the cost and power consumption of volatile memory devices, both of which can be higher than those of non-volatile memory devices. To address such problems, the embodiments described herein allow for the selective (e.g., intelligent) writing and retrieval of data to and from non-volatile memory devices deployed in a multi-user network.

[0021] For example, the embodiments described herein can allow monitoring of data (e.g., data associated with memory access requests generated by a virtual machine) to determine the characteristics of the data and / or the memory access requests. As described in more detail herein, the characteristics of the data may include information related to the frequency of access to this data (e.g., the frequency of executing memory access requests involving the same or similar data) and / or how long the data is typically stored in the memory device (e.g., how long data that is the same or similar to the data indicated by the memory access request is stored in the memory device), etc. Based on these monitored characteristics, data may be written to a persistent memory device (e.g., a persistent memory component) or a non-persistent memory device (e.g., a non-persistent memory component) associated with the memory device. By monitoring such characteristics, it can be determined whether the data associated with the memory access request should be written to non-persistent memory (e.g., to facilitate fast retrieval of the data) or to persistent memory (e.g., to reduce the amount of data written to non-persistent memory), which can allow the use of persistent and non-persistent memory optimized for the computing system.

[0022] As described herein, some embodiments of this disclosure relate to computing systems in which data from non-volatile and therefore non-deterministic memory resources is transferred via an interface limited to use by volatile and deterministic memory resources in other methods. For example, in some embodiments, data may be transferred back and forth to non-volatile, non-deterministic memory resources, such as NAND flash devices, resistive variable memory devices (e.g., phase-change memory devices and / or resistive memory devices (e.g., 3D XP memory devices)), solid-state drives (SSDs), self-selecting memory (SSM) devices, etc., via an interface reserved in some methods for data transfer between volatile and deterministic memory resources. That is, in some embodiments, the control circuitry may be operable such that data written to non-volatile memory resources is transferred via a DDR interface instead of a PCIe interface. Similarly, in some embodiments, the control circuitry may be operable such that data written to volatile memory resources is transferred via a PCIe interface instead of a DDR interface. Therefore, compared with methods in which volatile, deterministic memory devices are used to provide main memory to a computing system, the embodiments herein allow non-volatile, non-deterministic memory devices to be used as at least a portion of the main memory of a computing system.

[0023] In some embodiments, data (e.g., data redirected from a non-persistent memory device to a persistent memory device according to aspects of this disclosure) may be transferred intermediately from non-volatile memory resources to a cache (e.g., a small static random access memory (SRAM) cache) or buffer and subsequently made available to the application requesting the data. By storing data that is typically provided in a deterministic manner in non-deterministic memory resources and allowing access to said data as described herein, computing system performance can be improved, for example, by allowing a larger amount of memory resources to be available for users of virtual machines connected to a multi-user network and thus at a substantially lower cost than methods that typically operate using all or almost all of the volatile memory resources.

[0024] To facilitate embodiments of this disclosure, the visibility of non-volatile memory resources can obscure various devices in a computing system in which memory devices (e.g., memory devices comprising both persistent and non-volatile memory components) are deployed. For example, hosts, input / output (I / O) devices (e.g., network interface cards (NICs)) deployed in a computing system or multi-user network, alternatively referred to herein as network interface controllers, virtual machines, etc., may be unable to distinguish whether data is stored from volatile or non-volatile memory resources of the computing system. For example, hardware circuitry may be deployed in a computing system that allows hosts, I / O devices, NICs, virtual machines, etc., to register addresses corresponding to data in a manner that prevents hosts, I / O devices, NICs, virtual machines, etc., from distinguishing whether data is stored from volatile or non-volatile memory resources.

[0025] This allows the capacity of a memory device (e.g., the amount of overall storage availability) to appear generally persistent to external computing devices (e.g., host computing systems, virtual machines, etc.), while simultaneously allowing the capacity of a memory device to appear generally non-persistent to the circuitry (e.g., I / O devices) within the memory device. This can improve the performance of a computing system, wherein the embodiments described herein operate by obfuscating the difference between persistent and non-persistent memory resources presented as various devices available in a computing system, thereby allowing memory access control to be facilitated by a control circuitry residing on the memory device.

[0026] As described in more detail herein, a memory system may include a hardware circuitry (e.g., a control circuitry) that receives a memory access request, determines the characteristics of the data associated with the memory access request, and redirects the memory access request to non-persistent or persistent memory based on the characteristics of the data associated with the memory access request. In some embodiments, the hardware circuitry may perform such operations without notifying an external circuitry (e.g., an I / O device or host coupled to the hardware circuitry) that the data has been redirected to persistent or non-persistent memory. Furthermore, some embodiments may allow the control circuitry to register the address associated with the requested data (even though the hardware circuitry is not backed up by its own memory resources to store the data) in a data structure supplied to memory resources residing on the control circuitry, and use the control circuitry to map the address registered in the data structure to the physical address corresponding to the data in the non-volatile memory device and / or volatile memory device.

[0027] In the following detailed description of this disclosure, reference is made to the accompanying drawings, which form part of this disclosure and illustrate, by description, how one or more embodiments of this disclosure can be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the embodiments of this disclosure, and it should be understood that other embodiments may be utilized and process, electrical, and structural changes may be made without departing from the scope of this disclosure.

[0028] As used herein, especially with respect to element symbols in the drawings, identifiers such as “N,” “M,” “X,” etc., indicate that several specific features are so indicated. It should also be understood that the terminology used herein is for describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms “a / an” and “the” can include both singular and plural references, unless the context clearly indicates otherwise. Furthermore, “a number,” “at least one,” and “one or more” can refer to one or more such things (e.g., a number of memory units can refer to one or more memory units), while “more” is intended to refer to more than one such thing.

[0029] Furthermore, the word "can / may" is used throughout this application in a permissive sense (e.g., possible, able) rather than a mandatory sense (e.g., must). The term "comprising" and its derivatives mean "including (but not limited to)". Depending on the context, the terms "coupled" and "coupled" mean physically connected, directly or indirectly, or used for accessing and moving (transmitting) commands and / or data. Depending on the context, the terms "data" and "data value" are used interchangeably and may have the same meaning herein.

[0030] The figures in this document follow a numbering convention, where the first few digits correspond to the figure number and the remaining digits identify the elements or components within the figure. Similar elements or components between different figures can be identified by using similar numbers. For example, 104 could refer to... Figure 1 Component "04" in the text, and similar components in Figure 2 The reference numeral 204 may be used. A group or plurality of similar elements or components may generally be referred to herein by a single element symbol. For example, a plurality of reference elements 106-1, 106-2, ..., 106-N (e.g., 106-1 to 106-N) may generally be referred to as 106. It should be understood that the elements shown in the various embodiments herein may be added, interchanged, and / or eliminated to provide several additional embodiments of the present disclosure. In addition, the scale and / or relative dimensions of the elements provided in the figures are intended to illustrate particular embodiments of the present disclosure and should not be construed as limiting.

[0031] Figure 1This is a functional block diagram of a computing system 100 including a host 102 and a memory device 104, according to several embodiments of the present disclosure. The computing system 100 may be part of a device. As used herein, "device" may refer to (but is not limited to) any of a variety of structures or combinations thereof, such as (for example) a circuit or circuit system, one or more dies, one or more modules, one or more devices, or one or more systems. The memory device 104 may include one or more memory modules (e.g., single in-line memory modules, dual in-line memory modules, etc.). The memory device 104 may include volatile memory and / or non-volatile memory, such as non-persistent memory (e.g., volatile memory) 106-1 to 106-N and persistent memory (e.g., non-volatile memory) 108-1 to 108-M. In several embodiments, the memory device 104 may include a multi-chip device. A multi-chip device may include several different memory types and / or memory modules. For example, the memory system may include non-volatile or volatile memory on any type of module. Additionally, each of the components (e.g., host 102, memory device 104, non-persistent memory 106-1 to 106-N, persistent memory 108-1 to 108-M, network on-chip (NOC) 110, and / or control circuitry system 120) may be individually referred to herein as a “device”.

[0032] Memory device 104 can provide the main memory of computing system 100 or be used as additional memory or storage device for the entire computing system 100. For example... Figure 1As shown, memory device 104 may include one or more non-persistent memory components 106-1 to 106-N (hereinafter alternatively referred to as "volatile" memory components) and one or more persistent memory components 108-1 to 108-M (hereinafter alternatively referred to as "non-volatile" memory components). For example, non-persistent memory components 106-1 to 106-N may include volatile memory devices such as dynamic random access memory (DRAM) devices or the like, while persistent memory components 108-1 to 108-M may include non-volatile memory devices having a NAND architecture. However, embodiments are not limited to a particular type of memory device. For example, non-persistent memory components 106-1 to 106-N may include other volatile memory devices such as static random access memory (SRAM) devices, while persistent memory components 108-1 to 108-M may include other non-volatile memory devices, such as NOR architecture devices, non-volatile random access memory devices (e.g., NVRAM, ReRAM, FeRAM, MRAM, PCM), "emerging" memory devices (e.g., variable resistance (e.g., 3D crosspoint (3DXP)) memory devices, memory devices containing self-select memory (SSM) cell arrays, memory devices operating according to the Compute Fast Link (CXL) protocol, etc.) or any combination thereof.

[0033] Variable resistance memory devices can be combined with stackable cross-gate data access arrays to perform bit storage based on changes in bulk resistance. Furthermore, compared to many flash-based memories, variable resistance non-volatile memories can perform in-situ write operations, where non-volatile memory cells can be programmed without first erasing them. Compared to flash-based memories and variable resistance memories, self-selecting memory cells can contain a memory cell made of a single chalcogenide material that serves as both a switch and a storage element for the memory cell.

[0034] In some embodiments, memory device 104 may be a compute-fast link (CXL) compliant memory system (e.g., the memory device may include a PCIe / CXL interface). CXL is a high-speed central processing unit (CPU) to device and CPU to memory interconnect designed to accelerate next-generation data center execution. CXL technology maintains memory consistency between CPU memory space and memory on the attached device, allowing resource sharing to achieve higher performance, reduced software stack complexity, and lower overall system cost.

[0035] CXL is designed with an industry-open standard interface for high-speed communication, as accelerators are increasingly used to supplement CPUs to support emerging applications such as artificial intelligence and machine learning. CXL technology is built on a Peripheral Component Interconnect Rapid (PCIe) infrastructure, thereby leveraging PCIe physical and electrical interfaces to provide high-level protocols in the region, such as input / output (I / O) protocols, memory protocols (e.g., initially allowing the host and accelerator to share memory), and coherence interfaces. In some embodiments, CXL technology may include multiple I / O channels configured to transmit multiple commands back and forth at a rate of approximately thirty-two (32) gigabytes per second to circuitry outside the control circuitry 120, such as non-persistent memory components 106-1 to 106-N, persistent memory components 108-1 to 108-M, and / or the host 102. In another embodiment, the CXL technology may include a Peripheral Component Interconnect Fast (PCIe) 5.0 interface coupled to multiple I / O channels, and the controller 120 is configured to receive commands relating to at least one of non-persistent memory component 106 or persistent memory component 108, or both, via the PCIe 5.0 interface based on the computation of the fast link memory system.

[0036] like Figure 1 As shown, host 102 is coupled to memory device 104 via communication path 103. Communication path 103 can be a wired or wireless communication path, which can be used to transfer data, commands, and other information between host 102 and memory device 104. Host 102 can be a host system, such as a personal laptop computer, desktop computer, digital camera, smartphone, memory card reader, and / or Internet of Things (IoT) enabled device, as well as various other types of hosts. However, in some embodiments, host 102 includes instructions to execute to control virtual machines (e.g., as described herein). Figure 3 The virtual machine 332 described herein is one or more central processing units that operate.

[0037] Those skilled in the art will understand that "processor" can mean one or more processors, such as in a parallel processing system, several coprocessors, etc. The computing system 100 may include a single integrated circuit, or one or more of the following components may be on the same integrated circuit: host 102, memory device 104, control circuitry 120, non-persistent memory components 106-1 to 106-N, and / or persistent memory components 108-1 to 108-N. The computing system 100 may be, for example, a server system and / or a high-performance computing (HPC) system and / or a portion thereof. Although... Figure 1 The examples shown illustrate systems with a von Neumann architecture, but embodiments of this disclosure can be implemented in non-von Neumann architectures, which may not include one or more components typically associated with a von Neumann architecture (e.g., CPU, ALU, etc.).

[0038] Memory device 104 may include control circuitry 120, which may include processing units (e.g., as described herein). Figure 2 The processing unit 222 described herein. The processing unit may be provided in the form of an integrated circuit, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a reduced instruction set computing device (RISC), an advanced RISC machine, a single-chip system, or other combinations of hardware and / or circuitry configured to perform the operations described in more detail herein. In some embodiments, the processing unit may include one or more processors (e.g., processing devices, coprocessors, etc.).

[0039] The control circuitry 120 may reside on the memory device 104. As used herein, the term "reside on" means that something is physically located on a particular component. For example, "control circuitry 120 resides on memory device 104" means that the control circuitry 120 is physically coupled to or physically located within the memory device. In this document, the term "reside on" may be used interchangeably with other terms such as "deployed on" or "located on".

[0040] The control circuitry system 120 can perform operations to monitor and / or determine characteristics of a workload running on the memory device 104. These characteristics may include information such as bandwidth consumption, memory resource consumption, access frequency (e.g., whether the data associated with one or more of the workload is hot or cold), and / or power consumption while performing the workload. Figure 2 The I / O device 218 described herein controls the writing of at least a portion of the data associated with a memory access request received by the control circuitry 120, so as to write the data associated with the memory access request to non-persistent memory components 106-1 to 106-N and / or persistent memory components 108-1 to 108-M based on the determined characteristics of the memory access request and / or workload optimization performed by the memory device 104. As described herein, the I / O device may be a network interface card (NIC), which may be a standard NIC or a virtualized NIC.

[0041] Figure 2 This is a functional block diagram of a memory device 204 according to several embodiments of the present disclosure. The memory device 204 may be part of a computing system and / or may be similar to those previously disclosed. Figure 1 The memory device 104 described is provided in the form of an FPGA, an ASIC, several discrete circuit components, etc.

[0042] Memory device 204 may include input / output (I / O) device 218, which may be coupled to control circuitry system 220. Control circuitry system 220 may be similar to that described herein. Figure 1 The control circuit system 120 is described in the text. For example... Figure 2 As shown, the control circuit system 220 includes a processing unit 222, a memory resource 224, a sequence generator 226, and a data structure 228. In some embodiments, the data structure 228 may be stored in the memory resource 224.

[0043] I / O device 218 may be a network interface controller or a network interface card, both of which may be referred to herein as "NIC". I / O device 218 can communicate with the computing system (e.g., via the physical layer circuitry required to implement the physical layer circuitry for communication with the computing system through IEEE 802 data link layer standards (e.g., Ethernet or Wi-Fi) Figure 1 The computing system 100 described herein provides a dedicated, always-on connection to the network. In some embodiments, I / O device 218 may allow the computing system to communicate with virtual machines (e.g., as described herein). Figure 3 The virtual machines 332-1, 332-2, 332-3 to 332-X described in the document communicate with each other.

[0044] In some embodiments, I / O device 218 may be a device configured to provide direct memory access via physical addresses and / or virtual machine physical addresses. In some embodiments, I / O device 218 may be a NIC, a storage device, a graphics rendering device, or other I / O device. I / O device 218 may be a physical I / O device or I / O device 218 may be a virtualized I / O device 218. For example, in some embodiments, I / O device 218 may be a physical card that is physically coupled to the computing system via a bus or interface (e.g., a PCIe interface or other suitable interface). In embodiments where I / O device 218 is a virtualized I / O device 218, virtualized I / O device 218 may provide I / O functionality in a distributed manner. In some embodiments, I / O device 218 may be operable as an input / output coupled to control circuitry system 220. The control circuit system 220 can transmit commands via I / O device 218 indicating data access to non-persistent memory devices 206-1 to 206-N and / or persistent memory devices 208-1 to 208-M.

[0045] I / O device 218 may receive memory access requests (e.g., requests to write and / or read data from non-persistent memory devices 206-1 to 206-N and / or persistent memory devices 208-1 to 208-M). However, in at least one embodiment, I / O device 218 receives a memory access request to read data from or write data to one of the non-persistent memory devices 206-1 to 206-N. In such embodiments, control circuitry 220 may receive the memory access request from I / O device 218 and, instead of reading data from or writing data to one of the non-persistent memory devices 206-1 to 206-N, redirect the memory access request to one of the persistent memory devices 208-1 to 208-M. Advantageously, in such embodiments, the control circuitry system 220 may redirect memory access requests to one of the persistent memory devices 208-1 to 208-M without notifying the I / O device 218, such that the I / O device 218 is unaware that a memory access request involving one of the persistent memory devices 208-1 to 208-M but not one of the non-persistent memory devices 206-1 to 206-N has been executed, as described in more detail herein.

[0046] As generally used herein, the term "execution" and its variations typically refer to the execution of operations performed by a hardware circuitry system (e.g., control circuitry system 220) to access data at a target address stored in a memory device or memory assembly and / or to write data to a target address in a memory device or memory assembly. For example, the phrase "execute a memory access request" should generally be interpreted as the execution of an operation describing (via hardware circuitry system) writing or reading data from a specified or target address in a volatile (e.g., non-persistent) or non-volatile (e.g., persistent) memory device. The execution of such operations (e.g., the execution of a memory access request) may be entirely implemented in and / or by hardware circuitry system executing computational instructions to facilitate the execution of operations accessing a target address location in a memory device. Depending on the context of some embodiments described herein and the needs of the disclosure, the term "execution" and its variations may therefore be used interchangeably with access to data associated with a target address in a memory device and / or memory assembly.

[0047] In some embodiments, I / O device 218 may generate and append data (“I / O data” or “NIC data”) to a memory access request. The I / O data may contain data corresponding to an operation performed by I / O device 218 to determine whether data associated with the memory access request is “of interest”. As used herein, “of interest” for data associated with a memory access request generally refers to conditions where the data differs from previous data associated with the memory access request or is useful for a particular application performed using memory device 204. As a non-limiting example, some applications (e.g., monitoring a nuclear collider) may repeatedly receive data identical to previous data. Therefore, I / O device 218 may determine that data identical to previous data is not “of interest” and may append I / O device data indicating that the data not “of interest” will not be stored by memory device 204 or written to persistent memory device 208 by control circuitry system 220. In contrast, if the data associated with the memory access request is different from previously received data, then I / O device 218 may attach an indication that the data is "of interest" and therefore can be written to persistent memory device 208 and / or non-persistent memory device 206, as determined by control circuitry system 220.

[0048] In another non-limiting example, the data collected by the autonomous vehicle may include both data of interest and data of non-interest during its operation. For example, the autonomous vehicle may receive hundreds of data points per second; however, only some of these data points may relate to objects sufficiently close to the vehicle to qualify as data of interest. In these cases, I / O data may include data appended to memory access requests to indicate data of interest (e.g., a small number of data points relating to objects near the vehicle) and therefore to be written to non-persistent memory device 206 (assuming control circuitry 220 mandates this), or I / O data may include data appended to memory access requests to indicate data of non-interest (e.g., the majority of data points relating to objects not near the vehicle) and therefore to be written to persistent memory device 208 (assuming control circuitry 220 mandates this).

[0049] As mentioned above, the processing unit 222 may be provided in the form of an integrated circuit, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a reduced instruction set computing device (RISC), an advanced RISC machine, a single-chip system, or other combinations of hardware and / or circuitry configured to perform the operations described in more detail herein. In some embodiments, the processing unit may include one or more processors (e.g., processing devices, coprocessors, etc.).

[0050] In some embodiments, the processing unit may perform various operations described herein. For example, processing unit 222 may perform operations to monitor the characteristics of memory access requests and / or the characteristics of data associated with memory access requests. As described above, the characteristics of memory requests and / or data associated with memory access requests may include the frequency of different types of memory access requests (e.g., memory access requests involving continuous data versus discontinuous data, memory access requests involving a specific type of application and / or workload, memory access requests involving a specific type of data that can be stored by memory device 204 at different times, etc.). Processing unit 222 may selectively execute memory access requests using non-persistent memory 206-1 to 206-N and / or persistent memory 208-1 to 208-M based on the monitored characteristics of memory access requests and / or the data associated with them.

[0051] For example, I / O device 218 may receive a memory access request from circuitry outside memory device 204 and transmit the memory access request (or append I / O data to the memory access request and transmit the memory access request containing I / O device data) to control circuitry 220. In some embodiments, I / O device 218 may request the memory access request to be executed using non-persistent memory 206-1 to 206-N, as described herein. Control circuitry 220 (e.g., processing unit 222) may monitor and / or determine the characteristics of the memory access request and / or the data associated with the memory access request and determine whether to execute the memory access request using non-persistent memory 206-1 to 206-N or using persistent memory 208-1 to 208-M. In an embodiment where the control circuitry 220 uses persistent memory 208-1 to 208-M to execute a memory access request, the control circuitry 220 may prevent the transmission of information instructing the memory access request to be executed using persistent memory 208-1 to 208-M instead of non-persistent memory 206-1 to 206-N to the I / O device 218, as requested by the I / O device 218.

[0052] The control circuitry system 220 further includes a memory resource 224. The memory resource 224 may include one or more caches and / or buffers. In some embodiments, the memory resource 224 may include SRAM and / or DRAM, but embodiments are not limited to these enumerated examples. In some embodiments, a data structure 228 may be included within the memory resource 224. Data associated with a memory access request may be stored (e.g., buffered in the memory resource) as part of the execution of a read or write operation indicated by the memory access request.

[0053] like Figure 2As shown, the control circuitry 220 further includes a sequence generator 226. The sequence generator 226 may include hardware circuitry and / or may include instructions executable by the hardware circuitry to generate addresses associated with non-persistent memories 206-1 to 206-N and / or persistent memories 208-1 to 208-M. These addresses may indicate the physical location within the non-persistent memories 206-1 to 206-N and / or persistent memories 208-1 to 208-M in which data is written. Alternatively or additionally, the sequence generator 226 may include hardware circuitry and / or may include instructions executable by the hardware circuitry to determine the order in which incoming memory access requests are processed by the control circuitry 220.

[0054] In addition, such as Figure 2 As shown, control circuitry system 220 includes data structure 228. As used herein, "data structure" refers to a specific format for organizing and / or storing data, which may or may not be organized into rows and columns. Examples of data structures include arrays, files, records, tables, trees, linked lists, hash tables, etc. In some embodiments, data structure 228 may be configured to store address mapping information for redirecting memory access requests (e.g., physical addresses in persistent memory 208-1 to 208-M where control circuitry system 220 has executed a memory access request received by I / O device 218). This allows control circuitry system 220 to retrieve data associated with a memory access request received from an I / O device to, for example, retrieve data that has been redirected by control circuitry system 220 to persistent memory 208-1 to 208-M, as described herein.

[0055] like Figure 2 As shown, control circuitry system 220 includes address register 229. Address register 229 may include base address registers (“BAR”) (e.g., BAR_1, BAR_2, BAR_3, BAR_4, BAR_5, BAR_6, etc.). The base address register may be a PCI BAR field configured to store up to 32 bits of addressing information. Generally, the amount of memory allocated for executing various application programs can be indicated by the contents of address register 229. In some embodiments, control circuitry system 220 may redirect memory access requests as part of an operation to determine the address in address register 229 that will be accessed in response to an assertion of an interrupt signal (e.g., an interrupt asserted to the supervisor 330 coupled to memory device 104, an interrupt signal asserted to I / O device 218 as part of retrieving data associated with the memory access request, etc.).

[0056] In some embodiments, at least one of the address registers 229 may contain a certain amount of address space corresponding to the size of the memory component (e.g., persistent memory device 208 and / or non-persistent memory device 206). For example, if the memory component contains 1 terabyte of storage, then at least one of the address registers 229 may be configured to have an address space that can contain 1 terabyte of address space. However, in some embodiments, the address register 229 does not actually contain 1 terabyte of storage but is instead configured to appear to have 1 terabyte of storage space.

[0057] Different address registers in address register 229 can be used to store addresses corresponding to interrupt control, as described in more detail herein. In some embodiments, this address register may map direct memory access (DMA) read and DMA write control and / or status registers. For example, this address register may contain addresses corresponding to descriptors and / or control bits for a DMA command chain lock, which may contain information that can be used in conjunction with the information described herein. Figure 3 The operation of the virtual machine 332 described herein is partly asserted to the generation of one or more interrupt messages to the I / O device 218 and / or the hypervisor 330.

[0058] Another address register 229 can store the information corresponding to the back-and-forth access to... Figure 3 The address register is the address of the hypervisor 330 running on the virtual machine 332. In some embodiments, access to and from the hypervisor 330 may be provided via an Advanced Extensible Interface (AXI) DMA associated with the memory device 204. In some embodiments, this address register may map the address of data transferred via the DMA (e.g., AXI DMA) of the memory device 204 to a location outside the memory device 204.

[0059] In some embodiments, at least one address register 229 may store an address corresponding to the access control circuitry 220 of the I / O device 218. This address register may store addresses bypassed by a DMA component associated with the memory device 204. This address register may be configured such that the address mapped to it is not “backed up” by the physical memory location of the control circuitry 220. That is, in some embodiments, the memory device 204 may be configured with an address space that stores addresses corresponding to data stored in a persistent memory device (e.g., persistent memory device 208) but not to data stored in a non-persistent memory device 206. For example, this address register may be configured as a virtual address space that stores logical addresses corresponding to physical memory locations in memory components where data is stored.

[0060] The memory device 204 further includes non-persistent memories 206-1 to 206-N and persistent memories 208-1 to 208-M. As described above, the non-persistent memories 206-1 to 206-N may include volatile memory resources, while the persistent memories 208-1 to 208-M may include non-volatile memory resources. The non-persistent memories 206-1 to 206-N may be referred to as a "non-persistent memory assembly" or a "non-persistent memory device," and the persistent memories 208-1 to 208-M may be referred to as a "persistent memory assembly" or a "persistent memory device."

[0061] like Figure 2 As shown, non-persistent memories 206-1 to 206-N can be communicatively coupled to persistent memories 208-1 to 208-M via a network on-chip (NOC) 210. NOC 210 can be a communication subsystem configured to facilitate the transfer of memory access requests and / or corresponding data between control circuitry 220, non-persistent memories 206-1 to 206-N, and / or persistent memories 208-1 to 208-M. NOC 210 can be coupled to non-persistent memory devices 206-1 to 206-N and / or persistent memory devices 208-1 to 208-M via communication paths operable according to DDR, PCIe, and / or CXL protocols, but embodiments are not limited thereto. However, in at least one embodiment, NOC 210 can transfer data from persistent memory devices 208-1 to 208-M to non-persistent memory devices 206-1 to 206-N according to DDR or CXL protocols, or vice versa.

[0062] although Figure 2 While not explicitly shown to avoid confusion, memory device 204 may include various buffers (e.g., read buffers and / or write buffers) to buffer data and / or memory access requests received from I / O device 218. Buffers may be approximately 4KB in size, but embodiments are not limited to this specific size. In some embodiments, memory device 204 may include a multiplexer (MUX), which may include circuitry that may include one or more logic gates and be configured to control the data and / or address bus of memory device 204. For example, the MUX may enable messages to be transmitted back and forth between memory resource 224 and to communicate with other components of memory device 204. The MUX may redirect incoming messages, commands, and / or requests (e.g., read and / or write requests) received by control circuitry 220 (e.g., from the host, I / O device 218, hypervisor 330, and / or virtual 332) as part of its operation to determine whether to use non-persistent memory 206-1 to 206-N or persistent memory 208-1 to 208-M to perform the memory access request.

[0063] In a non-limiting example, the device (e.g., memory device 204) includes a non-persistent memory component 206 and a persistent memory component 208 coupled to the non-persistent memory component 206. As mentioned above, the non-persistent memory component 206 may be referred to as a "volatile memory component" and the persistent memory component 208 may be referred to as a "non-volatile memory component". The device may further include a network interface card (NIC), such as an input / output (I / O) device 218. The device may further include a control circuitry 220 coupled to the NIC, the non-persistent memory component 206, and the persistent memory component 208.

[0064] Control circuitry system 220 may receive multiple memory access requests from the NIC and analyze the memory access requests to determine characteristics associated with the data corresponding to the memory access requests. Control circuitry system 220 may access data associated with a specific memory access request targeting an address in non-persistent memory component 206 in response to determining that the characteristic associated with the data is below a threshold data characteristic value, and / or use persistent memory component 208 to access data associated with a specific memory access request at a target address in response to determining that the characteristic associated with the data is above a threshold data characteristic value. As used herein, "threshold data characteristic value" generally refers to a value in which the characteristics of the data and / or memory access requests can be redirected from non-persistent memory component 206 to persistent memory component 208 by control circuitry system 220. For example, if the predicted amount of time data will be stored by memory device 204 and / or the frequency of a specific memory access request is greater than a threshold data characteristic value, then control circuitry system 220 may redirect the data and / or memory access requests from non-persistent memory component 206 to persistent memory component 208. However, if the predicted amount of data to be stored by memory device 204 and / or the frequency of specific memory access requests is less than a threshold data characteristic value, then control circuitry system 220 may use non-persistent memory component 206 to execute memory access requests.

[0065] As in this article Figure 3 In more detail, the NIC can send memory access requests from a virtual machine (e.g., as described herein) before transmitting them to the control circuitry 220. Figure 3 One or more of the virtual machines 332 described herein receive memory access requests. However, embodiments are not limited thereto, and in some embodiments, the NIC may receive memory access requests from a physical server or other host computing system that can be coupled to the memory device 204.

[0066] In some embodiments, the control circuitry 220 may use the persistent memory component 208 to execute a specific memory access request (e.g., the number of items at the target address that can be accessed), while prohibiting the transmission of signaling instructing the specific memory access request to be executed using the persistent memory component 208 (e.g., a request to be executed to access data at the target address). For example, the control circuitry 220 may access data at the target address by executing the memory access request using the persistent memory component 208, independent of signaling transmitted back and forth to the NIC instructing the NIC to use the persistent memory component 208 instead of the non-persistent memory component 206 instructed by the NIC.

[0067] Continuing this example, control circuitry 220 may include a data structure 228 configured to store address information corresponding to multiple memory access requests received from the NIC. In such embodiments, control circuitry 220 may write address information into the data structure in response to receiving a memory access request from the NIC.

[0068] As mentioned above, the control circuitry 220 may further include a sequencer 226. In such embodiments, the sequencer 226 manages memory access requests and command sequencing for the NIC, non-persistent memory component 206, and persistent memory component 208. Generally, the sequencer 226 can sequence operations performed by the I / O device 218 and / or the control circuitry 220 to ensure that constraints associated with the execution order of memory access requests or other commands (e.g., read / write switching) are maintained. In some embodiments, the sequencer 226 can reorder the execution of memory access requests and other commands to maximize or optimize the throughput of the memory device 204.

[0069] In some embodiments, control circuitry 220 may determine the predicted amount of time that data will be stored by non-persistent memory component 206 and / or persistent memory component 208 based on determined characteristics associated with data corresponding to a memory access request. Continuing this example, control circuitry 220 may determine a threshold data characteristic value based on the determined predicted amount of time that data will be stored by non-persistent memory component 206 or persistent memory component 208.

[0070] As described herein, control circuitry 220 may receive signaling indicating a read operation relating to data associated with a specific memory access request performed using persistent memory component 208 and notify the NIC that the execution of the read operation will take an amount of time greater than that associated with the execution of a deterministic read operation (e.g., there will be a delay when retrieving data that the NIC did not expect). For example, because the NIC may not know that control circuitry 220 has written data corresponding to a previous write operation to persistent memory component 208, control circuitry 220 may notify the NIC that data retrieval can be performed in a nondeterministic manner as part of the read operation.

[0071] For example, in some embodiments, memory device 204 (e.g., control circuitry 220 of memory device 204) may generate and assert an interrupt to I / O device 218 to initiate an operation to transfer data into or out of persistent memory device 208. For example, due to the nondeterministic nature of data retrieval and storage associated with persistent memory device 208, control circuitry 220 may generate an interrupt signal when data stored in persistent memory device 208 is requested to be transferred. In response to this (page fault) interrupt signal generated by control circuitry 220, control circuitry 220 may retrieve information corresponding to the data from persistent memory device 208. For example, memory device 204 may retrieve data that may contain a logical-to-physical address mapping corresponding to data stored in address register 229 of control circuitry 220.

[0072] Once data is stored in persistent memory device 208, portions of non-persistent memory device 206 (e.g., pages, blocks, etc.) can be marked as inaccessible by control circuitry system 220, preventing the computing system in which memory device 204 is deployed from attempting to access data from non-persistent memory device 206. This allows data requests to be intercepted with page faults, which can be generated by control circuitry system when data already stored in persistent memory device 208 is requested by I / O device 218.

[0073] Compared to methods that result in a page fault exception in response to an application request to access a page of memory not mapped by the memory management unit, in embodiments of this disclosure, the aforementioned interrupt signal or "page fault" may be generated by control circuitry 220 in response to data being mapped into address register 229, which in turn maps the data to persistent memory device 208.

[0074] In some embodiments, control circuitry 220 may transfer data associated with a specific memory access request performed using persistent memory component 208 to non-persistent memory component 206 after notifying the NIC that the execution of a read operation will take an amount of time greater than that associated with the execution of a deterministic read operation. Then, control circuitry 220 may transfer data associated with the specific memory access request from non-persistent memory component 206 to the NIC.

[0075] In another non-limiting example, the device (e.g., memory device 204) includes a non-persistent memory component 206 and a persistent memory component 208 coupled to the non-persistent memory component 206. The persistent memory component 208 may be coupled to the non-persistent memory component 206 via an on-chip network (e.g., NOC 210). The device may further include an input / output (I / O) device 218. The device may further include a control circuitry system 220 coupled to the I / O device 218, the non-persistent memory component 206, and the persistent memory component 208.

[0076] Continuing this example, I / O device 218 may receive a command to access data previously intended to be written to non-persistent memory component 206 (e.g., a memory access request) and transmit the data access command to control circuitry system 220. For example, the data access command may specify that the data to be accessed is to be written to or read from non-persistent memory component 206. In other words, in some embodiments, before receiving the data access command, control circuitry system 220 may redirect data previously intended to be written to non-persistent memory component 206 to persistent memory component 208 based on the characteristics of the data described herein. For example, the characteristics of the data include a predicted amount of time between memory access requests involving data similar to the data indicated by the command, and other characteristics described herein. Furthermore, as described herein, control circuitry system 220 may redirect data to persistent memory component 208 without notifying I / O device 218 that the data has been redirected to persistent memory component 208.

[0077] After receiving a command to access data, the control circuitry 220 can determine, based on the characteristics of the data, that the data has been written to the persistent memory component 208 and notify the I / O device 218 that the execution of the data access command will take longer than the time associated with the execution of a deterministic read operation. Then, after notifying the I / O device 218 that the execution of the data access command will take longer than the time associated with the execution of a deterministic read operation, the control circuitry 220 can transfer the data from the persistent memory component 208 to the non-persistent memory component 206. In such an example, the control circuitry 220 can transfer the data from the non-persistent memory component 206 to the I / O device 218.

[0078] As described herein, in some embodiments, the control circuitry 220, I / O device 218, non-persistent memory component 206, and persistent memory component 208 include components that can be accessed by a virtual machine (e.g., as described herein). Figure 3 The virtual machine 332 described herein accesses a set of computing resources. For example, storage device 204 may be provided in a cloud computing environment to provide hardware resources accessible by one or more virtual machines.

[0079] Figure 3 This is a functional block diagram of a memory device 304 coupled to a plurality of virtual machines 322 according to several embodiments of the present disclosure. The memory device 304 may be similar to that described herein. Figure 1 The memory device 104 and / or described herein Figure 2 The memory device 204 is described in the document. For example... Figure 3 As shown in the diagram, memory device 304 includes I / O device 318, which can be similar to those described herein. Figure 2 The I / O device 218 is described in the document.

[0080] Memory device 304 and / or I / O device 318 may be communicatively coupled to hypervisor 330, which may have several virtual machines (VMs) 331-1, 332-2, 332-3 to 332-X running thereon. VMs generally refer to isolated end-user space examples that can execute within a virtualized environment. Other technologies besides hardware virtualization that provide isolated end-user space examples are also considered within the scope of this disclosure. For example, containers can run on a host operating system without requiring a hypervisor 330 or a separate operating system, such as containers running within Linux. Containers may be provided by VMs that include a container virtualization layer (e.g., Docker). In some embodiments, a VM operates on the host using resources virtualized by virtualization software (e.g., hypervisor 330, virtual machine monitor, etc.) along with its own guest operating system. Tenants (i.e., the owners of the VMs) can choose which applications run on top of the guest operating system. On the other hand, some containers run on top of a host operating system without requiring a hypervisor 330 or a separate guest operating system.

[0081] In some embodiments, VMs 332-1 to 332-X may receive or generate data relating to writing to or reading from memory device 304 (e.g., writing to this document). Figure 2This refers to memory access requests for data from or to the non-persistent memory components 206-1 to 206-N and / or persistent memory components 208-1 to 208-M as described herein. Generally, such memory access requests are sporadic. For example, some access requests received or generated by VMs 332-1 to 332-X may occur rapidly (e.g., approximately milliseconds to seconds), while other access requests received or generated by VMs 332-1 to 332-X may occur at slower intervals or rather infrequently (e.g., approximately days to months).

[0082] Therefore, memory device 304 (e.g., control circuitry 320) can monitor such access requests to determine the characteristics of the access request (or the data associated with the access request). As described herein, control circuitry 320 can selectively redirect some access requests to persistent memory components while performing other access requests using non-persistent memory components. For example, control circuitry 320 can execute access requests that occur rapidly using non-persistent memory components and can execute access requests that occur at slower intervals or less frequently using persistent memory components. As described herein, when control circuitry 320 performs an access request using a persistent memory component, control circuitry 320 can prevent indication to I / O device 318 that such access request has been redirected from a non-persistent memory component to a persistent memory component.

[0083] Therefore, when data that has been redirected to a persistent memory component is requested again (e.g., via I / O device 318 and / or one of VMs 332-1 to 332-X), the control circuitry 320 may generate a signaling (e.g., an interrupt message or other such command) to the I / O device 318 indicating that there will be a delay in retrieving the requested data. This is because, as described above, persistent memory components typically do not operate in a deterministic manner like non-persistent memory components. As mentioned above, because the I / O device 318 is unaware that the access request has been redirected to a persistent memory component by the control circuitry 320, the control circuitry 320 must notify the I / O device 318 that a delay due to the non-deterministic behavior of the persistent memory component will occur before the access request is fulfilled.

[0084] In a non-restricted instance, the system (e.g.) Figure 1 The computing system 100 described herein may include a virtual machine (VM) 332 and a memory device 304 coupled to the VM 332. The memory device 304 includes non-persistent memory components (e.g., as described herein). Figures 1 to 2 The non-persistent memory components 106 / 206 described herein and persistent memory components (e.g., those described herein) Figures 1 to 2 (Persistent storage components 108 / 208 as described in the document).

[0085] like Figure 3 As shown, memory device 304 further includes input / output (I / O) device 318. I / O device 318 can receive memory access requests for non-persistent memory components from VM 332. For example, the memory access request may specify a location within the non-persistent memory component where the memory access will be performed, and / or I / O device 318 may request the memory access request to be performed using the non-persistent memory component. In some embodiments, I / O device 318 may append data (e.g., I / O device data, NIC data, etc.) to the memory access request.

[0086] The system may further include a control circuitry system 320 coupled to the I / O device 318, the non-persistent memory component, and the persistent memory component. The control circuitry system 320 may receive a memory access request containing I / O device data and determine the characteristics of the data associated with the memory access request containing I / O device data. As discussed herein, the characteristics of the data associated with the memory access request may include a predicted amount of time that the data corresponding to the memory access request containing I / O device data will be stored by the memory device 304. In such embodiments, the control circuitry system 320 may monitor memory access requests similar in range to the memory access request containing I / O device data to determine the predicted amount of time that the data corresponding to the memory access request containing I / O device data will be stored by the memory device 304 and determine the characteristics of the data associated with the memory access request containing I / O device data based on the predicted amount of time that the data corresponding to the memory access request containing I / O device data will be stored by the memory device 304.

[0087] Continuing this example, the control circuitry 320 may execute a memory access request using a non-persistent memory component in response to determining that the characteristics of the data meet a first criterion, and may execute a memory access request using a persistent memory component residing on the memory device in response to determining that the characteristics of the data meet a second criterion. In some embodiments, the first criterion may indicate that the characteristics of the data are below a threshold data characteristic value, while the second criterion may indicate that the characteristics of the data are above a threshold data characteristic value.

[0088] In some embodiments, the control circuit system 320 may include a data structure configurable to store address information corresponding to I / O device data (e.g., as described herein). Figure 2 (Data structure 228 as described in the text). In such embodiments, the control circuitry 320 may write address information corresponding to the I / O device data into the data structure in response to receiving a memory access request containing I / O device data.

[0089] In some embodiments, the system may include a communication system residing on memory device 304 and coupled to control circuitry system 320, I / O device 318, non-persistent memory components, and persistent memory components (e.g., as described herein). Figures 1 to 2 (NOC 108 / 208 as described in the document). In such embodiments, the control circuitry system 320 may perform a sorting operation to write data associated with a memory access request received from the I / O device 318 to a non-persistent memory component or a persistent memory component or both.

[0090] Continuing this example, control circuitry 320 may receive a memory access request containing I / O device data after receiving multiple previous memory access requests, each containing corresponding I / O device data. Control circuitry 320 may use the multiple previous memory access requests containing corresponding I / O device data to perform one or more machine learning operations or one or more artificial intelligence operations to determine the predicted amount of time the data corresponding to the memory access request containing I / O device data is stored by memory device 304. Using this information, control circuitry 320 may determine the characteristics of the data associated with the memory access request containing I / O device data based on the predicted amount of time the data corresponding to the memory access request containing I / O device data is stored by memory device 304.

[0091] Figure 4 This is a flowchart illustrating an example method 440 for memory access control according to several embodiments of the present disclosure. Method 440 can be executed by processing logic, which may include hardware (e.g., processing units, processing devices, control circuitry systems, special-purpose logic, programmable logic, microcode, device hardware and / or integrated circuits, etc.), software (e.g., instructions running or executed on the processing unit), or a combination thereof. Although shown in a specific sequence or order, the order of processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0092] In operation 442, method 440 may include receiving a memory access request targeted at an address of a volatile memory component of the memory device by a control circuitry system residing on the memory device. For example, method 440 may include receiving a memory access request involving a non-persistent memory component of the memory device by a control circuitry system residing on the memory device. For example, method 440 may include receiving a memory access request specifying a location (e.g., a target memory address) in the volatile or non-persistent memory device. The control circuitry system may be similar to that described herein. Figures 1 to 3The control circuit system 120 / 220 / 320 described herein may have a memory device similar to that described herein. Figures 1 to 3 The memory devices 104 / 204 / 304 described herein, and volatile or non-persistent memory components may be similar to those described herein. Figures 1 to 2 The non-persistent memory components 106 / 206 are described herein. In some embodiments, method 440 includes receiving a memory access request from a virtual machine, such as those described herein. Figure 3 One of the virtual machines 332 described in the document.

[0093] In operation 444, method 440 may include determining, by the control circuitry system, characteristics of data associated with a target address. For example, method 440 may include determining, by the control circuitry system, characteristics of data associated with a memory access request. As described above, the characteristics of the data may include determining the memory access frequency associated with the data and / or the corresponding memory access request. For example, the characteristics of the data associated with a memory access request may include a predicted amount of time the data will be stored by a memory device. However, embodiments are not limited thereto, and in some embodiments, the characteristics associated with the data and / or the memory access request itself may include information indicating whether similar memory access requests typically occur frequently or infrequently, as described above. Furthermore, in at least one embodiment, the characteristics associated with the data and / or the memory access request itself may include that the memory access request involves a virtual machine (e.g., as described herein). Figure 3 (One of the virtual machines 332 described in the text) or the physical host computing device.

[0094] In operation 446, method 440 may include accessing data at a target address of a volatile memory component in response to determining that the characteristics of the data satisfy a first criterion. For example, method 440 may include performing a memory access request using a non-persistent memory component residing on a memory device in response to determining that the characteristics of the data satisfy the first criterion. In some embodiments, the first criterion may be similar to a data characteristic value that is less than the threshold data characteristic value described above.

[0095] In operation 448, method 440 may include accessing data at another address of a non-volatile memory component in response to determining that the characteristics of the data satisfy a second criterion. For example, method 440 may include using a persistent memory component residing on a memory device (e.g., as described herein) in response to determining that the characteristics of the data satisfy a second criterion. Figures 1 to 2 The persistent memory components 108 / 208 described herein execute the memory access request. In some embodiments, the second criterion may be similar to a data characteristic value greater than the threshold data characteristic value described above.

[0096] As described above, in some embodiments, method 440 may include receiving I / O device data, such as network interface card data, as part of receiving a memory access request. In such embodiments, the I / O device may be similar to that described herein. Figures 1 to 3 The I / O devices 118 / 218 / 318 are described in the document.

[0097] Method 440 may further include executing a memory access request involving a non-volatile or persistent memory component without notifying an I / O device, such as a network interface card coupled to a control circuitry system. For example, method 440 may include selectively redirecting a memory access request to non-volatile or persistent memory (even though the original memory access request specified volatile or non-persistent memory, as described herein). Figures 1 to 2 The non-persistent memory (106 / 206) described herein does not require notifying the I / O device that the memory access request has been redirected to non-volatile or persistent memory.

[0098] In some embodiments, method 440 may include using an on-chip network (e.g., as described herein) to couple the control circuitry system to both a non-volatile or persistent memory component and a volatile or non-persistent memory component. Figures 1 to 2 The NOC110 / 210 described herein transfers data to a non-volatile or persistent memory component to perform a memory access request using the non-volatile or persistent memory component.

[0099] Method 440 may further include: analyzing a plurality of memory access requests over time by a control circuitry system; determining characteristics of each of the memory access requests; and determining characteristics of data associated with the memory access requests based on the determined characteristics of the plurality of memory access requests. For example, the control circuitry system may monitor the frequency of identical or similar memory access requests over time to predict and / or determine the characteristics of a particular memory access request. However, embodiments are not limited thereto, and in some embodiments, the control circuitry system may monitor the amount of time that data corresponding to identical or similar memory access requests is stored in the memory device to predict and / or determine the characteristics of a particular memory access request. As described above, in some embodiments, the control circuitry system may analyze memory access requests over time using one or more machine learning or artificial intelligence techniques to predict the characteristics of a particular memory access request.

[0100] Although specific embodiments have been illustrated and described herein, those skilled in the art will understand that arrangements calculated to achieve the same results may be substituted for the specific embodiments shown. This disclosure is intended to cover adaptations or variations of one or more embodiments of this disclosure. It should be understood that the foregoing description has been carried out in an illustrative rather than restrictive manner. Those skilled in the art will understand, upon reviewing the foregoing description, combinations of the above embodiments and other embodiments not explicitly described herein. The scope of one or more embodiments of this disclosure includes other applications in which the above structures and processes are used. Therefore, the scope of one or more embodiments of this disclosure should be determined with reference to the appended claims and the full scope of their authorized equivalents.

[0101] In the foregoing detailed embodiments, some features are grouped together in a single embodiment for the purpose of simplifying this disclosure. The method of this disclosure should not be interpreted as reflecting an intention that the disclosed embodiments must use more features than are expressly recited in each claim. In fact, as reflected in the appended claims, the subject matter of the invention lies in not all features of a single disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed embodiments, wherein each claim is considered an independent, separate embodiment.

Claims

1. A method for memory access control, comprising: The control circuitry system (120, 220, 320) residing on the memory devices (104, 204, 304) receives a memory access request from an input / output I / O device targeting the address of the volatile memory component (106, 206) of the memory devices (104, 204, 304). The characteristics of the data associated with the target address are determined by the control circuit system (120, 220, 320); In response to determining that the characteristics of the data satisfy a first criterion, the data at the target address of the volatile memory components (106, 206) is accessed; and In response to determining that the characteristics of the data satisfy a second criterion, data at another address of a non-volatile memory component (108, 208) is accessed, wherein the control circuitry provides the I / O device with a notification that the execution of a command to access the data in the non-volatile memory component will take a longer time than the amount of time associated with the execution of a deterministic read operation.

2. The method of claim 1, further comprising receiving network interface card data as part of receiving the memory access request.

3. The method of claim 1, wherein the characteristic of the data associated with the memory access request includes a predicted amount of time the data will be stored by the memory device.

4. The method of claim 1, further comprising executing the memory access request relating to the non-volatile memory component without notifying the network interface card coupled to the control circuitry system.

5. The method of claim 1, further comprising receiving the memory access request from a virtual machine (332).

6. The method of claim 1, further comprising using the non-volatile memory component to execute the memory access request by transmitting the data to the non-volatile memory component via an on-chip network that couples the control circuitry system to the non-volatile memory component and the volatile memory component.

7. The method of claim 1, further comprising: The control circuit system analyzes multiple memory access requests over time; Determine the characteristics of each of the memory access requests; and The characteristics of the data associated with the received memory access requests are determined based on the determined characteristics of the plurality of memory access requests.

8. A device for memory access control, comprising: Volatile memory components (106, 206); Non-volatile memory components (108, 208) coupled to said volatile memory components (106, 206); Network Interface Card (NIC); and A control circuit system (120, 220, 320) coupled to the NIC, the volatile memory assembly (106, 206), and the non-volatile memory assembly (108, 208), wherein the control circuit system (120, 220, 320) is configured to: Receive multiple memory access requests from the NIC; Analyze the memory access requests to determine the characteristics associated with the data corresponding to the memory access requests among the plurality of memory access requests; In response to determining that the characteristic associated with the data is below a threshold data characteristic value, data associated with a specific memory access request is accessed; and In response to determining that the characteristic associated with the data is higher than the threshold data characteristic value, the non-volatile memory components (108, 208) are used to access the data associated with the specific memory access request. The control circuitry is further configured to receive signaling indicating a read operation relating to data associated with a particular memory access request performed using the non-volatile memory component; and The NIC is notified that the execution of the read operation will take a longer time than the time associated with the execution of a deterministic read operation.

9. The device of claim 8, wherein the control circuitry is configured to access the data associated with the particular memory access request using the non-volatile memory component, while prohibiting the transmission of signaling to the NIC instructing the particular memory access request to use the non-volatile memory component for access.

10. The device according to claim 8, wherein: The control circuitry includes a data structure configured to store address information corresponding to the plurality of memory access requests received from the NIC, and The control circuitry is configured to write the address information into the data structure in response to receiving the plurality of memory access requests from the NIC.

11. The device of claim 8, wherein the control circuitry includes a sequence generator, and wherein the sequence generator is configured to manage memory access requests and command sequencing for the NIC, the volatile memory component, and the non-volatile memory component.

12. The device of claim 8, wherein the control circuitry is configured to: Based on determined characteristics associated with the data corresponding to the memory access request, a predicted amount of time is determined for which the data will be stored by the volatile memory component or the non-volatile memory component; and The threshold data characteristic value is determined based on the data and the determined prediction time amount stored by the volatile memory component or the non-volatile memory component.

13. The device of claim 8, wherein the NIC is configured to receive the plurality of memory access requests from a virtual machine.

14. The device of claim 8, wherein the control circuitry is further configured to: After informing the NIC that the execution of the read operation will take a longer time than the time associated with the execution of the deterministic read operation, the data associated with the specific memory access request executed using the non-volatile memory component will be transferred to the volatile memory component; and The data associated with the specific memory access request is transferred from the volatile memory component to the NIC.

15. A device for memory access control, comprising: Non-persistent memory components (106, 206); Persistent memory components (108, 208) are coupled to the non-persistent memory components (106, 206); Input / output I / O devices (218, 318); and A control circuit system (120, 220, 320) coupled to the I / O devices (218, 318), the non-persistent memory components (106, 206), and the persistent memory components (108, 208), wherein... The I / O devices (218, 318) are configured to: Receive a command to access data previously intended to be written to the non-persistent memory components (106, 206); and The command to access the data is transmitted to the control circuit system (110, 220, 320), and wherein... The control circuit system (120, 220, 320) is configured to: Based on the characteristics of the data, it is determined that the data has been written to the persistent storage components (108, 208); The execution of the command to notify the I / O device (218, 318) to access the data will take a longer time than the amount of time associated with the execution of a deterministic read operation; After informing the I / O devices (218, 318) that the execution of the command to access the data will take an amount of time greater than the amount of time associated with the execution of the deterministic read operation, the data is transferred from the persistent memory component (108, 208) to the non-persistent memory component (106, 206); and The data is transferred from the non-persistent memory components (106, 206) to the I / O devices (218, 318).

16. The device of claim 15, wherein the control circuitry, I / O devices, the non-persistent memory component, and the persistent memory component include a set of computing resources accessible by a virtual machine.

17. The device of claim 15, wherein prior to receiving the command to access the data, the control circuitry is configured to redirect data previously intended for writing to the non-persistent memory component to the persistent memory component based on the characteristics of the data.

18. The device of claim 17, wherein the control circuitry is further configured to redirect the data to the persistent memory component without notifying the I / O device that the data has been redirected to the persistent memory component.

19. The device of claim 15, wherein the characteristic of the data includes a predicted amount of time between memory access requests for data similar to the data indicated by the command.

20. A system for memory access control, comprising: Virtual machine VM (332); Memory devices (104, 204, 304), communicatively coupled to the VM (332), and comprising: Non-persistent memory components (106, 206); Persistent memory components (108, 208) are coupled to the non-persistent memory components (106, 206); Input / output I / O devices (218, 318), configured to: Receive memory access requests for the non-persistent memory components (106, 206) from the VM (332); and Append I / O device data to the memory access request; and A control circuit system (120, 220, 320) coupled to the I / O device (218, 318), the non-persistent memory component (106, 206), and the persistent memory component (108, 208), wherein the control circuit system (120, 220, 320) is configured to: Receive the memory access request containing data from the I / O device; Determine the characteristics of the data associated with the memory access request containing data from the I / O device; In response to determining that the characteristics of the data satisfy a first criterion, the memory access request is executed using the non-persistent memory components (106, 206); and In response to determining that the characteristics of the data satisfy a second criterion, the persistent memory component (108, 208) residing on the memory device is used to execute the memory access request, wherein the control circuitry is further configured to provide the I / O device with a notification that the execution of the command to access the data residing in the persistent memory component of the memory device will take a longer time than the amount of time associated with the execution of a deterministic read operation.

21. The system of claim 20, wherein the control circuitry includes a data structure configured to store address information corresponding to the I / O device data, and wherein the control circuitry is configured to write the address information corresponding to the I / O device data into the data structure in response to receiving a memory access request containing the I / O device data.

22. The system of claim 20, wherein the control circuitry is configured to: The monitoring scope is similar to the memory access requests containing the I / O device data to determine the predicted amount of time that data corresponding to the memory access request containing the I / O device data is stored by the memory device; and The characteristics of the data associated with the memory access request containing the I / O device data are determined by the predicted time amount stored in the memory device based on the data corresponding to the memory access request containing the I / O device data.

23. The system of claim 20, wherein the control circuitry is configured to: After receiving a plurality of previous memory access requests, each containing data of the respective I / O device, the memory access request containing the I / O device data is received; One or more machine learning operations or one or more artificial intelligence operations are performed using the plurality of previous memory access requests, each containing data of the respective I / O device, to determine the predicted amount of time that data corresponding to the memory access request containing the data of the I / O device is stored by the memory device. and The characteristics of the data associated with the memory access request containing the I / O device data are determined by the predicted time amount stored in the memory device based on the data corresponding to the memory access request containing the I / O device data.

24. The system of claim 20, further comprising a communication system residing on the memory device and coupled to the control circuitry system, the I / O device, the non-persistent memory component, and the persistent memory component, wherein the control circuitry system is configured to perform a sorting operation to write data associated with the memory access request received from the I / O device to the non-persistent memory component or the persistent memory component or both.

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