System and method for outputting test data from multiple cores

Abstract

The present invention relates to a system for outputting test data from cores to a communication interface. The system comprises shared memories corresponding to the cores. Each shared memory comprises a ring buffer and an array of slots. Each core generates a diagnostic message and stores the generated diagnostic message in a selected memory area of the ring buffer corresponding to a first empty slot of the array of slots. A selected core finds a first diagnostic message among the diagnostic messages stored in the shared memory and outputs the first diagnostic message to a personal computer through the communication interface.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a testing system. Background Technology

[0002] The computing environment paradigm has shifted to ubiquitous computing systems that can be used anytime, anywhere. Consequently, the use of portable electronic devices such as mobile phones, digital cameras, and laptops has increased rapidly. These portable electronic devices typically use memory systems with memory devices (i.e., data storage devices). Data storage devices serve as either the main memory or auxiliary memory devices in portable electronic devices.

[0003] Because memory devices have no moving parts, memory systems using them offer excellent stability, durability, high data access speeds, and low power consumption. Examples of memory systems with these advantages include Universal Serial Bus (USB) memory devices, memory cards with various interfaces such as Universal Flash Memory (UFS), and solid-state drives (SSDs). Various testing tools can be used to test memory systems. Summary of the Invention

[0004] An aspect of the invention includes a system and method for outputting test data from multiple simultaneously accessed kernels to a communication interface without high latency.

[0005] In one aspect of the invention, a testing system includes: a personal computer configured to transmit test commands; and a testing apparatus including: a communication interface connected to the personal computer and configured to receive test commands from the personal computer; a plurality of cores simultaneously accessed in response to the test commands, each core configured to receive the test commands from the communication interface and perform tests on a plurality of memory blocks associated with each core in response to the test commands; and a plurality of shared memories corresponding to the plurality of cores, each shared memory including a ring buffer and a slot array. Each of the plurality of cores is configured to: generate a diagnostic message associated with the test; determine a) whether one or more empty slots exist in the slot array and b) whether one or more free memory regions exist in the ring buffer; and when it is determined that a) one or more empty slots exist in the slot array and b) one or more free memory regions exist in the ring buffer, store the generated diagnostic message in a memory region selected from the one or more free memory regions, the selected memory region corresponding to a first empty slot among the one or more empty slots. The core selected from the plurality of cores is configured to: find a first diagnostic message among the plurality of diagnostic messages stored in the plurality of shared memories and output the first diagnostic message to the personal computer via the communication interface.

[0006] In another aspect of the invention, a method for operating a test system is provided. The test system may include a personal computer and a test apparatus, the test apparatus including a) a communication interface for receiving test commands from the personal computer, and b) a plurality of kernels for performing tests on a plurality of memory blocks in response to simultaneous access to the test commands. The method may include: setting up a plurality of shared memories corresponding to the plurality of kernels, each shared memory including a circular buffer and a slot array; generating a diagnostic message associated with the test by each of the plurality of kernels; determining by each of the plurality of kernels a) whether one or more empty slots exist in the slot array, and b) whether one or more free memory regions exist in the circular buffer; when it is determined that one or more empty slots exist in the slot array and one or more free memory regions exist in the circular buffer, storing the generated diagnostic message by each of the plurality of kernels in a memory region selected from the one or more free memory regions, the selected memory region corresponding to a first empty slot among the one or more empty slots; finding a first diagnostic message among the plurality of diagnostic messages stored in the plurality of shared memories by the selected kernel; and outputting the first diagnostic message to the personal computer via the communication interface by the selected kernel.

[0007] Other aspects of the invention will become apparent from the following description. Attached Figure Description

[0008] Figure 1 This is a block diagram illustrating a data processing system according to an embodiment of the present invention.

[0009] Figure 2 This is a block diagram illustrating a memory system according to another embodiment of the present invention.

[0010] Figure 3 This is a circuit diagram illustrating a memory block of a memory device according to yet another embodiment of the present invention.

[0011] Figure 4 This is a diagram illustrating the state distribution of different types of cells in a memory device according to an embodiment of the present invention.

[0012] Figure 5 This is a diagram illustrating a test system for a multi-core storage device according to another embodiment of the present invention.

[0013] Figure 6 This is a diagram illustrating an implementation of a shared memory scheme corresponding to the mode of each core in a test system according to yet another embodiment of the present invention.

[0014] Figure 7 This is a diagram illustrating the structure of a shared memory according to an embodiment of the present invention.

[0015] Figure 8 This is a diagram illustrating an example of diagnostic data stored in a circular buffer according to another embodiment of the present invention.

[0016] Figure 9 This is a diagram illustrating an example of a ring buffer and slot array according to yet another embodiment of the present invention.

[0017] Figure 10 This is a flowchart illustrating a test operation of a multi-core storage device according to yet another embodiment of the present invention. Detailed Implementation

[0018] Various embodiments of the invention are described in more detail below with reference to the accompanying drawings. However, the invention may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to fully convey the scope of the invention to those skilled in the art. Furthermore, references herein to “embodiment,” “another embodiment,” etc., are not necessarily directed to only one embodiment, and different references to any such phrases are not necessarily directed to the same embodiment. The term “embodiment” as used herein does not necessarily refer to all embodiments. Throughout this disclosure, the same reference numerals in the drawings and embodiments refer to the same parts.

[0019] This invention can be embodied in various ways, including, for example, processes, apparatus, systems, computer program products implemented on a computer-readable storage medium; and / or processors, such as processors adapted to execute instructions stored on and / or provided thereto in memory coupled to a processor. In this specification, these embodiments or any other form in which the invention may take the form of a technique may be referred to. Generally, the order of operations of the disclosed processes can be varied within the scope of this invention. Unless otherwise stated, components such as processors or memory described as suitable for performing tasks can be implemented as general-purpose means or circuit components configured or otherwise programmed to perform tasks at a given time, or as specific means or circuit components manufactured or pre-configured or pre-programmed to perform tasks. As used herein, the term "processor," etc., refers to one or more means, circuits, and / or processing cores suitable for processing data (e.g., computer program instructions).

[0020] The methods, processes, and / or operations described herein can be executed by code or instructions to be run by a computer, processor, controller, or other signal processing device. The computer, processor, controller, or other signal processing device can be those described herein or other elements besides those described herein. Because the algorithms underlying the methods (or the operation of a computer, processor, controller, or other signal processing device) are described herein, the code or instructions for implementing the methods can convert a computer, processor, controller, or other signal processing device into a dedicated processor to execute any of the methods described herein.

[0021] If implemented at least in part in software, the controller, processor, device, module, unit, multiplexer, generator, logic, interface, decoder, driver, generator, and other signal generation and signal processing features may include, for example, a memory or other storage device for storing code or instructions to be executed by, for example, a computer, processor, microprocessor, controller, or other signal processing device.

[0022] The following provides a detailed description of various embodiments of the invention, along with accompanying drawings illustrating aspects of the invention. The invention has been described in conjunction with these embodiments, but is not limited to any particular embodiment. The invention includes many alternatives, modifications, and equivalents. Numerous specific details are set forth in the following description to provide a thorough understanding of the invention. These details are provided for illustrative purposes only; the invention may be practiced without some or all of these specific details. For clarity, technical materials known in the art related to the invention have not been described in detail, so as not to unnecessarily obscure the invention.

[0023] Figure 1 This is a block diagram illustrating a data processing system 2 according to an embodiment of the present invention.

[0024] Reference Figure 1 The data processing system 2 may include a host device 5 and a memory system 10. The memory system 10 may receive requests from the host device 5 and operate in response to the received requests. For example, the memory system 10 may store data to be accessed by the host device 5.

[0025] The host device 5 can be implemented using any of a variety of electronic devices. In various embodiments, the host device 5 can be an electronic device such as a desktop computer, workstation, 3D television, smart television, digital audio recorder, digital audio player, digital picture recorder, digital picture player, and / or digital video recorder and digital video player. In various embodiments, the host device 5 can be a portable electronic device such as a mobile phone, smartphone, e-book reader, MP3 player, portable multimedia player (PMP), and / or portable game console.

[0026] The memory system 10 can be implemented using any of a variety of storage devices such as solid-state drives (SSDs) and memory cards. In various embodiments, the memory system 10 can be configured as a component of a variety of electronic devices, such as computers, ultra-mobile personal computers (PCs) (UMPCs), workstations, netbooks, personal digital assistants (PDAs), portable computers, network tablet PCs, wireless phones, mobile phones, smartphones, e-book readers, portable multimedia players (PMPs), portable gaming devices, navigation devices, black boxes, digital cameras, digital multimedia broadcasting (DMB) players, 3D televisions, smart televisions, digital audio recorders, digital audio players, digital picture recorders, digital picture players, digital video recorders, digital video players, data center storage devices, devices capable of receiving and transmitting information in a wireless environment, radio frequency identification (RFID) devices, and a variety of electronic devices for home networks, computer networks, telematics networks, or a component of a computing system.

[0027] The memory system 10 may include a memory controller 100 and a semiconductor memory device 200. The memory controller 100 can control all operations of the semiconductor memory device 200.

[0028] The semiconductor memory device 200 can perform one or more erase, program, and read operations under the control of the memory controller 100. For example... Figure 1 As shown, the semiconductor memory device 200 can receive commands (CMD), addresses (ADDR), and data (DATA) via input / output lines. The semiconductor memory device 200 can receive power (PWR) via power lines and control signals (CTRL) via control lines. Depending on the design and configuration of the memory system 10, the control signal CTRL may include, for example, a command latch enable signal, an address latch enable signal, a chip enable signal, a write enable signal, a read enable signal, and other operation signals.

[0029] The memory controller 100 and the semiconductor memory device 200 can be integrated into a single semiconductor device, such as a solid-state drive (SSD). The SSD may include a storage device for storing data therein. In one embodiment of the invention, the semiconductor memory system 10 is used for the SSD, and a host device (e.g., connected to the memory system 10) is... Figure 1 The operating speed of the main unit 5) can be significantly improved.

[0030] The memory controller 100 and the semiconductor memory device 200 can be integrated into a single semiconductor device such as a memory card. For example, the memory controller 100 and the semiconductor memory device 200 can be integrated to configure PC cards, compact flash memory (CF) cards, smart media (SM) cards, memory sticks, multimedia cards (MMC), reduced-size multimedia cards (RS-MMC), miniature versions of MMC (micro MMC), secure digital cards (SD cards), mini secure digital cards (mini SD cards), micro secure digital cards (micro SD cards), secure digital high-capacity (SDHC) cards, and / or universal flash memory (UFS).

[0031] Figure 2 This is a block diagram illustrating a memory system according to an embodiment of the present invention. For example, Figure 2 The memory system can be described Figure 1 The memory system 10 shown.

[0032] Reference Figure 2 The memory system 10 may include a memory controller 100 and a semiconductor memory device 200. The memory system 10 can respond to requests from a host device (e.g., from...). Figure 1 It operates upon request from host device 5 and specifically stores data to be accessed by the host device.

[0033] The semiconductor memory device 200 can store data to be accessed by a host device.

[0034] The semiconductor memory device 200 can be implemented using volatile memory devices such as, for example, dynamic random access memory (DRAM) and / or static random access memory (SRAM) or non-volatile memory devices such as, for example, read-only memory (ROM), mask ROM (MROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), ferroelectric random access memory (FRAM), phase change RAM (PRAM), magnetoresistive RAM (MRAM) and / or resistive RAM (RRAM).

[0035] The controller 100 can control the storage of data in the semiconductor memory device 200. For example, the controller 100 can control the semiconductor memory device 200 in response to a request from a host device. The controller 100 can provide data read from the semiconductor memory device 200 to the host device, and can store data provided from the host device into the semiconductor memory device 200.

[0036] The controller 100 may include a storage device 110 connected via a bus 160, a control component 120 which may be implemented as a processor such as, for example, a central processing unit (CPU), an error correction code (ECC) component 130, a host interface (I / F) 140, and a memory interface (I / F) 150.

[0037] Storage device 110 can be used as working memory for memory system 10 and controller 100, and storage device 110 can store data used to drive memory system 10 and controller 100. For example, when controller 100 controls the operation of semiconductor memory device 200, storage device 110 can store data used by controller 100 and semiconductor memory device 200 for operations such as read operations, write operations, programming operations, and erase operations.

[0038] Storage device 110 can be implemented using volatile memory such as static random access memory (SRAM) or dynamic random access memory (DRAM). As described above, storage device 110 can store data used by a host device in semiconductor memory device 200 for read and write operations. To store data, storage device 110 may include, for example, program memory, data memory, write buffer, read buffer, map buffer, etc.

[0039] Control component 120 can control the general operation of memory system 10 and control write or read operations of semiconductor memory device 200 in response to write or read requests from host device. Control component 120 can drive firmware or other program instructions, which may be referred to as flash translation layer (FTL), to control the general operation of memory system 10. For example, FTL can perform operations such as logical-physical (L2P) mapping, wear leveling, garbage collection, and / or bad block disposal. L2P mapping is referred to as logical block addressing (LBA).

[0040] ECC component 130 can detect and correct errors in data read from semiconductor memory device 200 during a read operation. In one embodiment, when the number of error bits is greater than or equal to a threshold number of correctable error bits, ECC component 130 may not correct the error bits, but may instead output an error correction failure signal indicating that the correction of the error bits has failed.

[0041] In various embodiments, ECC component 130 may perform error correction operations based on coding modulations such as low-density parity-check (LDPC) codes, Bose-Chaudhuri-Hocquenghem (BCH) codes, turbo codes, turbo product codes (TPC), Reed-Solomon (RS) codes, convolutional codes, recursive systematic codes (RSC), trellis-coded modulation (TCM), or block-coded modulation (BCM). However, error correction is not limited to these techniques. Therefore, ECC component 130 may include any and all circuitry, systems, or devices suitable for error correction operations.

[0042] The host interface 140 can communicate with the host device through one or more of the following communication standards or interfaces: such as Universal Serial Bus (USB), Multimedia Card (MMC), High-Speed ​​Peripheral Component Interconnect (PCI-e or PCIe), Small Computer System Interface (SCSI), Serial SCSI (SAS), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Enhanced Small Disk Interface (ESDI), and Electronic Integrated Drive (IDE).

[0043] The memory interface 150 can provide an interface between the controller 100 and the semiconductor memory device 200, allowing the controller 100 to control the semiconductor memory device 200 in response to requests from the host device. The memory interface 150 can generate control signals for the semiconductor memory device 200 and process data under the control of the control component 120. In one embodiment, where the memory device 200 is a flash memory such as NAND flash memory, the memory interface 150 can generate control signals for the memory and process data under the control of the control component 120.

[0044] For example Figure 2 The illustrated semiconductor memory device 200 may include a memory cell array 210, control circuitry 220, voltage generation circuitry 230, row decoder 240, page buffer 250 (which may be in the form of a page buffer array), column decoder 260, and input / output (I / O) circuitry 270. The memory cell array 210 may include multiple memory blocks 211 capable of storing data. The voltage generation circuitry 230, row decoder 240, page buffer array 250, column decoder 260, and I / O circuitry 270 may form peripheral circuitry for the memory cell array 210. This peripheral circuitry may perform programming, reading, or erasing operations on the memory cell array 210. The control circuitry 220 may control the peripheral circuitry.

[0045] The voltage generation circuit 230 can generate operating voltages of various levels. For example, in an erase operation, the voltage generation circuit 230 can generate operating voltages of various levels, such as erase voltage and pass voltage.

[0046] The row decoder 240 can communicate electrically with the voltage generation circuit 230 and a plurality of memory blocks 211. The row decoder 240 can select at least one memory block among the plurality of memory blocks 211 in response to a row address generated by the control circuit 220, and transmit the operating voltage supplied from the voltage generation circuit 230 to the selected memory block.

[0047] Page buffer 250 can be accessed via bit line BL ( Figure 3 (As shown) is connected to the memory cell array 210. The page buffer 250 can precharge the bit line BL with a positive voltage during programming and reading operations, transfer data to and receive data from the selected memory block, or temporarily store the transferred data in response to a page buffer control signal generated by the control circuit 220.

[0048] The column decoder 260 can transmit data to and receive data from the page buffer 250, or it can transmit data to and receive data from the input / output circuit 270.

[0049] Input / output circuit 270 can input from external devices (e.g., Figure 1 The memory controller 100 receives commands and addresses and transmits them to the control circuit 220, which transmits data from an external device to the column decoder 260, or outputs data from the column decoder 260 to an external device.

[0050] The control circuit 220 can control one of the peripheral circuits in response to commands and addresses.

[0051] Figure 3 This is a circuit diagram illustrating a memory block of a semiconductor memory device 200 according to an embodiment of the present invention. For example, Figure 3 The storage block can be Figure 2 Any one of the memory blocks 211 in the memory cell array 210 of the semiconductor memory device 200 shown.

[0052] Reference Figure 3 Storage block 211 may include multiple word lines WL0 to WLn-1, drain select line DSL, and source select line SSL connected to line decoder 240. These lines may be arranged in parallel, with multiple word lines arranged between DSL and SSL.

[0053] The memory block 211 may further include multiple cell strings 221 respectively connected to bit lines BL0 to BLm-1. Each column of cell strings may include one or more drain select transistors (DSTs) and one or more source select transistors (SSTs). In the illustrated embodiment, each cell string has one DST and one SST. Within the cell string, multiple memory cells or memory cell transistors MC0 to MCn-1 may be connected in series between the select transistors DST and SST. Each of the memory cells may be formed as a multi-level cell. For example, each of the memory cells may be formed as a single-level cell (SLC) storing 1 bit of data. Each of the memory cells may be formed as a multi-level cell (MLC) storing 2 bits of data. Each of the memory cells may be formed as a three-level cell (TLC) storing 3 bits of data. Each of the memory cells may be formed as a four-level cell (QLC) storing 4 bits of data.

[0054] The source of each SST in a cell string can be connected to the common source line CSL, and the drain of each DST can be connected to the corresponding bit line. The gate of an SST in a cell string can be connected to SSL, and the gate of a DST in a cell string can be connected to DSL. The gates of memory cells across cell strings can be connected to their respective word lines. That is, the gate of memory cell MC0 is connected to the corresponding word line WL0, the gate of memory cell MC1 is connected to the corresponding word line WL1, and so on. A group of memory cells connected to a specific word line can be called a physical page. Therefore, the number of physical pages in memory block 211 can correspond to the number of word lines.

[0055] Page buffer array 250 may include multiple page buffers 251 connected to bit lines BL0 to BLm-1. Page buffers 251 may operate in response to page buffer control signals. For example, page buffers 251 may temporarily store data received through bit lines BL0 to BLm-1 or sense the voltage or current of the bit lines during read or verification operations.

[0056] In various embodiments of the present invention, memory block 211 may include NAND flash memory cells. However, memory block 211 is not limited to this cell type, but may include NOR flash memory cells. Memory cell array 210 may be implemented as a hybrid flash memory combining two or more types of memory cells, or as a 1-NAND flash memory with the controller embedded within the memory chip.

[0057] Figure 4 This is a diagram illustrating a data processing system 2 according to an embodiment of the present invention.

[0058] Reference Figure 4The data processing system 2 may include a host 5 and a memory system (i.e., storage device) 10. Storage device 10 may include a controller 100 and a memory device 200. Memory device 200 may include multiple memory cells (e.g., NAND flash memory cells). The memory cells are arranged in an array of rows and columns, such as... Figure 3 As shown. Cells in a specific row are connected to word lines (e.g., WL0), and cells in a specific column are connected to bit lines (e.g., BL0). These word lines and bit lines are used for read and write operations. During a write operation, the data to be written ("1" or "0") is provided on the bit line while the word line is addressed. During a read operation, the word line is addressed again, and the threshold voltage for each cell can then be obtained from the bit line. Multiple pages can share memory cells belonging to (i.e., connected to) the same word line.

[0059] The controller 100 may include firmware (FW), which is a specific category of software used to control various operations of the memory device 200, such as read operations, write operations, and erase operations. In some embodiments, the firmware may reside in the storage device 110 and may be controlled by [the controller / software]. Figure 2 The control component 120 is running.

[0060] The firmware may include a host interface layer (HIL) that controls communication with the host 5, a flash translation layer (FTL) that controls communication between the host 5 and the memory device 200, and a flash interface layer (FIL) that controls communication with the memory device 200. The FTL is the most complex part of the firmware.

[0061] Storage device 10, such as a solid-state drive (SSD), may include a controller 100 implemented using multiple cores. These multi-core systems may include a communication interface with an external test device used for testing (i.e., for logging and diagnostic purposes). In most cases, printing (or transmitting) to the test device can be implemented using a slow-transmission (or output) interface as the communication interface. The output interface may be implemented using a Universal Asynchronous Receiver and Transmitter (UART), a Serial (or Single) Wire Output (SWO), etc.

[0062] When the output interface is used for simultaneous access by multiple kernels, the following problems exist.

[0063] The first problem is that, in most cases, the output interface does not arbitrate or support queuing of data output from multiple sources. Combined with simultaneous access from multiple kernels, this leads to overlap of messages from different kernels during data output. In practice, the output interface's resources—the output components whose size equals the output interface's output buffer (e.g., an 8-byte buffer)—should be distributed across several kernels. This distribution can depend on the implementation of the mutexes within the output interface (i.e., one of multiple mutexes that synchronize / control data access) and the mutex's capture algorithm. In cases where one kernel exclusively captures the output interface mutex for the entire duration of an output message, other kernels may need to output diagnostic messages. In this situation, other kernels may be unable to output diagnostic messages because they will attempt to capture the mutex. Periodically checking the mutex while performing other tasks in parallel can result in the loss of data not output to the output interface, as new data may arrive.

[0064] The second issue is the output of diagnostic messages from higher-priority modes, such as interrupt or exception handlers. For example, output from interrupt mode to the output interface can interrupt output from user mode to the output interface. In other words, the execution of a higher-priority interrupt handler may block the execution of a lower-priority interrupt.

[0065] The third problem is that output to the output interface does not necessarily occur in the order of message output start time, but may occur in the order of capture by the output interface mutex. Even with minimal latency between messages on different kernels, it's impossible to determine which message will be transmitted first, as it awaits capture by the output interface mutex and may continue outputting on other kernels. This can reduce the value of output diagnostic messages.

[0066] The fourth problem is the extremely slow output of diagnostic data (or messages). Typically, preparing and displaying diagnostic messages can significantly delay the main program's execution. Given the high-speed processing of modern System-on-Chip (SoC) cores, this can render such SoC channels unusable, for example, due to their strong impact on the timing of critical tasks running in the main program. For instance, at a UART speed of 115200 baud, outputting one character takes approximately 87 microseconds. The internal UART output buffer is small and typically doesn't allow more than 8 to 32 bytes (characters) to be filled at once. Furthermore, the kernel needs a considerable amount of time to continuously check if the UART output buffer is empty before filling it further. Additionally, capturing exclusive access mutexes takes time. All of this impacts the main program's execution and results in significant latency. For example, for an 80-character message, using the simplest solution, it would take 6.264 milliseconds to output to a UART with an 8-byte buffer. This is precisely the time spent processing the data in the main program.

[0067] Therefore, various embodiments of the present invention can provide a solution that effectively outputs test data (i.e., diagnostic data) from multiple kernels accessed simultaneously to a single communication interface without high latency.

[0068] Figure 5 This is a diagram illustrating a test system 500 for a multi-core storage device according to an embodiment of the present invention.

[0069] Reference Figure 5 The test system 500 may include a personal computer (PC) 510 and a test device 520. The PC 510 can test the test device 520 and collect diagnostic data (or test data) from it. For example, the PC 510 may be a host computer 5, while the test device 520 may be a memory system 10, such as... Figure 4 As shown.

[0070] In various embodiments, the test apparatus 520 may be a multi-core storage device (or multi-core memory system), such as a multi-core solid-state drive (SSD). The test apparatus 520 may include multiple cores 530, a communication interface 540, and multiple shared memories 550. Figure 5 In the example shown, multiple cores 530 may include cores CORE 1 531 through CORE K 539. Each core can be implemented using a central processing unit (CPU).

[0071] The communication interface 540 can receive test commands from the personal computer 510 and transmit the test commands to multiple kernels 530. That is, the test commands can be commands for simultaneously accessing and testing all multiple kernels 530. Alternatively, the test commands can be commands for accessing and testing one or more kernels selected from the multiple kernels 530. In various embodiments, the communication interface 540 can be implemented using a universal asynchronous receiver and transmitter (UART).

[0072] Each kernel can receive test commands via communication interface 540 and execute specific tests in response to the test commands. For example, each kernel can communicate with multiple memory blocks (e.g., Figure 4 The kernel associates the memory blocks in the memory device 200 with the memory blocks and performs tests on multiple memory blocks. As a result of the tests, each kernel can generate diagnostic data and provide the diagnostic data to the corresponding shared memory in the multiple shared memories 550.

[0073] Multiple shared memories 550 may include first shared memories 551 to Kth shared memories 559. Figure 5 In the example shown, the first shared memory 551 to the Kth shared memory 559 can correspond to the first core CORE 1531 to the Kth core CORE K 539, respectively. That is, the number of shared memories 550 can be the same as the number of cores 530.

[0074] Optionally, the number of shared memory units 550 can be determined based on the number of cores 530 and the number of operating modes supported by each core. In various embodiments, each operating mode may include any one of user, interrupt, supervisory, and other modes associated with the CPU's architecture. If a core (i.e., the CPU) has few operating modes that should be handled individually, then that operating mode can be used as a separate core. In other words, in one embodiment of the invention, each operating mode exists as a separate CPU with its own architecture and processing. Figure 6 In the example shown, the first core 531 can support three operating modes and has three shared memories 11 to 13 corresponding to the three operating modes. The second core 532 can support two operating modes and has two shared memories 21 to 22 corresponding to the two operating modes.

[0075] Each shared memory 700 may include a circular buffer 710 and a slot array 720, such as Figure 7 As shown. Details for each shared memory are described below.

[0076] Each of the multiple cores 530 can execute specific tests (e.g., black-box, white-box, and unit tests) and generate diagnostic data associated with the tests. That is, each of the multiple cores 530 can be a producer (builder) of diagnostic data. Further, each core can determine whether one or more empty slots exist in the slot array 720 and whether one or more memory regions exist in the circular buffer 710. When it is determined that one or more empty slots exist in the slot array 720 and one or more free memory regions exist in the circular buffer 710, each core can store the generated diagnostic data in a memory region selected from the one or more free memory regions. The selected memory region may correspond to a first empty slot among the one or more empty slots.

[0077] A kernel can be selected from multiple kernels 530. The selected kernel can find a first diagnostic message among multiple diagnostic messages stored in multiple shared memories 550, and output the first diagnostic message to the personal computer 510 via the communication interface 540. In various embodiments, the selected kernel can be the kernel with the least load (the kernel with the least amount of stored data) among the multiple kernels 530. Figure 5 In the example shown, the first core 531 can be selected from multiple cores 530.

[0078] As described above, diagnostic data can be output to communication interface 540 via shared memory 550, instead of being directly output to communication interface 540. Shared memory 550 can be accessed by the kernel (e.g., Figure 5 The first kernel 531 is accessed, which directly interacts with the communication interface 540 and outputs diagnostic data. That is, during the output of diagnostic data, the test device 520 can use the output to the shared memory 550 instead of exclusively capturing diagnostic data at the communication interface 540. The shared memory 550 may not be globally shared, but may be shared between the kernel acting as the diagnostic data output controller (i.e., the selected kernel) and the kernel acting as the diagnostic data producer (i.e., all kernels).

[0079] Figure 7 This is a diagram illustrating the structure of a shared memory 700 according to another embodiment of the present invention. The shared memory 700 may be... Figure 5 Each of the multiple shared memories 550. The construction of diagnostic data, that is, the generation (production) of diagnostic data and the storage of diagnostic data in shared memory 700, can be accomplished by... Figure 5 Each kernel in the process executes.

[0080] Reference Figure 7As described above, the shared memory 700 may include a ring buffer 710 and a slot array 720. Further, the shared memory 700 may include regions 715 and 725. Figure 5 Each kernel can generate diagnostic data (i.e., diagnostic messages) and store the generated diagnostic data in a circular buffer 710. Each kernel can generate header information associated with the diagnostic data and store the generated header information in a slot array 720. Each kernel can generate buffer information about the circular buffer 710 and store the generated buffer information in region 715. Each kernel can generate array information about the slot array 720 and store the generated array information in region 725.

[0081] The circular buffer 710 may include multiple memory areas for storing diagnostic data, i.e., multiple diagnostic messages. Figure 7 In the example shown, the circular buffer 710 can store seven diagnostic messages, including the zeroth diagnostic message Message0 through the sixth diagnostic message Message6.

[0082] The slot array 720 may include multiple slots corresponding to multiple memory regions of the circular buffer 710. Figure 7 In the example shown, the slot array 720 may include (N+1) slots, which include the zeroth slot with index 0 to the Nth slot with index N. For example, the zeroth slot may correspond to the zeroth diagnostic message Message0, the first slot may correspond to the first diagnostic message Message1, and the second slot may correspond to the second diagnostic message Message2.

[0083] Each slot array 720 can store header information for a diagnostic message. In various embodiments, the header information may include a header address, a timestamp, and length information. The header address may indicate a specific memory region among multiple memory regions of the circular buffer 710 that stores the diagnostic message. The timestamp may indicate the time the diagnostic message was stored in the specific memory region. The length information may be information about the length of the diagnostic message.

[0084] The array information may include a head index, a tail index, and size information associated with the slot array. The head index may indicate the first slot in the slot array 720, while the tail index may indicate the first empty slot in the slot array 720. The size information may be information about the size of the slot array 720.

[0085] The buffer information may include the tail address indicating the first empty location in the circular buffer 710 and size information about the size of the circular buffer 710.

[0086] Return to reference Figure 5 The first diagnostic message can be found among multiple diagnostic messages stored in multiple shared memories 550, selected from among multiple kernels 530. Further, the first kernel 531 can output the first diagnostic message to the personal computer 510 via the communication interface 540. For example, the first kernel 531 can find the first diagnostic message among multiple diagnostic messages stored in a circular buffer 710 of each shared memory. The circular buffer 710 can have, for example, [details omitted]. Figure 8 The state shown.

[0087] exist Figure 8 In the example shown, seven diagnostic messages, including message 0 through message 6, have been stored in the circular buffer 710. Some diagnostic messages may have been output to the communication interface 540, while the remaining diagnostic messages remain stored in the circular buffer 710. Figure 8 As shown, the five diagnostic messages, including message 0 (zero) and messages 3 through 6 (sixth), are messages that have already been processed and sent to communication interface 540. Figure 8 As shown, the two diagnostic messages, including the first message Message1 and the second message Message2, are messages that have not yet been sent to the communication interface 540.

[0088] Figure 9 This is a diagram illustrating an example of a ring buffer 710 and a slot array 720 according to another embodiment of the present invention.

[0089] Reference Figure 9 Diagnostic messages can be stored sequentially in the circular buffer 710. Figure 9 In the example shown, four diagnostic messages, including message 0 through message 3, can be stored sequentially in the circular buffer 710. The diagnostic messages can have the same data length or different data lengths. Header and tail addresses can be managed for the circular buffer 710. The header address can indicate the location in the circular buffer 710 where each diagnostic message is stored. That is, the header address can be an offset in the circular buffer 710 relative to the starting position of the corresponding diagnostic message, i.e., an offset relative to the location of the memory region in the circular buffer 710 where the corresponding diagnostic message is stored. The tail address can indicate the first empty memory region in the circular buffer 710.

[0090] Header information associated with each diagnostic message can be generated and stored in each slot of slot array 720. Each slot can have an index and can store header information including a timestamp and data length. Slot with index 0 can store the timestamp "5" and data length "16" of the zeroth message Message0 in circular buffer 710. Slot with index 1 can store the timestamp "91" and data length "25" of the first message Message1 in circular buffer 710. Slot with index 2 can store the timestamp "108" and data length "9" of the second message Message2 in circular buffer 710. Slot with index 3 can store the timestamp "304" and data length "9" of the third message Message3 in circular buffer 710. Header and tail indices can be managed for slot array 720. The header index can indicate the first slot found in slot array 720 when searching the slot array 720 for stored data, and the tail index can indicate the first empty slot found when searching slot array 720.

[0091] In various embodiments, the header index and header address may remain unchanged during the construction (i.e., generation and storage) of one or more diagnostic messages. The header index and address may change when one or more diagnostic messages are output to communication interface 540. The tail index and address may be changed to indicate the location for adding a new diagnostic message.

[0092] Among the four diagnostic messages mentioned above, such as Figure 9 As shown, two diagnostic messages, Message0 (zero message) and Message3 (third message), have been sent to communication interface 540. Figure 9 As shown, the first message Message1 and the second message Message2 are still held in the circular buffer 710 and have not yet been sent to the communication interface 540.

[0093] In this case, such as Figure 7As shown, the size of slot array 720 can be set to N, the header index can be set to 1, which represents the slot with index "1" in slot array 720, and the tail index can be set to 3, which represents the first empty (or free) slot, i.e., the slot with index "3" in slot array 720. The header address in the slot with index "1" can point to the address of the first byte of the first message Message1 in the circular buffer 710. The header address in the slot with index "2" can point to the address of the first byte of the second message Message2 in the circular buffer 710. The tail address in the slot with index "3" can point to the address of the first byte after the second message Message2 in the circular buffer 710. That is, the tail address can point to the address corresponding to the sum of the header address and the data length of the second message Message2.

[0094] In various embodiments, Figure 5 The selected kernel can find the smallest timestamp among the timestamps of header information stored in multiple slot arrays 720 in multiple shared memories 550. Furthermore, the selected kernel can find the diagnostic message with the smallest timestamp from the circular buffer 710 and output the found diagnostic message to the communication interface 540.

[0095] Return to reference Figure 5 Multiple cores on the 530 can execute test operations (e.g., black-box, white-box, and unit tests) and generate test data (i.e., diagnostic messages) associated with those operations. Figure 5 In the example shown, multiple kernels CORE 1 through CORE K can run diagnostic data generation tasks. Due to these tasks, diagnostic messages can be generated and stored in the circular buffer 710 of each of the shared memories 550. Furthermore, various information associated with the diagnostic messages can be generated and stored in each shared memory.

[0096] The diagnostic data generation task can be executed by each of the multiple kernels. First, the kernel can check the head and tail indices of slot array 720 to determine if there are empty slots in slot array 720. When the head index and tail index are found to be different, the kernel can determine that there are empty slots in slot array 720.

[0097] Second, the kernel can obtain the head address of the circular buffer 710 from the slot with the head index in the slot array 720. Third, the kernel can check the head address and tail address of the circular buffer 710 to determine whether there is an empty (free) memory region among the multiple memory regions in the circular buffer 710. When the head address and tail address are found to be different, the kernel can determine that there is an empty memory region in the circular buffer 710.

[0098] Fourth, when it is determined that there is an empty memory region in the circular buffer 710, the kernel can store the new diagnostic message into the empty memory region pointed to by the tail address in the circular buffer 710. Fifth, the kernel can put (store) the header information of the new diagnostic message (i.e., header address, timestamp, and data length) into the slot pointed to by the tail index in the slot array 720. Finally, the kernel can change the tail address of the circular buffer 710 and change the tail index of the slot array 720.

[0099] The diagnostic data output task can be executed by a specific kernel among multiple kernels. In one embodiment, the specific kernel can be one of the less loaded kernels (e.g., the least loaded kernel). In an example shown, the specific kernel can be the first kernel CORE1. Therefore, the diagnostic data generation task and the diagnostic data output task do not overlap in time.

[0100] For a diagnostic data output task, a specific kernel can determine the diagnostic message to be output to the personal computer 510 (stored in the circular buffer of shared memory 550 and pointed to by a header index). In one embodiment, the specific kernel can find a first diagnostic message among the diagnostic messages stored in the circular buffer of shared memory 550 based on header information (e.g., timestamps) stored in slot array 720. The first diagnostic message can be the diagnostic message with the smallest (or lowest) timestamp among the diagnostic messages pointed to by the header index. Further, the specific kernel can retrieve the diagnostic message with the lowest timestamp (i.e., Figure 9 The first diagnostic message shown is output to the personal computer 510 via the communication interface 540.

[0101] The diagnostic message output task can cycle through the header information of slot array 720 to find the minimum timestamp. The diagnostic message output task can then output the found diagnostic message to communication interface 540. When communication interface 540 includes an internal buffer (e.g., 8 bytes), one or more message chunks of the same size as the internal buffer can be output to communication interface 540. For example, a chunk of diagnostic messages (e.g., 8 bytes) can be output to communication interface 540. As another example, two chunks of diagnostic messages (e.g., 2 × 4 bytes) can be output to communication interface 540.

[0102] After one or more diagnostic messages have been output, the header index of the slot array 720 and the header address of the circular buffer 710 can be changed. The location of the next diagnostic message to be output from or stored in the circular buffer 710 can occur automatically due to the header or tail address of the circular buffer 710. Afterward, the operation of finding the minimum timestamp can be repeated, and the next diagnostic message can be output to the communication interface 540.

[0103] Therefore, in one embodiment of the invention, no migration of diagnostic messages in memory occurs. Synchronization between kernels may also be unnecessary because different pointers (i.e., the head and tail) are changed on different kernels: the head is changed on the kernel that outputs diagnostic messages to shared memory 550, and the tail is changed on the kernel that outputs diagnostic messages to communication interface 540. In the case of kernel checks, there are no conflicts in the ring buffer 710 due to old tail values.

[0104] Figure 10 This is a flowchart illustrating a test operation of a multi-core storage device according to another embodiment of the present invention. Test operation 1000 can be performed by... Figure 5 The test system 500 is executed. For example... Figure 5 As shown, the test system 500 may include a personal computer 510 configured to transmit test commands to a test apparatus 520. The test apparatus 520 may include multiple cores 530 accessed simultaneously in response to test commands, a communication interface 540 connected to the personal computer 510 and configured to receive test commands from the personal computer, and multiple shared memories 550 corresponding to the number of cores 530. Each core may be configured to receive test commands from the communication interface 540 and, in response to the test commands, perform tests (e.g., black-box, white-box, and unit tests) on multiple memory blocks associated with each core. Each shared memory may include a ring buffer 710 and a slot array 720, such as... Figure 7 As shown.

[0105] Reference Figure 10 Test operation 1000 may include diagnostic data generation (or construction) operation 1010 and diagnostic data output operation 1050. Diagnostic data generation operation 1010 may be executed by each of a plurality of kernels, while diagnostic data output operation 1050 may be executed by a specific kernel selected from the plurality of kernels. In various embodiments, the specific kernel may be the least loaded kernel among the selected kernels.

[0106] Diagnostic data generation operation 1010 may include operations 1020 to 1040. In operation 1020, each of the plurality of cores may generate a diagnostic message associated with the test. In operation 1030, each of the plurality of cores may determine whether one or more empty slots exist in the slot array and whether one or more memory regions exist in the ring buffer. In operation 1040, when it is determined that one or more empty slots exist in the slot array and when it is determined that one or more free memory regions exist in the ring buffer, each of the plurality of cores may store the generated diagnostic message in a memory region selected from the one or more free memory regions. The selected memory region may correspond to a first empty slot among the one or more empty slots.

[0107] In various embodiments, each of the plurality of kernels can generate header information and can store the header information in a specific slot among the plurality of slots in the slot array, wherein the header information includes a header address indicating the specific memory region among the plurality of memory regions of the circular buffer where the diagnostic message is stored and a timestamp indicating the time when the diagnostic message was stored in the specific memory region. The header information may further include information about the length of the diagnostic message.

[0108] In various embodiments, each of the plurality of kernels can determine whether there are one or more empty slots in the slot array based on a head index and a tail index, wherein the head index indicates the first slot in the slot array and the tail index indicates the first empty slot in the slot array.

[0109] In various embodiments, each of the plurality of cores may generate array information including a head index and a tail index associated with the slot array, and may store the array information in shared memory.

[0110] In various embodiments, each of the plurality of kernels may generate buffer information including the tail address of a first empty memory region in a circular buffer, and may store the buffer information in shared memory.

[0111] The diagnostic data output operation 1050 may include operations 1060 to 1070. In operation 1060, the selected kernel can find a first diagnostic message among multiple diagnostic messages stored in multiple shared memories 550. In various embodiments, the selected kernel can find the smallest timestamp among the timestamps of header information stored in multiple slot arrays of the multiple shared memories, and can find the first diagnostic message with the smallest timestamp.

[0112] In operation 1070, the selected kernel can output a first diagnostic message to the personal computer 510 via communication interface 540.

[0113] As described above, various embodiments of the present invention provide a scheme for efficiently outputting test data from multiple simultaneously accessed kernels to a single communication interface without high latency.

[0114] Although the foregoing embodiments have been shown and described in detail for clarity and understanding, the invention is not limited to the details provided. As those skilled in the art will understand from the foregoing disclosure, many alternative ways of carrying out the invention exist. Therefore, the disclosed embodiments are exemplary and not restrictive. The invention is intended to cover all modifications and alternatives to the disclosed embodiments. Furthermore, the disclosed embodiments can be combined to form other embodiments.

Claims

1. A testing system, comprising: Personal computer, transmitting test commands; as well as The testing apparatus includes: A communication interface is connected to the personal computer and receives the test commands from the personal computer. Multiple kernels, accessed simultaneously in response to the test command, each kernel receiving the test command from the communication interface and performing tests on multiple memory blocks associated with each kernel in response to the test command; and Multiple shared memories, corresponding to the multiple cores, each shared memory including a circular buffer and a slot array. Each of the plurality of kernels mentioned above: Generate diagnostic messages associated with the test; Determine a) whether there are one or more empty slots in the slot array, and b) whether there are one or more free memory regions in the annular buffer; and When it is determined that a) one or more empty slots exist in the slot array and b) one or more free memory regions exist in the annular buffer, the generated diagnostic message is stored in a memory region selected from the one or more free memory regions, the selected memory region corresponding to the first empty slot among the one or more empty slots, and The kernel selected from the plurality of kernels: finds a first diagnostic message among the plurality of diagnostic messages stored in the plurality of shared memory, and outputs the first diagnostic message to the personal computer through the communication interface.

2. The test system of claim 1, wherein the circular buffer in each shared memory comprises a plurality of memory regions, and the slot array in each shared memory comprises a plurality of slots corresponding to the plurality of memory regions, and Each of the plurality of kernels further includes: Generate header information, which includes a header address and a timestamp. The header address indicates a specific memory region among the multiple memory regions of the circular buffer where the diagnostic message is stored, and the timestamp indicates the time the diagnostic message was stored in that specific memory region. The header information is stored in a specific slot among the multiple slots of the slot array.

3. The testing system according to claim 2, wherein the header information further includes information about the length of the diagnostic message.

4. The test system of claim 2, wherein each of the plurality of cores determines whether one or more empty slots exist in the slot array based on a head index and a tail index, the head index indicating a first slot in the slot array and the tail index indicating a first empty slot in the slot array.

5. The test system of claim 4, wherein each of the plurality of kernels further comprises: Array information including head and tail indices associated with the slot array is generated and stored in the shared memory.

6. The test system of claim 5, wherein the array information further includes information about the size of the slot array.

7. The test system of claim 2, wherein each of the plurality of kernels further comprises: Generate buffer information including a tail address, the tail address indicating a first empty memory region in the circular buffer, and The buffer information is stored in the shared memory.

8. The test system of claim 7, wherein the buffer information further includes information about the size of the circular buffer.

9. The test system of claim 2, wherein the selected kernel: Find the smallest timestamp among the timestamps of the header information stored in the slot array of the multiple shared memories, and Find the first diagnostic message with the minimum timestamp.

10. The test system of claim 9, wherein the selected kernel is the kernel with the least load among the plurality of kernels.

11. The test system of claim 1, wherein the number of the plurality of shared memories is determined based on the number of the plurality of cores and the number of operating modes supported by each core.

12. A method of operating a test system, the test system comprising a personal computer and a test apparatus, the test apparatus comprising a) a communication interface for receiving test commands from the personal computer, and b) a plurality of kernels simultaneously accessed in response to the test commands to perform tests on a plurality of memory blocks, the method comprising: Multiple shared memories are configured corresponding to the multiple cores, and each shared memory includes a ring buffer and a slot array; Each of the plurality of kernels generates a diagnostic message associated with the test; Each of the plurality of cores determines a) whether there are one or more empty slots in the slot array, and b) whether there are one or more free memory regions in the circular buffer; When it is determined that a) there are one or more empty slots in the slot array and b) there are one or more free memory regions in the ring buffer, each of the plurality of kernels stores the generated diagnostic message in a memory region selected from the one or more free memory regions, the selected memory region corresponding to the first empty slot among the one or more empty slots; The first diagnostic message is found by the kernel selected from the plurality of kernels among the plurality of diagnostic messages stored in the plurality of shared memories; and The selected kernel outputs the first diagnostic message to the personal computer via the communication interface.

13. The method of claim 12, further comprising: Each of the plurality of kernels generates header information, the header information including a header address and a timestamp, the header address indicating a specific memory region among the plurality of memory regions of the circular buffer where the diagnostic message is stored, and the timestamp indicating the time the diagnostic message was stored in the specific memory region; and Each of the plurality of cores stores the header information in a specific slot among the plurality of slots in the slot array.

14. The method of claim 13, wherein the header information further includes information about the length of the diagnostic message.

15. The method of claim 13, wherein determining whether one or more empty slots exist in the slot array comprises: The presence of one or more empty slots in the slot array is determined based on a head index and a tail index, wherein the head index indicates the first slot in the slot array and the tail index indicates the first empty slot in the slot array.

16. The method of claim 15, further comprising: Each of the plurality of cores generates array information including a head index and a tail index associated with the slot array, and each of the plurality of cores stores the array information in the shared memory.

17. The method of claim 13, further comprising: Each of the plurality of kernels generates buffer information including a tail address, the tail address indicating a first empty memory region in the circular buffer; and Each of the plurality of kernels stores the buffer information in the shared memory.

18. The method of claim 13, wherein finding the first diagnostic message comprises: Find the smallest timestamp among the timestamps of the header information stored in the multiple slot arrays of the multiple shared memories; and Find the first diagnostic message with the minimum timestamp.

19. The method of claim 18, wherein the selected kernel is the least loaded kernel among the plurality of kernels.

20. The method of claim 12, wherein the number of the plurality of shared memories is determined based on the number of the plurality of cores and the number of operating modes supported by each core.

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