Data error checking and correction method and flash memory

Abstract

The application discloses a data error checking and correcting method and a flash memory. The data error checking and correcting method is characterized in that a calculation formula of each non-flag error correction code includes an even number of check factors. When each data bit in the data to be checked is 1, i.e. in a correct erasing condition, the check result indicated by each error correction code is 0, which means that the erasing of the data to be checked is correct, and the accuracy of the check result after erasing in the Nor flash is improved.

Description

Technical Field

[0001] This application relates to the field of data processing technology, specifically to a data error checking and correction method and a flash memory. Background Technology

[0002] During the data verification process, the verification technology can be ECC (Error Correcting Code). However, due to differences in the calculation formulas for each ECC, errors can easily occur in the verification results after erasure in NorFlash. Summary of the Invention

[0003] This application provides a data error checking and correction method and a flash memory to alleviate the technical problem that the inspection results after erasure in Nor Flash are prone to errors.

[0004] In a first aspect, this application provides a data error checking and correction method, which includes: configuring error correction codes including non-flag error correction codes; constructing a calculation formula for each non-flag error correction code that includes an even number of check factors, each check factor being a data bit, a check bit, or a virtual bit.

[0005] Secondly, this application provides a data error checking and correction method, which includes: configuring error correction codes including non-flag error correction codes; constructing a calculation formula for each non-flag error correction code that includes the same number of check factors, each check factor being a data bit, a check bit, or a virtual bit.

[0006] Thirdly, this application provides a data error checking and correction method, which includes: determining the number of check bits and the number of error correction codes corresponding to the data to be checked based on the bit width of the data bits in the data to be checked; determining the mapping relationship between the arrangement result of the error correction codes and the check bits and data bits based on the weighted ascending order of the arrangement result; determining the calculation formula of the error correction codes based on the encoding position and the mapping relationship; and obtaining the check result of the data to be checked based on the calculation result of the error correction codes.

[0007] In some implementations, the step of determining the mapping relationship between the permutation results and the check bits and data bits based on the weighted ascending order of the permutation results of the error correction codes includes: obtaining the number of 1s in each permutation result; obtaining the weight coefficient corresponding to each permutation result according to the number of 1s in each permutation result, wherein the more 1s in each permutation result, the higher the weight coefficient; and obtaining the weighted ascending order according to the sorting of multiple weight coefficients from low to high.

[0008] In some implementations, the step of determining the mapping relationship between the permutation result and the check bit and data bits based on the weighted ascending order of the permutation result of the error correction code further includes: constructing a one-to-one correspondence between each check bit and a permutation result containing a 1; constructing a one-to-one correspondence between each data bit and a permutation result containing multiple 1s according to the encoding ascending order, wherein the encoding ascending order is the permutation order of the permutation result from smallest to largest.

[0009] In some implementations, the step of constructing a one-to-one correspondence between each check bit and a permutation containing a 1 includes: configuring check bits including the least check bit to the most check bit; configuring the least check bit to the most check bit to correspond one-to-one with a permutation in ascending order of the encoding.

[0010] In some implementations, the step of constructing a one-to-one correspondence between each data bit and a permutation result containing multiple 1s in ascending order of encoding, wherein the ascending order of encoding is the permutation order from smallest to largest, includes: configuring the data bits to include the lowest data bit to the highest data bit; and the lowest data bit to the highest data bit are respectively assigned to a permutation result in ascending order of encoding.

[0011] In some implementations, the step of determining the calculation formula of the error correction code based on the encoding position and mapping relationship includes: configuring the error correction code to include a flag error correction code and multiple non-flag error correction codes; constructing the calculation formula of each non-flag error correction code to include an even number of the same number of check factors, each check factor being a data bit, a check bit, or a virtual bit.

[0012] In some implementations, the step of constructing the calculation formula for each non-flag error correction code includes an even number of identical check factors, each check factor being a data bit, a check bit, or a virtual bit, includes: configuring the calculation formulas for different non-flag error correction codes to include one check bit, an even number of virtual bits, and an odd number of distinct data bits; and determining the calculation formula for the flag error correction code based on the intermediate calculation data and calculation results of the calculation formula for each non-flag error correction code.

[0013] In some implementations, the step of determining the calculation formula of the error correction code based on the encoding position and mapping relationship further includes: obtaining the encoding ascending order according to the ascending order of the error correction code arrangement results; and determining the encoding positions of the parity bit and data bit according to the encoding ascending order.

[0014] In some implementations, the step of determining the calculation formula of the error correction code based on the encoding position and mapping relationship further includes: configuring the check bits to include a flag check bit and multiple non-flag check bits; and determining the calculation formula of each non-flag error correction code based on the sequential arrangement, encoding position and mapping relationship of the multiple non-flag check bits.

[0015] In some implementations, the step of determining the calculation formula for each non-flag error correction code based on the sequential arrangement, encoding position, and mapping relationship of multiple non-flag check bits includes: constructing a non-flag error correction code calculation formula in which the check factor includes a non-flag check bit; and constructing a flag error correction code calculation formula in which the check factor includes a flag check bit.

[0016] In some embodiments, the calculation formula for constructing each non-flag error-correcting code includes an even number of identical check factors, and the step of each check factor being a data bit, a parity bit, or a virtual bit further includes: constructing the data of each parity bit as 0 during encoding; and constructing the data of each virtual bit as 0. Fourthly, this application provides a flash memory that performs the data error checking and correction method described in at least one of the above embodiments after an erase operation.

[0017] The data error checking and correction method and flash memory provided in this application include an even number of check factors in the calculation formula of each non-flag error correction code. When all data bits in the data to be checked are 1, that is, the erasure is correct, the check result represented by each error correction code is 0, which means that the erasure of the data to be checked is without error. This improves the accuracy of the check result after erasure in Nor Flash. Attached Figure Description

[0018] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0019] Figure 1 This is a schematic diagram of the Hamming code algorithm in related technologies.

[0020] Figure 2 This is a schematic diagram of the Hsiao code algorithm in related technologies.

[0021] Figure 3 This is a schematic diagram of the ECC verification algorithm in related technologies.

[0022] Figure 4 A flowchart illustrating the data error checking and correction method provided in this application embodiment.

[0023] Figure 5 A schematic diagram of the algorithm for the 16-bit data error checking and correction method provided in the embodiments of this application.

[0024] Figure 6 A schematic diagram illustrating the structure for determining the number of error correction codes provided in this application embodiment.

[0025] Figure 7 This is a mapping diagram between error correction codes, data bits, and check bits provided in the embodiments of this application.

[0026] Figure 8 This is a schematic diagram of an algorithm for a 32-bit data error checking and correction method provided in an embodiment of this application.

[0027] Figure 9 A schematic diagram of another algorithm for the 32-bit data error checking and correction method provided in the embodiments of this application.

[0028] Figure 10 for Figure 9 The circuit diagram shown illustrates the calculation formulas for E5-E0 in the 32-bit data error checking and correction method.

[0029] Figure 11 for Figure 10 The diagram shows the package layout of the circuits corresponding to E5-E0 in the 32-bit data error checking and correction method.

[0030] Figure 12 for Figure 9 The circuit diagram shows the calculation formula for E6 in the 32-bit data error checking and correction method.

[0031] Figure 13 for Figure 12 The diagram shows the circuit package of the calculation formula for E6 in the 32-bit data error checking and correction method. Detailed Implementation

[0032] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0033] In certain applications (especially automotive applications), verification techniques / functions (such as ECC) have become essential to further improve reliability. SEC-DED (Single Error Correction-Double Error Detection) has the capability to correct one bit of error or detect two bits of error. Common implementations of SEC-DED include... Figure 1 The Hamming code shown is Figure 2 The Hsiao encoding shown.

[0034] Specifically, Figure 1 This is a schematic diagram of the Hamming code algorithm in related technologies, using 32-bit data (e.g., Figure 1The example shown is D0-D31 + 7 check bits (P0-P6). Here, 32 bits of data are used as the data to be checked. During the SEC-DED check, the data to be checked (32 bits / D0-D31) and the check bits P0-P5 are processed according to... Figure 1 The encoded data positions shown are data positions 1-38 arranged sequentially. Figure 1 The checkmark "V" indicates the coverage of the parity bits (check bits), and based on this parity bit coverage, the seven-bit error correction code E6-E0 is determined as follows:

[0035] E0=P0^D0^D1^D3^D4^D6^D8^D10^D11^D13^D15^D17^D19^D21^D23^D25^D26^D28^D30

[0036] E1=P1^D0^D2^D3^D5^D6^D9^D10^D12^D13^D16^D17^D20^D21^D24^D25^D27^D28^D31

[0037] E2=P2^D1^D2^D3^D7^D9^D9^D10^D14^D15^D16^D17^D22^D23^D24^D25^D29^D30^D31

[0038] E3=P3^D4^D5^D6^D7^D8^D9^D10^D18^D19^D20^D21^D22^D23^D24^D25

[0039] E4=P4^D11^D12^D13^D14^D15^D16^D17^D18^D19^D20^D21^D22^D23^D24^D25

[0040] E5=P5^D26^D27^D28^D29^D30^D31

[0041] E6=P0^P1^P2^P3^P4^P5^P6^D0^D1^D2^D3^D4^D5^D6^D7^D8^D9^D10^D11^D12^D13^ D14^D15^D16^D17^D18^D19^D20^D21^D22^D23^D24^D25^D26^D27^D28^D29^D30^D31

[0042] Here, "^" represents the XOR operation, and each "^" requires an XOR gate. P6 represents another checksum. During encoding, P6~0 are set to all zeros, and the calculated result E6~0 is the corresponding checksum. During decoding, if E6~0 is all zeros, there is no error; if E5~0 is not all zeros and E6 is 1, one error occurs, and the corresponding data to be checked or the check bit is modified according to E5~0; if E5~0 is not all zeros and E6 is 0, two errors occur.

[0043] It should be noted that, Figure 1 The Hamming code algorithm shown requires 90+38 XOR gates and 5 levels of gate delay to be implemented.

[0044] Figure 2 This is a schematic diagram of the Hsiao code algorithm in related technologies, also using 32-bit data (e.g. Figure 1 The example shown is D0-D31 + 7 check bits (P0-P6). Here, 32 bits of data are used as the data to be checked. During the SEC-DED check, the data to be checked (32 bits / D0-D31) and the check bits P0-P6 are processed according to... Figure 1 The encoded data positions shown are data positions 1-39 arranged sequentially. Figure 1 The checkmark "V" indicates the coverage of the parity bits (check bits), and based on this parity bit coverage, the six-bit error correction code E6-E0 is determined as follows:

[0045] E0=P0^D0^D1^D2^D4^D5^D7^D10^D11^D12^D18^D19^D23^D27

[0046] E1=P1^D0^D1^D3^D4^D6^D8^D10^D13^D15^D18^D20^D22^D24^D28

[0047] E2=P2^D0^D2^D3^D5^D6^D9^D11^D14^D16^D19^D20^D25^D29

[0048] E3=P3^D1^D2^D3^D7^D8^D9^D12^D13^D14^D17^D21^D22^D26^D30

[0049] E4=P4^D4^D5^D6^D7^D8^D9^D15^D16^D17^D23^D24^D25^D26^D31

[0050] E5=P5^D10^D11^D12^D13^D14^D15^D16^D17^D27^D28^D29^D30^D31

[0051] E6=P6^D18^D19^D20^D21^D22^D23^D24^D25^D26^D27^D28^D29^D30^D31

[0052] C = E0^E1^E2^E3^E4^E5^E6

[0053] Here, "^" represents the XOR operation, and each "^" requires an XOR gate. During encoding, P6~0 are set to all zeros, and the calculated result E6~0 is the corresponding check code. During decoding, if E6~0 is all zeros and C is also 0, there is no error; if E6~0 is not all zeros and C is 1, one error occurs, and the corresponding data bits or check bits are modified according to E6~0; if E6~0 is not all zeros and E6 is 0, two errors occur. Due to the limitations of Hsiao code's error correction and detection capabilities, this analysis only considers cases with two or fewer errors.

[0054] It should be noted that, Figure 2 The Hsiao code algorithm shown requires 96+6 XOR gates and 4 levels of gate delay to be implemented.

[0055] go through Figure 1 , Figure 2 A comparison shows that, Figure 1 The Hamming code shown has the advantage of simple encoding and decoding, but it has a large area and slow speed; the Hsiao code has the advantages of small area and fast speed, but it has complex encoding and decoding.

[0056] In another related technology, taking 16 bits of data to be checked (D0-D15) + 5 bits of parity (P0-P4) as an example, the values ​​read from all memory cells in the flash memory are inverted before ECC calculation. Since the ECC calculation formula performs an XOR operation on the data bits, when all cell values ​​are 1, the result is all 0s, and the result obtained by the ECC algorithm will inevitably be all 0s. The calculation formulas for error correction codes E0-E4 are as follows:

[0057] E0=~P0^~D0^~D1^~D3^~D4^~D6^~D8^~D10^~D11^~D13^~D15

[0058] E1=~P1^~D0^~D2^~D3^~D5^~D6^~D9^~D10^~D12^~D13

[0059] E2=~P2^~D1^~D2^~D3^~D7^~D8^~D9^~D10^~D14^~D15

[0060] E3=~P3^~D4^~D5^~D6^~D7^~D9^~D9^~D10

[0061] E4=~P4^~D11^~D12^~D13^~D14^~D15

[0062] In this context, “~” indicates negation, and “^” indicates XOR.

[0063] It should be noted that the ECC algorithm in this related technology requires a total of 40 XOR gates and 45 inverters, and is implemented through 5 levels of gate delay.

[0064] Figure 3 This diagram illustrates the ECC verification algorithm in related technologies, using 16 bits of data to be verified (D0-D15) + 5 check bits (P0-P4) as an example. During the ECC verification process, the data to be verified (16 bits / D0-D15) and the check bits P0-P4 are processed according to... Figure 3 The encoded data positions shown are arranged sequentially from 1 to 21. Figure 3 The checkmark "V" indicates the coverage of the parity bits (check bits), and based on this parity bit coverage, the five-bit error correction code E4-E0 is determined as follows:

[0065] E0=~(P0^D0^D1^D3^D4^D6^D8^D10^D11^D13^D15)

[0066] E1=P1^D0^D2^D3^D5^D6^D9^D10^D12^D13

[0067] E2=P2^D1^D2^D3^D7^D8^D9^D10^D14^D15

[0068] E3=P3^D4^D5^D6^D7^D9^D9^D10

[0069] E4=P4^D11^D12^D13^D14^D15

[0070] In this context, “~” indicates negation, and “^” indicates XOR.

[0071] It should be noted that, Figure 3The ECC calculation shown assumes that both the data bits and the parity bits are 1. Each ECC bit that results in a 1 (e.g., E0) is inverted, while bits that result in a 0 (e.g., E1-E4) remain unchanged. In other words, the ECC algorithm in this related technology requires 40 XOR gates and 1 inverter, and undergoes 5 levels of gate delay to be implemented.

[0072] The reason for adding an extra inverter is that when all cells are 1 after erasure, the XOR operation will cause an ECC error.

[0073] In view of the technical problem that the aforementioned verification techniques require a large number of logic devices, resulting in a large area footprint, this embodiment provides a data error checking and correction method. Please refer to [link to relevant documentation]. Figures 4 to 13 ,like Figure 4 As shown, this data error checking and correction method includes the following steps:

[0074] Step S10: Determine the number of check bits and the number of error correction codes corresponding to the data to be checked based on the bit width of the data bits in the data to be checked.

[0075] Step S20: Based on the weighted ascending order of the error correction code arrangement results, determine the mapping relationship between the arrangement results and the check bits and data bits.

[0076] Step S30: Determine the calculation formula for the error correction code based on the encoding position and mapping relationship.

[0077] Step S40: Obtain the verification result of the data to be verified based on the calculation result of the error correction code.

[0078] It is understood that the data error checking and correction method provided in this embodiment first determines the number of check bits and the number of error correction codes corresponding to the data to be checked based on the bit width of the data bits in the data to be checked. Then, it determines the mapping relationship between the arrangement result and the check bits and data bits based on the weighted ascending order of the error correction code arrangement result. Finally, it determines the calculation formula of the error correction code based on the encoding position and the mapping relationship. This not only enables the verification result of the data to be checked to be obtained based on the calculation result of the error correction code, but also simplifies the logical operations in the mapping relationship by determining the mapping relationship between the arrangement result and the check bits and data bits based on the weighted ascending order of the error correction code arrangement result. This reduces the number of logic devices used and thus reduces the occupied area.

[0079] It should be noted that this embodiment can be applied to various data verification applications, such as automotive applications, especially storage products in automotive applications. It can not only improve the reliability of storage products but also reduce their size. Furthermore, the bit width of the data to be verified provided in this application is not specifically limited; it can be applied to data of any bit width. Specifically, the bit width of the data to be verified can be an integer, such as 4 bits, 8 bits, 16 bits, 32 bits, 64 bits, 128 bits, or 256 bits, etc.

[0080] The permutation of error correction codes E3-E0 can be as follows: Figure 6 , Figure 7 The permutations from 0000 to 1111 shown are each composed of binary 0s and / or 1s. The weight coefficients are defined as increasing with the number of 1s in the permutation. Therefore, ascending weight order is a sorting of weight coefficients from low to high. For example, the weight coefficient of 0000 is less than that of 0001, the weight coefficient of 0001 is less than that of 0011, the weight coefficient of 0001 is equal to that of 0010, and so on. The mapping relationship could be, for example, permutation result (E3-E0)0001 corresponding to parity bit P0, or permutation result (E3-E0)0011 corresponding to data bit D0. The encoding positions can be as follows: Figure 8 , Figure 9 The encoded data positions shown are P0, P1, D0, P2, D1, D2, P3, D3-D8, P4, D9-D18, P5, D19 to D31.

[0081] In one embodiment, the step of determining the mapping relationship between the permutation results and the check bits and data bits based on the ascending weight order of the error correction code permutation results includes: obtaining the number of 1s in each permutation result; obtaining the weight coefficient corresponding to each permutation result based on the number of 1s in each permutation result, with a higher weight coefficient for a larger number of 1s in each permutation result; and obtaining the ascending weight order based on the sorting of multiple weight coefficients from low to high.

[0082] It should be noted that each 1 in each permutation corresponds to a logic device to perform the corresponding logic operation. For example, an XOR gate performs a corresponding XOR operation. Therefore, the lower the weight coefficient of the permutation result corresponding to the parity bit and the data bit in the mapping relationship, the fewer 1s there are in the permutation result. This results in fewer logic devices used in the data error checking and correction method, and a smaller area occupied.

[0083] For example, in Figure 6 , Figure 7In this arrangement, the weighting coefficient of the result 0011 is higher than that of the result 0001. The logic device can be, but is not limited to, an XOR gate, or any other suitable device.

[0084] In one embodiment, the step of determining the mapping relationship between the permutation result and the check bit and data bits based on the weighted ascending order of the error correction code permutation result further includes: constructing a one-to-one correspondence between each check bit and a permutation result containing a 1; and constructing a one-to-one correspondence between each data bit and a permutation result containing multiple 1s according to the encoding ascending order, where the encoding ascending order is the permutation result in ascending order.

[0085] It should be noted that in this embodiment, each check bit is further constructed to correspond to an arrangement result with only one 1, while each data bit is corresponded to an arrangement result with a higher weight coefficient. In this way, the total number of 1s in each arrangement result is minimized, the number of logic devices used in the data error checking and correction method is minimized, and the area occupied is minimized.

[0086] In one embodiment, the step of constructing a one-to-one correspondence between each parity bit and a permutation containing a 1 includes: configuring the parity bits, including the least parity bit to the most parity bit. The least parity bit to the most parity bit are configured to correspond one-to-one with a permutation in ascending order of the encoding.

[0087] It should be noted that this embodiment provides a correspondence between each check bit and each arrangement result, but it is not limited to this one correspondence. Other feasible solutions are also possible. For example, configuring the highest check bit to the lowest check bit to correspond one-to-one with an arrangement result in ascending order of encoding is also possible.

[0088] The lowest parity bit can be Figure 5 , Figure 8 as well as Figure 9 In the ECC algorithm, the highest parity bit P0 can be either P5 in the 16-bit data to be checked or P6 in the 32-bit data to be checked.

[0089] In one embodiment, the step of constructing a one-to-one correspondence between each data bit and a permutation containing multiple 1s in ascending encoding order, wherein the ascending encoding order is the order of the permutation from smallest to largest, includes: configuring the data bits, including the lowest data bit to the highest data bit. The lowest data bit to the highest data bit are sequentially mapped one-to-one with a permutation in ascending encoding order.

[0090] It should be noted that this embodiment provides a correspondence between each data bit and each arrangement result, but it is not limited to this one correspondence. Other feasible solutions are also possible. For example, configuring the highest data bit to the lowest data bit to correspond one-to-one with an arrangement result in ascending order of encoding is also possible.

[0091] Among them, Figure 6 , Figure 7 In the code, the permutation results of error correction codes E3-E0 range from 0000 to 1111, which is represented by decimal data from 0 to 15. In other words, the permutation results increase in decimal data representation, which is the above-mentioned encoding ascending order.

[0092] The lowest data bit can be Figure 5 , Figure 8 as well as Figure 9 In D0, the highest data bit can be Figure 5 D15 in the middle can also be Figure 8 as well as Figure 9 D31 in the middle.

[0093] In one embodiment, the step of determining the calculation formula for the error correction code based on the encoding position and mapping relationship includes: configuring the error correction code to include a flag error correction code and multiple non-flag error correction codes. The calculation formula for each non-flag error correction code includes an even number of equal check factors, each check factor being a data bit, a parity bit, or a virtual bit.

[0094] It should be noted that the calculation formula for each non-flag error correction code includes an even number of identical check factors. This not only allows for obtaining the result of each non-flag error correction code when all data bits and check bits are 1 and virtual bits are 0 (if any), which is suitable for verifying the erasure result, but also ensures that the calculation formula for each non-flag error correction code is the same. In other words, the calculation formula for each non-flag error correction code can be implemented using logic circuits with the same topology. This means that only the circuit layout design of one non-flag error correction code needs to be completed, and the circuit layout design of other non-flag error correction codes only requires changing the corresponding input connection lines. This not only simplifies the layout process, but also, since the circuit structure of each non-flag error correction code is the same, the output delay of each non-flag error correction code is also the same. Compared to non-flag error correction codes with different numbers of check factors, which result in longer output delays for non-flag error correction codes with more check factors, leading to excessively long overall output delays for the error correction code, this embodiment, because the output delays of each non-flag error correction code are the same, can shorten the overall output time of the error correction code and improve the verification speed.

[0095] In order to ensure that the calculation formula of each non-flag error correction code includes an even number of the same number of check factors, when the number of data bits and check bits in the calculation formula of the same non-flag error correction code is insufficient to meet the requirements, it can be achieved by adding virtual bits.

[0096] Among them, the flag error correction code can be Figure 8 or Figure 9 The error correction code E6 in the illustrated embodiment can be a non-flag error correction code. Figure 8 or Figure 9 Any one of the error correction codes E5-E0 in the illustrated embodiment.

[0097] In one embodiment, the step of constructing a calculation formula for each non-flag error correction code that includes an even number of identical check factors, each check factor being a data bit, a parity bit, or a dummy bit, includes: configuring different non-flag error correction code calculation formulas to each include one parity bit, an even number of dummy bits, and an odd number of distinct but similarly sized data bits. Based on the intermediate calculation data and calculation results of the calculation formula for each non-flag error correction code, the calculation formula for the flag error correction code is determined.

[0098] It should be noted that the calculation formula of the same non-flag error correction code includes multiple data bits that are different from each other but similar in number. This not only helps to reduce the number of check factors in the calculation formula of each non-flag error correction code, but also helps that the calculation formula of the flag error correction code can be implemented based on the intermediate calculation data and calculation results of the calculation formula of the non-flag error correction code. This can save some logic devices and further reduce the area.

[0099] Furthermore, since the calculation formula for each non-flag error correction code includes an odd number of data bits and one parity bit, this data error checking and correction method is still applicable after the flash memory has completed the erase operation.

[0100] In one embodiment, the step of determining the calculation formula for the error correction code based on the encoding position and mapping relationship further includes: obtaining the encoding ascending order according to the ascending order of the error correction code arrangement results; and determining the encoding positions of the parity bit and data bits based on the encoding ascending order.

[0101] It should be noted that the encoding ascending order is in Figure 6 , Figure 7 The sequence is arranged from 0000 to 1111, where the arrangement result (E3-E0)1111 is greater than the arrangement result (E3-E0)0000.

[0102] In one embodiment, the step of determining the calculation formula for the error correction code based on the encoding position and mapping relationship further includes: configuring the check bits to include a flag check bit and multiple non-flag check bits. Based on the sequential arrangement, encoding position, and mapping relationship of the multiple non-flag check bits, the calculation formula for each non-flag error correction code is determined.

[0103] It should be noted that the check flag can be the checksum P6 in some embodiments, while the non-check flag bits can be... Figure 8 or Figure 9 Any one of the check codes P5-P0 in the illustrated embodiment.

[0104] In one embodiment, the step of determining the calculation formula for each non-flag error correction code based on the sequential arrangement, encoding position, and mapping relationship of multiple non-flag check bits includes: constructing a check factor in the calculation formula of a non-flag error correction code that includes a non-flag check bit; and constructing a check factor in the calculation formula of a flag error correction code that includes a flag check bit.

[0105] It should be noted that the sequential arrangement of multiple non-flag check bits can be... Figure 8 , Figure 9 The P0-P5 are arranged in a vertical column as shown in the figure.

[0106] In one embodiment, the calculation formula for constructing each non-flag error-correcting code includes an even number of identical check factors, each check factor being a data bit, a parity bit, or a virtual bit. The step further includes: constructing the data of each parity bit as 0 during encoding; and constructing the data of each virtual bit as 0.

[0107] It should be noted that the check bit is not always 1. Specifically, during encoding, the check bit is set to all 0s, and the resulting error correction code is the check code corresponding to the input data. The check code and the input data are stored together in the flash memory. During decoding, all data (including the user's input data and the encoded check code) is read from the flash memory and used to calculate the error correction code. The value of the error correction code indicates whether the data has an error, whether it is 1 bit or 2 bits, and automatic error correction is performed for 1 bit errors. This embodiment can perform SEC-DED verification on data to be verified where all data bits are 1.

[0108] The above concept will be explained in detail below with specific examples. Figure 5 This is a schematic diagram of the algorithm for a 16-bit data error checking and correction method. Taking 16-bit data to be checked for ECC verification as an example, it also requires 5 check bits (P0-P4). During the ECC verification process, the data to be checked (16-bit data / D0-D15) and the check bits P0-P4 are processed according to... Figure 5 The encoded data positions shown are arranged sequentially from 1 to 21. Figure 5 The checkmark "V" indicates the coverage of the parity bits (check bits), and based on this parity bit coverage, the five-bit error correction code E4-E0 is determined as follows:

[0109] E0=P0^D0^D1^D3^D4^D6^D9^D14

[0110] E1=P1^D0^D2^D3^D5^D6^D8^D10^D13^D14

[0111] E2=P2^D1^D2^D3^D7^D8^D11^D15

[0112] E3=P3^D4^D5^D6^D7^D8^D12^D13^D14^D15

[0113] E4=P4^D9^D10^D11^D12^D13^D14^D15

[0114] Here, "^" represents the XOR operation, and each "^" requires an XOR gate to implement. The data positions and weight coefficients of each data bit and parity bit are rearranged so that the number of parity factors in the calculation formula of each error correction code is an even number, in order to maximize the efficiency of each XOR gate and thus help reduce the number of XOR gates used.

[0115] It should be noted that, in order to reduce the final area and improve speed, each data bit and check bit is preferentially arranged in a one-to-one correspondence with the arrangement result of the lower weight coefficient in the error correction code.

[0116] Understandably, compared to the aforementioned 16-bit ECC verification, this embodiment requires only 39 XOR gates, which can be achieved through 4 levels of gate delay. This not only reduces the footprint due to the fewer logic devices used, but also increases speed due to the fewer gate delays.

[0117] Figure 6 The diagram illustrates the structure for determining the number of error correction codes. To perform ECC verification on 8-bit data, the length of the check bits needs to be determined. Assuming the length of the data to be verified is k, and the length of the check bits is r, the total length n = k + r. Since the arrangement of E3-E0 as 0000 is used to indicate that there are no errors in the ECC verification, and other arrangements need to correspond to all data bits and check bits, r and k should satisfy the following relationship:

[0118] 2 r -1>=k+r

[0119] Here, r can have multiple values. To reduce unnecessary waste, r is usually chosen as the smallest integer value that satisfies the above relationship. Therefore, when k is 8, r is 4. That is to say, 8 bits of data to be checked require 4 bits of check code, i.e., P<3:0>(P3-P0). Since the number of check codes is equal to the number of error correction codes, correspondingly, 4 bits of error correction code are also needed, i.e., E<3:0>(E3-E0).

[0120] It should be noted that if a 2-bit error detection capability is required, i.e., to implement the SEC-DED function, the length of the check bit needs to be increased by 1 bit.

[0121] To demonstrate the results of ECC verification, the arrangement of E3-E0 as 0000 indicates that no errors have occurred in the data to be verified.

[0122] Then, it is necessary to design the calculation formula for each error correction code: Suppose that when the final calculation result of E3-E0 is 0011, the data bit D0 can be repaired.

[0123] like Figure 7 As shown, when the data in D0 is correct, the Hamming code calculation result E3-E0 is 0000. Therefore, D0 is unrelated to E3 and E2; D0 only affects the values ​​of E1 and E0. When the data in D0 is incorrect (0 becomes 1, or 1 becomes 0), E1 and E0 also change from 0 to 1.

[0124] Similarly, E0 is only related to the data bits D0, D1, D3, D4, D6 and the parity bit P0. Among them, P0 is the parity check result of D0, D1, D3, D4, D6 during encoding; E0 is the parity check result of D0, D1, D3, D4, D6, P0 during decoding.

[0125] Then, the other permutations or calculation results of E3-E0 explain the other results applied to indicate ECC verification. For example... Figure 6 , Figure 7 As shown, the arrangement results of E3-E0, 0001, 0010, 0100, and 1000, are used to indicate the repair check bits P0-P3 respectively. The arrangement results of E3-E0, 0011, 0101, 0110, 0111, and 1001-1100, are used to indicate the repair data bits D0-D7 respectively. Up to this point, there are still 16-1-4-8=3 states in the arrangement results of E3-E0 that do not have a corresponding relationship. That is to say, these 3 unused arrangement results can still indicate the repair information of three more data bits.

[0126] Figure 8 This is a schematic diagram of an algorithm for a 32-bit data error checking and correction method provided in an embodiment of this application, using 32-bit data (such as...) Figure 8The example shown is D0-D31 + 7 check bits (P0-P6). Here, 32 bits of data are used as the data to be checked. During the SEC-DED check, the data to be checked (32 bits / D0-D31) and the check bits P0-P5 are processed according to... Figure 8 The encoded data positions shown are data positions 1-38 arranged sequentially. Figure 8 The checkmark "V" indicates the coverage of the parity bits (check bits), and based on this parity bit coverage, the six-bit error correction code E6-E0 is determined as follows:

[0127] E0=(P0^D0^D1^D3^D4)^D6^D8^D10^D12^D14^D17^D19^D24^D28^Dm

[0128] E1=(P1^D5^D6^D9^D11)^D0^D2^D3^D12^D15^D18^D20^D22^D25^D29

[0129] E2=(P2^D2^D7^D13^Dm)^D1^D3^D8^D9^D14^D15^D21^D22^D26^D30

[0130] E3=(P3^D8^D16^D17^D18)^D4^D5^D6^D7^D9^D23^D24^D25^D26^D31

[0131] E4=(P4^D10^D12^D14^D15)^D11^D13^D16^D17^D18^D27^D28^D29^D30^D31

[0132] E5=(P5^D19^D20^D21^D22)^D23^D24^D25^D26^D27^D28^D29^D30^D31^Dm

[0133] E6 = E5^S0^S1^S2^S3^S4

[0134] Where Dm = 1'b0 (one bit of binary data 0)

[0135] S0=(P0^D0^D1^D3^D4)

[0136] S1=(P1^D5^D6^D9^D11)

[0137] S2=(P2^D2^D7^D13^Dm)

[0138] S3=(P3^D8^D16^D17^D18)

[0139] S4=(P4^D10^D12^D14^D15)

[0140] It should be noted that in this embodiment, as shown in the example... Figure 6 , Figure 7 Based on the shown correspondence, the data positions and weight coefficients of each data bit and check bit have been rearranged, prioritizing the use of error correction codes with lower weights as data bits to maximize the efficiency of each XOR gate, thereby reducing the number of XOR gates used. Preferably, the number of data bits selected in each calculation formula is relatively similar. To ensure that the number of check factors in each error correction code calculation formula is equal, a virtual bit Dm is added, with its data set to 0.

[0141] Meanwhile, in order to reduce the final area and improve speed, each data bit and check bit is preferentially arranged in a one-to-one correspondence with the arrangement result of the lower weight coefficient in the error correction code.

[0142] Understandably, compared to Figure 1 , Figure 2 The 32-bit data to be verified shown is subjected to SEC-DED verification. In this embodiment, a total of 84+5 XOR gates are required, which can be achieved through 4 levels of gate delay. This not only reduces the footprint due to the fewer logic devices used, but also improves the speed due to the fewer gate delays.

[0143] The E6 calculation formula is formed by subtracting the same number of check factors from the E5 to E0 calculation formulas, and the number of check factors in the E5 to E0 calculation formulas is the same.

[0144] Among them, S0, S1, S2, S3 and S4, as part of the above intermediate calculation data, are directly applied to the calculation formula of error correction code E6.

[0145] Figure 9 A schematic diagram of another algorithm for the 32-bit data error checking and correction method provided in the embodiments of this application is shown. Figure 8 The difference lies in the change in the coverage of the parity bits. In other words, the check factor in the calculation formula for each error-correcting code has changed. The specific calculation formula for the determined six-bit error-correcting code E6-E0 is as follows:

[0146] E0=((P0^D0^D1^D3)^D5^D7^D9^D11)^D13^D16^D19^D20^D24^D28^Dm^Dm

[0147] E1=((P1^D4^D10^D11)^D0^D2^D5^D8)^D14^D17^D20^D22^D25^D29^Dm^Dm

[0148] E2=((P2^D2^D6^D12^D13^D14^D18^Dm)^D1^D7^D8^D21^D22^D26^D30^Dm

[0149] E3=((P3^D5^D7^D8)^D3^D4^D6^D15)^D16^D17^D18^D23^D24^D25^D26^D31

[0150] E4=((P4^D15^D16^D17)^D9^D10^D11^D12)^D13^D14^D18^D27^D28^D29^D30^D31

[0151] E5=((P5^D19^D20^D21)^D22^D23^D24^D25)^D26^D27^D28^D29^D30^D31^Dm^Dm

[0152] E6 = P6^E5^S0^S1^Q2^S3^S4

[0153] Where Dm = 1'b0 (one bit of binary data 0)

[0154] S0=(P0^D0^D1^D3), Q0=S0^D5^D7^D9^D11

[0155] S1=(P1^D4^D10^D11), Q1=S1^D0^D2^D5^D8

[0156] S2=(P2^D12^D13^D14), Q2=S2^D13^D14^D18^Dm

[0157] S3=(P3^D5^D7^D8), Q3=S3^D3^D4^D6^D15

[0158] S4=(P4^D15^D16^D17), Q4=S4^D9^D10^D11^D12

[0159] It should be noted that this embodiment is different from... Figure 1 , Figure 2The 32-bit data to be verified shown is subjected to SEC-DED verification. In this embodiment, a total of 90+6 XOR gates are required, which can be achieved through 4 levels of gate delay. This not only reduces the footprint due to the fewer logic devices used, but also improves the speed due to the fewer gate delays.

[0160] S0-S4 and Q0-Q4 are both part of the intermediate calculation data mentioned above and are partially and directly applied to the calculation formula of error correction code E6.

[0161] Specifically, Figure 10 for Figure 9 The circuit diagram shown illustrates the calculation formulas for E5-E0 in the 32-bit data error checking and correction method. The calculation formula for each error correction code in E5-E0 can be adopted as follows: Figure 10 The circuit shown has 16 inputs (IN0-IN15), three outputs (PART1, PART2, OUT) and 15 XOR gates.

[0162] Figure 11 for Figure 10 The diagram shows the package layout of the circuits corresponding to E5-E0 in the 32-bit data error checking and correction method. The calculation formula for error correction code E0 corresponds to the package module CAL0, and the specific construction of this package module CAL0 is shown below. Figure 10 As shown, the input terminals IN0-IN15 are connected to P0, D0, D1, D3, D5, D7, D9, D11, D13, D16, D19, D20, D24, D28, Dm, and Dm respectively, and the output terminals PART1, PART2, and OUT output S0, Q0, and E0 respectively.

[0163] The calculation formula for error correction code E1 corresponds to the encapsulation module CAL1. The specific construction of the encapsulation module CAL1 is as follows: Figure 10 As shown, the input terminals IN0-IN15 are connected to P1, D4, D10, D11, D0, D2, D5, D8, D14, D17, D20, D22, D25, D29, Dm, Dm respectively, and the output terminals PART1, PART2, OUT output S1, Q1, E1 respectively.

[0164] The calculation formula for error correction code E2 corresponds to the encapsulation module CAL2. The specific construction of the encapsulation module CAL2 is as follows: Figure 10 As shown, the input terminals IN0-IN15 are connected to P2, D2, D6, D12, D13, D14, D18, Dm, D1, D7, D8, D21, D22, D26, D30, and Dm respectively, and the output terminals PART1, PART2, and OUT output S2, Q2, and E2 respectively.

[0165] The calculation formula for error correction code E3 corresponds to the encapsulation module CAL3. The specific construction of the encapsulation module CAL3 is as follows: Figure 10 As shown, the input terminals IN0-IN15 are connected to P3, D5, D7, D8, D3, D4, D6, D15, D16, D17, D18, D23, D24, D25, D26, and D31 respectively, and the output terminals PART1, PART2, and OUT output S3, Q3, and E3 respectively.

[0166] The calculation formula for error correction code E4 corresponds to the encapsulation module CAL4, and the specific construction of the encapsulation module CAL4 is as follows: Figure 10 As shown, the input terminals IN0-IN15 are connected to P4, D15, D16, D17, D9, D10, D11, D12, D13, D14, D18, D27, D28, D29, D30, and D31 respectively, and the output terminals PART1, PART2, and OUT output S4, Q4, and E4 respectively.

[0167] The calculation formula for error correction code E5 corresponds to the encapsulation module CAL5. The specific construction of the encapsulation module CAL5 is as follows: Figure 10 As shown, the input terminals IN0-IN15 are connected to P5, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30, D31, Dm, and Dm respectively, and the output terminals PART1, PART2, and OUT output S5, Q5, and E5 respectively.

[0168] Figure 12 for Figure 9 The circuit diagram shown illustrates the calculation formula for E6 in the 32-bit data error checking and correction method. The circuit includes seven input terminals (IN0-IN6), one output terminal (OUT), and six XOR gates.

[0169] Figure 13 for Figure 12 The diagram shows the circuit package of the calculation formula for E6 in the 32-bit data error checking and correction method. The corresponding package module CAL6 for the calculation formula of error correction code E6 is shown below. The specific structure of package module CAL6 is as follows: Figure 12 As shown, the input terminals IN0-IN6 are connected to E5, S0, S1, Q2, S3, S4, and P6 respectively, and the output terminal OUT outputs E6.

[0170] It should be noted that in this embodiment, the verification result of the data to be verified is as follows: During encoding, P6~0 is set to all 0s, and the calculated result E6~0 is the corresponding check code. During decoding, if E6~0 is all 0s, there is no error; if E5~0 is not all 0s and E6 is 1, one error occurs, and the corresponding data bits or check bits are modified according to E5~0; if E5~0 is not all 0s and E6 is 0, two errors occur.

[0171] The advantages of this embodiment are as follows:

[0172] 1) with Figure 1 Compared to the Hamming code shown, this embodiment requires fewer XOR gates, resulting in a smaller area. Figure 1 The Hamming codes shown have varying numbers of XOR gates for each error correction code, and their speed is limited by the longest path. However, in this embodiment, the error correction codes E5-E0 all have the same number of XOR gates. Therefore, compared to the two, this embodiment is faster.

[0173] 2) with Figure 2 Compared to the Hsiao code shown, this embodiment requires fewer XOR gates, resulting in a smaller area. Taking 32-bit data to be verified as an example, the speeds of the two are the same, but since the Hsiao code requires more XOR gates, the algorithm speed of this embodiment will be faster than that of the Hsiao code as the number of bits of data to be verified increases. Moreover, during decoding, the Hsiao code has one more bit, resulting in a larger area.

[0174] 3) In Nor Flash applications, after the erase command or erase operation is executed, all data bits and parity bits are "1". At this time, since the number of parity factors in the calculation formulas of all error correction codes E6-E0 is even, the calculation result is all 0, which means there is no error. If traditional Hamming code or Hsiao code is used, an additional inverter needs to be added to achieve this function.

[0175] 4) In the algorithm of this embodiment, the error correction code E6 is just a flag bit. It is used together with the error correction codes E5 to 0 to determine how many bits of the current data are wrong. It does not affect the final data output, so it does not affect the speed.

[0176] Based on the above analysis, this embodiment provides a data error checking and correction method, which includes: configuring error correction codes including non-flag error correction codes; constructing a calculation formula for each non-flag error correction code that includes an even number of check factors, each check factor being a data bit, a check bit, or a virtual bit.

[0177] It is understood that the data error checking and correction method provided in this embodiment includes an even number of check factors in the calculation formula of each non-flag error correction code. When all data bits in the data to be checked are 1, that is, the erasure is correct, the check result represented by each error correction code is 0, which means that the erasure of the data to be checked is without error. This improves the accuracy of the check result after erasure in Nor Flash.

[0178] Based on the above analysis, this embodiment further provides a data error checking and correction method, which includes: configuring error correction codes including non-flag error correction codes; constructing a calculation formula for each non-flag error correction code that includes the same number of check factors, each check factor being a data bit, a check bit, or a virtual bit.

[0179] It is understandable that the data error checking and correction method provided in this embodiment not only includes an even number of check factors in the calculation formula of each non-flag error correction code, but also ensures that when all data bits in the data to be checked are 1, indicating that the erasure was correct, the check result represented by each error correction code is 0, meaning that the erasure of the data to be checked was error-free. This improves the accuracy of Nor... The accuracy of the verification results after erasure in Flash memory is improved. Furthermore, the calculation formula for each non-flag error correction code can be implemented using logic circuits with the same topology. This means that only one non-flag error correction code circuit layout design needs to be completed; the circuit layout designs for other non-flag error correction codes only require changing the corresponding input connections. This simplifies the layout process. Moreover, since the circuit structures of each non-flag error correction code are identical, their output delays are also identical. In contrast, the calculation formulas for each non-flag error correction code have different numbers of check factors, leading to longer output delays for non-flag error correction codes with more check factors, thus resulting in excessively long overall output delays for the error correction code. In this embodiment, because the output delays of each non-flag error correction code are identical, the overall output time of the error correction code can be shortened, improving the verification speed.

[0180] In one embodiment, this embodiment provides a flash memory that performs the data error checking and correction method described in at least one embodiment above after an erase operation.

[0181] It is understood that the flash memory provided in this embodiment includes an even number of check factors in the calculation formula of each non-flag error correction code. When all data bits in the data to be checked are 1, that is, the erasure is correct, the check result represented by each error correction code is 0, which means that the erasure of the data to be checked is without error. This improves the accuracy of the check result after erasure in Nor Flash.

[0182] Furthermore, the calculation formula for each non-flag error correction code can be implemented using logic circuits with the same topology. This means that only the circuit layout design for one non-flag error correction code needs to be completed, and the circuit layout designs for other non-flag error correction codes can be modified by changing the corresponding input connection lines. This not only simplifies the layout process, but also ensures that the output delay of each non-flag error correction code is the same since the circuit structure of each non-flag error correction code is identical. In contrast, the calculation formulas for each non-flag error correction code have different numbers of check factors, resulting in longer output delays for non-flag error correction codes with more check factors, which in turn leads to excessively long overall output delays for the error correction code. In this embodiment, since the output delays of each non-flag error correction code are identical, the overall output time of the error correction code can be shortened, thus improving the verification speed.

[0183] It is understood that the flash memory provided in this embodiment first determines the number of parity bits and the number of error correction codes corresponding to the data to be verified based on the bit width of the data bits in the data to be verified. Then, it determines the mapping relationship between the arrangement result and the parity bits and data bits based on the weighted ascending order of the error correction code arrangement result. Finally, it determines the calculation formula of the error correction code based on the encoding position and the mapping relationship. This not only enables the verification result of the data to be verified to be obtained based on the calculation result of the error correction code, but also simplifies the logical operations in the mapping relationship by determining the mapping relationship between the arrangement result and the parity bits and data bits based on the weighted ascending order of the error correction code arrangement result. This reduces the number of logic devices used and thus reduces the occupied area.

[0184] It should be noted that the aforementioned flash memory can preferably be Nor Flash. Since Nor Flash is erased as a whole, after erasure, the value in all storage cells is 1. ECC must still work normally under this special condition (that is, when all cell values ​​are 1, the ECC check result is all 0, and the data is considered to be without error).

[0185] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0186] The data error checking and correction method and flash memory provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A method for checking and correcting data errors, characterized in that, The data error checking and correction method includes: Configure error correction codes including non-flag error correction codes; Each non-flag error correction code is constructed with an even number of check factors. The calculation formulas of different non-flag error correction codes each include one check bit, an even number of virtual bits, and an odd number of distinct data bits. Based on the intermediate calculation data and calculation results of the calculation formulas of each non-flag error correction code, the calculation formula of the flag error correction code is determined.

2. The data error checking and correction method according to claim 1, characterized in that, The data error checking and correction method also includes: Based on the bit width of the data bits in the data to be verified, determine the number of the verification bits and the number of the error correction codes corresponding to the data to be verified; Based on the weighted ascending order of the error correction code arrangement, the mapping relationship between the arrangement result and the check bit and the data bit is determined; The calculation formula for the error correction code is determined based on the encoding position and the mapping relationship; The verification result of the data to be verified is obtained based on the calculation result of the error correction code.

3. The data error checking and correction method according to claim 2, characterized in that, The step of determining the mapping relationship between the permutation result and the check bit and the data bits based on the weighted ascending order of the error correction code permutation result includes: Obtain the number of 1s in each of the given permutation results; The weight coefficient corresponding to each arrangement result is obtained based on the number of 1s in each arrangement result. The more 1s there are in each arrangement result, the higher the weight coefficient. The weight ascending order is obtained by sorting the multiple weight coefficients from low to high.

4. The data error checking and correction method according to claim 3, characterized in that, The step of determining the mapping relationship between the permutation result and the check bit and the data bit based on the weighted ascending order of the permutation result of the error correction code further includes: Each of the aforementioned check bits is configured to correspond one-to-one with a permutation containing a 1; Each data bit is constructed to correspond one-to-one with an arrangement result containing multiple 1s in ascending order of encoding, wherein the ascending order of encoding is the arrangement order of the arrangement results from smallest to largest.

5. The data error checking and correction method according to claim 2, characterized in that, The step of determining the calculation formula for the error-correcting code based on the encoding position and the mapping relationship further includes: The encoding ascending order is obtained by arranging the error correction codes from smallest to largest. The encoding positions of the check bit and the data bits are determined according to the encoding ascending order.

6. The data error checking and correction method according to claim 5, characterized in that, The step of determining the calculation formula for the error-correcting code based on the encoding position and the mapping relationship further includes: The configuration of the check bits includes one flag check bit and multiple non-flag check bits; Based on the sequential arrangement of the multiple non-flag check bits, the encoding position, and the mapping relationship, the calculation formula for each of the non-flag error correction codes is determined.

7. The data error checking and correction method according to claim 6, characterized in that, The step of configuring error correction codes, including non-flag error correction codes, includes: The error correction code configuration includes the flag error correction code.

8. The data error checking and correction method according to claim 7, characterized in that, The step of determining the calculation formula for each non-flag error correction code based on the sequential arrangement of the plurality of non-flag check bits, the encoding position, and the mapping relationship includes: The check factor in the formula for constructing the non-flag error-correcting code includes a non-flag check bit; The check factor in the formula for constructing the flag error correction code includes the flag check bit.

9. A method for checking and correcting data errors, characterized in that, The data error checking and correction method includes: Configure error correction codes including non-flag error correction codes; Each non-flag error correction code is constructed with an even number of check factors. The calculation formulas of different non-flag error correction codes each include one check bit, an even number of virtual bits, and an odd number of distinct data bits. Based on the intermediate calculation data and calculation results of the calculation formulas of each non-flag error correction code, the calculation formula of the flag error correction code is determined.

10. The data error checking and correction method according to claim 9, characterized in that, The data error checking and correction method also includes: Based on the bit width of the data bits in the data to be verified, determine the number of the verification bits and the number of the error correction codes corresponding to the data to be verified; Based on the weighted ascending order of the error correction code arrangement, the mapping relationship between the arrangement result and the check bit and the data bit is determined; The calculation formula for the error correction code is determined based on the encoding position and the mapping relationship; The verification result of the data to be verified is obtained based on the calculation result of the error correction code.

11. The data error checking and correction method according to claim 10, characterized in that, The step of determining the mapping relationship between the permutation result and the check bit and the data bits based on the weighted ascending order of the error correction code permutation result includes: Obtain the number of 1s in each of the given permutation results; The weight coefficient corresponding to each arrangement result is obtained based on the number of 1s in each arrangement result. The more 1s there are in each arrangement result, the higher the weight coefficient. The weight ascending order is obtained by sorting the multiple weight coefficients from low to high.

12. The data error checking and correction method according to claim 11, characterized in that, The step of determining the mapping relationship between the permutation result and the check bit and the data bit based on the weighted ascending order of the permutation result of the error correction code further includes: Each of the aforementioned check bits is configured to correspond one-to-one with a permutation containing a 1; Each data bit is constructed to correspond one-to-one with an arrangement result containing multiple 1s in ascending order of encoding, wherein the ascending order of encoding is the arrangement order of the arrangement results from smallest to largest.

13. The data error checking and correction method according to claim 10, characterized in that, The step of determining the calculation formula for the error-correcting code based on the encoding position and the mapping relationship further includes: The encoding ascending order is obtained by arranging the error correction codes from smallest to largest. The encoding positions of the check bit and the data bits are determined according to the encoding ascending order.

14. The data error checking and correction method according to claim 13, characterized in that, The step of determining the calculation formula for the error-correcting code based on the encoding position and the mapping relationship further includes: The configuration of the check bits includes one flag check bit and multiple non-flag check bits; Based on the sequential arrangement of the multiple non-flag check bits, the encoding position, and the mapping relationship, the calculation formula for each of the non-flag error correction codes is determined.

15. The data error checking and correction method according to claim 14, characterized in that, The step of configuring error correction codes, including non-flag error correction codes, includes: The error correction code configuration includes the flag error correction code.

16. The data error checking and correction method according to claim 15, characterized in that, The step of determining the calculation formula for each non-flag error correction code based on the sequential arrangement of the plurality of non-flag check bits, the encoding position, and the mapping relationship includes: The check factor in the formula for constructing the non-flag error-correcting code includes a non-flag check bit; The check factor in the formula for constructing the flag error correction code includes the flag check bit.

17. A flash memory, characterized in that, The flash memory performs the data error checking and correction method as described in any one of claims 1 to 16 after the erase operation.

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