A magnetic tunnel junction based flip flop circuit and electronic device

Abstract

The application discloses a trigger circuit based on a magnetic tunnel junction and electronic equipment, comprising: a main trigger module for sending a trigger signal; a read logic module connected with the main trigger module, the read logic module comprising two logic branches, each logic branch comprising a magnetic tunnel junction and an inverting amplification unit, the magnetic tunnel junction being connected with the inverting amplification unit, the read logic module being used for controlling the working state of the inverting amplification unit according to the discharge state of the magnetic tunnel junction to output a branch voltage corresponding to the logic branch; and a write-in module connected with the read logic module, the write-in module being used for receiving the branch voltage and writing the branch voltage into the magnetic tunnel junction corresponding to the logic branch for storage. In the embodiment of the application, the read-write circuit separation can be realized through the read logic module, the read circuit error rate is reduced, and the storage of non-volatile data is realized.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a trigger circuit and electronic device based on a magnetic tunnel junction. Background Technology

[0002] With the rapid development of science and technology and the microelectronics industry, many experts and scholars generally believe that the research and mass production of non-volatile electronic devices related to magnetism may become the source of the fourth industrial revolution after microelectronics technology. Furthermore, with the advent of the big data era, the traditional von Neumann computing architecture, which separates logic computation and data storage circuits, is no longer suitable for processing massive amounts of data, and the required dynamic power consumption is increasing exponentially. Therefore, power consumption has gradually become one of the main factors limiting the scalability of traditional logic circuits and traditional computing systems. Spin-Torque-Transfer Magnetic Tunnel Junctions (STT-MTJs) have attracted widespread attention and research due to their numerous advantages, such as unlimited write cycles and non-volatility.

[0003] However, when the magnetization directions of the two ferromagnetic layers in a spin-transfer torque magnetic tunnel junction are opposite, spin electrons with a high density of states in one magnetic layer will enter empty states with a low density of states in the other magnetic layer, and vice versa. This results in a low electron tunneling probability, a smaller total tunneling current, and consequently, a higher resistance in the tunnel junction. To address these issues, existing read logic circuits are primarily designed based on pre-charge sensitive amplifiers (Personal Computing System Architecture, PCSA). When the read logic circuit enters the pre-charge phase, the charging node can be charged to the power supply voltage. However, due to the high charging voltage, excessive read current can cause the magnetic tunnel junction devices to flip, leading to an increase in read error rate and power consumption. Summary of the Invention

[0004] The present invention aims to at least solve one of the technical problems existing in the prior art, and provides a trigger circuit and electronic device based on a magnetic tunnel junction, which can realize the separation of read and write circuits through a read logic module, reduce the error rate of read circuits, and realize the storage of non-volatile data.

[0005] In a first aspect, the present invention provides a triggering circuit based on a magnetic tunnel junction, comprising:

[0006] The main trigger module is used to send trigger signals;

[0007] A read logic module is connected to the main trigger module. The read logic module includes two logic branches. Each logic branch includes a magnetic tunnel junction and an inverting amplifier unit. The magnetic tunnel junction is connected to the inverting amplifier unit. The read logic module is used to control the working state of the inverting amplifier unit according to the discharge state of the magnetic tunnel junction, and outputs the branch voltage corresponding to the logic branch according to the trigger signal. The discharge state is used to characterize the discharge rate of the magnetic tunnel junction.

[0008] The write module is connected to the read logic module. The write module is used to receive the branch voltage and write the branch voltage into the magnetic tunnel junction corresponding to the logic branch for storage.

[0009] The aforementioned trigger circuit based on a magnetic tunnel junction has at least the following beneficial effects: A trigger signal is sent by the main trigger module, causing the logic branch in the read logic module to control the operating state of the inverting amplifier unit according to the discharge rate of the magnetic tunnel junction, thereby separating the pre-charge path and the discharge path. The signal is amplified by the inverting amplifier unit, and the branch voltage corresponding to the logic branch is output according to the trigger signal, thereby improving the read margin of the trigger circuit. The branch voltage is then written into the magnetic tunnel junction corresponding to the logic branch for storage by the write module, thus ensuring that the trigger circuit does not lose data when power is off and that the input data is non-volatilely preserved.

[0010] According to some embodiments of the present invention, the read logic module includes a first PMOS transistor, a fourth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a seventh NMOS transistor. The logic branch includes a first logic branch and a second logic branch. The first logic branch includes a first magnetic tunnel junction, and the second logic branch includes a second magnetic tunnel junction. The first logic branch is connected to the first PMOS transistor, and the second logic branch is connected to the fourth PMOS transistor. The inverting amplifier unit includes a first inverter, a second inverter, a second PMOS transistor, a third PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor. The source of the second PMOS transistor is connected to the power supply voltage, and the drain of the second PMOS transistor is connected to the drain of the first NMOS transistor. The gate of the second PMOS transistor is connected to the gate of the first NMOS transistor. The source of the third PMOS transistor is connected to the power supply voltage, and the drain of the third PMOS transistor is connected to the gate of the second NMOS transistor. The source of the fifth PMOS transistor is connected to the power supply voltage, and the drain of the fifth PMOS transistor is connected to the drain of the fifth NMOS transistor. The source of the sixth PMOS transistor is connected to the power supply voltage, and the drain of the sixth PMOS transistor is connected to the drain of the sixth NMOS transistor. The output of the first inverter is connected to the gate of the third NMOS transistor, and the input of the first inverter is connected to the junction of the fifth PMOS transistor and the fifth NMOS transistor. The output of the second inverter is connected to the gate of the fourth NMOS transistor, and the input of the second inverter is connected to the junction of the sixth PMOS transistor and the sixth NMOS transistor.

[0011] According to some embodiments of the present invention, the first logic branch is provided with a first sampling point, and the second logic branch is provided with a second sampling point. The first sampling point is used to output the first branch voltage of the first logic branch, and the second sampling point is used to output the second branch voltage of the second logic branch.

[0012] In some embodiments, a third sampling point is provided at the connection between the fifth PMOS transistor and the fifth NMOS transistor, and a fourth sampling point is provided at the connection between the sixth PMOS transistor and the sixth NMOS transistor.

[0013] According to some embodiments of the present invention, when the pre-input control signal is low, the read logic module turns on the first PMOS transistor and the fourth PMOS transistor according to the control signal, so that the first sampling point and the second sampling point are pre-charged to the power supply voltage, turns off the seventh NMOS transistor, and turns on the fifth PMOS transistor and the sixth PMOS transistor, so that the third sampling point and the fourth sampling point are in a pre-charge state, and turns off the third NMOS transistor and the fourth NMOS transistor to isolate the discharge state;

[0014] or,

[0015] When the pre-input control signal is high, the read logic module cuts off the first PMOS transistor and the fourth PMOS transistor according to the control signal, turns on the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, and the fourth NMOS transistor to put the first sampling point and the second sampling point in a discharge state, and turns on the seventh NMOS transistor to discharge the third sampling point and the fourth sampling point.

[0016] According to some embodiments of the present invention, when the pre-input control signal is low, the read logic module cuts off the fifth NMOS transistor and the sixth NMOS transistor to protect the write module according to the control signal, and turns on the write module so that the write module performs voltage acquisition on the first sampling point and the second sampling point respectively, writes the first branch voltage into the first magnetic tunnel junction, and writes the second branch voltage into the second magnetic tunnel junction to realize the storage of the branch voltage.

[0017] According to some embodiments of the present invention, the source of the first PMOS transistor is connected to the power supply voltage, the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor and the main trigger module, the source of the fourth PMOS transistor is connected to the power supply voltage, the drain of the fourth PMOS transistor is connected to the drain of the second NMOS transistor and the main trigger module, the source of the first NMOS transistor is connected to the drain of the third NMOS transistor, the gate of the third NMOS transistor is connected to the output terminal of the first inverter, the source of the third NMOS transistor is connected to a reference ground, the source of the second NMOS transistor is connected to the drain of the fourth NMOS transistor, the gate of the fourth NMOS transistor is connected to the output terminal of the second inverter, and the source of the fourth NMOS transistor is connected to a reference ground.

[0018] According to some embodiments of the present invention, the source of the fifth PMOS transistor is connected to the power supply voltage, the drain of the fifth PMOS transistor is connected to the drain of the fifth NMOS transistor, the gate of the fifth PMOS transistor is connected to the gate of the sixth PMOS transistor, the source of the sixth PMOS transistor is connected to the power supply voltage, the drain of the sixth PMOS transistor is connected to the drain of the sixth NMOS transistor, the source of the fifth NMOS transistor is connected to the first magnetic tunnel junction, the source of the sixth NMOS transistor is connected to the second magnetic tunnel junction, the drain of the seventh NMOS transistor is connected to both the first and second magnetic tunnel junctions, and the source of the seventh NMOS transistor is connected to a reference ground.

[0019] According to some embodiments of the present invention, the writing module includes a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, and a twelfth PMOS transistor. The source of the seventh PMOS transistor is connected to a power supply voltage, the drain of the seventh PMOS transistor is connected to the first magnetic tunnel junction, and the gate of the seventh PMOS transistor is connected to the drain of the ninth PMOS transistor. The source of the eighth PMOS transistor is connected to a power supply voltage, the drain of the eighth PMOS transistor is connected to the second magnetic tunnel junction, and the gate of the eighth PMOS transistor is connected to the drain of the tenth PMOS transistor. The ninth PMOS transistor's source is connected to the drain of the first PMOS transistor via the first sampling point; the ninth PMOS transistor's gate is connected to the gate of the eleventh PMOS transistor; the eleventh PMOS transistor's source is connected to the drain of the first PMOS transistor via the first sampling point; the tenth PMOS transistor's source is connected to the drain of the fourth PMOS transistor via the second sampling point; the tenth PMOS transistor's gate is connected to the gate of the twelfth PMOS transistor; and the twelfth PMOS transistor's source is connected to the drain of the fourth PMOS transistor via the second sampling point.

[0020] In a second aspect, embodiments of the present invention provide an electronic device including a trigger circuit based on a magnetic tunnel junction as described in the first aspect.

[0021] Other features and advantages of the invention will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the description and the drawings. Attached Figure Description

[0022] The accompanying drawings are provided to further understand the technical solutions of the present invention and constitute a part of the specification. They are used together with the embodiments of the present invention to explain the technical solutions of the present invention, and do not constitute a limitation on the technical solutions of the present invention.

[0023] Figure 1 This is an overall schematic diagram of a trigger circuit based on a magnetic tunnel junction provided in an embodiment of the present invention;

[0024] Figure 2 This is a circuit schematic diagram of a read logic module provided in an embodiment of the present invention;

[0025] Figure 3 This is a circuit schematic diagram of a writing module provided in an embodiment of the present invention;

[0026] Figure 4 This is a schematic diagram of the structure of an electronic device provided in one embodiment of the present invention;

[0027] Figure 5 This is a waveform diagram of a trigger circuit based on a magnetic tunnel junction provided in a specific example of the present invention. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0029] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0030] In the description of this invention, "several" means one or more, "more than" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0031] In the description of this invention, the use of "first" and "second" is for the purpose of distinguishing technical features only, and should not be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated or the order of the technical features indicated.

[0032] In the description of this invention, unless otherwise explicitly defined, terms such as "set up," "install," and "connect" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this invention in conjunction with the specific content of the technical solution.

[0033] The embodiments of the present invention will be further described below with reference to the accompanying drawings.

[0034] refer to Figure 1 , Figure 1 This is an overall schematic diagram of a trigger circuit based on a magnetic tunnel junction provided in an embodiment of the present invention;

[0035] In some embodiments, the triggering circuit based on a magnetic tunnel junction includes: a main triggering module 100 for sending a trigger signal; a read logic module 200 connected to the main triggering module 100, the read logic module 200 including two logic branches, each logic branch including a magnetic tunnel junction and an inverting amplifier unit, the magnetic tunnel junction being connected to the inverting amplifier unit, the read logic module 200 controlling the operating state of the inverting amplifier unit based on the discharge state of the magnetic tunnel junction to output the branch voltage corresponding to the logic branch; and a write module 300 connected to the read logic module 200, the write module 300 receiving the branch voltage and writing the branch voltage into the magnetic tunnel junction corresponding to the logic branch for storage.

[0036] It should be noted that the main trigger module 100 sends a trigger signal so that the logic branch in the read logic module 200 controls the working state of the inverting amplifier unit according to the discharge speed of the magnetic tunnel junction, thereby separating the pre-charge path and the discharge path. The signal is amplified by the inverting amplifier unit, and the branch voltage corresponding to the logic branch is output according to the trigger signal, thereby improving the read margin. Then, the branch voltage is written to the magnetic tunnel junction corresponding to the logic branch by the write module 300 for storage, thereby realizing that the trigger circuit does not lose data when power is off and the input data is non-volatilely saved.

[0037] Understandably, the read logic module is used to control the operating state of the inverting amplifier unit based on the discharge speed of the magnetic tunnel junction. The magnetic tunnel junction has low resistance and discharges quickly, so it can reach the threshold first and start working first.

[0038] It is worth noting that when the main trigger module 100 sends a trigger signal to the read logic module 200, the read logic module 200 can directly output the trigger signal, or write it into the magnetic tunnel junction for storage when the circuit is powered off. Then, when the control signal is input, the stored state is read from the magnetic tunnel junction, thereby realizing the power-off preservation of the trigger circuit.

[0039] In some embodiments, the trigger circuit includes two inverter structures, wherein the trigger circuit includes a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a thirteenth PMOS transistor, a fourteenth PMOS transistor, a fifteenth PMOS transistor, a sixteenth PMOS transistor, a third inverter I3, a fourth inverter I4, a fifth inverter I5, a sixth inverter I6, and a seventh inverter I7. The input terminal vi of the third inverter I3 is connected to the source of the tenth NMOS transistor and the drain of the thirteenth PMOS transistor, and is also connected to the source of the fifteenth PMOS transistor and the drain of the twelfth NMOS transistor. The output terminal vo of the third inverter I3 is connected to the drain of the eleventh NMOS transistor and the fourteenth PMOS transistor. The source terminals of the first inverter I4 and the second inverter I5 are connected. The input terminal vi of the fourth inverter I4 is connected to the input terminal vi of the fifth inverter I5. The output terminal vo of the fourth inverter I4 is connected to the drain of the fifteenth PMOS transistor and the source of the twelfth NMOS transistor. The output terminal vo of the fifth inverter I5 is connected to the drain of the sixteenth PMOS transistor and the source of the thirteenth NMOS transistor. The input terminal vi of the sixth inverter I6 is connected to the source of the sixteenth PMOS transistor and the drain of the thirteenth NMOS transistor, and is also connected to the drain of the third PMOS transistor, the drain of the fourth PMOS transistor, the drain of the second NMOS transistor, the gate of the second PMOS transistor, and the gate of the first NMOS transistor. The output terminal vo of the sixth inverter I6 is connected to the input terminal vi of the seventh inverter I7.

[0040] refer to Figure 2 , Figure 2 This is a circuit schematic diagram of a read logic module 200 provided in an embodiment of the present invention;

[0041] In some embodiments, the read logic module 200 includes a first PMOS transistor, a fourth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a seventh NMOS transistor. Logic branches include a first logic branch 210 and a second logic branch 220. The first logic branch 210 includes a first magnetic tunnel junction MTJ1, and the second logic branch 220 includes a second magnetic tunnel junction MTJ2. The first logic branch 210 is connected to the first PMOS transistor, and the second logic branch 220 is connected to the fourth PMOS transistor. The inverting amplifier unit includes a first inverter I1, a second inverter I2, a second PMOS transistor, a third PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor. The source of the second PMOS transistor is connected to the power supply voltage, and the drain of the second PMOS transistor is connected to the drain of the first NMOS transistor. The gate of the OS transistor is connected to the gate of the first NMOS transistor. The source of the third PMOS transistor is connected to the power supply voltage. The drain of the third PMOS transistor is connected to the gate of the second NMOS transistor. The source of the fifth PMOS transistor is connected to the power supply voltage. The drain of the fifth PMOS transistor is connected to the drain of the fifth NMOS transistor. The source of the sixth PMOS transistor is connected to the power supply voltage. The drain of the sixth PMOS transistor is connected to the drain of the sixth NMOS transistor. The output terminal vo of the first inverter I1 is connected to the gate of the third NMOS transistor. The input terminal vi of the first inverter I1 is connected to the junction of the fifth PMOS transistor and the fifth NMOS transistor. The output terminal vo of the second inverter I2 is connected to the gate of the fourth NMOS transistor. The input terminal vi of the second inverter I2 is connected to the junction of the sixth PMOS transistor and the sixth NMOS transistor. This achieves the separation of the two ends of the read logic module 200, separating the pre-charge path and the discharge path of the trigger circuit.

[0042] It should be noted that existing read logic circuits are basically designed based on pre-charge sensitive amplifiers. PCSA-based read logic circuits include two stages: a pre-charge stage and a discharge stage, controlled by control signals. When the read logic circuit enters the pre-charge stage, the charging node can be charged to the power supply voltage. Due to the high charging voltage, excessive read current can cause the magnetic tunnel junction device to flip, leading to an increased read error rate and higher power consumption. Therefore, this embodiment uses an improved two-terminal split read logic module 200, dividing the first magnetic tunnel junction MTJ1 and the second magnetic tunnel junction MTJ2 into a fixed terminal T1 connecting to the fixed layer of the magnetic tunnel junction, and a free terminal T2 connecting to the free layer of the magnetic tunnel junction. The switching between parallel and antiparallel states is achieved by injecting current into the magnetic tunnel junction. The transition depends on the direction, magnitude, and duration of the applied current. When the applied current exceeds the critical switching current or the time is sufficiently long, the magnetic tunnel junction state may switch, exhibiting a high-low resistance state.

[0043] Understandably, injecting current into a magnetic tunnel junction typically requires injecting a current higher than the critical switching current.

[0044] In some embodiments, the source of the first PMOS transistor is connected to the power supply voltage, the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor, the drain of the second PMOS transistor, and the drain of the eighth PMOS transistor, respectively; the source of the fourth PMOS transistor is connected to the power supply voltage, and the drain of the fourth PMOS transistor is connected to the drain of the second NMOS transistor; the source of the third NMOS transistor is connected to the reference ground, the drain of the third NMOS transistor is connected to the source of the first NMOS transistor, the source of the fourth NMOS transistor is connected to the reference ground, the drain of the fourth NMOS transistor is connected to the source of the second NMOS transistor, the source of the seventh NMOS transistor is connected to the reference ground, the gate of the seventh NMOS transistor is connected to the control signal, and the drain of the seventh NMOS transistor is connected to the fixing layer of the first magnetic tunnel junction MTJ1 and the fixing layer of the second magnetic tunnel junction MTJ2, respectively.

[0045] It should be noted that the inverting amplifier unit is used to amplify the small signal in the trigger circuit, thereby realizing the control of the circuit.

[0046] In some embodiments, the first logic branch 210 is provided with a first sampling point out, and the second logic branch 220 is provided with a second sampling point out-. The first sampling point out is used to output the first branch voltage of the first logic branch 210, and the second sampling point out- is used to output the second branch voltage of the second logic branch 220, thereby facilitating the subsequent input of the first branch voltage and the second branch voltage into the magnetic tunnel junction for storage, and realizing non-volatile storage.

[0047] It should be noted that the first sampling point out is connected to the source of the ninth PMOS transistor and the source of the eleventh PMOS transistor of the writing module 300, respectively, and the second sampling point out- is connected to the source of the tenth PMOS transistor and the source of the twelfth PMOS transistor of the writing module 300, respectively.

[0048] In some embodiments, a third sampling point is provided at the connection between the fifth PMOS transistor and the fifth NMOS transistor, and a fourth sampling point is provided at the connection between the sixth PMOS transistor and the sixth NMOS transistor.

[0049] In some embodiments, when the pre-input control signal se is low, the read logic module 200 enters the pre-charging stage. The read logic module 200 turns on the first PMOS transistor and the fourth PMOS transistor according to the control signal se, so that the first sampling point out and the second sampling point out- are pre-charged to the power supply voltage, turns off the seventh NMOS transistor, and turns on the fifth PMOS transistor and the sixth PMOS transistor, so that the third sampling point and the fourth sampling point are connected to the power supply voltage to be in the pre-charging state. At this time, the input terminals vi of the first inverter I1 and the second inverter I2 are high, and the output terminals vo of the first inverter I1 and the second inverter I2 are low. The third NMOS transistor and the fourth NMOS transistor are turned off to be in the isolated discharge state, so that the write module is not disturbed. The pre-charging circuit and the discharge circuit can be separated to avoid mutual interference, thereby effectively reducing the read error rate and effectively reducing the power consumption of the trigger circuit.

[0050] In some embodiments, when the pre-input control signal se is high, the read logic circuit performs a discharge phase. The read logic module 200 cuts off the first PMOS transistor and the fourth PMOS transistor according to the control signal se, and turns on the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, and the fourth NMOS transistor to make the first sampling point out and the second sampling point out- in a discharge state, and discharges. It also turns on the seventh NMOS transistor to make the third sampling point and the fourth sampling point discharge. The circuit sets the first magnetic tunnel junction MTJ1 and the second magnetic tunnel junction MTJ2 to opposite directions, so that one end of the first magnetic tunnel junction MTJ1 and the second magnetic tunnel junction MTJ2 discharges fast and the other end discharges slowly. The end that discharges fast first turns on the inverter and performs a new round of charging, so that one end of the inverter outputs a high level, and the other end outputs a low level because it is constantly discharging, thus realizing the separation of the pre-charging circuit and the discharge circuit.

[0051] In some embodiments, when the pre-input control signal se is low, the read logic module 200 cuts off the fifth and sixth NMOS transistors according to the control signal se to protect the write module 300, so that the write module 300 is not disturbed, and turns on the ninth, tenth, eleventh and twelfth PMOS transistors in the write module 300, so that the write module 300 collects voltages at the first sampling point out and the second sampling point out- respectively, and controls the working state of the write module 300 by the voltages of the first sampling point out and the second sampling point out-, writing the first branch voltage into the first magnetic tunnel junction MTJ1 and the second branch voltage into the second magnetic tunnel junction MTJ2 to realize the storage of the branch voltage, thereby realizing the non-volatile storage of the trigger circuit.

[0052] In some embodiments, the source of the first PMOS transistor is connected to the power supply voltage, the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor and the main trigger module 100, the source of the fourth PMOS transistor is connected to the power supply voltage, the drain of the fourth PMOS transistor is connected to the drain of the second NMOS transistor and the main trigger module 100, the source of the first NMOS transistor is connected to the drain of the third NMOS transistor, the gate of the third NMOS transistor is connected to the output terminal vo of the first inverter I1, the source of the third NMOS transistor is connected to the reference ground, the source of the second NMOS transistor is connected to the drain of the fourth NMOS transistor, the gate of the fourth NMOS transistor is connected to the output terminal vo of the second inverter I2, and the source of the fourth NMOS transistor is connected to the reference ground.

[0053] It should be noted that, since the lower half of the original dual-ended read logic circuit only has a PMOS transistor connected to the magnetic tunnel junction, when the write circuit is active, it will be affected by the current on the PMOS transistor, causing the magnetic tunnel junction to flip incorrectly, thus increasing the error rate. This embodiment adds two symmetrical NMOS transistors, namely the third NMOS transistor and the fourth NMOS transistor, to the original design. This ensures that this part is not turned on when the write circuit is active, thus preventing interference and effectively reducing the error rate.

[0054] In some embodiments, the source of the fifth PMOS transistor is connected to the power supply voltage, the drain of the fifth PMOS transistor is connected to the drain of the fifth NMOS transistor, the gate of the fifth PMOS transistor is connected to the gate of the sixth PMOS transistor, the source of the sixth PMOS transistor is connected to the power supply voltage, the drain of the sixth PMOS transistor is connected to the drain of the sixth NMOS transistor, the source of the fifth NMOS transistor is connected to the first magnetic tunnel junction MTJ1, the source of the sixth NMOS transistor is connected to the second magnetic tunnel junction MTJ2, the drain of the seventh NMOS transistor is connected to the first magnetic tunnel junction MTJ1 and the second magnetic tunnel junction MTJ2 respectively, and the source of the seventh NMOS transistor is connected to the reference ground, thereby realizing the power-off retention of the trigger circuit.

[0055] refer to Figure 3 , Figure 3 This is a circuit schematic diagram of a writing module provided in an embodiment of the present invention;

[0056] In some embodiments, the write module 300 includes a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, and a twelfth PMOS transistor. The source of the seventh PMOS transistor is connected to the power supply voltage, the drain of the seventh PMOS transistor is connected to a first magnetic tunnel junction, and the gate of the seventh PMOS transistor is connected to the drain of the ninth PMOS transistor. The source of the eighth PMOS transistor is connected to the power supply voltage, the drain of the eighth PMOS transistor is connected to a second magnetic tunnel junction, and the gate of the eighth PMOS transistor is connected to the drain of the tenth PMOS transistor. The source of the ninth PMOS transistor is connected to a first magnetic tunnel junction. The sampling point out is connected to the drain of the first PMOS transistor, the gate of the ninth PMOS transistor is connected to the gate of the eleventh PMOS transistor, the source of the eleventh PMOS transistor is connected to the drain of the first PMOS transistor through the first sampling point out, the source of the tenth PMOS transistor is connected to the drain of the fourth PMOS transistor through the second sampling point out-, the gate of the tenth PMOS transistor is connected to the gate of the twelfth PMOS transistor, and the source of the twelfth PMOS transistor is connected to the drain of the fourth PMOS transistor through the second sampling point out-. This allows for read / write separation of the trigger circuit while ensuring read margin.

[0057] It should be noted that the write module 300 also includes an eighth NMOS transistor and a ninth NMOS transistor. The source of the eighth NMOS transistor is connected to the reference ground, the gate of the eighth NMOS transistor is connected to the drain of the eleventh PMOS transistor, the drain of the eighth NMOS transistor is connected to the drain of the seventh PMOS transistor, the source of the ninth NMOS transistor is connected to the reference ground, the drain of the ninth NMOS transistor is connected to the drain of the eighth PMOS transistor, and the gate of the ninth NMOS transistor is connected to the drain of the twelfth PMOS transistor.

[0058] Understandably, reference Figure 3 In the write module 300, labels a and b are connected to leads a and b above the magnetic tunnel junction in the read logic module 200, respectively.

[0059] refer to Figure 4 , Figure 4 This is a schematic diagram of the structure of an electronic device provided in one embodiment of the present invention;

[0060] Furthermore, another embodiment of the present invention provides an electronic device including a trigger circuit based on a magnetic tunnel junction as described in any of the above embodiments. Therefore, this electronic device possesses the beneficial effects of the trigger circuit based on a magnetic tunnel junction as described in any of the above embodiments.

[0061] It is understood that the electronic device in this embodiment may be a semiconductor device including a trigger circuit based on a magnetic tunnel junction, a white goods appliance including a trigger circuit based on a magnetic tunnel junction, a financial machine including a trigger circuit based on a magnetic tunnel junction, or an automobile including a trigger circuit based on a magnetic tunnel junction, etc. This embodiment does not impose specific limitations.

[0062] To more clearly illustrate the execution process of the trigger circuit based on the magnetic tunnel junction, a specific example is provided below.

[0063] Example 1:

[0064] Figure 5 This is a waveform diagram of a trigger circuit based on a magnetic tunnel junction provided in a specific example of the present invention;

[0065] In some embodiments, the triggering circuit based on the magnetic tunnel junction is a non-volatile master-slave flip-flop, which can be divided into three parts: a master triggering module 100, a read logic module 200, and a write module 300. The master triggering module 100 retains the two inverter structure of a traditional flip-flop. The read logic circuit includes a read circuit and a slave flip-flop. The read circuit and slave flip-flop adopt an improved double-ended separated pre-charge read circuit structure. This structure can implement the slave flip-flop function while also saving relevant stored information to the magnetic tunnel junction, thus achieving the characteristic of not losing data even when power is off. In read mode, the information stored in the magnetic tunnel junction is restored to the latch. Figure 5 The diagram shows the simulation results of the trigger circuit based on the magnetic tunnel junction. It was found that although there is a delay between the output and the input of the trigger, the basic waveform can be guaranteed to be undistorted. The improved two-end separation structure can achieve read-write separation while ensuring read margin, and the relevant input data can be non-volatilely saved through the write circuit.

[0066] It should be understood that in this application, the terms “comprising” and “having”, and any variations thereof, are intended to cover non-exclusive inclusion, for example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units that are explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to such process, method, product, or device.

[0067] Furthermore, "at least one item" refers to one or more items, while "more than one" refers to two or more items. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0068] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0069] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

[0070] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

[0071] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present invention.

Claims

1. A trigger circuit based on a magnetic tunnel junction, characterized in that, include: The main trigger module is used to send trigger signals; A read logic module is connected to the main trigger module. The read logic module includes two logic branches. Each logic branch includes a magnetic tunnel junction and an inverting amplifier unit. The magnetic tunnel junction is connected to the inverting amplifier unit. The read logic module is used to control the working state of the inverting amplifier unit according to the discharge state of the magnetic tunnel junction, and outputs the branch voltage corresponding to the logic branch according to the trigger signal. The discharge state is used to characterize the discharge rate of the magnetic tunnel junction. A write module is connected to the read logic module. The write module is used to receive the branch voltage and write the branch voltage into the magnetic tunnel junction corresponding to the logic branch for storage. The read logic module includes a first PMOS transistor, a fourth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a seventh NMOS transistor. The logic branch includes a first logic branch and a second logic branch. The first logic branch includes a first magnetic tunnel junction, and the second logic branch includes a second magnetic tunnel junction. The first logic branch is connected to the first PMOS transistor, and the second logic branch is connected to the fourth PMOS transistor. The inverting amplifier unit includes a first inverter, a second inverter, a second PMOS transistor, a third PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor. The source of the second PMOS transistor is connected to the power supply voltage, and the drain of the second PMOS transistor is connected to the drain of the first NMOS transistor. The gate of the PMOS transistor is connected to the gate of the first NMOS transistor. The source of the third PMOS transistor is connected to the power supply voltage. The drain of the third PMOS transistor is connected to the gate of the second NMOS transistor. The source of the fifth PMOS transistor is connected to the power supply voltage. The drain of the fifth PMOS transistor is connected to the drain of the fifth NMOS transistor. The source of the sixth PMOS transistor is connected to the power supply voltage. The drain of the sixth PMOS transistor is connected to the drain of the sixth NMOS transistor. The output of the first inverter is connected to the gate of the third NMOS transistor. The input of the first inverter is connected to the junction of the fifth PMOS transistor and the fifth NMOS transistor. The output of the second inverter is connected to the gate of the fourth NMOS transistor. The input of the second inverter is connected to the junction of the sixth PMOS transistor and the sixth NMOS transistor.

2. The trigger circuit based on a magnetic tunnel junction according to claim 1, characterized in that, The first logic branch is provided with a first sampling point, and the second logic branch is provided with a second sampling point. The first sampling point is used to output the first branch voltage of the first logic branch, and the second sampling point is used to output the second branch voltage of the second logic branch.

3. The trigger circuit based on a magnetic tunnel junction according to claim 2, characterized in that, A third sampling point is provided at the connection between the fifth PMOS transistor and the fifth NMOS transistor, and a fourth sampling point is provided at the connection between the sixth PMOS transistor and the sixth NMOS transistor.

4. The trigger circuit based on a magnetic tunnel junction according to claim 3, characterized in that, When the pre-input control signal is low, the read logic module turns on the first PMOS transistor and the fourth PMOS transistor according to the control signal, so that the first sampling point and the second sampling point are pre-charged to the power supply voltage, turns off the seventh NMOS transistor, and turns on the fifth PMOS transistor and the sixth PMOS transistor, so that the third sampling point and the fourth sampling point are in a pre-charge state, and turns off the third NMOS transistor and the fourth NMOS transistor to isolate the discharge state. or, When the pre-input control signal is high, the read logic module cuts off the first PMOS transistor and the fourth PMOS transistor according to the control signal, turns on the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, and the fourth NMOS transistor to put the first sampling point and the second sampling point in a discharge state, and turns on the seventh NMOS transistor to discharge the third sampling point and the fourth sampling point.

5. The trigger circuit based on a magnetic tunnel junction according to claim 2, characterized in that, When the pre-input control signal is low, the read logic module cuts off the fifth NMOS transistor and the sixth NMOS transistor to protect the write module according to the control signal, and turns on the write module so that the write module can collect voltages at the first sampling point and the second sampling point respectively, write the first branch voltage into the first magnetic tunnel junction, and write the second branch voltage into the second magnetic tunnel junction to realize the storage of the branch voltage.

6. The triggering circuit based on a magnetic tunnel junction according to claim 1, characterized in that, The source of the first PMOS transistor is connected to the power supply voltage, and the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor and the main trigger module. The source of the fourth PMOS transistor is connected to the power supply voltage, and the drain of the fourth PMOS transistor is connected to the drain of the second NMOS transistor and the main trigger module. The source of the first NMOS transistor is connected to the drain of the third NMOS transistor, and the gate of the third NMOS transistor is connected to the output terminal of the first inverter. The source of the third NMOS transistor is connected to a reference ground. The source of the second NMOS transistor is connected to the drain of the fourth NMOS transistor, and the gate of the fourth NMOS transistor is connected to the output terminal of the second inverter. The source of the fourth NMOS transistor is connected to a reference ground.

7. The trigger circuit based on a magnetic tunnel junction according to claim 1, characterized in that, The source of the fifth PMOS transistor is connected to the power supply voltage, the drain of the fifth PMOS transistor is connected to the drain of the fifth NMOS transistor, the gate of the fifth PMOS transistor is connected to the gate of the sixth PMOS transistor, the source of the sixth PMOS transistor is connected to the power supply voltage, the drain of the sixth PMOS transistor is connected to the drain of the sixth NMOS transistor, the source of the fifth NMOS transistor is connected to the first magnetic tunnel junction, the source of the sixth NMOS transistor is connected to the second magnetic tunnel junction, the drain of the seventh NMOS transistor is connected to both the first and second magnetic tunnel junctions, and the source of the seventh NMOS transistor is connected to a reference ground.

8. The trigger circuit based on a magnetic tunnel junction according to claim 2, characterized in that, The writing module includes a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, and a twelfth PMOS transistor. The source of the seventh PMOS transistor is connected to the power supply voltage, the drain of the seventh PMOS transistor is connected to the first magnetic tunnel junction, and the gate of the seventh PMOS transistor is connected to the drain of the ninth PMOS transistor. The source of the eighth PMOS transistor is connected to the power supply voltage, the drain of the eighth PMOS transistor is connected to the second magnetic tunnel junction, and the gate of the eighth PMOS transistor is connected to the drain of the tenth PMOS transistor. The source of the ninth PMOS transistor is connected to the drain of the first PMOS transistor through the first sampling point. The gate of the ninth PMOS transistor is connected to the gate of the eleventh PMOS transistor. The source of the eleventh PMOS transistor is connected to the drain of the first PMOS transistor through the first sampling point. The source of the tenth PMOS transistor is connected to the drain of the fourth PMOS transistor through the second sampling point. The gate of the tenth PMOS transistor is connected to the gate of the twelfth PMOS transistor. The source of the twelfth PMOS transistor is connected to the drain of the fourth PMOS transistor through the second sampling point.

9. An electronic device, characterized in that, It includes a trigger circuit based on a magnetic tunnel junction as described in any one of claims 1-8.

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