On-die termination configurations for memory devices

Abstract

This application is directed to an on-die termination (ODT) configuration for a memory device. In some examples, a memory device can determine, from a set of connection options, a connection option for which to configure ODT pins of the memory device. Each connection option can correspond to a termination configuration for different pins, such as command and address (CA) pins, clock (CK) pins, or chip select (CS) pins. Based on the determined connection option, the memory device can identify a respective termination option for each of the different pins, such as a first termination option for the CA pins, a second termination option for the CK pins, and a third termination option for the CS pins, and configure each of the different pins according to the respective termination option for the pin.

Description

[0001] Cross-reference

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 494,701, filed October 5, 2021, entitled “On-Die Termination Configuration for a Memory Device,” which is assigned to the assignee and is expressly incorporated herein by reference. Technical Field

[0003] The technical field relates to on-die termination (ODT) configurations for memory devices. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, user devices, wireless communication devices, cameras, digital displays, etc. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to one of two supported states, often indicated by logic 1 or logic 0. In some instances, a single memory cell can support more than two states, any one of which can be stored. To access the stored information, a component can read or sense at least one stored state in the memory device. To store information, a component can write states into the memory device or program states.

[0005] Various types of memory devices and memory cells exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), auto-select memory, and chalcogenide memory technology. Memory cells can be volatile or non-volatile. For example, non-volatile FeRAM can maintain its stored logic state for a long time even without an external power supply. Volatile DRAM devices, on the other hand, may lose their stored state when disconnected from an external power source. Summary of the Invention

[0006] A method is described. The method may include: determining, from a set of candidate connection options comprising three or more candidate connection options, a connection option for configuring an on-die termination (ODT) pin of a memory device, wherein each candidate connection option in the set of candidate connection options corresponds to a corresponding termination configuration for one or more additional pins of the memory device; identifying a corresponding termination option for each of the one or more additional pins of the memory device based on the corresponding termination configuration of the connection option for configuring the ODT pin; and configuring each of the one or more additional pins of the memory device according to the corresponding termination option for the additional pin.

[0007] An apparatus is described. The apparatus may include a memory device, and the memory device may include an ODT pin and a controller, the controller being configured to cause the apparatus to: detect the state of the ODT pin, wherein the state is one of a set of potential states comprising three or more potential states; identify a termination configuration from a set of termination configurations based on the detected state of the ODT pin, the termination configuration corresponding to a corresponding termination option for each of one or more additional pins of the memory device; and configure each of one or more additional pins according to the corresponding termination option for the additional pins corresponding to the identified termination configuration.

[0008] An apparatus is described. The apparatus may include a set of memory devices, and each memory device in the set of memory devices may include a corresponding ODT pin and a corresponding set of one or more additional pins. Furthermore, the apparatus may include: one or more signal lines, each including a corresponding signal line for each of the sets of one or more additional pins, wherein the corresponding signal line for the additional pins in the set of one or more additional pins is coupled to an additional pin of each memory device in the set of memory devices, and each memory device in the set of memory devices may include a corresponding controller configured to cause the memory device to: detect the state of a corresponding ODT pin of the memory device, wherein the state is one of a set of potential states comprising three or more potential states, and identify a termination configuration for each additional pin in the corresponding set of one or more additional pins of the memory device based on the detected state of the ODT pin of the memory device. Attached Figure Description

[0009] Figure 1 This describes an example of a system that supports die-on termination (ODT) configuration for memory devices, based on examples disclosed herein.

[0010] Figure 2 and 3 This describes an example of a component diagram supporting ODT configuration for a memory device, based on examples disclosed herein.

[0011] Figure 4 A block diagram showing a memory device that supports ODT configuration for the memory device, based on examples disclosed herein.

[0012] Figure 5 and 6 The flowchart illustrates one or more methods for supporting ODT configuration of memory devices, based on examples disclosed herein. Detailed Implementation

[0013] In some instances, a memory device may comprise a set of pins. A pin can be described as a conductive input or output point of the device. Each pin may be coupled to a signal line. A host device may use the signal line to communicate with the memory device. In some instances, as a signal travels along a signal line from the host device to the memory device, the signal may be reflected back in the opposite direction. Signal reflection may be a result of discontinuous impedance along the signal line and can adversely affect the signal by altering its characteristics (e.g., changing the signal's phase, amplitude, frequency, etc.). To mitigate the effects of signal reflection, the memory device may implement resistive termination techniques. Some memory devices can be selected from two different termination configurations upon power-up. For example, such memory devices may be selected from a first termination configuration or a second termination configuration. Each termination configuration may specify whether a particular pin of the memory device can be resistively terminated using on-die termination (ODT), which may refer to resistive termination within the memory device (e.g., on the same die as the memory array within the memory device).

[0014] Memory devices can select termination configurations based on the state of their ODT pins. For example, if the memory device senses that an ODT pin is biased to a high voltage, it can select a first termination configuration, and if it senses that an ODT pin is biased to a low voltage, it can select a second termination configuration. However, in some cases, having more than two termination configurations when the memory device is powered on can be beneficial. More termination configurations allow the memory system greater flexibility in terminating its pins. In some instances, after the memory device is powered on, it can update or change two termination configurations that provide some flexibility. However, the signaling involved in changing or updating two termination configurations can introduce latency during system initialization.

[0015] As described herein, after powering on the memory device, the memory device can select a termination configuration from three or more termination configurations for one or more pins. For example, the memory device can select from a first termination configuration, a second termination configuration, or a third termination configuration. The memory device can select a termination configuration based on the state of the ODT pin of the memory device. The ODT pin can be biased to a first voltage, biased to a second voltage, biased to a third voltage, or electrically floated. If the ODT pin is biased to the first voltage, the memory device can select the first termination configuration. If the ODT pin is biased to the second voltage, the memory device can select the second termination configuration. If the ODT pin is biased to the third voltage or electrically floated, the memory device can select the third termination configuration. In some cases, all four states of the ODT pin can be supported together with a fourth termination configuration (e.g., the ODT pin being biased to the third voltage or electrically floated can correspond to the third and fourth possible states of the ODT pin, respectively). By having more than two termination configurations, memory devices can have more flexibility in terms of pin termination (including when powered on) compared to having only two termination configurations.

[0016] Originally in reference Figure 1 The features of this disclosure are described in the context of the system described. (See references...) Figure 2 and 3 The features of this disclosure are described in the context of the component diagrams described herein. This is achieved through references to, for example... Figure 4-6 The device diagrams and flowcharts describing the ODT configuration for the memory device further illustrate, and these and other features of this disclosure are further described with reference to the device diagrams and flowcharts. In some cases, the termination configurations described herein for a given type of pin can be applied to multiple pins of the same type, wherein the memory device comprises multiple pins of the same type. For example, termination configurations for command and address (CA) pins of a memory device can be used for multiple CA pins (e.g., one or more CA buses) contained in the memory device.

[0017] Figure 1 This describes an example of a system 100 that supports ODT configuration for a memory device, based on examples disclosed herein. System 100 may include a host device 105, a memory module 110, and multiple channels 115 coupling the host device 105 to the memory module 110. System 100 may include one or more memory modules 110, but aspects of the one or more memory modules 110 may be described in the context of a single memory device (e.g., memory module 110).

[0018] System 100 may include portions of electronic devices, such as computing devices, mobile computing devices, wireless devices, graphics processing devices, vehicles, or other systems. For example, system 100 may describe aspects of computers, laptop computers, tablet computers, smartphones, cellular phones, wearable devices, internet-connected devices, vehicle controllers, etc. Memory module 110 may be a component of the system operable to store data for use by one or more other components of system 100.

[0019] At least a portion of system 100 may be an instance of host device 105. Host device 105 may be an instance of a processor or other circuitry within a device that uses memory to perform processes within, for example, a computing device, mobile computing device, wireless device, graphics processing device, computer, laptop computer, tablet computer, smartphone, cellular phone, wearable device, internet-connected device, vehicle controller, system-on-a-chip (SoC), or other fixed or portable electronic device, and other examples. In some instances, host device 105 may refer to hardware, firmware, software, or a combination thereof that implements the functions of external memory controller 120. In some instances, external memory controller 120 may be referred to as a host or host device 105.

[0020] Memory module 110 may be a separate device or component operable to provide physical memory address / space available for use or reference by system 100. In some instances, memory module 110 may be configurable to work with one or more different types of host devices. Signaling between host device 105 and memory module 110 may be operable to support one or more of the following: modulation schemes for modulating signals, various pin configurations for conveying signals, various form factors for the physical packages of host device 105 and memory module 110, clock signaling and synchronization between host device 105 and memory module 110, timing conventions, or other factors.

[0021] Memory module 110 may be operable to store data for components of host device 105. In some instances, memory module 110 may act as a secondary or subordinate device to host device 105 (e.g., responding to and executing commands provided by host device 105 via external memory controller 120). Such commands may include one or more of the following: write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands.

[0022] The host device 105 may include an external memory controller 120, a processor 125, a basic input / output system (BIOS) component 130, or one or more other components such as one or more peripheral components or one or more input / output controllers. The components of the host device 105 may be coupled to each other using bus 135.

[0023] Processor 125 may be operable to provide control or other functionality to at least a portion of system 100 or at least a portion of host device 105. Processor 125 may be a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or combinations thereof. In such instances, processor 125 may be an instance of a central processing unit (CPU), graphics processing unit (GPU), general-purpose GPU (GPGPU), or SoC, and other instances. In some instances, external memory controller 120 may be implemented by processor 125 or be part of said processor.

[0024] BIOS component 130 may be a software component containing a BIOS operating as firmware, which can initialize and run various hardware components of system 100 or host device 105. BIOS component 130 may also manage data flow between processor 125 and various components of system 100 or host device 105. BIOS component 130 may contain programs or software stored in one or more read-only memory (ROM), flash memory, or other non-volatile memory.

[0025] In some instances, system 100 or host device 105 may include various peripheral components. Peripheral components may be any input or output device, or an interface for such devices, which may be integrated into or with system 100 or host device 105. Examples may include one or more of the following: disk controller, sound controller, graphics controller, Ethernet controller, modem, universal serial bus (USB) controller, serial or parallel port, or peripheral card slots, such as Peripheral Component Interconnect (PCI) or dedicated graphics ports. Peripheral components may be other components that are understood by those skilled in the art to be peripheral devices.

[0026] In some instances, system 100 or host device 105 may include an I / O controller. The I / O controller manages data communication between processor 125 and peripheral components, input devices, or output devices. The I / O controller can also manage peripheral devices not integrated into or not integrated with system 100 or host device 105. In some instances, the I / O controller may represent a physical connection or port to an external peripheral component.

[0027] In some instances, system 100 or host device 105 may include input components, output components, or both. Input components may represent devices or signals external to system 100 that provide information, signals, or data to system 100 or its components. In some instances, input components may include a user interface or an interface with other devices or between other devices. In some instances, input components may be peripheral devices that interface with system 100 via one or more peripheral components, or may be managed by an I / O controller. Output components may represent devices or signals external to system 100 that are operable to receive output from any of system 100 or its components. Examples of output components may include a display, an audio speaker, a printing device, another processor on a printed circuit board, etc. In some instances, outputs may be peripheral devices that interface with system 100 via one or more peripheral components, or may be managed by an I / O controller.

[0028] Memory module 110 may include module memory controller 155 and one or more memory devices 160 (e.g., memory chips) to support a desired or specified capacity for data storage. Each memory device 160 (e.g., memory device 160-a, memory device 160-b, memory device 160-N) may include local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, local memory controller 165-N) and one or more memory arrays 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). Memory array 170 may be a collection of memory cells (e.g., one or more grids, one or more banks, one or more tiles, one or more segments), wherein each memory cell is operable to store at least one bit of data. Memory devices 160 comprising two or more memory dies may be referred to as multi-die memory or multi-die packages, or multi-chip memory or multi-chip packages.

[0029] Module memory controller 155 may include circuitry, logic, or components operable to control the operation of memory module 110. Module memory controller 155 may include hardware, firmware, or instructions enabling memory module 110 to perform various operations, and may be operable to receive, transmit, or execute commands, data, or control information related to components of memory module 110. Module memory controller 155 may be operable to communicate with one or more of external memory controller 120, memory devices 160, or processors 125. In some instances, module memory controller 155 may control the operation of memory module 110 as described herein in conjunction with local memory controller 165 of memory device 160.

[0030] A local memory controller 165 (e.g., local to memory device 160) may include circuitry, logic, or components operable to control the operation of memory device 160. In some instances, the local memory controller 165 may be operable to communicate with module memory controller 155 (e.g., to receive or transmit data or commands, or both). In some instances, memory module 110 may not include module memory controller 155, and either the local memory controller 165 or the external memory controller 120 may perform the various functions described herein. Thus, the local memory controller 165 may be operable to communicate with module memory controller 155, with other local memory controllers 165, or directly with external memory controller 120, processor 125, or combinations thereof. Examples of components that may be included in module memory controller 155 or local memory controller 165 or both may include a receiver for receiving signals (e.g., from external memory controller 120), a transmitter for transmitting signals (e.g., to external memory controller 120), a decoder for decoding or demodulating received signals, an encoder for encoding or modulating signals to be transmitted, or various other circuitry or controllers operable to support the described operation of module memory controller 155 or local memory controller 165 or both.

[0031] External memory controller 120 may be operable to enable communication of one or more of the information, data, or commands between a component of system 100 or host device 105 (e.g., processor 125) and memory module 110. External memory controller 120 may translate or interpret the communication exchanged between the components of host device 105 and memory module 110. In some instances, external memory controller 120, or other components of system 100 or host device 105, or their functionality as described herein, may be implemented by processor 125. For example, external memory controller 120 may be hardware, firmware, or software, or a combination thereof, implemented by processor 125, or other components of system 100 or host device 105. Although external memory controller 120 is depicted as being external to memory module 110, in some instances, external memory controller 120, or its functionality as described herein, may be implemented by one or more components of memory module 110 (e.g., module memory controller 155, local memory controller 165), or vice versa.

[0032] Components of host device 105 may exchange information with memory module 110 or memory devices 160 therein using one or more channels 115. Channels 115 may be operable to support communication between external memory controller 120 and memory module 110 or memory devices 160 therein. Each channel 115 may be an example of a transmission medium carrying information between host device 105 and memory devices 160. In some cases, one or more channels 115 may be shared by multiple memory devices 160 of memory module 110 (e.g., channel 115 may be coupled to a corresponding pin at each of memory devices 160). Each channel 115 may include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of system 100. Signal paths may be examples of conductive paths operable to carry signals. For example, channel 115 may include a first terminal comprising one or more pins or pads at host device 105 and one or more pins or pads at memory module 110 or memory devices 160 therein. The pin may be an instance of a conductive input or output point of the device of system 100, and the pin may be operable to act as a channel.

[0033] Channel 115 (and associated signal paths and terminals) may be dedicated to conveying one or more types of information. For example, channel 115 may include one or more CA channels 186, one or more clock (CK) signal channels 188, one or more chip select (CS) channels 189, one or more data (DQ) channels 190, one or more other channels 192, or combinations thereof. In some instances, single data rate (SDR) signaling or dual data rate (DDR) signaling may be used to convey signaling via channel 115. In SDR signaling, one modulation symbol (e.g., signal level) of the signal may be registered for each clock cycle (e.g., on the rising or falling edge of the CK signal). In DDR signaling, two modulation symbols (e.g., signal levels) of the signal may be registered for each clock cycle (e.g., on both the rising and falling edges of the CK signal).

[0034] In some instances, CA channel 186 may be operable to communicate commands between host device 105 and memory module 110, including control information (e.g., address information) associated with the commands. For example, a command carried by CA channel 186 may include a read command with an address containing desired data. In some instances, CA channel 186 may include any number of signal paths (e.g., eight or nine signal paths) for decoding one or more of the address or command data. In some instances, CA channel 186 may be coupled to one or more CA pins included in each memory device 160.

[0035] In some instances, the CK signal channel 188 may be operable to communicate one or more CK signals between the host device 105 and the memory module 110. Each CK signal may be operable to oscillate between high and low states and may support coordination (e.g., timing) between the actions of the host device 105 and the memory module 110. In some instances, the CK signal may be single-ended. In some instances, the CK signal may provide a timing reference for command and addressing operations of the memory module 110 or other system-level operations of the memory module 110. Therefore, the CK signal may be referred to as a control CK signal, a command CK signal, or a system CK signal. The system CK signal may be generated by a system clock, which may include one or more hardware components (e.g., an oscillator, crystal, logic gate, transistor). In some instances, the CK signal channel 188 may be coupled to one or more CK pins included in each memory device 160.

[0036] In some instances, CS channel 189 may be operable to communicate one or more CS signals between host device 105 and memory module 110. The purpose of the CS signals may be to enable or disable memory device 160 or the memory dies therein. In some instances, CS channel 189 may be coupled to one or more CS pins included in each memory device 160.

[0037] In some instances, data channel 190 may be operable to transmit one or more data or control information between host device 105 and memory module 110. For example, data channel 190 may transmit (e.g., bidirectional) information to be written to or read from memory module 110.

[0038] Channel 115 may each contain any number of signal paths (including a single signal path) coupled to any number of pins. In some instances, channel 115 may contain multiple individual signal paths. For example, a channel may be x4 (e.g., containing four signal paths and coupled to four corresponding pins at each of one or more memory devices 160), x8 (e.g., containing eight signal paths and coupled to eight corresponding pins at each of one or more memory devices 160), x16 (containing sixteen signal paths and coupled to sixteen corresponding pins at each of one or more memory devices 160), etc.

[0039] In some instances, one or more other channels 192 may include one or more error detection code (EDC) channels. The EDC channels may be operable to convey error detection signals, such as checksums, to improve system reliability. The EDC channels may contain any number of signal paths.

[0040] Signals transmitted via channel 115 may be modulated using one or more different modulation schemes. In some instances, a binary symbol (or binary level) modulation scheme may be used to modulate signals transmitted between host device 105 and memory module 110. The binary symbol modulation scheme may be an example of an M-ary modulation scheme where M equals two. Each symbol of the binary symbol modulation scheme may be operable to represent one bit of digital data (e.g., a symbol may represent logic 1 or logic 0). Examples of binary symbol modulation schemes include, but are not limited to, non-return-to-zero (NRZ), single-pole coding, bipolar coding, Manchester coding, pulse amplitude modulation (PAM) with two symbols (e.g., PAM2), etc.

[0041] In some instances, multi-symbol (or multi-level) modulation schemes can be used to modulate signals transmitted between host device 105 and memory module 110. A multi-symbol modulation scheme may be an example of an M-ary modulation scheme where M is greater than or equal to three. Each symbol of a multi-symbol modulation scheme may be operable to represent more than one bit of digital data (e.g., the symbol may represent logic 00, logic 01, logic 10, or logic 11). Examples of multi-symbol modulation schemes include, but are not limited to, PAM3, PAM4, PAM8, quadrature amplitude modulation (QAM), quadrature phase shift keying (QPSK), etc. A multi-symbol signal (e.g., a PAM3 signal or a PAM4 signal) may be a signal modulated using a modulation scheme comprising at least three levels for encoding more than one bit of information. Multi-symbol modulation schemes and symbols may alternatively be referred to as non-binary, multi-bit, or higher-order modulation schemes and symbols.

[0042] In some instances, signals (e.g., CA, CK, or CS signals) transmitted between host device 105 and memory module 110 may experience signal reflection. Signal reflection can occur when impedance is not constant along the signal line and may adversely affect the signal. To reduce signal reflection, memory module 110 may implement resistive termination techniques. That is, the memory module may couple signal lines (e.g., CA, CK, or CS signal lines) to a voltage source (e.g., a fixed voltage reference or power supply, or a ground reference), and a resistor assembly may be located between the signal line and the voltage source.

[0043] In some cases, the resistive termination for channel 115 may include one or more on-die terminations (ODTs) implemented by one or more memory devices 160. The ODT for a pin may include a memory device 160 that couples the pin to a voltage source within the memory die of the memory device 160 via a resistive component within the memory die. If a signal line is shared by multiple memory devices 160 and coupled to a corresponding pin at each of the multiple memory devices 160, the overall termination impedance (e.g., resistance) of the signal line termination may depend on the termination configuration for the corresponding pin at each of the multiple memory devices 160. As an example, if CA channel 186 includes signal lines coupled to a first CA pin at a first memory device 160 and a second CA pin at a second memory device 160, then the first memory device 160 implementing a 50-ohm ODT for the first CA pin while the second memory device does not implement any ODT for the second CA pin can result in a total termination impedance of 50 ohms for the signal lines, and the first memory device 160 implementing a 50-ohm ODT for the first CA pin while the second memory device also implements a 50-ohm ODT for the second CA pin can result in a total termination impedance of 25 ohms for the signal lines (due to the two 50-ohm ODTs being electrically in parallel).

[0044] In some instances, each memory device 160 may include an ODT pin, and the state of the ODT pin may indicate the termination configuration for one or more pins at the respective memory device 160. The termination configuration may indicate whether or how one or more pins of the memory device 160 are internally terminated within the memory device 160. Some memory devices 160 may support two different termination configurations. For example, a first termination configuration may specify that one or more CA pins, one or more CS pins, and one or more CK pins of the memory device 160 will be resistively terminated (e.g., using a 40-ohm resistor). Alternatively, a second termination configuration may specify that one or more CA pins, one or more CS pins, or one or more CK pins of the memory device 160 will not be resistively terminated.

[0045] Memory device 160 can select a first termination configuration or a second termination configuration based on the state (or connection option) of the corresponding ODT pin. For example, if memory device 160 detects a high voltage (e.g., Vcc, which may be a positive voltage supply or reference) on the ODT pin, memory device 160 can terminate the pin according to the first termination configuration, and if memory device 160 detects a low voltage (e.g., Vss, which may be a negative voltage supply, reference, or ground voltage) on the ODT pin, memory device 160 can terminate the pin according to the second termination configuration. The state of the ODT pin can be configured separately (e.g., independently) for each memory device 160 included in the memory module. Thus, pins of different memory devices 160 can be terminated according to a specified configuration for each of the memory devices 160. Furthermore, each memory device 160 can share a common CA signal line, CK signal line, or CS signal line, and the total termination resistance of the common CA signal line, CK signal line, or CS signal line can be based on the state of the ODT pin at each memory device 160.

[0046] However, the implementation described above may only allow two termination configurations when powered on. For example, where for each individual memory device 160, all pins of the memory device 160 terminated based on the state of the ODT pin are either terminated or not terminated at all. This can result in each pin and signal line being terminated based on the state of the ODT pins of different memory devices 160 having the same overall termination impedance. But different signaling lines terminated based on the state of the ODT pins may have different characteristics, and therefore different overall termination impedances may be required for different signal lines, including when powered on. For example, some pins of the memory device 160 terminated based on the state of the ODT pins may be more loaded (e.g., capacitively loaded) than other pins. For example, the CK pin may be more loaded than the CA or CS pins. Therefore, it may be advantageous to allow the memory device 160 to select from more than two termination configurations.

[0047] As described herein, memory device 160 can select a termination configuration from at least three termination configurations as part of a power-on procedure for one or more pins of memory device 160. For example, memory device 160 can select from at least a first termination configuration, a second termination configuration, and a third termination configuration. As an example, a first termination configuration may specify the termination of all corresponding pins of memory device 160 (e.g., one or more CK pins, one or more CA pins, and one or more CS pins) using a resistor (e.g., a 40-ohm resistor). A second termination configuration may specify that all pins of memory device 160 are not terminated. A third configuration may specify that one type of pin (e.g., one or more CK pins) is terminated and other types of pins of memory device 160 (e.g., one or more CS pins or one or more CA pins) are not terminated.

[0048] In some instances, memory device 160 can select a first termination configuration, a second termination configuration, or a third termination configuration based on the state of the ODT pin. For example, if the ODT pin is biased to a first voltage, memory device 160 can terminate the pin according to the first termination configuration. If the ODT pin is biased to a second voltage, memory device 160 can terminate the pin according to the second termination configuration. If the ODT pin is biased to a third voltage or is electrically floating, memory device 160 can terminate the pin according to the third termination configuration. Using the methods described herein allows specific signal lines (e.g., the CK signal line) to have different overall termination resistances compared to other signal lines (e.g., the CS signal line and the CA signal line). Thus, memory device 160 can customize termination resistances for specific signal lines to support higher signaling speeds, improved signaling reliability, or both, and other possible advantages.

[0049] Figure 2 This describes an example of component diagram 200 supporting ODT configuration for a memory device, as disclosed herein. In some instances, component diagram 200 may implement aspects of system 100. For example, component diagram 200 may include elements that are, for example, […]. Figure 1 The memory device 160 described herein is an example of memory device 205. Memory device 160 may include an ODT controller 210, a buffer 215, a mode register 220, and an I / O component 225. Each of the buffer 215, mode register 220, and I / O component 225 may be coupled to or in electronic communication with the ODT controller 210.

[0050] like Figure 1As described, memory device 205 can determine the termination configuration of its pins based on the state (or connection options) of its ODT pins. In some instances, the ODT pins of memory device 205 can be coupled to ODT controller 210, and ODT controller 210 can be configured to sense the state of the ODT pins. The ODT pins can have multiple states. For example, a first state can be an ODT pin coupled to a first voltage, a second state can be an ODT pin coupled to a second voltage, and a third ODT state can be an ODT pin coupled to a third voltage. The first, second, and third voltages can be different from each other. For example, the first voltage can be a positive voltage (e.g., Vcc), the second voltage can be ground or a negative voltage (e.g., Vss), and the third voltage can be a voltage between or different from (e.g., greater than) the first and second voltages (e.g., Vpp). As an example, the first voltage can be 1.1 volts, the second voltage can be ground, and the third voltage can be 1.8 volts. An additional fourth state (or alternative to the third state) may be an electrically floating ODT pin. In such a case, memory device 205 may include multiple (e.g., two or more) sensing circuits located between ODT controller 210 and the ODT pin.

[0051] ODT controller 210 can determine the state of the ODT pin by sensing (or detecting) the voltage of the ODT pin (e.g., when the memory device 205 is powered on). For example, if ODT controller 210 senses that the voltage of the ODT pin is equal to or close to a first voltage, ODT controller 210 can determine that the ODT pin is in a first state. In some instances, after determining the state of the ODT pin, ODT controller 210 can store two or more bits in buffer 215, where the logic state of two or more bits represents the determined state of the ODT pin. For example, ODT controller 210 can store 11 if the first state is detected, 00 if the second state is detected, 10 if the third state is detected, or 01 if the fourth state is detected. In some instances, the state of the ODT pin is determined during the manufacture of the memory device 205. That is, the state of the ODT pin is predetermined.

[0052] The ODT controller 210 can select a termination configuration from a set of termination configurations based on the state of the ODT pins. Each termination configuration can specify whether to terminate a pin of the memory device 205 (e.g., the CA pin, CK pin, or CS pin) using a resistor. The set of termination configurations can be stored in a mode register 220 contained in the memory device 205. In some instances, multiple fields may exist in the mode register 220. As an example, one field may exist for each pin type and for each termination configuration option for a specific pin type. For example, if the memory device 205 contains one pin type, three fields may exist in the mode register 220 for three different configuration options. In some instances, the memory device 205 may contain multiple mode registers 220. For example, the memory device 205 may contain mode registers for each type of pin (e.g., corresponding mode registers for the CA pin, CK pin, and CS pin).

[0053] In some instances, the termination configuration set may contain at least three termination configurations. Table 1 illustrates three different termination configuration options (e.g., Option A, Option B, and Option C). Option A may specify terminating the CA pin, the CS pin, and the CK pin with a 40Ω resistor. Alternatively, Option B may specify not terminating the CA, CS, and CK pins. Option C may specify not terminating the CA and CS pins, but terminating the CK pin with a 40Ω resistor. As used herein, a resistor may refer to any component configured to have a specific amount of resistance and may alternatively be referred to as a resistive component. Although three termination configuration options are shown in Table 1, it should be understood that more than three termination configuration options may exist (e.g., four termination configuration options). The termination configuration options in Table 1 may illustrate the default termination configuration option (e.g., the termination configuration when the memory device 205 is powered on). In some instances, the termination configuration options may be updated or changed during operation of the memory device 205.

[0054] CA pin 40Ω disconnect disconnect CS pin 40Ω disconnect disconnect CK pin 40Ω disconnect 40Ω

[0055] Table 1

[0056] Each termination configuration in the termination configuration set may correspond to a state of an ODT pin. For example, option A may correspond to a first state of an ODT pin, option B to a second state, and option C to a third state. The ODT controller 210 determines the state of the ODT pin and consults the mode register 220 to determine which termination configuration in the termination configuration set to implement. As an example, the ODT controller 210 may determine that the ODT pin is in the first state and determine (from the mode register 220) to terminate the pin of the memory device 205 according to option A. In some instances, the ODT controller 210 may determine the state of the ODT pin by reading the logic state of two or more bits stored in the buffer 215. Once the ODT controller 210 determines the termination configuration, it can instruct the I / O component 225 to terminate the pin of the memory device 205 according to the determined termination configuration. Once memory device 205 terminates the pins according to the determined termination configuration, memory device 205 can "disconnect" or stop power supply to one or more of the ODT controller 210, mode register 220, buffer 215, or I / O component 225. The method described herein allows memory device 205 to select from three or more termination configuration options, which allows the memory system to customize combined terminal resistors for specific signal lines.

[0057] Figure 3 This describes an example of component diagram 300 supporting ODT configuration for a memory module, as disclosed herein. In some instances, component diagram 300 may implement aspects of system 100 and component diagram 200. For example, component diagram 300 may include memory device 310, which may be as described in reference... Figure 1 The described memory device 160 and as referenced Figure 2 An example of the described memory device 205. Component Figure 300 may also include a memory module 305, which includes a memory device 310 and a driver 315. The memory device 310 may also be referred to as a DRAM chip, the driver 315 may also be referred to as a register clock driver (RCD), and the memory module 305 may also be referred to as a dual in-line memory module (DIMM).

[0058] The memory module 305 can be divided into channels 320-a and 320-b. Channel 320-a may include memory devices 310-a, 310-b, 310-c, 310-d, and 310-e. Furthermore, channel 320-a may include five additional memory devices 310 located on the rear side of the memory module 305. Figure 3(Not shown in the image). Channel 320-b may include memory devices 310-f, 310-g, 310-h, 310-i, and 310-j. Similar to channel 320-a, channel 320-b may include five additional memory devices 310 located on the rear side of memory module 305. Figure 3 (Not shown in the image). In some instances, channel 320-a can operate independently of channel 320-b. Although Figure 3 The memory module 305 is shown to contain five memory devices 310 per channel 320 (on one side), but it should be understood that any number of memory devices 310 may be included in the memory module 305.

[0059] In some instances, memory module 305 may communicate with a host device. Memory module 305 may be coupled via driver 315. Driver 315 may receive signals from the host device and redistribute signals to components of memory module 305. In some instances, driver 315 may have multiple pins that allow communication with components of memory module 305. For example, driver 315 may have one or more CS pins, one or more CK pins, and one or more CA pins. The CK pin of driver 315 may be coupled to the CK signal line 335 of the corresponding CK pin of memory device 310 (e.g., 10 memory devices 310) routed to channel 320-a or to the corresponding CK signal line 335 of memory device 310 (e.g., 10 memory devices 310) routed to channel 320-b. Alternatively, the CS pin of driver 315 may be coupled to the CS signal line 325 of the front or rear memory devices 310 (e.g., five memory devices) routed to channel 320-a, or coupled to the CS signal line 325 of the front or rear memory devices 310 (e.g., five memory devices) routed to channel 320-b. CA signal line 330 may be routed to the memory devices 310 of memory module 305 in a similar manner to CS signal line 325. Because CK signal line 335 can be shared among more memory devices 310 than CS signal line 325 and CA signal line 330, CK pin can handle more loads and may require different signaling compared to CS and CA pins.

[0060] like Figure 1 and 2As described, each memory device 310 of memory module 305 can determine whether to resistively terminate one or more pins of memory device 310 (e.g., CA pins, CS pins, or CK pins) based on the state of the ODT pins contained in each memory device 310. In some instances, an internally terminated pin at one memory device 310 can affect other memory devices 310. For example, one or more CA pins resistively terminated at memory device 310-b and one or more CA pins resistively terminated at memory device 310-e can create a combined parallel resistance on a shared CA signal line 330. In some memory modules 305, each memory device 310 can be selected from two different termination configurations. For example, if the ODT pin of the corresponding memory device 310 is tied high (as shown at memory device 310-a), then memory device 310 can internally terminate all pin types, while if the ODT pin is tied low (e.g., memory device 310-b), then memory device 310 may not internally terminate all pin types. However, allowing only two different termination configurations may not provide the desired level of flexibility for memory module 305 when considering the different signaling requirements for each pin type. For example, the two termination configurations could specify that all pin types are resistively terminated or that all pin types are not resistively terminated. Using such an approach can result in each type of signal line having the same combined termination resistance. But as discussed above, different pin types may have different signaling requirements, and therefore, different pin types can benefit from having different combined termination resistances.

[0061] As described herein, each memory device 310 can be selected from three or more termination configurations based on the state of the corresponding ODT pin contained in each memory device 310. Allowing the memory device 310 to be selected from three or more different termination configurations allows for customizable combined termination resistors for different signal lines used in the memory module 305. In one example, a first termination configuration may specify internal termination of all types of pins. For example, a first termination configuration may specify terminating each of one or more CA pins, one or more CS pins, or one or more CK pins of the corresponding memory device 310 using a 40-ohm resistor. A second termination configuration may specify not to internally terminate all types of pins. For example, a second termination configuration may specify not to terminate each of one or more CA pins, one or more CS pins, or one or more CK pins of the corresponding memory device 310. A third termination configuration may specify terminating one type of pin without terminating the other types of pins. For example, the third termination configuration may specify the use of a 40-ohm resistor to terminate each of one or more CK pins and not to terminate each of one or more CA pins and one or more CS pins of the corresponding memory device 310.

[0062] In some instances, each of three or more termination configurations may be associated with a state of the ODT pin contained in the memory device 310. In some instances, a first state of the ODT pin may include the ODT pin being biased to a first voltage (e.g., a positive voltage), a second state of the ODT pin may include the ODT pin being biased to a second voltage (e.g., ground voltage), and a third state may include the ODT pin being electrically floating. As an example, a first termination configuration may be associated with a first state, a second termination configuration may be associated with a second state, and a third termination configuration may be associated with a third state.

[0063] When the memory module 305 is powered on, each memory device 310 can sense the state of the ODT pin. For example... Figure 3 As shown, the ODT pin of memory device 310-a can be biased to a first voltage. Alternatively, the ODT pins of memory devices 310-b and 310-d can be biased to a second voltage. Furthermore, the ODT pins of memory devices 310-c and 310-d can be electrically floating. This ODT pin configuration causes the CS signal line 325 and the CA signal line to have the same combined termination resistance and causes the CK signal line 335 to have a different combined termination resistance than the CS signal line 325 and the CA signal line 330. In other words, the method described herein allows different signal lines of the memory module to have different combined termination resistances that support higher signaling speeds, improved signaling reliability, or both, and other possible advantages.

[0064] Figure 4 A block diagram 400 illustrates a memory device 420 supporting ODT configuration for a memory device, according to examples disclosed herein. The memory device 420 may be as described in the references... Figures 1 to 3 Examples of aspects of the described memory device. Memory device 420 or its various components may be examples of components for performing the various aspects of ODT configuration for the memory device as described herein. For example, memory device 420 may include pin connection component 425, termination option component 430, pin termination component 435, device setup component 440, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0065] Pin connection component 425 may be configured or otherwise support components for determining a connection option on which an ODT pin of a memory device is based from a set of candidate connection options comprising three or more candidate connection options, wherein each candidate connection option in the set of candidate connection options corresponds to a corresponding termination configuration for one or more additional pins of the memory device (e.g., the CA pin, CK pin, or CS pin of the memory device). Termination option component 430 may be configured or otherwise support components for identifying a corresponding termination option for each of one or more additional pins of the memory device (e.g., a first termination option for the CA pin of the memory device, a second termination option for the CK pin of the memory device, and a third termination option for the CS pin of the memory device) based at least in part on the corresponding termination configuration for the connection option on which the ODT pin is based. Pin termination assembly 435 may be configured or otherwise support components for configuring each of one or more additional pins of the memory device according to the corresponding termination option for the additional pin (e.g., configuring the CA pin, CK pin, or CS pin according to a first termination option, a second termination option, or a third termination option, respectively).

[0066] In some instances, the set of candidate connection options includes at least: a first connection option that includes biasing the ODT pin at a first voltage, a second connection option that includes biasing the ODT pin at a second voltage, and a third connection option that includes biasing or electrically floating the ODT pin at a third voltage. In some instances, the first, second, and third voltages are different from each other.

[0067] In some instances, the third connection option includes biasing the ODT pin at a third voltage. In some instances, the set of candidate connection options includes a fourth connection option, in which the ODT pin is electrically floating.

[0068] In some instances, one or more additional pins of the memory device may include a CA pin, and in order to support the identification of the appropriate termination option for the CA pin, the termination option component 430 may be configured or otherwise support the determination, at least in part, of whether the CA pin is terminated within the memory device via a resistor termination or whether the CA pin is not terminated within the memory device, based on the determined connection option.

[0069] In some instances, one or more additional pins of the memory device may include a CK pin, and in order to support the identification of the appropriate termination option for the CK pin, the termination option component 430 may be configured or otherwise support the determination, at least in part, of whether the CK pin is terminated within the memory device via a resistor termination or whether the CK pin is not terminated within the memory device, based on the determined connection option.

[0070] In some instances, one or more additional pins of the memory device may include a CS pin, and in order to support the identification of the appropriate termination option for the CS pin, the termination option component 430 may be configured or otherwise support the determination, at least in part, of whether the CS pin is terminated within the memory device via a resistor termination or whether the CS pin is not terminated within the memory device, based on the determined connection option.

[0071] In some instances, to support the determination of connection options, the pin connection component 425 may be configured or otherwise supported for the component to detect the voltage of the ODT pin, wherein the detected voltage corresponds to the connection option.

[0072] In some instances, device setup component 440 may be configured or otherwise support components for powering on the memory device, wherein determining a connection option from a set of candidate connection options is at least in part based on powering on the memory device.

[0073] Figure 5 The flowchart illustrates a method 500 for supporting ODT configuration of a memory device according to examples disclosed herein. The operation of method 500 can be implemented by a memory device or its components as described herein. For example, it can be implemented by... (refer to...) Figures 1 to 4 The described memory device performs the operation of method 500. In some instances, the memory device may execute an instruction set to control the functional elements of the device to perform the described function. Alternatively, the memory device may use dedicated hardware to perform aspects of the described function.

[0074] At 505, the method may include determining, from a set of candidate connection options comprising three or more candidate connection options, the connection option on which the ODT pin of the memory device is configured, wherein each candidate connection option in the set of candidate connection options corresponds to a corresponding termination configuration for one or more additional pins of the memory device (e.g., the CA pin, the CK pin, and the CS pin of the memory device). The operation of 505 may be performed according to examples disclosed herein. In some instances, it may be performed by reference to... Figure 4 The described pin connection assembly 425 performs aspects of the operation of 505.

[0075] At 510, the method may include identifying, at least in part, a corresponding termination option for each of one or more additional pins of the memory device based on a corresponding termination configuration for configuring the connection options upon which the ODT pin is based (e.g., a first termination option for the CA pin of the memory device, a second termination option for the CK pin of the memory device, or a third termination option for the CS pin of the memory device). Operation 510 may be performed according to examples disclosed herein. In some examples, it may be performed by reference to... Figure 4 The described termination option component 430 performs the operation of 510.

[0076] At 515, the method may include configuring each of one or more additional pins of the memory device according to a corresponding termination option for the additional pin (e.g., configuring the CA pin, CK pin, or CS pin according to a first termination option, a second termination option, or a third termination option, respectively). Operation of 515 may be performed according to examples disclosed herein. In some examples, it may be performed by reference to... Figure 4 The described pin termination component 435 performs aspects of the operation of 515.

[0077] In some instances, the device as described herein may perform one or more methods, such as method 500. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) or any combination thereof for performing aspects of this disclosure:

[0078] Aspect 1: An apparatus comprising features, circuitry, logic, components, or instructions, or any combination thereof, for: determining, from a set of candidate connection options comprising three or more candidate connection options, a connection option on which an ODT pin of a memory device is based, wherein each candidate connection option in the set of candidate connection options corresponds to a corresponding termination configuration for one or more additional pins of the memory device; identifying, at least in part, a corresponding termination option for each of the one or more additional pins of the memory device based on the corresponding termination configuration for configuring the connection option on which the ODT pin is based; and configuring each of the one or more additional pins of the memory device according to the corresponding termination option for the additional pins.

[0079] Aspect 2: The device according to aspect 1 further includes operations, features, circuitry, logic, components, or instructions or any combination thereof for the following: the set of candidate connection options includes at least: a first connection option including the ODT pin biased at a first voltage, a second connection option including the ODT pin biased at a second voltage, and a third connection option including the ODT pin biased at a third voltage or electrically floating, wherein the first voltage, the second voltage, and the third voltage are different from each other.

[0080] Aspect 3: The device according to aspect 2 further includes operations, features, circuitry, logic, components, or instructions or any combination thereof for: the third connection option includes the ODT pin being biased at the third voltage, and wherein the set of candidate connection options includes a fourth connection option, the fourth connection option including the ODT pin being electrically floating.

[0081] Aspect 4: The device according to any one of aspects 2 to 3, wherein the one or more additional pins of the memory device include a CA pin, and wherein identifying the corresponding termination option for the CA pin further includes operations, features, circuitry, logic, components or instructions or any combination thereof for determining, at least in part, whether the CA pin is terminated within the memory device via a resistor termination or whether the CA pin is not terminated within the memory device, based on the determined connection option.

[0082] Aspect 5: The device according to any one of aspects 2 to 4, wherein the one or more additional pins of the memory device include a CK pin, and wherein identifying the corresponding termination option for the CK pin further includes operations, features, circuitry, logic, components or instructions or any combination thereof for determining, at least in part, whether the CK pin is terminated within the memory device via a resistor termination or whether the CK pin is not terminated within the memory device, based on the determined connection option.

[0083] Aspect 6: The device according to any one of aspects 2 to 5, wherein the one or more additional pins of the memory device include a CS pin, and wherein identifying the corresponding termination option for the CS pin further includes an operation, feature, circuit system, logic, component or instruction or any combination thereof for determining, at least in part, whether the CS pin is terminated within the memory device via a resistor termination or whether the CS pin is not terminated within the memory device, based on the determined connection option.

[0084] Aspect 7: The device according to any one of aspects 1 to 6, wherein determining the connection option further includes operations, features, circuitry, logic, components or instructions or any combination thereof for detecting the voltage of the ODT pin, wherein the detected voltage corresponds to the connection option.

[0085] Aspect 8: The device according to any one of aspects 1 to 7 further includes an operation, feature, circuit system, logic, component or instruction or any combination thereof for energizing the memory device, wherein determining the connection option from the set of candidate connection options is at least in part based on energizing the memory device.

[0086] Figure 6 The flowchart illustrates a method 600 for supporting ODT configuration of a memory device according to examples disclosed herein. The operation of method 600 can be implemented using a memory device or its components as described herein. For example, it can be implemented using... (See reference...) Figures 1 to 4 The described memory device performs the operation of method 600. In some instances, the memory device may execute an instruction set to control the functional elements of the device to perform the described functions. Alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0087] At 605, the method may include energizing the memory device. The operation at 605 may be performed according to examples disclosed herein. In some instances, it may be performed by means of, as referenced... Figure 4 The described device sets up the aspect of the operation of component 440 performing 605.

[0088] At 610, the method may include determining a connection option based on powering on the memory device and from a set of candidate connection options comprising three or more candidate connection options, wherein each candidate connection option in the set of candidate connection options corresponds to a corresponding termination configuration for one or more additional pins of the memory device (e.g., the CA pin, CK pin, or CS pin of the memory device). Operation 610 may be performed according to examples disclosed herein. In some examples, it may be performed by reference to... Figure 4 The described pin connection component 425 performs aspects of the operation of 610.

[0089] At 615, the method may include identifying, at least in part, a corresponding termination option for each of one or more additional pins of the memory device based on a corresponding termination configuration for configuring the connection option upon which the ODT pin is based (e.g., a first termination option for the CA pin of the memory device, a second termination option for the CK pin of the memory device, or a third termination option for the CS pin of the memory device). Operation 615 may be performed according to examples disclosed herein. In some examples, it may be performed by reference to... Figure 4 The described termination option component 430 performs the operation of 615.

[0090] At 620, the method may include configuring each of one or more additional pins of the memory device according to a corresponding termination option for the additional pin (e.g., configuring the CA pin, CK pin, or CS pin according to a first termination option, a second termination option, or a third termination option, respectively). The operation of 620 may be performed according to examples disclosed herein. In some examples, it may be performed by reference to... Figure 4 The described pin termination component 435 performs aspects of the operation of 620.

[0091] It should be noted that the methods described herein describe possible implementations, and the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods may be combined.

[0092] A device is described. An overview of aspects of the device as described herein is provided below:

[0093] Aspect 9: An apparatus comprising: a memory device including an ODT pin and a controller configured to cause the apparatus to: detect a state of the ODT pin, wherein the state is one of a plurality of potential states comprising three or more potential states; identify a termination configuration from a plurality of termination configurations based at least in part on the detected state of the ODT pin, the termination configurations corresponding to a corresponding termination option for each of one or more additional pins of the memory device; and configure each of the one or more additional pins according to the corresponding termination option for the additional pins corresponding to the identified termination configuration.

[0094] Aspect 10: The device according to aspect 9, wherein the memory device further comprises: a mode register configured to store the plurality of termination configurations, wherein the controller is configured to identify the termination configuration at least in part based on reading the termination configuration from the mode register.

[0095] Aspect 11: The device according to any one of aspects 9 to 10, wherein the memory device further comprises: a buffer configured to store two or more bits representing a logic value at least in part based on the detected state of the ODT pin, wherein the controller is configured to identify the termination configuration at least in part based on the logic value represented by the two or more bits.

[0096] Aspect 12: The device according to any one of aspects 9 to 11, wherein the plurality of potential states include at least: a first state including the ODT pin being biased at a first voltage, a second state including the ODT pin being biased at a second voltage, and a third state including the ODT pin being biased at a third voltage or electrically floating.

[0097] Aspect 13: The device according to aspect 12, wherein the one or more additional pins of the memory device include a CA pin, and wherein, in order to identify the termination configuration from the plurality of termination configurations, the controller is configured to determine, at least in part, based on the detected state of the ODT pin, whether the CA pin is terminated via a resistor termination within the memory device or whether the CA pin is not terminated within the memory device.

[0098] Aspect 14: The device according to any one of aspects 12 to 13, wherein the one or more additional pins of the memory device include a CK pin, and wherein, in order to identify the termination configuration from the plurality of termination configurations, the controller is configured to determine, at least in part, based on the detected state of the ODT pin, whether the CK pin is terminated via a resistor termination within the memory device or whether the CK pin is not terminated within the memory device.

[0099] Aspect 15: The device according to any one of aspects 12 to 14, wherein the one or more additional pins of the memory device include a CS pin, and wherein, in order to identify the termination configuration from the plurality of termination configurations, the controller is configured to determine, at least in part, based on the detected state of the ODT pin, whether the CS pin is terminated within the memory device via a resistor termination or whether the CS pin is not terminated within the memory device.

[0100] A device is described. An overview of aspects of the device as described herein is provided below:

[0101] Aspect 16: An apparatus comprising: a plurality of memory devices, each including a respective ODT pin and a respective set of one or more additional pins; and one or more signal lines including a respective signal line for each of the sets of one or more additional pins, wherein the respective signal line for the additional pins in the sets of one or more additional pins is coupled to the additional pin of each of the plurality of memory devices, wherein each of the plurality of memory devices includes a respective controller configured to cause the memory device to: detect a state of the respective ODT pin of the memory device, wherein the state is one of a plurality of potential states including three or more potential states; and identify a termination configuration for each of the respective sets of one or more additional pins of the memory device based at least in part on the detected state of the ODT pin of the memory device.

[0102] Aspect 17: The device according to aspect 16, wherein the plurality of potential states include at least: a first state including the ODT pin being biased at a first voltage, a second state including the ODT pin being biased at a second voltage, and a third state including the ODT pin being biased at a third voltage or electrically floating.

[0103] Aspect 18: The apparatus according to aspect 17, wherein the respective set of one or more additional pins for each of the plurality of memory devices includes a respective CA pin coupled to a CA line in the one or more signal lines, and wherein, in order to identify the termination configuration of the respective CA pin for the memory device, the respective controller of the memory device is configured to determine, at least in part, whether the respective CA pin is terminated within the memory device via a resistor termination or whether the respective CA pin is not terminated within the memory device, based on the detected state of the respective ODT pin.

[0104] Aspect 19: The apparatus according to any one of aspects 17 to 18, wherein the corresponding set of one or more additional pins for each of the plurality of memory devices includes a corresponding CK pin coupled to a CK line among the one or more signal lines, and wherein, in order to identify the termination configuration of the corresponding CK pin for the memory device, the corresponding controller of the memory device is configured to determine, at least in part, whether the corresponding CK pin is terminated within the memory device via a resistor termination or whether the corresponding CK pin is not terminated within the memory device, based on the detected state of the corresponding ODT pin.

[0105] Aspect 20: The apparatus according to any one of aspects 17 to 19, wherein the corresponding set of one or more additional pins for each of the plurality of memory devices includes a corresponding CS pin coupled to a CS line among the one or more signal lines, and wherein, in order to identify the termination configuration of the corresponding CS pin for the memory device, the corresponding controller of the memory device is configured to determine, at least in part, whether the corresponding CS pin is terminated within the memory device via a resistor termination or whether the corresponding CS pin is not terminated within the memory device, based on the detected state of the corresponding ODT pin.

[0106] The information and signals described herein can be represented using any of a variety of different techniques and methods. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, the signal may represent a bus of signals, wherein the bus may have various bit widths.

[0107] The terms "electronic communication," "conductive contact," "connection," and "coupling" can refer to the relationship between components that enables the flow of signals between them. Components are considered to be in electronic communication (or in conductive contact, connected, or coupled) with each other if there is any conductive path between them that enables the flow of signals at any given time. At any given time, the conductive path between components that are in electronic communication (or in conductive contact, connected, or coupled) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between components, or an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some instances, the signal flow between connected components can be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0108] The term "coupling" refers to the condition that moves from an open-circuit relationship between components to a closed-circuit relationship, in which a signal is currently unable to travel between components via a conductive path, and in which a signal can travel between components via a conductive path. When a component, such as a controller, couples other components together, the component initiates a change that allows signals to flow between the other components via conductive paths that were previously not permitted.

[0109] The term "isolation" refers to a relationship between components in which signals are currently unable to flow between them. Components are isolated from each other if there is an open circuit between them. For example, components separated by a switch positioned between two components are isolated from each other when the switch is open. When a controller isolates two components, it performs the following change: preventing signals from flowing between the components using previously permitted conductive paths.

[0110] The devices discussed herein, including memory arrays, can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, and gallium nitride. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by using doping with various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, either by ion implantation or by any other doping method.

[0111] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include three-terminal devices comprising a source, drain, and gate. The terminals may be connected to other electronic components via a conductive material such as a metal. The source and drain may be conductive and may comprise heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., the majority of charge carriers are electrons), the FET may be called an n-type FET. If the channel is p-type (i.e., the majority of charge carriers are holes), the FET may be called a p-type FET. The channel may be end-capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET accordingly can cause the channel to become conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "turned on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor can be "disconnected" or "deactivated".

[0112] The descriptions herein, illustrated with reference to the accompanying drawings, depict exemplary configurations and do not represent all implementable or claim-scoped instances. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "superior to" other instances. The detailed description includes specific details that provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some instances, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0113] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by a dash following the reference numeral and a second numeral used to differentiate between similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components that have the same first reference numeral but are independent of the second reference numeral.

[0114] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored as one or more instructions or code on or transmitted via a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described herein can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions can also be physically located in various locations, including distributed implementations such that portions of the functions are implemented in different physical locations.

[0115] For example, the various illustrative blocks and modules described in connection with this disclosure may be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0116] As used herein (included in the claims), the word "or" as used in a list of items (e.g., a list of items followed by phrases such as "at least one of" or "one or more of") indicates a list containing endpoints, such that a list of at least one of, for example, A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0117] Computer-readable media includes both non-transitory computer storage media and communication media, wherein the communication media includes any media that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any usable media accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then such coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used in this article, disks and optical discs include CDs, laser discs, optical discs, digital multifunction discs (DVDs), floppy disks, and Blu-ray discs. Disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. This combination also includes computer-readable media.

[0118] The description herein is provided to enable those skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but is given the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for configuring a semiconductor device, comprising: The termination option on which the die-on termination pins of the memory device are configured is determined from a set of three or more candidate termination options, wherein each candidate termination option in the set of three or more candidate termination options corresponds to a corresponding termination configuration for one or more additional pins of the memory device. The corresponding termination option for each of the one or more additional pins of the memory device is identified at least in part based on the corresponding termination configuration used to configure the termination option upon which the die-on termination pins are based; and Each of the one or more additional pins of the memory device is configured according to the corresponding termination option for the additional pin.

2. The method of claim 1, wherein the set of three or more candidate termination options comprises at least: The options include a first termination option where the die-on termination pin is biased at a first voltage, a second termination option where the die-on termination pin is biased at a second voltage, and a third termination option where the die-on termination pin is biased at a third voltage or electrically floated, wherein the first voltage, the second voltage, and the third voltage are different from each other.

3. The method of claim 2, wherein the third termination option includes the die-on termination pin being biased at the third voltage, and wherein the set of three or more candidate termination options includes a fourth termination option, the fourth termination option including the die-on termination pin being electrically floating.

4. The method of claim 2, wherein the one or more additional pins of the memory device include command and address pins, and wherein identifying the respective termination options for the command and address pins includes: The determination of whether the command and address pins are terminated via resistor termination within the memory device or not within the memory device is based at least in part on the determined termination options.

5. The method of claim 2, wherein the one or more additional pins of the memory device include clock pins, and wherein identifying the respective termination option for the clock pin includes: The determination of whether the clock pin is terminated within the memory device via a resistor or not is based at least in part on the determined termination option.

6. The method of claim 2, wherein the one or more additional pins of the memory device include chip select pins, and wherein identifying the respective termination option for the chip select pin includes: The determination of whether the chip select pin is terminated via a resistor within the memory device or not within the memory device is based at least in part on the determined termination option.

7. The method of claim 1, wherein determining the termination option comprises: The voltage at the termination pins on the die is detected, wherein the detected voltage corresponds to the termination option.

8. The method of claim 1, further comprising: Powering on the memory device, wherein determining the termination option from the set of three or more candidate termination options is at least in part based on powering on the memory device.

9. A semiconductor device comprising: A memory device, the memory device including die-top termination pins and a controller, the controller being configured to cause the semiconductor device to: Detect the termination status of the termination pins on the die, wherein the termination status is one of three or more potential termination statuses; A termination configuration is identified from a plurality of termination configurations, at least in part, based on the detected termination state of the termination pins on the die, the termination configuration corresponding to a corresponding termination option for each of one or more additional pins of the memory device; and Each of the one or more additional pins is configured according to the corresponding termination option for the additional pins corresponding to the identified termination configuration.

10. The semiconductor device of claim 9, wherein the memory device further comprises: A mode register is configured to store the plurality of termination configurations, wherein the controller is configured to identify the termination configuration at least in part based on reading the termination configuration from the mode register.

11. The semiconductor device of claim 9, wherein the memory device further comprises: A buffer configured to store two or more bits representing a logic value at least in part based on the detected termination state of the termination pin on the die, wherein the controller is configured to identify the termination configuration at least in part based on the logic value represented by the two or more bits.

12. The semiconductor device of claim 9, wherein the plurality of three or more potential termination states at least include: This includes a first termination state where the die upper termination pin is biased under a first voltage, a second termination state where the die upper termination pin is biased under a second voltage, and a third termination state where the die upper termination pin is biased under a third voltage or electrically floating.

13. The semiconductor device of claim 12, wherein the one or more additional pins of the memory device include command and address pins, and wherein the controller is configured to: The determination is made, at least in part, based on the detected termination status of the termination pins on the die, whether the command and address pins are terminated via resistors within the memory device or are not terminated within the memory device.

14. The semiconductor device of claim 12, wherein the one or more additional pins of the memory device include clock pins, and wherein the controller is configured to: The determination of whether the clock pin is terminated via a resistor within the memory device or not within the memory device is based at least in part on the detected termination state of the termination pin on the die.

15. The semiconductor device of claim 12, wherein the one or more additional pins of the memory device include chip select pins, and wherein the controller is configured to: The determination of whether the chip select pin is terminated via a resistor within the memory device or not within the memory device is based at least in part on the detected termination state of the termination pin on the die.

16. A semiconductor device comprising: Multiple memory devices, each including a corresponding set of on-die termination pins and one or more additional pins; as well as One or more signal lines, including a corresponding signal line for each of the set of one or more additional pins, wherein the corresponding signal line for each of the additional pins in the set of one or more additional pins is coupled to the additional pin of each of the plurality of memory devices. Each of the plurality of memory devices includes a corresponding controller, the corresponding controller being configured to cause the memory device to: Detecting the termination state of the corresponding die-on termination pin of the memory device, wherein the termination state is one of three or more potential termination states; and The termination configuration for each additional pin in the corresponding set of one or more additional pins of the memory device is identified, at least in part, based on the detected termination status of the termination pins on the die of the memory device.

17. The semiconductor device of claim 16, wherein the plurality of three or more potential termination states include at least: This includes a first termination state where the die upper termination pin is biased under a first voltage, a second termination state where the die upper termination pin is biased under a second voltage, and a third termination state where the die upper termination pin is biased under a third voltage or electrically floating.

18. The semiconductor device according to claim 17, wherein: The corresponding set of one or more additional pins for each of the plurality of memory devices includes corresponding command and address pins coupled to command and address lines in the one or more signal lines; and In order to identify the termination configuration of the corresponding command and address pins for the memory device, the corresponding controller of the memory device is configured to: The determination is made, at least in part, based on the detected termination status of the corresponding die-on termination pins, whether the corresponding command and address pins are terminated via resistor termination within the memory device or are not terminated within the memory device.

19. The semiconductor device according to claim 17, wherein: The respective set of one or more additional pins for each of the plurality of memory devices includes a respective clock pin coupled to a clock line among the one or more signal lines; and In order to identify the termination configuration for the corresponding clock pin of the memory device, the corresponding controller of the memory device is configured to: The determination is made, at least in part, based on the detected termination status of the corresponding die-terminated pin, whether the corresponding clock pin is terminated via a resistor within the memory device or is not terminated within the memory device.

20. The semiconductor device according to claim 17, wherein: The respective set of one or more additional pins for each of the plurality of memory devices includes a respective chip select pin coupled to a chip select line among the one or more signal lines; and In order to identify the termination configuration of the corresponding chip select pin for the memory device, the corresponding controller of the memory device is configured to: The determination is made, at least in part, based on the detected termination status of the corresponding die-on termination pin, whether the corresponding chip select pin is terminated via a resistor within the memory device or is not terminated within the memory device.

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