Memory device and operating method thereof

Abstract

The present application relates to a memory device and an operating method thereof. The present technology relates to an electronic device. According to the present technology, a memory device with improved verification accuracy can include a memory block including memory cells, a read-write circuit including a plurality of page buffers, a current sensing circuit configured to perform a verification operation comparing a sensed voltage with a reference voltage, and a control logic configured to control the current sensing circuit to perform the verification operation. The control logic controls to perform a first verification operation for each page buffer group having the same logical group number, and to perform a second verification operation for each page buffer group having the same physical group number, and the current sensing circuit outputs a verification pass signal in response to both a result of the first verification operation and a result of the second verification operation satisfying a pass criterion.

Description

Technical Field

[0001] This disclosure relates to electronic devices, and more specifically, to memory devices and methods of operating the same. Background Technology

[0002] A storage device is a device that stores data under the control of a host device such as a computer or smartphone. A storage device may include a memory device for storing data and a memory controller for controlling the memory device. Memory devices can be classified as volatile memory devices and non-volatile memory devices.

[0003] A volatile memory device is a device that stores data only while powered on and loses the stored data when power is cut off. Volatile memory devices can include static random access memory (SRAM), dynamic random access memory (DRAM), and the like.

[0004] Non-volatile memory devices are devices that retain data even when power is cut off. Non-volatile memory devices include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, etc. Summary of the Invention

[0005] Embodiments of this disclosure provide a memory device with improved operating speed and a method for operating the same.

[0006] According to embodiments of this disclosure, a memory device may include: a memory block comprising memory cells; read / write circuitry including a plurality of page buffers respectively connected to the memory cells via multiple bit lines; a current sensing circuit configured to perform a verification operation comparing a sensed voltage received from the plurality of page buffers with a reference voltage corresponding to a number of error-correctable bits; and control logic configured to group the plurality of page buffers into a plurality of page buffer groups and control the current sensing circuit to perform a verification operation for each of the plurality of page buffer groups. The control logic is further configured to determine a logical group number and a physical group number corresponding to a column address of each of the plurality of page buffers, and is configured to control the current sensing circuit to perform a first verification operation on the sensed voltage of each page buffer group having the same logical group number, and a second verification operation on the sensed voltage of each page buffer group having the same physical group number. The current sensing circuit is also configured to output a verification pass signal in response to both the result of the first verification operation and the result of the second verification operation satisfying a pass criterion.

[0007] According to an embodiment of the present disclosure, a method of operating a memory device includes: a read / write circuit having a plurality of page buffers respectively connected via a plurality of bit lines to memory cells included in a memory block; a current sensing circuit configured to perform a verification operation comparing a sensed voltage received from the plurality of page buffers with a reference voltage corresponding to an error-correctable bit number; and control logic configured to group the plurality of page buffers into a plurality of page buffer groups and control the current sensing circuit to perform a verification operation for each of the plurality of page buffer groups. The method may include: determining that a predetermined number of page buffers having consecutive column addresses among the plurality of page buffers have the same logical group number; determining that a predetermined number of page buffers adjacent in the read / write circuit among the plurality of page buffers have the same physical group number; performing a first verification operation on the sensed voltage of each page buffer group having the same logical group number; performing a second verification operation on the sensed voltage of each page buffer group having the same physical group number; and outputting a verification pass signal in response to both the result of the first verification operation and the result of the second verification operation satisfying a pass criterion.

[0008] According to embodiments of this disclosure, a memory device may include: memory cells coupled to corresponding bit lines; page buffers coupled to the corresponding bit lines and each configured to sense the voltage of a corresponding memory cell in the memory cells; and control circuitry configured to perform a first verification operation and a second verification operation on memory cells in a first group and a second group respectively using the sensed voltages to determine whether the memory cells contain uncorrectable errors. The first group is coupled to a first number of bit lines having consecutive column addresses, and the second group is coupled to a second number of physically adjacent page buffers.

[0009] According to this technology, a memory device with improved accuracy in verification operations can be provided. Attached Figure Description

[0010] Figure 1 This is a diagram illustrating a storage device including a memory device according to an embodiment of the present disclosure.

[0011] Figure 2 This is an example of an embodiment according to the present disclosure. Figure 1 A diagram of a memory device.

[0012] Figure 3 This is an example of an embodiment according to the present disclosure. Figure 2 A diagram showing the configuration of the storage blocks.

[0013] Figure 4 This is a block diagram illustrating a verification operation according to an embodiment of the present disclosure.

[0014] Figure 5 The diagram illustrates successful and unsuccessful verification according to embodiments of this disclosure.

[0015] Figure 6 This is a diagram illustrating a method for determining logical group numbers and physical group numbers according to an embodiment of the present disclosure.

[0016] Figure 7 This is a block diagram illustrating a current sensing circuit according to an embodiment of the present disclosure.

[0017] Figure 8 This is an example of an embodiment according to the present disclosure. Figure 7 A diagram of a sensing voltage receiver and a comparison voltage generator.

[0018] Figure 9 This is an example of an embodiment according to the present disclosure. Figure 7 The diagram shows the comparator circuit and the reference voltage generator.

[0019] Figure 10 This is a diagram illustrating a method of grouping multiple page buffers into physical groups according to an embodiment of the present disclosure.

[0020] Figure 11 This is a flowchart illustrating a method for performing a verification operation according to an embodiment of the present disclosure.

[0021] Figure 12 This is a diagram illustrating a data processing system including a solid-state drive according to an embodiment of the present disclosure.

[0022] Figure 13 This is an example Figure 12 A diagram showing the configuration of the controller.

[0023] Figure 14 This is a diagram illustrating a data processing system including a data storage device according to an embodiment of the present disclosure.

[0024] Figure 15 This is a diagram illustrating a data processing system including a data storage device according to an embodiment of the present disclosure.

[0025] Figure 16 This is a diagram illustrating a network system including a data storage device according to an embodiment of the present disclosure. Detailed Implementation

[0026] The specific structural or functional descriptions of embodiments based on the concepts disclosed in this specification are merely illustrative of embodiments based on the concepts disclosed herein. Embodiments based on the concepts disclosed herein may be implemented in various forms and should not be construed as limited to those described in this specification.

[0027] Figure 1 This is a diagram illustrating a storage device including a memory device according to an embodiment of the present disclosure.

[0028] Reference Figure 1 The storage device 50 may include a memory device 100 and a memory controller 200 for controlling the operation of the memory device. The storage device 50 may be a device for storing data under the control of a host 300, such as a cellular phone, smartphone, MP3 player, laptop computer, desktop computer, game console, TV, tablet PC, or in-vehicle infotainment system.

[0029] Depending on the host interface, which serves as the communication method with the host 300, the storage device 50 can be manufactured as one of various types of storage devices. For example, the storage device 50 can be configured as one of various types of storage devices such as SSDs, multimedia cards in the form of MMC, eMMC, RS-MMC, and micro MMC, secure digital cards in the form of SD, mini SD, and micro SD, universal serial bus (USB) storage devices, universal flash memory (UFS) devices, PCMCIA card-type storage devices, peripheral component interconnect (PCI) card-type storage devices, high-speed PCI (PCI-e or PCIe) card-type storage devices, compact flash memory (CF) cards, smart media cards, and memory sticks.

[0030] Storage device 50 can be manufactured as one of various types of packages. For example, storage device 50 can be manufactured as one of various package types such as point-of-purchase (POP), system-in-package (SIP), system-on-chip (SOC), multi-chip package (MCP), chip-on-board (COB), wafer-level fabrication package (WFP), and wafer-level stacked package (WSP).

[0031] The memory device 100 can store data. The memory device 100 operates under the control of the memory controller 200. The memory device 100 may include a memory cell array (not shown) comprising a plurality of memory cells for storing data.

[0032] Each memory cell can be configured as a single-level cell (SLC) that stores one data bit, a multi-level cell (MLC) that stores two data bits, a three-level cell (TLC) that stores three data bits, or a four-level cell (QLC) that can store four data bits.

[0033] A memory cell array (not shown) may include multiple memory blocks. Each memory block may include multiple memory cells. A memory block may include multiple pages. In an embodiment, a page may be a unit for storing data in the memory device 100 or retrieving data stored in the memory device 100. A memory block may be a unit for erasing data.

[0034] In embodiments, the memory device 100 may be Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate 4 (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR), Rambus Dynamic Random Access Memory (RDRAM), NAND flash memory, Vertical NAND flash memory, NOR flash memory, Resistive Random Access Memory (RRAM), Phase Change Random Access Memory (PRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), Spin-Transfer Torque Random Access Memory (STT-RAM), etc. In this specification, for ease of description, the memory device 100 is referred to as NAND flash memory.

[0035] Memory device 100 can be configured to receive a command CMD and an address ADDR from memory controller 200 and access a region in the memory cell array selected by the address. Memory device 100 can perform operations indicated by the command CMD on the region selected by the address ADDR. For example, memory device 100 can perform programming operations, read operations, and erase operations. During a programming operation, memory device 100 can store data in the region selected by the address ADDR. During a read operation, memory device 100 can read data from the region selected by the address ADDR. During an erase operation, memory device 100 can erase data stored in the region selected by the address ADDR.

[0036] In this embodiment, the memory device 100 may include multiple planes. A plane can be a unit capable of performing operations independently. For example, the memory device 100 may include two planes, four planes, or eight planes. Multiple planes can simultaneously and independently perform each of a programming operation, a read operation, or an erase operation.

[0037] The memory controller 200 can control the overall operation of the storage device 50.

[0038] When power is applied to storage device 50, memory controller 200 may execute firmware (FW). When storage device 100 is a flash memory device, the firmware (FW) may include a host interface layer (HIL) that controls communication with host 300, and memory controller 200 may include a flash translation layer (FTL) that controls communication between host 300 and storage device 100, and a flash interface layer (FIL) that controls communication with storage device 100.

[0039] The memory controller 200 can receive write data and LBAs from the host 300, and can translate the LBAs into physical block addresses (PBAs), which indicate the address of the memory cell in the memory device 100 where the data is to be stored. In this specification, LBA and "logical address" or "logical address" can be used interchangeably. In this specification, PBA and "physical address" can be used interchangeably.

[0040] The memory controller 200 can control the memory device 100 to perform programming operations, read operations, erase operations, etc., according to the request of the host 300. During programming operations, the memory controller 200 can provide programming commands, PBAs, and data to the memory device 100. During read operations, the memory controller 200 can provide read commands and PBAs to the memory device 100. During erase operations, the memory controller 200 can provide erase commands and PBAs to the memory device 100.

[0041] In this implementation, the memory controller 200 can independently generate commands, addresses, and data independent of requests from the host 300, and send these commands, addresses, and data to the memory device 100. For example, the memory controller 200 can provide the memory device 100 with commands, addresses, and data for performing read operations and programming operations that accompany wear leveling, read recycling, garbage collection, etc.

[0042] In one implementation, the memory controller 200 can control at least two or more memory devices 100. In this case, the memory controller 200 can control the memory devices 100 according to an interleaving method to improve operational performance. The interleaving method can be a method of controlling the operation of at least two memory devices 100 to overlap with each other. Alternatively, the interleaving method can be a method in which at least two or more memory devices 100 operate in parallel.

[0043] A buffer memory (not shown) can temporarily store data provided from the host 300, i.e., data to be stored in the memory device 100, or can temporarily store data read from the memory device 100. In an embodiment, the buffer memory (not shown) can be a volatile memory device. For example, the buffer memory (not shown) can be dynamic random access memory (DRAM) or static random access memory (SRAM).

[0044] The host 300 can communicate with the storage device 50 using at least one of various communication standards or protocols such as Universal Serial Bus (USB), Serial AT Accessory (SATA), Serial Attached SCSI (SAS), High Speed ​​Chip Interconnect (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCIe), High Speed ​​Non-Volatile Memory (NVMe), Universal Flash Memory (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Load-Degraded DIMM (LRDIMM).

[0045] Figure 2 This is an example of an embodiment according to the present disclosure. Figure 1 A diagram of a memory device.

[0046] Reference Figure 2 The memory device 100 may include a memory cell array 110, an address decoder 120, a read / write circuit 130, control logic 140, a voltage generator 150, and a current sensing circuit 160. The address decoder 120, the read / write circuit 130, the voltage generator 150, and the current sensing circuit 160 may be referred to as peripheral circuits controlled by the control logic 140.

[0047] The memory cell array 110 may include a plurality of memory blocks BLK1 to BLKz. The plurality of memory blocks BLK1 to BLKz can be connected to the address decoder 120 via word lines WL. The plurality of memory blocks BLK1 to BLKz can be connected to the read / write circuitry 130 via bit lines BL1 to BLm. Each of the plurality of memory blocks BLK1 to BLKz may include a plurality of memory cells. In one embodiment, the plurality of memory cells are non-volatile memory cells and may be configured as non-volatile memory cells with a vertical channel structure. The memory cell array 110 may be configured as a two-dimensional memory cell array. In another embodiment, the memory cell array 110 may be an SLC storing one bit of data. In yet another embodiment, the plurality of memory cells included in the memory cell array 110 may be an MLC storing two bits of data. In yet another embodiment, the plurality of memory cells included in the memory cell array 110 may be a TLC storing three bits of data. In another embodiment, each of the plurality of memory cells included in the memory cell array 110 may be a QLC storing four bits of data. According to embodiments, the memory cell array 110 may include a plurality of memory cells each storing five or more bits of data.

[0048] Address decoder 120 can be connected to memory cell array 110 via word line WL. Address decoder 120 can be configured to operate in response to control of control logic 140. Address decoder 120 can receive addresses via input / output buffers (not shown) inside memory device 100.

[0049] Address decoder 120 can be configured to decode block addresses among received addresses. Address decoder 120 can select at least one memory block based on the decoded block address. Furthermore, during a read operation, address decoder 120 can apply a read voltage Vread generated in voltage generator 150 to the selected word line of the selected memory block during a read voltage application operation, and apply a voltage Vpass to the remaining unselected word lines. Additionally, during a programming verification operation, address decoder 120 can apply a verification voltage generated in voltage generator 150 to the selected word line of the selected memory block, and apply a voltage Vpass to the remaining unselected word lines.

[0050] Address decoder 120 can be configured to decode the column address in a received address. Address decoder 120 can then send the decoded column address to read / write circuitry 130.

[0051] Read and programming operations on the memory device 100 can be performed on a page-by-page basis. The address received when requesting a read or program operation may include a block address, a row address, and a column address. The address decoder 120 can select a memory block and a word line based on the block address and row address. The column address can be decoded by the address decoder 120 and provided to the read / write circuitry 130. In this specification, a memory cell connected to a word line may be referred to as a "physical page".

[0052] The read / write circuit 130 may include multiple page buffers PB1 to PBm. The read / write circuit 130 can operate as a "read circuit" during read operations of the memory cell array 110 and as a "write circuit" during write operations of the memory cell array 110. The multiple page buffers PB1 to PBm can be connected to the memory cell array 110 via bit lines BL1 to BLm. During read and program verification operations, in order to sense the threshold voltage of the memory cell, the multiple page buffers PB1 to PBm can sense changes in the amount of current flowing according to the programming state of the corresponding memory cell through sensing nodes while continuously providing sensing current to the bit lines connected to the memory cell, and latch the sensed changes as sensed data. The read / write circuit 130 can operate in response to a page buffer control signal output from control logic 140. In this specification, the write operation of the write circuit can be used to have the same meaning as a programming operation on a selected memory cell.

[0053] During a read operation, the read / write circuit 130 can sense data in the memory cell, temporarily store the read data, and output the data to an input / output buffer (not shown) of the memory device 100. In embodiments, in addition to a page buffer (or page register), the read / write circuit 130 may also include a column select circuit, etc. According to embodiments of this disclosure, the read / write circuit 130 may be a page buffer.

[0054] Control logic 140 can be connected to address decoder 120, read / write circuitry 130, voltage generator 150, and current sensing circuitry 160. Control logic 140 can receive commands CMD and control signals CTRL via input / output buffers (not shown) of memory device 100. Control logic 140 can be configured to control the overall operation of memory device 100 in response to control signal CTRL. Furthermore, control logic 140 outputs control signals for adjusting the precharge potential levels of sensing nodes in multiple page buffers PB1 to PBm. Control logic 140 can control read / write circuitry 130 to perform read operations on memory cell array 110.

[0055] Control logic 140 can determine whether the verification operation for a specific target programming state passes or fails in response to a verification pass signal PASS or a verification fail signal FAIL received from current sensing circuit 160.

[0056] Voltage generator 150 generates a read voltage Vread and a pass voltage Vpass during a read operation in response to a control signal output from control logic 140. To generate multiple voltages with various voltage levels, voltage generator 150 may include multiple pump capacitors that receive an internal power supply voltage. Voltage generator 150 may generate multiple voltages by selectively activating the multiple pump capacitors in response to control from control logic 140.

[0057] The current sensing circuit 160 can generate a reference current and a reference voltage in response to the enable bit VRY_BTI<#> received from the control logic 140 during the verification operation. The verification pass signal PASS or verification failure signal FAIL can be output by comparing the generated reference voltage with the sensed voltage VPB received from the page buffers PB1 to PBm included in the read / write circuit 130, or by comparing the generated reference current with the sensed current received from the page buffers PB1 to PBm included in the read / write circuit 130.

[0058] The address decoder 120, read / write circuit 130, voltage generator 150, and current sensing circuit 160 can be used as "peripheral circuitry" to perform read, write, and erase operations on the memory cell array 110. The peripheral circuitry can perform read, write, and erase operations on the memory cell array 110 based on the control logic 140.

[0059] Figure 3 This is an example of an embodiment according to the present disclosure. Figure 2 A diagram showing the configuration of any of the storage blocks.

[0060] Storage block BLKz is Figure 2 Storage blocks BLK1 to BLKz include storage block BLKz.

[0061] Reference Figure 3 Multiple word lines arranged in parallel to each other can be connected between a first select line and a second select line. Here, the first select line can be a source select line (SSL), and the second select line can be a drain select line (DSL). More specifically, the memory block BLKz can include multiple strings (ST) connected between bit lines BL1 to BLm and the source line SL. Bit lines BL1 to BLm can be connected to strings ST individually, and the source line SL can be connected together to strings ST. Since strings ST can be configured equally to each other, the string connected to the first bit line BL1 is described specifically as an example.

[0062] A string may include a source selection transistor SST connected in series between the source line SL and the first bit line BL1, a plurality of memory cells MC1 to MC16, and a drain selection transistor DST. A string may include at least one or more of the source selection transistor SST and the drain selection transistor DST, and may include more than the number of memory cells MC1 to MC16 shown in the figure.

[0063] The source of the source select transistor SST can be connected to the source line SL, and the drain of the drain select transistor DST can be connected to the first bit line BL1. Memory cells MC1 to MC16 can be connected in series between the source select transistor SST and the drain select transistor DST. The gate of the source select transistor SST included in different string STs can be connected to the source select line SSL, the gate of the drain select transistor DST can be connected to the drain select line DSL, and the gate of memory cells MC1 to MC16 can be connected to multiple word lines WL1 to WL16. A group of memory cells connected to the same word line among the memory cells included in different string STs can be called a page PG. Therefore, the memory block BLKz can include the number of page PGs equal to the number of word lines WL1 to WL16.

[0064] A memory cell can store one bit of data. This is often referred to as SLC. In this case, a physical page (PG) can store one logical page (LPG) of data. A logical page (LPG) of data can include the same number of data bits as the cells included in a physical page (PG).

[0065] A memory cell can store two or more bits of data. In this case, a physical page (PG) can store two or more logical pages (LPGs) of data.

[0066] Figure 4 This is a block diagram illustrating a verification operation according to an embodiment of the present disclosure.

[0067] Reference Figure 4 The control logic can control peripheral circuitry, including page buffers and current sensing circuitry. This peripheral circuitry can perform write, read, and erase operations on the memory blocks included in the memory cell array. The peripheral circuitry can apply voltages to the word lines and bit lines of the memory cells included in the memory blocks. For example, the peripheral circuitry can perform a programming operation comprising multiple programming cycles. Each of the multiple programming cycles can include a programming pulse application operation that increases the threshold voltage of the memory cell by applying a programming pulse, and a verification operation that verifies whether the threshold voltage of the memory cell has reached a target threshold voltage.

[0068] According to embodiments of this disclosure, control logic 140 can send control signals to read / write circuit 130 and current sensing circuit 160. Memory cell array 110 may include multiple memory blocks. The multiple memory blocks can be connected to read / write circuit 130 via bit lines BL. Each of the multiple memory blocks may include multiple memory cells.

[0069] The read / write circuit 130 may include multiple page buffers. These page buffers can be connected to the memory cell array 110 via bit lines. The page buffers can send sensed data corresponding to the amount of current flowing according to the programming state of the corresponding memory cell to the current sensing circuit 160.

[0070] The current sensing circuit 160 can receive sensing data from the read / write circuit 130 to perform a verification operation. The verification operation can be an operation to determine whether a memory cell has been programmed to a target state, and can include individual verification operations and overall verification operations.

[0071] The current sensing circuit 160 can generate a reference current and a reference voltage corresponding to the number of error-correctable bits, and can generate a sense current and a sense voltage based on the sensed data. The current sensing circuit 160 can compare the reference voltage and the sensed voltage with each other, and send a verification pass signal or a verification failure signal to the control logic 140. The current sensing circuit 160 can perform a verification operation that compares the sensed voltage received from multiple page buffers with the reference voltage corresponding to the number of error-correctable bits.

[0072] Control logic 140 can group multiple page buffers into multiple page buffer groups. Control logic 140 can control current sensing circuit 160 to perform a verification operation on each of the multiple page buffer groups.

[0073] Control logic 140 can determine the logical group number and physical group number corresponding to the column address of each of the plurality of page buffers. Control logic 140 can be controlled to perform a first verification operation, which is a verification operation for each page buffer group having the same logical group number. Control logic 140 can be controlled to perform a second verification operation, which is a verification operation for each page buffer group having the same physical group number.

[0074] The current sensing circuit 160 can output a verification pass signal in response to the fact that both the results of the first verification operation and the results of the second verification operation meet the pass criteria. The current sensing circuit 160 can also execute the first and second verification operations in reverse order. The current sensing circuit 160 can output a verification failure signal in response to the result of the first verification operation that does not meet the pass criteria. Even if the result of the first verification operation meets the pass criteria, the current sensing circuit 160 can still output a verification failure signal if the result of the second verification operation does not meet the pass criteria.

[0075] Control logic 140 can determine that page buffers with consecutive column addresses among multiple page buffers have the same logical group number. In this case, the number of page buffers with the same logical group number can be predetermined. For example, when the column addresses of the multiple page buffers are from number 0 to number 1024, the number of page buffers with the same logical group number can be determined to be 128. Control logic 140 can determine that the logical group number of the page buffers corresponding to column addresses from number 0 to number 127 is number 0. Similarly, control logic 140 can determine that the logical group number of the page buffers corresponding to column addresses from number 128 to number 255 is number 1.

[0076] Control logic 140 can determine that adjacent page buffers in read / write circuit 130 among multiple page buffers have the same physical group number. The number of page buffers with the same physical group number can be predetermined. For example, the number of page buffers with the same physical group number can be determined to be 128. Control logic 140 can determine that 128 adjacent page buffers in read / write circuit 130 have physical group number 0. The column addresses of page buffers with this physical group number can have a difference of 8. That is, for a page buffer with physical group number 0, the column address can be number 0, number 8, number 16, ..., number 1016.

[0077] In embodiments of this disclosure, control logic 140 may determine logical group numbers and physical group numbers based on the layout of multiple page buffers. The layout of the multiple page buffers may vary depending on the design of the memory device.

[0078] Control logic 140 can send a first signal indicating the page buffer corresponding to the logic group number to the current sensing circuit. For example, the first signal can indicate that the logic group number of the page buffer corresponding to column addresses from 0 to 127 is 0, and the logic group number of the page buffer corresponding to column addresses from 128 to 255 is 1.

[0079] Control logic 140 may send a second signal indicating the page buffer corresponding to a physical group number to the current sensing circuit. For example, the second signal may indicate that the physical group number of the page buffer corresponding to the low byte in memory bank (memory) number 0 is number 0, and the physical group number of the page buffer corresponding to the high byte in memory bank number 0 is number 1. In another embodiment of this disclosure, the second signal may indicate that the physical group number of a page buffer in which the column address of the page buffer has a difference of 8 (such as 0, 8, 16, ..., 1016) is number 0.

[0080] Figure 5 The diagram illustrates successful and unsuccessful verification according to embodiments of this disclosure.

[0081] Reference Figure 5 The current sensing circuit can output a verification pass signal only when both the logic verification operation and the physical verification operation meet the pass conditions.

[0082] The current sensing circuit can perform both logical and physical verification operations. It can perform verification operations on a per-page buffer group basis. Logical verification can be performed using verification operations corresponding to each page buffer group with the same logical group number. Physical verification can be performed using verification operations corresponding to each page buffer group with the same physical group number.

[0083] The control logic can control the current sensing circuit to perform logic verification operations. The control logic can send a first signal, indicating the page buffers corresponding to their respective logic group numbers, to the current sensing circuit. The current sensing circuit can then perform logic verification operations on page buffers with the same logic group number based on the first signal.

[0084] The control logic can send a second signal, indicating the page buffers corresponding to the physical group numbers, to the current sensing circuit. The current sensing circuit can then perform a physical verification operation on page buffers with the same physical group number based on the second signal.

[0085] The current sensing circuit can output a verification pass signal only when both the results of the logic verification operation and the physical verification operation meet the verification pass condition. The current sensing circuit can perform the logic verification operation first, followed by the physical verification operation. Conversely, the current sensing circuit can perform the physical verification operation first, followed by the logic verification operation.

[0086] When either the result of the logical verification operation or the result of the physical verification operation fails to meet the pass condition, the current sensing circuit can output a verification failure signal. In embodiments of this disclosure, the pass conditions for the logical verification operation and the physical verification operation can be different from each other.

[0087] The current sensing circuit compares the sensed voltage corresponding to the page buffer group with a reference voltage corresponding to the number of error-correctable bits. When the failure bits included in the page buffer group are distributed, failure bits may still exist even if the verification is passed. Because the column addresses of the page buffers included in the page buffer group are different from each other, the logical verification operation and the physical verification operation can complement each other.

[0088] Figure 6 This is a diagram illustrating a method for determining logical group numbers and physical group numbers according to an embodiment of the present disclosure.

[0089] Reference Figure 6 A physical page can be divided into four memory banks. Each memory bank can be further divided into low bytes and high bytes. Figure 6 In this context, the page buffers corresponding to column addresses numbered 0 to 1023 are grouped. Figure 6 This shows the logic group number 0INVER_LOG. <0> The page buffer and the corresponding physical group number 0INVER_PHY <0> Page buffer.

[0090] Corresponding to logic group number 0INVER_LOG <0> The column addresses of the page buffers can be consecutive. In embodiments of this disclosure, the page buffers corresponding to column addresses numbered 0 to 127 can correspond to logical group number 0INVER_LOG. <0> (610). Despite Figure 6 The page buffers corresponding to column addresses 128 to 255 are not shown, but they can correspond to logical group number 1. Similarly, page buffers for logical groups 2 to 6 can be grouped. The column addresses of the page buffer corresponding to logical group number 7 can be from 896 to 1023.

[0091] Corresponding to physics group number 0INVER_PHY <0> The page buffer can be the page buffer (620) corresponding to the low byte of memory bank 0. This corresponds to physical group number 0INVER_PHY. <0> The column address of the page buffer can have a difference of 8. For example, corresponding to physical group number 0INVER_PHY <0> The column addresses of the 128 page buffers can be numbered 0, 8, 16, ..., 1016.

[0092] Similarly, the page buffer corresponding to physical group number 1 can be the page buffer corresponding to the high byte of memory bank 0. The page buffer corresponding to physical group number 2 can be the page buffer corresponding to the high byte of memory bank 1. The page buffer corresponding to physical group number 3 can be the page buffer corresponding to the low byte of memory bank 1. The page buffer corresponding to physical group number 4 can be the page buffer corresponding to the low byte of memory bank 2. The page buffer corresponding to physical group number 5 can be the page buffer corresponding to the high byte of memory bank 2. The page buffer corresponding to physical group number 6 can be the page buffer corresponding to the high byte of memory bank 3. The page buffer corresponding to physical group number 7 can be the page buffer corresponding to the low byte of memory bank 3. The column address of the page buffer corresponding to each of physical group numbers 1 to 7 can also have a difference of 8.

[0093] Figure 7 This is a block diagram illustrating a current sensing circuit according to an embodiment of the present disclosure.

[0094] Reference Figure 7 The current sensing circuit may include at least one or more comparators. The number of comparators may be the same as the number of page buffer groups. For example, when the number of page buffer groups is eight, the number of comparators included in the current sensing circuit may also be eight. Figure 7 The comparator corresponding to group number 0 among at least one or more comparators can be shown.

[0095] In embodiments of this disclosure, the current sensing circuit can sum and output the outputs of the comparator. When all outputs of the comparator are verified as passed, the current sensing circuit can output a verification signal relative to all page buffers.

[0096] The comparator may include a sense voltage receiver, a comparison voltage generator, a reference voltage generator, a comparator circuit, and a power supply. The sense voltage receiver 710 may receive sensed data from multiple page buffers. In embodiments of this disclosure, the sense voltage receiver 710 may receive a sensed voltage. The sensed voltage may be a voltage stored in a latch circuit of a page buffer.

[0097] In embodiments of this disclosure, the sensing voltage receiver 710 can receive sensing data from "m" number of page buffers. The sensing voltage receiver 710 can receive sensing voltages SO1, ..., SOm from page buffer numbers 1 to m. The sensing voltage receiver 710 can provide the received sensing data to the comparison voltage generator 720.

[0098] The comparison voltage generator 720 can generate a comparison voltage based on a first signal and a second signal received from the control logic. This comparison voltage is the sum of the sensed voltages to be compared with a reference voltage. The comparison voltage generator 720 can provide the generated comparison voltage to the comparison circuit 740 through the positive terminal VP of the comparison circuit 740.

[0099] In embodiments of this disclosure, the first signal may be a signal indicating a page buffer corresponding to a logical group number. The second signal may be a signal indicating a page buffer corresponding to a physical group number. The first signal may include a signal SEL_LOG for selecting the page buffer corresponding to logical group number 0 among the page buffers. <0> The second signal may include the signal SEL_PHY for selecting the page buffer corresponding to physical group number 0 in the page buffer. <0> In embodiments of this disclosure, SEL_LOG <0> and SEL_PHY <0> Not both can be turned on at the same time.

[0100] The reference voltage generator 730 can generate a reference voltage corresponding to the number of error-correctable bits. The reference voltage generator 730 can provide the generated reference voltage to the comparator circuit 740 through the negative terminal VN of the comparator circuit 740.

[0101] Comparator circuit 740 can output a comparison result Vout0 obtained by comparing the comparison voltage with a reference voltage. Comparator circuit 740 can output a verification failure signal in response to the comparison voltage exceeding the reference voltage. Comparator circuit 740 can output a verification success signal in response to the comparison voltage being less than or equal to the reference voltage.

[0102] In embodiments of this disclosure, the comparison voltage generator 720 can generate a logic comparison voltage as the sum of sensed voltages corresponding to the first signal. The comparison circuit 740 can perform a first verification operation by comparing the logic comparison voltage with a reference voltage. The comparison circuit 740 can output the comparison result of the first verification operation. At this time, the comparison voltage generator 720 can generate the logic comparison voltage using at least two or more transistors connected in series.

[0103] In embodiments of this disclosure, the comparison voltage generator 720 can generate a physical comparison voltage as the sum of sensed voltages corresponding to the second signal. The comparison circuit 740 can perform a second verification operation by comparing the physical comparison voltage with a reference voltage. The comparison circuit 740 can output the comparison result of the second verification operation. In this case, the comparison voltage generator 720 can use at least two or more transistors connected in series to generate the physical comparison voltage.

[0104] The reference voltage generator 730 can generate a first reference voltage corresponding to a comparison voltage generated based on a first signal. The reference voltage generator 730 can also generate a second reference voltage corresponding to a comparison voltage generated based on a second signal.

[0105] In embodiments of this disclosure, the first reference voltage and the second reference voltage may be different from each other. The first reference voltage and the second reference voltage may vary depending on the number of active transistors among the plurality of transistors included in the reference voltage generator 730.

[0106] Figure 8 This is an example Figure 7 A diagram of a sensing voltage receiver and a comparison voltage generator.

[0107] Reference Figure 8 The sensing voltage receiver 710 can be implemented with a number of "2m" transistors, and the comparison voltage generator can be implemented with a number of "2m+2" transistors. Figure 8 In this context, the number of page buffers is "m".

[0108] The sensed voltages SO1, ..., SOm received by the sensed voltage receiver 710 can be input to m transistors TR21, ..., TR2m, respectively. The transistors connected in series within the sensed voltage receiver 710 can indicate the sensed data received from the page buffer. The sensed voltage receiver 710 can provide the sensed voltage to the comparator voltage generator 720.

[0109] The comparison voltage generator 720 can generate a comparison voltage for the comparison circuit 740 based on a first signal and a second signal from the sensed voltage provided by the sensed voltage receiver 710. The comparison voltage generator 720 can generate both a logic comparison voltage and a physical comparison voltage using 2m transistors TR31, ..., TR3m and TR41, ..., TR4m. The comparison voltage generator 720 can use two transistors TR5 and TR6 to provide one of the logic comparison voltage and the physical comparison voltage to the comparison circuit 740.

[0110] exist Figure 8 In this configuration, the number of page buffers is 1024, and the column address of the sensed voltage connected via TR31 and TR41 is number 0. Furthermore, the column address of the sensed voltage connected via TR3n and TR4n is number 513, and the column address of the sensed voltage connected via TR3m and TR4m is number 1023.

[0111] With logic group number 0INVER_LOG <0> The corresponding column address of the page buffer can be from number 0 to number 127. This is related to the physical group number 0 in the `INVER_PHY` column. <0> The column addresses of the corresponding 128 page buffers can be numbered 0, 8, 16, ..., 1016. This corresponds to the physical group number 0INVER_PHY. <0> The column address of the corresponding page buffer can have a difference of 8.

[0112] Since transistors TR31 and TR41, corresponding to column address 0, correspond to logic group number 0INVER_LOG <0> and physics group number 0INVER_PHY <0> Therefore, SEL_LOG <0> It can be applied to TR31 and SEL_PHY <0> It can be applied to TR41. Since transistors TR3n and TR4n, corresponding to column address 513, do not correspond to logic group number 0INVER_LOG <0> and physics group number 0INVER_PHY <0> Therefore, UNSEL_LOG <0> It can be applied to TR3n, and UNSEL_PHY <0> It can be applied to TR4n. Since transistors TR3m and TR4m, corresponding to column address 1023, do not correspond to logic group number 0INVER_LOG... <0> And corresponding to the physics group number 0INVER_PHY <0> Therefore, UNSEL_LOG <0> It can be applied to TR3m, and SEL_PHY <0> It can be applied to TR4m.

[0113] In embodiments of this disclosure, the SEL_LOG applied to TR5 can be used as a reference. <0> To select the logical verification operation. Based on the SEL_PHY applied to TR6. <0> You can choose physical verification.

[0114] Figure 9 This is an example of an embodiment according to the present disclosure. Figure 7 The diagram shows the comparator circuit and the reference voltage generator.

[0115] Reference Figure 9 The reference voltage generator 730 may include multiple transistors TR71, TR72, TR81, TR82, TR91, and TR92. The comparator circuit 740 may be configured with a differential amplifier.

[0116] The reference voltage generator 730 can generate a reference voltage corresponding to the number of error-correctable bits. TR81 and TR82, included in the reference voltage generator 730, can indicate the number of error-correctable bits. In embodiments of this disclosure, with Figure 9 Unlike other components, TR83 and TR84 can be included in the reference voltage generator 730.

[0117] The reference voltage generated by the reference voltage generator 730 can vary depending on the number of transistors included.

[0118] In embodiments of this disclosure, TR71 and TR72 can be added to match the current path. In response to the comparison voltage input to the positive terminal VP of the comparator circuit 740 via four transistors, a reference voltage input to the negative terminal VN of the comparator circuit 740 can also be input via the four transistors. A predetermined voltage drop may occur as the reference voltage passes through the transistors.

[0119] Comparator circuit 740 compares the provided comparison voltage with a reference voltage. The comparison result can be fed back as the gate voltages of transistors TR81 and TR82, which indicate the error-correctable bit number of the reference voltage generator 730.

[0120] When the comparison voltage supplied through the positive terminal VP of comparator circuit 740 is a logic comparison voltage, the output Vout1 can be a logic verification result. In this case, output Vout1 can be the verification result for logic group number 0. Similarly, when the comparison voltage supplied through the positive terminal VP of comparator circuit 740 is a physical comparison voltage, the output Vout1 can be a physical verification result. In this case, output Vout1 can be the verification result for physical group number 0.

[0121] Figure 10 This is a diagram illustrating a method of grouping multiple page buffers into physical groups according to an embodiment of the present disclosure.

[0122] Reference Figure 10 Physical pages can be grouped into 16 physical groups. Physical pages can be partitioned according to the memory bank number of the cell matrix. Furthermore, within the same memory bank number, physical pages can be divided into low bytes and high bytes. Additionally, within the low byte, physical pages can be partitioned based on whether the bit line number is odd or even (1010).

[0123] exist Figure 10 In this context, the logical group number can be determined by the column address. The physical group number within a physical page can be determined based on adjacent page buffers. In embodiments of this disclosure, the physical group number can be determined based on the bit line number. A page buffer with odd bit line numbers can have a different physical group number than a page buffer with even bit line numbers.

[0124] In another embodiment of this disclosure, the physical group number can be determined such that the bit line numbers are consecutive (1020). According to embodiments of this disclosure, adjacent page buffers in a physical page can be grouped together. The number of page buffer groups can be 16. The number of page buffers corresponding to the physical group number can be the same.

[0125] Figure 11 This is a flowchart illustrating a method for performing a verification operation according to an embodiment of the present disclosure.

[0126] Reference Figure 11 Verification operations can be performed within the memory device. Verification operations can be performed on each page buffer group with the same logical group number. Verification operations can also be performed on each page buffer group with the same physical group number. The current sensing circuit can output a verification pass signal in response to both the results of the logical verification operation and the results of the physical verification operation meeting the verification pass criteria.

[0127] In operation S1110, the control logic can determine that a predetermined number of page buffers with consecutive column addresses have the same logical group number. In operation S1120, the control logic can determine that a predetermined number of page buffers adjacent to each other in the read / write circuit have the same physical group number.

[0128] The control logic can group multiple page buffers into multiple page buffer groups. The control logic can control the current sensing circuitry to perform a verification operation on each of the multiple page buffer groups. The control logic can determine the logical group number and physical group number corresponding to the column address of each of the multiple page buffers.

[0129] The control logic can determine that page buffers with consecutive column addresses among multiple page buffers have the same logical group number. In this case, the number of page buffers with the same logical group number can be predetermined. For example, when the column addresses of multiple page buffers range from 0 to 1024, the number of page buffers with the same logical group number can be determined to be 128. The control logic can determine that the logical group number of the page buffers corresponding to column addresses from 0 to 127 is 0. Similarly, the control logic can determine that the logical group number of the page buffers corresponding to column addresses from 128 to 255 is 1.

[0130] The control logic can determine that adjacent page buffers in the read / write circuit 130 have the same physical group number. The number of page buffers with the same physical group number can be predetermined. For example, the control logic can determine that 128 adjacent page buffers in the read / write circuit 130 belong to physical group number 0. The column addresses of page buffers with physical group numbers have a difference of 8. That is, for a page buffer with physical group number 0, the column address could be number 0, number 8, number 16, ..., number 1016.

[0131] In embodiments of this disclosure, the control logic can determine the logical group number and physical group number based on the layout of the multiple page buffers. The layout of the multiple page buffers can vary depending on the design of the memory device.

[0132] In operation S1130, the control logic can control the execution of a first verification operation, which is a verification operation for each page buffer group having the same logic group number. The control logic can send a first signal indicating the page buffer corresponding to the logic group number to the current sensing circuit.

[0133] The control logic can send a first signal indicating the page buffer corresponding to the logic group number to the current sensing circuit. For example, the first signal can indicate that the logic group number of the page buffer corresponding to column addresses from 0 to 127 is 0, and the logic group number of the page buffer corresponding to column addresses from 128 to 255 is 1.

[0134] In operation S1140, the control logic can control the execution of a second verification operation, which is a verification operation for each page buffer group with the same physical group number. The control logic can send a second signal indicating the page buffer corresponding to the physical group number to the current sensing circuit.

[0135] Control logic 140 may send a second signal indicating the page buffer corresponding to a physical group number to the current sensing circuit. For example, the second signal may indicate that the physical group number of the page buffer corresponding to the low byte in memory bank number 0 is number 0, and the physical group number of the page buffer corresponding to the high byte in memory bank number 0 is number 1. In another embodiment of this disclosure, the second signal may indicate that the physical group number of a page buffer in which the column address of the page buffer has a difference of 8 (such as 0, 8, 16, ..., 1016) is number 0.

[0136] In operation S1150, the current sensing circuit can output a verification pass signal in response to both the results of the first verification operation and the results of the second verification operation meeting the verification pass criteria. The current sensing circuit can also execute the first and second verification operations in reverse order. The current sensing circuit can output a verification failure signal in response to the result of the first verification operation not meeting the pass criteria. Even if the result of the first verification operation meets the pass criteria, the current sensing circuit can still output a verification failure signal if the result of the second verification operation does not meet the pass criteria.

[0137] The current sensing circuit can output a pass signal only when both the logical and physical verification operations meet the pass conditions. The current sensing circuit compares the sensed voltage corresponding to the page buffer group with a reference voltage corresponding to the number of error-correctable bits. When the failure bits included in the page buffer group are distributed, failure bits may still exist even if a pass signal is output. Because the column addresses of the page buffers included in the page buffer group are different from each other, the logical and physical verification operations can be complementary.

[0138] When either the result of the logical verification operation or the result of the physical verification operation fails to meet the pass condition, the current sensing circuit can output a verification failure signal. In embodiments of this disclosure, the pass conditions for the logical verification operation and the physical verification operation can be different from each other.

[0139] Figure 11 The verification operation can correspond to the reference. Figures 4 to 9 The verification operation described in this disclosure.

[0140] Figure 12 This is a diagram illustrating a data processing system including a solid-state drive (SSD) according to an embodiment of the present disclosure. (Refer to...) Figure 12 The data processing system 2000 may include a host device 2100 and an SSD 2200.

[0141] The SSD 2200 may include a controller 2210, a buffer memory device 2220, non-volatile memory 2231 to 223n, a power supply 2240, a signal connector 2250, and a power connector 2260. The controller 2210 can control the overall operation of the SSD 2200.

[0142] The buffer memory device 2220 can temporarily store data to be stored in the non-volatile memories 2231 to 223n. Furthermore, the buffer memory device 2220 can temporarily store data read from the non-volatile memories 2231 to 223n. Under the control of the controller 2210, the data temporarily stored in the buffer memory device 2220 can be sent to the host device 2100 or the non-volatile memories 2231 to 223n.

[0143] Non-volatile memories 2231 to 223n can be used as storage media for the SSD 2200. Each of the non-volatile memories 2231 to 223n can be connected to the controller 2210 through multiple channels CH1 to CHn. One or more non-volatile memories can be connected to one channel. Non-volatile memories connected to one channel can be connected to the same signal bus and data bus.

[0144] Power supply 2240 can provide power PWR, which is input through power connector 2260, to SSD 2200. Power supply 2240 may include auxiliary power supply 2241. Auxiliary power supply 2241 can provide power to enable SSD 2200 to terminate normally in the event of a sudden power failure. Auxiliary power supply 2241 may include a large-capacity capacitor capable of charging power PWR.

[0145] The controller 2210 can exchange signals SGL with the host device 2100 via signal connector 2250. Here, signal SGL may include commands, addresses, data, etc. Depending on the interface method between the host device 2100 and the SSD 2200, signal connector 2250 can be configured as various types of connectors.

[0146] Figure 13 This is an example of an embodiment according to the present disclosure. Figure 12 A diagram showing the controller configuration. (Refer to...) Figure 13 The controller 2210 may include a host interface unit 2211, a control unit 2212, a random access memory 2213, an error correction code (ECC) unit 2214, and a memory interface unit 2215.

[0147] The host interface unit 2211 can interface with the host device 2100 and the SSD 2200 according to the protocol of the host device 2100. For example, the host interface unit 2211 can communicate with the host device 2100 via one of the following protocols: Secure Digital, Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), PCMCIA, Parallel Advanced Technology Attachment (PATA), Serial Advanced Technology Attachment (SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI), Fast PCI (PCI-e or PCIe), and Universal Flash Memory (UFS). Furthermore, the host interface unit 2211 can perform disk emulation functions that enable the host device 2100 to recognize the SSD 2200 as a general-purpose data storage device (e.g., a hard disk drive (HDD)).

[0148] Control unit 2212 can analyze and process the signal SGL input from host device 2100. Control unit 2212 can control the operation of internal function blocks according to the firmware or software used to drive SSD 2200. Random access memory 2213 can be used as operating memory to drive such firmware or software.

[0149] ECC unit 2214 can generate parity data for the data to be sent to non-volatile memories 2231 to 223n. The generated parity data can be stored together with the data in non-volatile memories 2231 to 223n. ECC unit 2214 can detect errors in the data read from non-volatile memories 2231 to 223n based on the parity data. When the detected error is within the correction range, ECC unit 2214 can correct the detected error.

[0150] The memory interface unit 2215, under the control of the control unit 2212, can provide control signals such as commands and addresses to the non-volatile memories 2231 to 223n. Furthermore, the memory interface unit 2215, under the control of the control unit 2212, can exchange data with the non-volatile memories 2231 to 223n. For example, the memory interface unit 2215 can provide data stored in the buffer memory device 2220 to the non-volatile memories 2231 to 223n, or provide data read from the non-volatile memories 2231 to 223n to the buffer memory device 2220.

[0151] Figure 14 This is a diagram illustrating a data processing system including a data storage device according to an embodiment of the present disclosure. (Refer to...) Figure 14 The data processing system 3000 may include a host device 3100 and a data storage device 3200.

[0152] The host device 3100 may be configured as a board, such as a printed circuit board. Although not shown, the host device 3100 may include internal function blocks for performing the functions of the host device.

[0153] The host device 3100 may include connection terminals 3110 such as sockets, slots, or connectors. The data storage device 3200 may be mounted on the connection terminals 3110.

[0154] The data storage device 3200 can be configured in the form of a board, such as a printed circuit board. The data storage device 3200 can be referred to as a memory module or a memory card. The data storage device 3200 may include a controller 3210, a buffer memory device 3220, non-volatile memory 3231 to 3232, a power management integrated circuit (PMIC) 3240, and a connection terminal 3250.

[0155] The controller 3210 can control the overall operation of the data storage device 3200. The controller 3210 can interact with... Figure 12 The controller 2210 shown is configured identically.

[0156] The buffer memory device 3220 can temporarily store data to be stored in the non-volatile memories 3231 to 3232. Furthermore, the buffer memory device 3220 can temporarily store data read from the non-volatile memories 3231 to 3232. Under the control of the controller 3210, the data temporarily stored in the buffer memory device 3220 can be sent to the host device 3100 or the non-volatile memories 3231 to 3232.

[0157] Non-volatile memories 3231 to 3232 can be used as storage media for data storage device 3200.

[0158] The PMIC 3240 can supply power to the data storage device 3200 via the connection terminal 3250. The PMIC 3240 can manage the power supply of the data storage device 3200 under the control of the controller 3210.

[0159] Connection terminal 3250 can be connected to connection terminal 3110 of the host device. Power and signals such as commands, addresses, and data can be transmitted between the host device 3100 and the data storage device 3200 via connection terminal 3250. Connection terminal 3250 can be configured in various types depending on the interface method between the host device 3100 and the data storage device 3200. Connection terminal 3250 can be located on either side of the data storage device 3200.

[0160] Figure 15 This is a diagram illustrating a data processing system including a data storage device according to an embodiment of the present disclosure. (Refer to...) Figure 15 The data processing system 4000 may include a host device 4100 and a data storage device 4200.

[0161] The host device 4100 may be configured as a board, such as a printed circuit board. Although not shown, the host device 4100 may include internal function blocks for performing the functions of the host device.

[0162] The data storage device 4200 can be configured in a surface mount package. The data storage device 4200 can be mounted on the host device 4100 via solder balls 4250. The data storage device 4200 may include a controller 4210, a buffer memory device 4220, and a non-volatile memory 4230.

[0163] The controller 4210 can control the overall operation of the data storage device 4200. The controller 4210 can interact with... Figure 12 The controller 2210 shown is configured similarly.

[0164] The buffer memory device 4220 can temporarily store data to be stored in the non-volatile memory 4230. Furthermore, the buffer memory device 4220 can temporarily store data read from the non-volatile memory 4230. Under the control of the controller 4210, the data temporarily stored in the buffer memory device 4220 can be sent to the host device 4100 or the non-volatile memory 4230.

[0165] The non-volatile memory 4230 can be used as the storage medium of the data storage device 4200.

[0166] Figure 16 This is a diagram illustrating a network system including a data storage device according to an embodiment of the present disclosure. (Refer to...) Figure 16 The network system 5000 may include a server system 5300 and multiple client systems 5410 to 5430 connected via the network 5500.

[0167] Server system 5300 can service data in response to requests from multiple client systems 5410 to 5430. For example, server system 5300 can store data provided from multiple client systems 5410 to 5430. As another example, server system 5300 can provide data to multiple client systems 5410 to 5430.

[0168] Server system 5300 may include host device 5100 and data storage device 5200. Data storage device 5200 may include... Figure 1 Storage device 50 Figure 12 SSD 2200, Figure 14 Data storage device 3200 and Figure 15 Data storage device 4200.

[0169] Because this disclosure can be implemented in other specific forms without altering its technical spirit or essential characteristics, those skilled in the art to which this disclosure pertains should understand that the above embodiments are illustrative and not limited in any respect. The scope of this disclosure is indicated by the claims to be described below rather than by detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be included within the scope of this disclosure. Furthermore, embodiments can be combined to form additional embodiments.

[0170] Cross-references to related applications

[0171] This application claims priority to Korean Patent Application No. 10-2021-0105640, filed on August 10, 2021, the entire contents of which are incorporated herein by reference.

Claims

1. A memory device, the memory device comprising: Storage block, the storage block comprising memory units; A read / write circuit, the read / write circuit including multiple page buffers respectively connected to the memory cell via multiple bit lines; A current sensing circuit that performs a verification operation by comparing the sensed voltage received from the plurality of page buffers with a reference voltage corresponding to the number of error-correctable bits; as well as The control logic groups the plurality of page buffers into a plurality of page buffer groups and controls the current sensing circuit to perform the verification operation for each of the plurality of page buffer groups. The control logic further determines the logical group number and physical group number of each of the plurality of page buffers based on the column address of each of the plurality of page buffers, and controls the current sensing circuit to perform a first verification operation on the sensed voltage of each page buffer group having the same logical group number, and a second verification operation on the sensed voltage of each page buffer group having the same physical group number. In this context, page buffers with the same logical group number have consecutive column addresses. In this context, the column addresses of page buffers with the same physical group number increase sequentially with the number of physical groups, and... The current sensing circuit also outputs a verification pass signal in response to the fact that both the result of the first verification operation and the result of the second verification operation meet the pass criteria.

2. The memory device according to claim 1, wherein, The control logic determines a predetermined number of page buffers with consecutive column addresses among the plurality of page buffers as having the same logical group number.

3. The memory device according to claim 2, wherein, The control logic determines a predetermined number of page buffers that are adjacent in the read / write circuit among the plurality of page buffers as having the same physical group number.

4. The memory device according to claim 3, wherein, The control logic determines the logical group number and the physical group number based on the layout of the plurality of page buffers.

5. The memory device according to claim 3, wherein, The control logic also sends a first signal to the current sensing circuit indicating the page buffer corresponding to the logic group number.

6. The memory device according to claim 5, wherein, The control logic also sends a second signal to the current sensing circuit, indicating the page buffer corresponding to the physical group number.

7. The memory device according to claim 6, wherein, The current sensing circuit includes: A sensing voltage receiver, which receives the sensing voltage from the plurality of page buffers; A comparison voltage generator generates a comparison voltage based on the first signal and the second signal, the comparison voltage being the sum of the sensed voltages to be compared with the reference voltage; A reference voltage generator, which generates the reference voltage; and A plurality of comparators, each of the plurality of comparators including a comparator circuit that outputs a comparison result obtained by comparing the comparison voltage with the reference voltage.

8. The memory device according to claim 7, wherein, The comparison voltage generator generates a logic comparison voltage as the sum of the sensed voltages corresponding to the first signal, which is then used as the comparison voltage.

9. The memory device according to claim 8, wherein, The comparison circuit performs the first verification operation by comparing the logic comparison voltage with the reference voltage, and outputs the comparison result of the first verification operation.

10. The memory device according to claim 8, wherein, The comparison voltage generator uses at least two or more transistors connected in series to generate the logic comparison voltage.

11. The memory device according to claim 7, wherein, The comparison voltage generator generates a physical comparison voltage as the sum of the sensed voltages corresponding to the second signal.

12. The memory device according to claim 11, wherein, The comparison circuit performs the second verification operation by comparing the physical comparison voltage with the reference voltage, and outputs the comparison result of the second verification operation.

13. The memory device according to claim 11, wherein, The comparison voltage generator uses at least two or more transistors connected in series to generate the physical comparison voltage.

14. The memory device according to claim 7, wherein, The reference voltage generator generates a first reference voltage corresponding to the comparison voltage generated based on the first signal as the reference voltage, and generates a second reference voltage corresponding to the comparison voltage generated based on the second signal as the reference voltage.

15. The memory device according to claim 14, wherein, The first reference voltage and the second reference voltage are different from each other.

16. The memory device according to claim 14, wherein, The reference voltage generator also includes at least one transistor corresponding to the number of transistors constituting the comparison voltage generator.

17. The memory device according to claim 7, wherein, The number of comparators is the same as the number of the plurality of page buffer groups.

18. A method of operating a memory device, the memory device comprising: A read / write circuit, the read / write circuit including multiple page buffers that are respectively connected to memory cells included in the memory block via multiple bit lines; A current sensing circuit that performs a verification operation by comparing the sensed voltage received from the plurality of page buffers with a reference voltage corresponding to the number of error-correctable bits; The method includes control logic that groups the plurality of page buffers into a plurality of page buffer groups and controls the current sensing circuit to perform the verification operation for each of the plurality of page buffer groups. The logical group numbers of page buffers with consecutive column addresses among the plurality of page buffers are determined to be the same; The physical group numbers of the page buffers whose column addresses are sequentially increased by the number of physical groups are determined to be the same. A first verification operation is performed on the sensed voltage for each of the page buffer groups having the same logical group number; Perform a second verification operation on the sensed voltage of each of the page buffer groups having the same physical group number; and A verification pass signal is output in response to the fact that both the result of the first verification operation and the result of the second verification operation meet the pass criteria.

19. The method of claim 18, further comprising the step of: Send a first signal to the current sensing circuit indicating the page buffer corresponding to the logic group number; as well as A second signal is sent to the current sensing circuit to indicate the page buffer corresponding to the physical group number.

20. The method according to claim 19, wherein, The step of outputting the verification pass signal includes the following steps: The sensed voltage is received from the plurality of page buffers; A comparison voltage is generated based on the first signal and the second signal, wherein the comparison voltage is the sum of the sensed voltages that are to be compared with the reference voltage. Generate the reference voltage; and The output is the comparison result obtained by comparing the comparison voltage with the reference voltage.

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