High-reliability fast read-write OTP embedded memory and read-write method thereof
By employing an M×N antifuse memory module array with a shared word line in the OTP embedded memory, the problems of power consumption, time consumption, and large area in the prior art are solved, achieving highly reliable fast read and write and simplifying the design of peripheral circuits.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SICHUAN KILOWAY TECHNOLOGIES CO LTD
- Filing Date
- 2022-12-30
- Publication Date
- 2026-07-31
AI Technical Summary
Existing OTP embedded memories require frequent switching of word line voltages during write and read operations, which increases power consumption, time consumption, circuit complexity, and occupies a large area.
An M×N antifuse memory module array is adopted, with each module containing two gate capacitors sharing a word line. This eliminates the need for WL decoding circuits and high-voltage level conversion circuits, and enables fast read and write operations by sharing a common row line, thereby reducing the complexity and area of the external circuitry.
It achieves highly reliable and fast read/write, and has the advantages of saving power, time and chip area, simplifying the design of peripheral circuits.
Smart Images
Figure CN115938449B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to integrated circuit technology, and in particular to a highly reliable, fast read / write OTP embedded memory and its read / write method. Background Technology
[0002] US patents US6,667,902, US6,700,151B2, US6,798,693B2, and US6,650,143B1 disclose XPM memory technology, which can be seen as prior art. Figure 1 Existing technologies require independent WL and WS decoders. The word line WS uses LV or IO devices. During write (programming, Prog) and read operations, the voltage on the word line WL needs to be constantly switched from Vpp to Vdd / Float, requiring a decoder or level conversion circuit. This results in drawbacks such as high power consumption, long processing time, complex circuitry, and large footprint.
[0003] Table 1 shows the operating voltages of the prior art. Taking a 0.18-micron CMOS process as an example, Vpp=8V, Vcc=1.8V, Vdd=3.3V, and Vrd=Vdd / Vcc. The symbol " / " indicates "or".
[0004] Table 1
[0005]
[0006] Meaning:
[0007] Prog: Programming (Writing Data)
[0008] Read: Reading
[0009] SXSY: Select X, select Y (select row, select column)
[0010] SXUY: Select X, not Y (rows selected, columns not selected)
[0011] UXSY: Select Y (rows not selected, columns selected)
[0012] UXUY: Neither X nor Y is selected (rows and columns are not selected).
[0013] WS(X): The WS line of x rows
[0014] BL(Y): The BL line in column Y
[0015] Prog: Writing (or Programming)
[0016] Read: Reading
[0017] Vrd: Read voltage
[0018] dVox: Voltage difference across the gate capacitor
[0019] Vpp: Programming voltage
[0020] Float: floats. Summary of the Invention
[0021] The technical problem to be solved by the present invention is to provide a highly reliable, fast read / write OTP embedded memory and its read / write method, which has the characteristics of power saving, time saving and small area.
[0022] The technical solution adopted by this invention to solve the aforementioned technical problem is a highly reliable, fast read / write OTP embedded memory, comprising an array composed of M×N antifuse storage modules, where M and N are both integers greater than 2, characterized in that...
[0023] Each antifuse storage module includes a first storage unit and a second storage unit.
[0024] The first memory cell is composed of a first select MOS transistor, a first isolation MOS transistor and a first gate capacitor. One active terminal of the first select MOS transistor is connected to the column line of the column where it is located, and the other active terminal is connected to the active terminal of the first gate capacitor through the first isolation MOS transistor.
[0025] The second memory cell consists of a second gate capacitor, a second isolation MOSFET, and a second selection MOSFET. One active terminal of the second selection MOSFET is connected to the column line of the column, and the other active terminal is connected to the active terminal of the second gate capacitor through the second isolation MOSFET.
[0026] The gate capacitor consists of a gate plate, an active region, and a gate oxide layer between the two.
[0027] The gate terminals of the first gate capacitor and the second gate capacitor are connected to the first common row line (WL).
[0028] The gate of the first isolation MOSFET is connected to the first isolation line (WB1).
[0029] The gate of the second isolation MOSFET is connected to the second isolation line (WB2).
[0030] The gate terminal of the first selected MOSFET is connected to the first row line (WS1) of the row.
[0031] The gate terminal of the second selected MOSFET is connected to the second row line (WS2) of the row.
[0032] The first common line in each row is connected to the others.
[0033] All first and second isolation lines are connected to the same common point;
[0034] The antifuse storage module includes six type B doped regions arranged sequentially along the column lines within the type A doped region, wherein...
[0035] The first and second class-B doped regions constitute the source and drain regions of the first-select MOSFET.
[0036] The second and third type B doped regions constitute the source and drain regions of the first isolated MOSFET.
[0037] The third type B doped region, the shared gate plate, and the oxide layer between them constitute the first gate capacitance;
[0038] The fourth Class B doped region, the shared gate plate, and the oxide layer between them constitute the second gate capacitance;
[0039] The fourth and fifth type B doped regions constitute the source and drain regions of the second isolated MOSFET.
[0040] The fifth and sixth type B doped regions constitute the source and drain regions of the second-select MOSFET.
[0041] The type A doped region is an N-type doped region, and the type B doped region is a P-type doped region; or the type A doped region is a P-type doped region, and the type B doped region is an N-type doped region.
[0042] This invention also provides a highly reliable and fast read / write method for OTP embedded memory, which has the characteristics of saving power and time for selected storage cells of the aforementioned highly reliable and fast read / write OTP embedded memory.
[0043] The writing steps include:
[0044] (p1) Connect a voltage level sufficient to turn on the MOSFET to the first common row line (WL);
[0045] (p2) Connect a voltage level sufficient to turn on the MOSFET at the common point;
[0046] (p3) Apply a voltage level sufficient to turn on the MOS transistor to the row line (WS) connected to the gate terminal of the select MOS transistor in the write target memory cell;
[0047] (p4) The column line of the column where the target memory cell is located is grounded, and the column line of the column not connected to the target memory cell is connected to a high level or floating.
[0048] The reading steps include:
[0049] (r1) Connect the read level to the first common row line (WL);
[0050] (r2) Read the level at the common point;
[0051] (r3) Apply the read level to the row line (WS) connected to the gate terminal of the select MOS transistor in the target memory cell;
[0052] (r4) The column line (BL) of the column where the target memory cell is located is grounded, and the column line of the column not connected to the target memory cell is connected to the read level or floated.
[0053] In this invention, each antifuse memory module includes two gate capacitors, which share a single word line WL, saving chip area. Furthermore, in this invention, the common row line WL (word line) in all rows is connected during write and read operations, eliminating the need for a WL decoding circuit and a high-voltage level conversion circuit, significantly reducing the complexity and footprint of the external circuitry.
[0054] This invention requires only one power-on time for both write and read operations, and has the advantages of saving power, saving time, and having a small footprint. Attached Figure Description
[0055] Figure 1 It is a circuit diagram of existing technology.
[0056] Figure 2 This is the circuit diagram of the present invention.
[0057] Figure 3 This is a schematic diagram of the structure of an antifuse storage module in this invention.
[0058] Explanation of reference numerals in the attached figures:
[0059] WS1: First line
[0060] WS2: Second line
[0061] BL: Column line (bit line)
[0062] WB1: First isolation line
[0063] WB2: Second isolation line
[0064] WL: First Public Lane
[0065] 101: Second choice MOSFET gate plate
[0066] 102: Gate plate of the second isolated MOSFET
[0067] 103: Gate plate of the first isolated MOSFET
[0068] 104: First choice MOSFET gate plate
[0069] 105: First connecting line
[0070] 106: First Class B Doped Region
[0071] 107: Second Class B doped region
[0072] 108: Class A doped region
[0073] 109: The third type B doped region
[0074] 110: Intra-unit isolation zone
[0075] 111: Oxides
[0076] 112: The fourth type B doped region
[0077] 113: The fifth type B doped region
[0078] 114: The sixth type B doped region
[0079] 115: Second connecting line
[0080] 116: Top wire
[0081] 201: First choice MOSFET
[0082] 202: First isolation MOSFET
[0083] 203: First gate capacitance
[0084] 204: Second gate capacitor
[0085] 205: Second isolation MOSFET
[0086] 206: Second choice MOSFET. Detailed Implementation
[0087] In this invention, "active terminal" refers to the circuit connection terminal of the active region. See also... Figure 3 The first Class B doped region 106 and the second Class B doped region 107 constitute the source and drain regions of the first selected MOSFET. The source and drain terminals of the first selected MOSFET are collectively referred to as the active terminals. The first gate capacitor, which is composed of the third Class B doped region 109, the shared gate plate 117, and the oxide between them, is equivalent to half a MOSFET. The circuit connection terminal of its active region is also called the "active terminal".
[0088] Row lines are character lines, and column lines are position lines.
[0089] The present invention includes an array consisting of M×N antifuse storage modules, where M and N are both integers greater than 4. Figure 2 An array (2 rows and 4 columns) consisting of 2×4 antifuse memory modules is shown, with each antifuse memory module located within an elliptical region.
[0090] Each antifuse storage module includes a first storage unit and a second storage unit.
[0091] The first memory cell is composed of a first selection MOS transistor 201, a first isolation MOS transistor 202 and a first gate capacitor 203. One active terminal of the first selection MOS transistor 201 is connected to the column line of the column where it is located, and the other active terminal is connected to the active terminal of the first gate capacitor 203 through the first isolation MOS transistor 202.
[0092] The second memory cell is composed of a second gate capacitor 204, a second isolation MOS transistor 205, and a second selection MOS transistor 206. One active terminal of the second selection MOS transistor 206 is connected to the column line of the column, and the other active terminal is connected to the active terminal of the second gate capacitor 204 through the second isolation MOS transistor 205.
[0093] The gate capacitor consists of a gate plate, an active region, and a gate oxide layer between them. See [link to relevant documentation]. Figure 3 The third type B doped region 109 serves as the active region in the gate capacitor, and the shared gate plate 117 serves as the gate plate of the gate capacitor. The oxide between the two is the gate oxide layer.
[0094] Figure 3 The internal structure of an antifuse memory module is shown, with the X direction being... Figure 2 The direction of the line, the Y direction is Figure 2 The antifuse memory module includes six Class B doped regions arranged sequentially along the column direction in the Class A doped region 108. Class A doping and Class B doping represent two different doping types, one of which is N-type doping and the other is P-type doping.
[0095] The first Class B doped region 106 and the second Class B doped region 107 constitute the source and drain regions of the first selected MOSFET. 104 is the gate plate of the first selected MOSFET. The first Class B doped region 106 is connected to the top conductor 116 through the first connecting line 105. The top conductor 116 serves as a column line.
[0096] The second type B doped region 107 and the third type B doped region 109 constitute the source and drain regions of the first isolated MOSFET, and 103 is the gate plate of the first isolated MOSFET.
[0097] The third type B doped region 109, the shared gate plate 117, and the oxide layer between them constitute the first gate capacitance.
[0098] The fourth type B doped region 112, the shared gate plate 117, and the oxide layer between them constitute the second gate capacitor.
[0099] Below the shared grid 117 is an internal isolation area 110, which is made of insulating material.
[0100] The fourth Class B doped region 112 and the fifth Class B doped region 113 constitute the source and drain regions of the second isolation MOSFET, and 102 is the gate plate of the second isolation MOSFET.
[0101] The fifth Class B doped region 113 and the sixth Class B doped region 114 constitute the source and drain regions of the second selected MOSFET, and 101 is the gate plate of the second selected MOSFET.
[0102] The sixth type B doped region 114 is connected to the top conductor 116 via the second connecting line 115;
[0103] The type A doped region is an N-type doped region, and the type B doped region is a P-type doped region; or the type A doped region is a P-type doped region, and the type B doped region is an N-type doped region.
[0104] Figure 2 The internal structure of the antifuse memory module consisting of 201 to 206 is as follows: Figure 3 As shown, Figure 3 As a module, it is extended and arranged along the XY direction to form an array (the active regions of adjacent units are isolated by an insulating medium). The shared grid plate 117 in the same row is a whole, corresponding to Figure 2 In WL, the gate plate 104 of the first selected MOSFET in the same row is a whole, corresponding to Figure 2 WS1. Therefore, it can be seen that the present invention can greatly save space.
[0105] The operating voltage table for this embodiment is shown in Table 2, where Vpp=8V, Vdd=3.3V, Vcc=1.8V, Vrd=Vdd / Vcc, and the symbol " / " represents "or"; X and Y represent the serial number (row number and column number). WB1 and WB2 in each row are connected to the same common point, referred to as WB.
[0106] Compared with Table 1, the voltage of WL remains stable during the writing process and the reading process remains unchanged, thus saving the area of the external circuit.
[0107] Table 2
[0108]
[0109] The above operating voltage indicates the read / write method of the highly reliable and fast OTP embedded memory of the present invention, specifically including the following steps:
[0110] The writing steps include:
[0111] (p1) Connect the breakdown level Vpp to the first common line (WL);
[0112] (p2) Enable Vdd access at the common point;
[0113] (p3) Apply Vcc level to the row line connected to the gate terminal of the select MOS transistor in the write target memory cell to enable it;
[0114] (p4) The column line of the column where the target memory cell is located is grounded, and the column line of the column not connected to the target memory cell is connected to a high level or floating.
[0115] The reading steps include:
[0116] (r1) Connect the read level Vrd to the first common row line (WL);
[0117] (r2) Connect the common point to read the voltage level Vrd;
[0118] (r3) Apply the read level Vrd to the row line connected to the gate terminal of the select MOS transistor in the target memory cell;
[0119] (r4) The column line of the column where the target memory cell is located is grounded, and the column line of the column not connected to the target memory cell is connected to the read level Vrd or floated.
[0120] Compared to Table 1, this invention does not require frequent switching of the WL voltage, which can save on external decoder circuitry.
Claims
1. A highly reliable, fast read / write OTP embedded memory, comprising an array of M×N antifuse memory modules, where M and N are both integers greater than 2, characterized in that... Each antifuse storage module includes a first storage unit and a second storage unit. The first memory cell is composed of a first select MOS transistor, a first isolation MOS transistor and a first gate capacitor. One active terminal of the first select MOS transistor is connected to the column line of the column where it is located, and the other active terminal is connected to the active terminal of the first gate capacitor through the first isolation MOS transistor. The second memory cell consists of a second gate capacitor, a second isolation MOSFET, and a second selection MOSFET. One active terminal of the second selection MOSFET is connected to the column line of the column, and the other active terminal is connected to the active terminal of the second gate capacitor through the second isolation MOSFET. The first gate capacitor and the second gate capacitor are each composed of a gate plate, an active region and a gate oxide layer between them; The gate terminals of the first gate capacitor and the second gate capacitor are connected to the first common row line (WL). The gate of the first isolation MOSFET is connected to the first isolation line (WB1). The gate of the second isolation MOSFET is connected to the second isolation line (WB2). The gate terminal of the first selected MOSFET is connected to the first row line (WS1) of the row. The gate terminal of the second selected MOSFET is connected to the second row line (WS2) of the row. All rows are connected by their first common row line; All first and second isolation rows are connected to the same common point.
2. The high reliable fast read-write OTP embedded memory of claim 1, wherein, The antifuse storage module includes six type B doped regions arranged sequentially along the column lines within the type A doped region, wherein... The first Class B doped region (106) and the second Class B doped region (107) constitute the source and drain regions of the first selected MOSFET. The second type B doped region (107) and the third type B doped region (109) constitute the source and drain regions of the first isolated MOS transistor. The third type B doped region (109), the shared gate plate (117), and the oxide layer between them constitute the first gate capacitance; The fourth type B doped region (112), the shared gate plate (117), and the oxide layer between them constitute the second gate capacitance; The fourth type B doped region (112) and the fifth type B doped region (113) constitute the source and drain regions of the second isolation MOS transistor. The fifth type B doped region (113) and the sixth type B doped region (114) constitute the source and drain regions of the second-select MOSFET. The type A doped region is an N-type doped region, and the type B doped region is a P-type doped region; or the type A doped region is a P-type doped region, and the type B doped region is an N-type doped region.
3. A highly reliable and fast OTP embedded memory read / write method, characterized in that, The high-reliability, fast-read / write OTP embedded memory includes an array of M×N antifuse memory modules, where M and N are both integers greater than 2. Each antifuse memory module includes a first memory cell and a second memory cell. The first memory cell consists of a first select MOS transistor, a first isolation MOS transistor, and a first gate capacitor. One active terminal of the first select MOS transistor is connected to the column line of the column it belongs to, and the other active terminal is connected to the active terminal of the first gate capacitor through the first isolation MOS transistor. The second memory cell consists of a second gate capacitor, a second isolation MOSFET, and a second selection MOSFET. One active terminal of the second selection MOSFET is connected to the column line of the column, and the other active terminal is connected to the active terminal of the second gate capacitor through the second isolation MOSFET. The first gate capacitor and the second gate capacitor are each composed of a gate plate, an active region and a gate oxide layer between them; The gate terminals of the first gate capacitor and the second gate capacitor are connected to the first common row line (WL). The gate of the first isolation MOSFET is connected to the first isolation line (WB1). The gate of the second isolation MOSFET is connected to the second isolation line (WB2). The gate terminal of the first selected MOSFET is connected to the first row line (WS1) of the row. The gate terminal of the second selected MOSFET is connected to the second row line (WS2) of the row. The first common line in each row is interconnected. All first and second isolation lines are connected to the same common point; The writing steps include: (p1) Connect the breakdown level to the first common line (WL); (p2) Connect a voltage level sufficient to turn on the MOSFET at the common point; (p3) Connect the row line connected to the gate terminal of the select MOS transistor in the write target memory cell to a level sufficient to turn on the MOS transistor; (p4) The column line of the column where the target memory cell is located is grounded, and the column line of the column not connected to the target memory cell is connected to a high level or floating. The reading steps include: (r1) Connect the read level to the first common row line (WL); (r2) Read the level at the common point; (r3) Apply the read level to the row line connected to the gate terminal of the select MOS transistor in the target memory cell; (r4) The column line of the column where the target memory cell is located is grounded, and the column line of the column not connected to the target memory cell is connected to the read level or floated.