Wafer structure

Abstract

A wafer structure and a method of trimming the same. The method of trimming includes the following steps. A first wafer is provided, the first wafer having a first surface and a second surface opposite the first surface. A first pre-trim mark is formed on the first surface of the first wafer, wherein forming the first pre-trim mark includes forming a plurality of grooves arranged in a path along a periphery of the first wafer. The first wafer is trimmed on and along the path of the first pre-trim mark to remove a portion of the first wafer and form a trimmed edge having a plurality of first regions on the trimmed edge.

Description

[0001] This invention is a divisional application of the invention patent application filed on November 13, 2018, with application number 201811346956.1 and invention title "Wafer Structure and its Trimming Method". Technical Field

[0002] The embodiments of the present invention relate to a wafer structure and a method for trimming the same, particularly to a semiconductor wafer structure having trimmed edges and a method for trimming the outer edges of the semiconductor wafer structure. Background Technology

[0003] In recent years, due to the demand for miniaturization of semiconductor chips, the requirements for wafer thinning processes in semiconductor manufacturing have become more stringent. Generally, during the wafer thinning process, the grinding process performed on the back side of the semiconductor wafer may damage the wafer edges. Subsequently, an edge trimming process can be performed to remove the outer edges of the wafer. Summary of the Invention

[0004] According to some embodiments, a trimming method is provided. The trimming method includes the following steps: A first wafer is provided, the first wafer having a first surface and a second surface opposite to the first surface. A first pre-trimming mark is formed on the first surface of the first wafer, wherein forming the first pre-trimming mark includes forming a plurality of grooves arranged along a path along the periphery of the first wafer. The first wafer is trimmed on the first pre-trimming mark and along the path of the first pre-trimming mark to remove a portion of the first wafer and form a trimmed edge having a plurality of first regions.

[0005] According to some alternative embodiments, a trimming method is provided. The trimming method includes the following steps: providing a first wafer having a first surface and a second surface opposite to the first surface; performing a first marking trimming step on the first wafer along a thickness direction from the first surface to remove annular structures surrounding the periphery of the first wafer; forming a stacked wafer structure by providing a second wafer and stacking the second wafer onto the first surface of the first wafer; performing a second marking trimming step on the stacked wafer structure along the thickness direction from the second surface of the first wafer to remove edge portions of the stacked wafer structure.

[0006] According to some alternative embodiments, a wafer structure is provided. A wafer has a first surface, a second surface opposite to the first surface, and an edge connecting the first surface and the second surface. The edge is substantially perpendicular to the first surface and the second surface of the wafer, and the edge has a plurality of first regions surrounded by second regions, each of the first regions being separated and spaced apart from each other by the second regions, and the texture features of the second regions being different from the texture features of the first regions. Attached Figure Description

[0007] A thorough understanding of the various aspects of this disclosure will be best achieved by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of explanation.

[0008] Figures 1A to 1H A schematic cross-sectional view showing a method for trimming a stacked wafer structure according to some embodiments of the present disclosure.

[0009] Figure 2A A schematic top view of a first wafer after the formation of a first pre-trimmed mark is shown, according to some embodiments of the present disclosure.

[0010] Figure 2B and Figure 2C A schematic perspective view of a marking and trimming process performed on a first wafer according to some embodiments is shown.

[0011] Figure 2D Some embodiments according to this disclosure are shown. Figure 2C A schematic enlarged cross-sectional view of the edge surface in region A shown.

[0012] Figure 3A A schematic top view of a stacked wafer structure after the formation of a second pre-trimmed mark, according to some embodiments of the present disclosure.

[0013] Figure 3B and Figure 3C A schematic perspective view shows a marking and trimming process performed on a first wafer and a second wafer according to some embodiments of the present disclosure.

[0014] Figure 3D Some embodiments according to this disclosure are shown. Figure 3C A schematic enlarged cross-sectional view of the edge surface in region D shown.

[0015] Figure 4A This illustrates the process before performing the second trimming step according to some embodiments of the present disclosure. Figure 1F A schematic enlarged cross-sectional view of region B shown.

[0016] Figure 4BSome embodiments according to this disclosure are shown. Figure 1H A schematic enlarged cross-sectional view of region C shown.

[0017] Explanation of icon numbers

[0018] 50: First pre-trim mark

[0019] 50a, 70a: Groove

[0020] 60: Repair tools

[0021] 70: Second pre-trim mark

[0022] 100: First chip

[0023] 102: First Surface

[0024] 103, 204, 303: Bottom surface

[0025] 104: Second Surface

[0026] 106, 206: Edges

[0027] 106a, 302: Trimmed edges

[0028] 110a: Defect

[0029] 112: Device

[0030] 120: Circuit Layer

[0031] 130: Precision Protrusion

[0032] 140: Backside alignment mark

[0033] 200: Second chip

[0034] 202: Top surface

[0035] 300: Stacked chip structure

[0036] 310: Edge section

[0037] A, B, C, D: Regions

[0038] C1: Main crack section

[0039] C2: Middle crack section

[0040] d1, d2: Marker depth

[0041] D1: Thickness direction

[0042] Es: Etching marks

[0043] O1, O2: Openings

[0044] P1, P2: Pitch

[0045] Pt1: Trimming Depth / Thickness / First Thickness

[0046] Pt2: Trimming depth / thickness / second thickness

[0047] Pt3: Trimming Depth / Thickness / Third Thickness

[0048] Pw1: First width

[0049] Pw2: Second width

[0050] Pw3: Third width

[0051] R1, R3: Zone 1

[0052] R2, R4: Second Zone

[0053] T1: Thickness

[0054] TF1, TF2, TF3, TF4: Texture Features

[0055] TR1, TR2, TR3: Ring structure

[0056] Wl: Fine features Detailed Implementation

[0057] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be reused in various instances of this disclosure. Such reuse is for the sake of brevity and clarity and does not in itself imply a relationship between the various embodiments and / or configurations discussed.

[0058] Furthermore, for ease of explanation, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship between one element or feature shown in the figures and another element or feature. These spatially relative terms are intended to cover different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptions used herein will be interpreted accordingly.

[0059] Figures 1A to 1H A schematic cross-sectional view illustrating a method for trimming a stacked wafer structure according to some embodiments of the present disclosure. (Refer to...) Figure 1A A first wafer 100 is provided. In some embodiments, the first wafer 100 has a first surface 102, a second surface 104 opposite to the first surface 102, and an edge 106 connecting the first surface 102 and the second surface 104. For example, the side containing the first surface 102 may be referred to as the front side of the first wafer 100, and the opposite side containing the second surface 104 may be referred to as the back side of the first wafer 100. The first wafer 100 may have any suitable size and shape. In some embodiments, the first wafer 100 is substantially a circular wafer. Figure 1A Edge 106 is shown as a curved edge or a rounded edge. In other embodiments, the first wafer 100 may have a chamfered edge or a beveled edge.

[0060] In some embodiments, the first wafer 100 may be a semiconductor wafer, such as a bulk silicon wafer or a gallium arsenide wafer. In some embodiments, the first wafer 100 may comprise, for example, silicon, strained silicon, silicon alloy, silicon carbide, silicon germanium, silicon carbide germanium, germanium, germanium alloy, germanium arsenide, indium arsenide, or group III-V semiconductors. In some embodiments, the first wafer 100 is a device wafer. In some embodiments, the first wafer 100 includes a plurality of devices 112, which may be formed on a first surface 102 of the first wafer 100. The devices 112 may be, for example, photosensitive devices or image sensors capable of converting light into electrical signals, which are formed on and located on the front side of the first wafer 100. In some embodiments, the devices 112 may include, for example, a photodiode (PD), a phototransistor, or a combination thereof. In some embodiments, device 112 may include, for example, a complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) or a charge-coupled device (CCD) sensor. Device 112 is located relatively remote from edge 106 (the periphery of the first wafer 100) to allow subsequent finishing processes to be performed without damaging device 112. In some embodiments, additional semiconductor devices or electrical components with different functions or integrated circuits may also be included in the first wafer 100. In some embodiments, interconnect structures (not shown) electrically coupled to device 112 and / or other electrical components may be formed on the first wafer 100. The scope of this disclosure is not limited to the embodiments or figures described herein.

[0061] After the first chip 100 is provided, a first marking-trimming step is performed. Figure 2A A schematic top view of a first wafer after the formation of a first pre-trimmed mark is shown, according to some embodiments of the present disclosure. Figure 2B and Figure 2C A schematic perspective view shows a marking and trimming process performed on a first wafer according to some embodiments of the present disclosure. Figure 2D Some embodiments according to this disclosure are shown. Figure 2C A schematic enlarged cross-sectional view of the edge surface in region A shown. (Refer to...) Figures 2A to 2CIn some embodiments, the first wafer 100 may be a circular wafer, and a first pre-trimming mark 50 is formed on a first surface 102 of the first wafer 100 to define an annular ring TR1. In some embodiments, the annular ring TR1 defined between the first pre-trimming mark 50 and the edge 106 of the first wafer 100 (i.e., the periphery of the first wafer 100) has a first width Pw1. In some embodiments, the first pre-trimming mark 50 may be formed as a discontinuous pattern or an intermittent pattern on the first surface 102. In some embodiments, the first pre-trimming mark 50 includes a plurality of grooves 50a, and the grooves 50a are individual narrow trenches separated from each other. For example, the grooves 50a are arranged in a circular path along the periphery of the first wafer 100 to form the first pre-trimming mark 50.

[0062] In some embodiments, the groove 50a is formed by etching (e.g., wet etching or dry etching). In some embodiments, the groove 50a is formed by laser marking or other suitable marking processes. Each groove 50a may include a marking depth d1 relative to a reference plane corresponding to the first surface 102 of the first wafer 100. Figure 2B The marking depth d1 of each groove 50a shown may be between 10 μm and 150 μm, preferably between 80 μm and 120 μm. It should be noted that the marking depth d1 may vary depending on the trimming depth of the wafer in subsequent trimming steps. It should be understood that the number, shape, or size of the grooves 50a and their arrangement may be modified according to product design requirements. In some embodiments, the intermittent pattern of the first pre-trimming marks 50 may include individual grooves 50a separated from each other and spaced apart by a fixed pitch. In some embodiments, any two nearest adjacent grooves 50a are spaced apart by a pitch P1. For example, the pitch P1 between these two nearest adjacent grooves 50a may be between 5 μm and 100 μm, preferably between 8 μm and 40 μm. In some embodiments, the sum of the pitches P1 along a circular path may be approximately half the total length of the circular path. For example, the grooves 50a may be uniformly distributed on the first surface 102 as a circular path along the periphery of the first wafer 100. It should be noted that the pitch P1 can be modified according to the wafer size and design requirements. In some other embodiments, the ratio of the sum of the pitches P1 along the circular path to the total length of the circular path of the first pre-trimming mark 50 is between 30% and 80%. In alternative embodiments, the pattern of the first pre-trimming mark 50 may be sporadic. In other embodiments, the pattern includes individual grooves 50a that are separated from each other and spaced apart by various pitches.

[0063] After the first pre-trim mark 50 is formed, the first trimming step is performed. Figures 2A to 2C The process shown can be referred to as the first marking and finishing step. For example, by means of... Figures 2B to 2C and Figure 1B As shown, a first trimming step is performed along the first pre-trimming mark 50 to remove the annular structure TR1 surrounding the periphery of the first wafer 100 from the first wafer 100. In some embodiments, the first trimming step includes cutting or trimming away a portion of the first wafer 100 by machining perpendicularly downwards from the first surface 102 along the thickness direction D1 (i.e., cutting toward the second surface 104 but not through the second surface 104) to achieve the desired effect. Figure 2C and Figure 1B A trimmed edge 106a is formed near the periphery of the first wafer 100. In some embodiments, the first trimming step is performed by trimming tool 60 cutting substantially vertically or obliquely into the first wafer 100 to a trimming depth Pt1. In some embodiments, during the first trimming step, the first wafer 100 is cut directly above the first pre-trimming mark 50 and the first pre-trimming mark 50 is cut through, resulting in a trimming depth Pt1 greater than the marking depth d1 of the groove 50a of the first pre-trimming mark 50. In some embodiments, the trimming tool includes a scribing wheel or a trimming blade wheel. Alternatively, the first trimming step may be performed by any other suitable tool capable of mechanically cutting away material from the wafer structure, and the scope of this disclosure is not limited thereto. For example, during the first trimming step, trimming tool 60 rotates and moves along a circular path of the first pre-trimming mark 50 to trim the wafer edge. In some embodiments, when the first wafer is cut or trimmed on and along the path of the first pre-trimming mark 50, the path of the first pre-trimming mark 50 (e.g., Figure 2B The circular path shown is used as a trimming path. Because the trimming tool 60 moves along the circular path formed by the groove 50a, the direct contact between the trimming tool 60 and the first wafer 100 is reduced along the trimming path, thereby reducing localized stress concentration at the first surface 102 and mitigating stress-induced chip cracks. Therefore, production yield is significantly improved. Furthermore, the shorter cutting distance or path reduces damage to the trimming tool 60, thus improving the efficiency of the trimming operation and extending the service life of the trimming tool 60.

[0064] In some embodiments, after the first trimming step, the annular structure TR1 is removed to form an annular opening O1 around the periphery of the first wafer 100, such as... Figure 2CAs shown. During the first mark trimming step, the removed annular structure TR1 may have a first width Pw1 (defined by the first pre-trimming mark 50) and a thickness Pt1 (trimming depth Pt1). See reference... Figure 1B From the cross-sectional view, the annular opening O1 appears to be L-shaped and the sidewalls of the annular opening O1 are trimmed edges 106a. In some embodiments, the trimmed edges 106a are substantially perpendicular to the first surface 102. In some embodiments, the trimmed edges 106a are inclined relative to the first surface 102.

[0065] In some embodiments, the first thickness Pt1 (i.e., the trimming depth Pt1) is from the bottom surface 103 of the opening O1. Figure 1B The first thickness Pt1 is measured from the trimmed edge 106a to a reference plane extending from the first surface 102 (as shown). In some embodiments, the first width Pw1 is measured from the trimmed edge 106a to a reference plane extending from the edge 106a. In some embodiments, the first wafer 100 is a silicon wafer with a diameter of about 12 inches (about 300 mm). In these embodiments, the trimming depth Pt1 is in the range of about 50 micrometers to about 150 micrometers or about 100 micrometers. In these embodiments, the first width Pw1 is in the range of about 0.8 mm to about 1.5 mm or about 1.2 mm. It should be understood that the first thickness Pt1 and the first width Pw1 can be modified, but are not limited to, depending on the wafer size and product design requirements.

[0066] Reference Figure 2D After performing the first marking and trimming step, the sidewall surface of the trimmed edge 106a (e.g.) Figure 2C and Figure 2D The region A shown may have a plurality of first regions R1 surrounded by a second region R2. In some embodiments, the first region R1 is formed by a groove 50a cut through during the trimming step. Figure 2B The first regions R1 are formed by multiple cut-through recesses. Each first region R1 can be separated from and spaced apart from each other by a second region R2 surrounding it. In some embodiments, the texture feature TF1 of the first region R1 differs from the texture feature TF2 of the second region R2. In some embodiments, when the recess 50a is formed by etching, the first region R1 includes multiple etching streaks as texture feature TF1. In some embodiments, when the recess 50a is formed by laser marking, the first region R1 includes multiple laser marking streaks as texture feature TF1. For example, etching streaks Es can be presented in the first region R1 as fine straight lines extending in the thickness direction D1, as in... Figure 2D An enlarged view of the upper portion is shown. In some embodiments, as in Figure 2DAs shown in the enlarged view in the lower part, the texture feature TF2 of the second region R2 includes a fracture texture that presents as a main crack portion C1 and an intermediate crack portion C2 located below the main crack portion C1 in the second region R2. For example, the thickness of the main crack portion C1 may be less than the thickness of the intermediate crack portion C2. Due to the formation of pre-trimming marks before the trimming step, a smaller main crack portion C1 is formed due to smaller local stress concentrations. It should be understood that the thickness and profile of the intermediate crack portion C2 depend on the type of trimming tool used. In some embodiments, a plurality of fine features Wl (also known as Wallner lines) may be formed on the surface of the intermediate crack portion C2 in the second region R2. These fine features may be uniformly distributed and substantially parallel curves that extend relative to the thickness direction without irregular transverse cracks.

[0067] Reference Figure 1C A second wafer 200 is provided, having a top surface 202, a bottom surface 204 opposite to the top surface 202, and an edge 206 connecting the top surface 202 and the bottom surface 204. For example, the second wafer 200 is a semiconductor wafer and is used herein as a carrier wafer. In some embodiments, the second wafer 200 may comprise, for example, silicon, strained silicon, silicon alloy, silicon carbide, silicon germanium, silicon carbide germanium, germanium, germanium alloy, germanium arsenide, indium arsenide, or group III-V semiconductors. In some embodiments, the second wafer 200 comprises glass or ceramic material. After performing a first marking and trimming step, the first wafer 100 and the second wafer 200 are bonded together to form a stacked wafer structure 300. In some embodiments, the first wafer 100 and the second wafer 200 have the same diameter. In other embodiments, the first wafer 100 and the second wafer 200 may have different diameters. The dimensions of the first wafer 100 and the second wafer 200 may be determined according to design requirements and are not limited herein. When bonding the first wafer 100 and the second wafer 200, a molecular bonding technique can be used. For example, by making the first surface 102 of the first wafer 100 and the top surface 202 of the second wafer 200 in direct contact, the first wafer 100 and the second wafer 200 are bonded by van der Waals force without using specific bonding materials or adhesives.

[0068] It should be noted that molecular bonding techniques may require that the surfaces of the first wafer 100 and the second wafer 200 to be bonded are smooth and free of particles or contaminants. Before bonding the first wafer 100 and the second wafer 200, a cleaning process can be used to treat the first surface 102 of the first wafer 100 and / or the top surface 202 of the second wafer 200 to remove particles. After cleaning, the first wafer 100 and the second wafer 200 are placed close enough together to initiate contact. In these cases, the attraction between the first surface 102 of the first wafer 100 and the top surface 202 of the second wafer 200 is sufficiently strong to achieve molecular bonding caused by van der Waals forces.

[0069] In some embodiments, Figure 1C In this process, after bonding the first wafer 100 and the second wafer 200, an annealing process can be performed to strengthen the bond between the first wafer 100 and the second wafer 200. The temperature of the annealing process can be determined according to design requirements. For example, the higher the annealing temperature, the stronger the bond. In other embodiments where electrical components are distributed in the first wafer 100, the annealing temperature is limited to a relatively low temperature to avoid damaging the electrical components. In some other embodiments, the first wafer 100 and the second wafer 200 can be bonded by forming a bonding layer on the bonding interface of the first wafer 100 or on the second wafer 200 before the wafers are brought into contact.

[0070] Reference Figure 1D The stacked wafer structure 300 is flipped vertically. After flipping, the second surface 104 of the first wafer 100 faces upward and the first wafer 100 is supported by the second wafer 200 for subsequent processes. In some embodiments, the flipping process may be optional.

[0071] Reference Figure 1E The first wafer 100 is thinned (i.e., the thickness of the first wafer 100 is reduced) by performing mechanical processing techniques, including, for example, grinding, chemical mechanical polishing (CMP), or other suitable polishing processes. In some embodiments, the first wafer 100 is thinned downward from the second surface 104 toward the first surface 102. For example, during the thinning process, the stacked wafer structure 300 is held by a wafer holder (not shown). In some embodiments, the first wafer 100 may be thinned to a remaining thickness that is approximately equal to or slightly less than the first thickness Pt1. Because the edges 106 of the first wafer 100 are trimmed prior to the wafer thinning process, edge cracking problems caused by sharp edges of the thinned wafer can be eliminated.

[0072] Reference Figure 1F In some embodiments, the wafer thinning process further includes an etching process. In some embodiments, the first wafer 100 is further thinned by performing, for example, a wet etching process. In some embodiments, the wet etching process uses hydrofluoric acid / nitric acid / acetic acid (HNA) as the etchant. In some other embodiments, the first wafer 100 is further thinned by performing a dry etching process, and the dry etching process may include a reactive ion etching (RIE) process. This stage of the etching process further thins the first wafer 100 to a desired thickness Pt2. For example, the thickness Pt2 of the first wafer 100 is in the range of about 3.8 micrometers to about 4.3 micrometers. In some embodiments, the wafer thinning process includes one or more thinning processes. The wafer thinning process is performed to reduce the thickness of the first wafer 100 on which devices 112 (e.g., image sensors) or other electrical components are formed until the thickness of the first wafer 100 reaches the desired thickness Pt2. For example, in performing... Figure 1E and Figure 1F After the thinning process shown, the thickness Pt2 of the first wafer 100 is small enough that light can reach the device 112 or other electrical components.

[0073] After the first wafer 100 is thinned, a second marking trimming step is performed on the thinned first wafer 100 having a thickness of Pt2. Figure 3A A schematic top view of a stacked wafer structure after the formation of a second pre-trimmed mark, according to some embodiments of the present disclosure. Figure 3B and Figure 3C A schematic perspective view shows a marking and trimming process performed on a first wafer and a second wafer according to some embodiments of the present disclosure. Figure 3D Some embodiments according to this disclosure are shown. Figure 3C A schematic enlarged cross-sectional view of the edge surface in region D shown. (Refer to...) Figures 3A to 3C After thinning the first wafer 100, a second pre-trimming mark 70 is formed on the second surface 104 of the thinned first wafer 100. In some embodiments, the second pre-trimming mark 70 defines an edge portion to be removed in a subsequent trimming step, and the portion to be removed includes... Figures 3A to 3BThe annular structures TR2 and TR3 are shown. In some embodiments, the annular structure TR2, defined between the second pre-trimmed mark 70 and the trimmed edge 106a of the first wafer 100 (i.e., the periphery of the first wafer 100), has a second width Pw2. In some embodiments, the annular structure TR3, defined between the second pre-trimmed mark 70 and the edge 206 of the second wafer 200 (i.e., the periphery of the second wafer 200), has a third width Pw3. In some embodiments, the second pre-trimmed mark 70 may be formed as a discontinuous pattern or intermittent pattern on the second surface 104. In some embodiments, the second pre-trimmed mark 70 includes a plurality of grooves 70a, and the grooves 70a are separate, individual narrow trenches. For example, the grooves 70a are arranged in a circular path along the trimmed edge 106a to form the second pre-trimmed mark 70. In some embodiments, the grooves 70a may be formed using a process similar to that used to form the grooves 50a, and detailed descriptions will not be repeated herein.

[0074] Each groove 70a may include a marking depth d2 relative to a reference plane corresponding to the second surface 104 of the thinned first wafer 100. The marking depth d2 of each groove 70a may be in the range of 1 μm to 35 μm, preferably in the range of 15 μm to 30 μm. In some embodiments, the marking depth d2 is less than the thickness Pt2 of the thinned first wafer 100. It should be understood that the number, shape or size, and arrangement of the grooves 70a may be modified according to the design requirements of the product. In some embodiments, the intermittent pattern of the second pre-trimmed markings 70 may include individual grooves 70a separated from each other and spaced apart by a fixed pitch. In some embodiments, any two nearest adjacent grooves 70a are spaced apart by a pitch P2. For example, the pitch P2 between these two nearest adjacent grooves 70a may be in the range of 5 μm to 100 μm, preferably in the range of 20 μm to 40 μm. In some embodiments, the sum of the pitches P2 along the circular path may be approximately half the total length of the circular path. In other words, after performing the first marking trimming step, the grooves 70a can be uniformly distributed on the second surface 104 as circular paths along the periphery of the first wafer 100. In some other embodiments, the ratio of the sum of the pitches P2 along the circular paths to the total length of the circular paths of the second pre-trimmed marks 70 is between 30% and 80%. It should be noted that the pitch P2 can be modified according to the wafer size and design requirements. In alternative embodiments, the pattern of the second pre-trimmed marks 70 can be dispersed. In other embodiments, the pattern comprises individual grooves 70a separated from each other and spaced apart by various pitches.

[0075] After the second pre-trimming mark 70 is formed, a second trimming step is performed on the stacked wafer structure 300. Figures 3A to 3CThe process described may be referred to as a second trimming step. For example, during the second trimming step, when the stacked wafer structure 300 is cut or trimmed directly above and along the second pre-trimming mark 70, the annular structure TR2 surrounding the periphery of the first wafer 100 and the annular structure TR3 of the second wafer 200 located below the annular structure TR2 of the first wafer 100 are removed. For example, the second trimming step is performed from the second surface 104 of the first wafer 100 down to the second wafer 200 along the thickness direction D1 to form a trimmed edge 302 around the periphery of the stacked wafer structure 300. In some embodiments, the second trimming step is performed by trimming tool 60 cutting substantially vertically or obliquely into the stacked wafer structure 300 to a trimming depth (i.e., the sum of Pt2 and Pt3). That is, during the second trimming step, the thinned first wafer 100 with a thickness of Pt2 is cut through and the second wafer 200 is cut or trimmed to a trimming depth Pt3. In some embodiments, the second trimming step is performed by machining similar to the first trimming step, and detailed descriptions will not be repeated herein.

[0076] During the second marking trimming step, the removed annular structure TR2 may have a second width Pw2 (defined by the second pre-trimming mark 70) and a thickness Pt2 (trimming depth Pt2), and the removed annular structure TR3 may have a third width Pw3 (also defined by the second pre-trimming mark 70) and a thickness Pt3 (trimming depth Pt3). In some embodiments, after removing the annular structure TR2 of the first wafer 100 and the annular structure TR3 of the second wafer 200, an annular opening O2 is formed around the periphery of the stacked wafer structure 300, such as Figure 3C As shown. (Refer to...) Figure 1G From a cross-sectional view, the annular opening O2 appears L-shaped, and the sidewalls of the annular opening O2 are trimmed edges 302. In some embodiments, the trimmed edges 302 are substantially perpendicular to the second surface 104 of the first wafer 100. In some other embodiments, the trimmed edges 302 of the stacked wafer structure 300 are inclined relative to the second surface 104. The depth of the opening O2 is the total thickness of the second thickness Pt2 and the third thickness Pt3. Since the first wafer 100 has been thinned, the first wafer 100 in the stacked wafer structure 300 can be trimmed by a second thickness Pt2 that is smaller than the first thickness Pt1 during the first trimming step.

[0077] In some embodiments, the second thickness Pt2 (i.e., trimming depth Pt2) is measured from a reference plane extending from the top surface 202 of the second wafer 200 to a reference plane extending from the second surface 104 of the first wafer 100. In some embodiments, the second width Pw2 is measured from a reference plane extending from the trimmed edge 106a to a reference plane extending from the trimmed edge 302. The third thickness Pt3 (i.e., trimming depth Pt3) is measured from the bottom surface 303 of the opening O2 (… Figure 1G The third width Pw3 is measured from a reference plane extending from the top surface 202 of the second wafer 200 (as shown). In some embodiments, the third width Pw3 is measured from a reference plane extending from edge 206 to a reference plane extending from the trimmed edge 302. In some embodiments where the first wafer 100 and the second wafer 200 are silicon wafers with a diameter of about 12 inches, the third width Pw3 is in the range of about 2 mm to about 3 mm or about 2.6 mm. In some embodiments, the total thickness of the second thickness Pt2 and the third thickness Pt3 is in the range of 20 micrometers to 30 micrometers or about 25 micrometers. For example, the third thickness Pt3 may be greater than the second thickness Pt2. It should be noted that the dimensions of the annular structures TR2 and TR3 can be modified, and are not limited to, depending on the wafer size and product design requirements.

[0078] Reference Figure 3D After performing the second mark-trimming step, with Figure 2D Similar to the edge surface of the trimmed edge 106a shown, the edge surface of the trimmed edge 302 may have a plurality of first regions R3 surrounded by a second region R4. In some embodiments, the first region R3 is formed by a groove 70a cut during the trimming step. Figure 3B The first regions R3 are spaced apart from each other by the second regions R4 surrounding them. Similarly, since the second pre-trimming mark is formed before the second trimming step, a smaller main crack portion C1 will be formed due to less local stress concentration. The texture feature TF3 of the first region R3 exhibited on the edge surface of the trimmed edge 302 of the stacked wafer structure 300 is different from the texture feature TF4 of the second region R4, as explained above, and will not be repeated here.

[0079] Reference Figure 1HAfter performing the second marking and trimming step, the thickness of the stacked wafer structure 300 can be further reduced by, for example, performing a grinding process, a chemical mechanical polishing (CMP) process, or other suitable polishing processes. In some embodiments, after the second marking and trimming step, while the second wafer 200 is supporting the first wafer 100, the first wafer 100 is thinned from the second surface 104 along the thickness direction D1. This thinning process gives the first wafer 100 a desired thickness T1. For example, the thickness T1 of the first wafer 100 is approximately 2.6 μm. In some embodiments, after the thinning process, the stacked wafer structure 300 can be cleaned by wet cleaning using a liquid medium (e.g., tetramethylammonium hydroxide (TMAH)), which selectively removes surface contaminants and particles without damaging or chemically altering the second surface 104 of the first wafer 100. Subsequently, the trimming method of the stacked wafer structure is substantially completed, as follows: Figure 1H As shown.

[0080] Figure 4A This illustrates the process before performing the second trimming step according to some embodiments. Figure 1F A schematic enlarged cross-sectional view of region B shown. Figure 4B This illustrates the process after performing the second trimming step, according to some embodiments. Figure 1H A schematic enlarged cross-sectional view of region C shown. (Refer to...) Figure 4A and Figure 4B The first wafer 100 may include a back-side alignment mark 140, which is located on the back side below the second surface 104 of the first wafer 100. For example, the first wafer 100 and the second wafer 200 may be aligned using the back-side alignment mark 140 to achieve better alignment during the bonding of the first wafer 100 and the second wafer 200. In some embodiments, when the first wafer 100 is thinned, the trimmed edge 106a of the first wafer 100 is prone to chipping and cracking. In other words, in situations such as Figure 1E and / or Figure 1FAfter the first wafer 100 is thinned, the edge portion 310 may include defects 110a present at the periphery of the stacked wafer structure 300. Defects 110a may be edge peeling defects, cracks, edge chipping defects, etc. These defects 110a may cause contaminant intrusion during subsequent processes and may damage or disrupt the function of the circuit layer 120 of the first wafer 100. In other words, if the edge portion 310 with defects 110a is not trimmed, the manufacturing yield may be adversely affected. Therefore, a second trimming step is performed to trim the edge portion 310 from the stacked wafer structure 300 to form a trimmed edge 302 without affecting the circuit layer 120, thereby reducing potential edge peeling or chipping problems and preventing loss of manufacturing yield. For example, by performing the second trimming step, the edge chipping problem can be reduced to approximately 5% to 20% compared to a process without performing the second trimming step.

[0081] In some embodiments, such as Figure 1F As shown, after thinning the first wafer 100, fine protrusions 130 can be formed on the thinned second surface 104. In other words, thinning the first wafer 100 (as shown) Figure 1E and Figure 1F As shown, the second surface 104 may not be planarized or polished to a high degree. These micro-protrusions 130 on the second surface 104 can be critical for very thin wafers. Therefore, planarization processes such as CMP can be performed to remove the micro-protrusions 130 to form a substantially flat second surface 104, as shown. Figure 4B As shown.

[0082] Based on the above, since pre-trimming marks are formed before trimming, the contact between the trimming tool and the wafer along the trimming path is reduced, thereby decreasing localized stress concentration at the wafer surface. Therefore, trimming efficiency is improved and tool damage is reduced, extending tool life. Furthermore, performing the first trimming step eliminates edge cracking problems caused by sharp edges of the thinned wafer. Additionally, performing the second trimming step reduces edge chipping or peeling and prevents loss of manufacturing yield.

[0083] According to some embodiments, a trimming method is provided. The trimming method includes the following steps: A first wafer is provided, the first wafer having a first surface and a second surface opposite to the first surface. A first pre-trimming mark is formed on the first surface of the first wafer, wherein forming the first pre-trimming mark includes forming a plurality of grooves arranged along a path along the periphery of the first wafer. The first wafer is trimmed on the first pre-trimming mark and along the path of the first pre-trimming mark to remove a portion of the first wafer and form a trimmed edge having a plurality of first regions.

[0084] In some embodiments, forming the first pre-trimming mark on the first surface of the first wafer includes: performing an etching process on the first surface of the first wafer to form the first pre-trimming mark, and the first region including a plurality of etching streaks. In some embodiments, forming the first pre-trimming mark on the first surface of the first wafer includes: performing a laser marking process on the first surface of the first wafer to form the first pre-trimming mark, and the first region including a plurality of laser marking streaks. In some embodiments, trimming the first wafer includes: cutting into the first wafer and cutting through the first pre-trimming mark to a trimming depth greater than the depth of each groove in the groove. In some embodiments, the trimmed edge further includes a second region surrounding the first region, and the second region having a texture feature different from the texture feature of the first region. In some embodiments, after trimming the first wafer, a second wafer is provided bonded to the first surface of the first wafer, and a wafer thinning process is performed on the second surface of the first wafer. In some embodiments, after performing the wafer thinning process, a second pre-trimming mark is formed on the second surface of the first wafer. In some embodiments, after forming the second pre-trimming mark on the second surface of the first wafer, the first wafer and the second wafer are trimmed on the second pre-trimming mark.

[0085] According to some alternative embodiments, a trimming method is provided. The trimming method includes the following steps: providing a first wafer having a first surface and a second surface opposite to the first surface; performing a first marking trimming step on the first wafer along a thickness direction from the first surface to remove annular structures surrounding the periphery of the first wafer; forming a stacked wafer structure by providing a second wafer and stacking the second wafer onto the first surface of the first wafer; performing a second marking trimming step on the stacked wafer structure along the thickness direction from the second surface of the first wafer to remove edge portions of the stacked wafer structure.

[0086] In some embodiments, performing the first marking trimming step on the first wafer includes: forming a first pre-trimming mark on the first surface of the first wafer, wherein the first pre-trimming mark is formed by forming a plurality of grooves spaced apart from each other and distributed in a circular path along the periphery of the first wafer. In some embodiments, forming the first pre-trimming mark includes: performing an etching process on the first surface of the first wafer to form a plurality of grooves. In some embodiments, forming the first pre-trimming mark includes: performing a laser marking process on the first surface of the first wafer to form a plurality of grooves. In some embodiments, performing the first marking trimming step on the first wafer further includes: trimming the first wafer by cutting on the first pre-trimming mark and cutting into the first wafer along the circular path of the first pre-trimming mark to remove the annular structure. In some embodiments, forming the stacked wafer structure includes: bonding the first wafer and the second wafer to form the stacked wafer structure, wherein the first surface of the first wafer is directly bonded to the second wafer. In some embodiments, after bonding the first wafer and the second wafer, the first wafer is thinned from the second surface of the first wafer. In some embodiments, performing the second marking trimming step on the stacked wafer structure includes: forming a second pre-trimming mark on the second surface of the first wafer; and trimming the stacked wafer structure by cutting along the second pre-trimming mark into the first and second wafers to remove the edge portion of the stacked wafer structure.

[0087] According to some alternative embodiments, a wafer structure is provided. A wafer has a first surface, a second surface opposite to the first surface, and an edge connecting the first surface and the second surface. The edge is substantially perpendicular to the first surface and the second surface of the wafer, and the edge has a plurality of first regions surrounded by second regions, each of the first regions being separated and spaced apart from each other by the second regions, and the texture features of the second regions being different from the texture features of the first regions.

[0088] In some embodiments, the texture feature of the second region includes a main crack portion and an intermediate crack portion located below the main crack portion, the main crack portion being smaller than the intermediate crack portion. In some embodiments, the wafer includes alignment marks at the second surface of the wafer.

[0089] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or realize the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and modifications thereto without departing from the spirit and scope of this disclosure.

Claims

1. A wafer structure, characterized in that, include: A wafer has a first surface, a second surface opposite to the first surface, and an edge connecting the first surface and the second surface; The edge is substantially perpendicular to the first and second surfaces of the wafer. The edge has a plurality of first regions surrounded by second regions, each of the first regions being separated and spaced apart from each other by the second regions, and the texture features of the second regions differ from the texture features of the first regions. The texture features of the second region include a main crack portion and an intermediate crack portion located below the main crack portion, wherein the thickness of the main crack portion is less than the thickness of the intermediate crack portion.

2. The wafer structure according to claim 1, characterized in that, The texture features of the first region include a plurality of streaks extending in the thickness direction of the wafer within the first region.

3. The wafer structure according to claim 1, characterized in that, The surface of the intermediate crack portion in the second region has a number of fine vanilla lines.

4. The wafer structure according to claim 1, characterized in that, The wafer includes alignment marks on the second surface of the wafer.

5. A wafer structure, characterized in that, include: A first wafer has a front surface, a back surface, and a sidewall connecting the front surface and the back surface. The sidewall includes a plurality of first regions and a second region between two adjacent first regions. The plurality of first regions are located at the edges of the sidewall and the back surface and are laterally spaced apart from each other by a pitch. Each first region extends from the back surface to the front surface and has a plurality of etching marks thereon. The texture features of the second region include a main crack portion and an intermediate crack portion located below the main crack portion, and the thickness of the main crack portion is less than the thickness of the intermediate crack portion.

6. The wafer structure according to claim 5, characterized in that, The plurality of etching marks extend along the thickness direction of the first wafer within each of the first regions.

7. The wafer structure according to claim 5, characterized in that, The plurality of first zones are arranged along the periphery of the sidewall, and the total length of the pitch between two adjacent first zones is equal to half the periphery of the sidewall.

8. The wafer structure according to claim 5, characterized in that, The length of each of the first regions in the thickness direction of the first wafer is less than the pitch.

9. The wafer structure according to claim 5, characterized in that, The width of the second region is the pitch of the plurality of first regions.

10. The wafer structure according to claim 5, characterized in that, The surface of the intermediate crack portion in the second region has a number of fine vanilla lines.

11. The wafer structure according to claim 5, characterized in that, Multiple parallel curved stripes are distributed within the middle crack portion of the second zone on the sidewall.

12. The wafer structure according to claim 5, characterized in that, The first wafer includes a circuit layer and a back-side alignment mark isolated from the circuit layer, wherein the back-side alignment mark is disposed below the back surface and adjacent to the sidewall.

13. The wafer structure according to claim 5, characterized in that, Further includes: A second wafer is bonded to the front surface of the first wafer, wherein there is no bonding material at the interface between the first wafer and the second wafer.

14. A wafer structure, characterized in that, include: A first wafer has a front surface, a back surface, and a sidewall connecting the front surface and the back surface. The sidewall includes a plurality of first regions and a plurality of second regions. The plurality of first regions are located at the edges of the sidewall and the back surface and are laterally spaced apart from each other by a pitch. The plurality of first regions have a plurality of straight streaks. The plurality of second regions include a main crack portion and an intermediate crack portion located below the main crack portion and including a plurality of curved streaks. The thickness of the intermediate crack portion is greater than the thickness of the main crack portion.

15. The wafer structure according to claim 14, characterized in that, The pitch between two adjacent first regions in the plurality of first regions is less than the length of each first region in the thickness direction of the first wafer.

16. The wafer structure according to claim 14, characterized in that, The plurality of first zones are spaced apart from each other by the pitch, and the sum of the pitches is equal to half the perimeter of the sidewall.

17. The wafer structure according to claim 14, characterized in that, The multiple curved streaks in the intermediate crack portions of the multiple second zones are subtle features of multiple Vana lines.

18. The wafer structure according to claim 14, characterized in that, Further includes: A second wafer is bonded to the front surface of the first wafer, wherein there is no bonding material at the interface between the first wafer and the second wafer.

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