Method for manufacturing a metal gate structure

Abstract

This invention provides a method for fabricating a metal gate structure. After forming a first oxide layer, a nitride stop layer is added, and then a second oxide layer is formed on the nitride stop layer. Thus, in the chemical mechanical polishing (CMP) step, the nitride stop layer can serve as a stop layer for subsequent CMP. Since the hardness of the second oxide layer is greater than that of the first oxide layer, the harder silicon oxide layer is removed in the polishing step, which can significantly improve the depression problem of the oxide layer after CMP. Furthermore, since the fabrication process does not require hard mask etch-back and POP CMP steps, it can reduce destructive processes and steps, reduce costs, improve efficiency, reduce defect risks, and improve product quality.

Description

Technical Field

[0001] This invention relates to a method for fabricating a gate structure, and more particularly to a method for fabricating a metal gate structure. Background Technology

[0002] With the development of integrated circuit technology and the continuous miniaturization of device size, in the manufacturing of advanced logic circuit chips at the 28nm node, the gate material will be replaced by metals such as aluminum and tungsten to avoid the depletion effect of polysilicon gates, which can lead to transistor switching delay and thus limit the operating frequency of the device.

[0003] In fabricating metal gates, existing processes mostly involve: forming a hard mask stack consisting of silicon nitride and silicon oxide layers on a polysilicon gate; forming gate sidewalls; forming a silicon nitride contact hole etch stop layer; forming a silicon oxide layer using HARP; performing silicon oxide chemical mechanical planarization (CMP); etching back the silicon nitride contact hole etch stop layer and silicon oxide layer; forming a silicon oxide layer using HDP; opening the top of the polysilicon gate using Poly Opening Nitride Polish CMP (POP CMP); removing the polysilicon gate to form a trench; and fabricating the metal gate within the trench. This method requires two silicon oxide stacks and two etch-back and two polishing processes to provide isolation for the gate structure. The polishing process also addresses the recess problem, thus avoiding metal residue and preventing short circuits. However, this method involves many steps and destructive processes (etching / polishing), resulting in high manufacturing costs, long tape-out times, poor efficiency, and a significantly increased risk of defects.

[0004] Therefore, it is necessary to provide a method for fabricating a metal gate structure to improve the existing fabrication process of metal gate structures. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method for preparing a metal gate structure, so as to solve the above-mentioned defects in the preparation process of metal gate structures in the prior art.

[0006] To achieve the above and other related objectives, the present invention provides a method for fabricating a metal gate structure, comprising the following steps:

[0007] A semiconductor substrate is provided, the semiconductor substrate including a polysilicon dummy gate;

[0008] A first oxide layer is formed on the semiconductor substrate;

[0009] A nitriding stop layer is formed on the first oxide layer;

[0010] A second oxide layer is formed on the nitriding stop layer, and the hardness of the second oxide layer is greater than that of the first oxide layer;

[0011] The second oxide layer is removed by grinding to expose the nitride stop layer;

[0012] The polysilicon virtual gate is exposed by etching.

[0013] Optionally, the first oxide layer includes a silicon oxide layer formed using HARP; the second oxide layer includes a silicon oxide layer formed using HDP.

[0014] Optionally, the nitriding stop layer includes a silicon nitride layer.

[0015] Optionally, the grinding method includes chemical mechanical grinding.

[0016] Optionally, an STI isolation structure is further formed in the semiconductor substrate, the polysilicon virtual gate includes a polysilicon virtual gate with a gate insulating layer with a high dielectric constant, and the side of the polysilicon virtual gate includes a gate sidewall.

[0017] Optionally, the method further includes the step of removing the polysilicon virtual gate to form a trench using an etching method, and the step of forming a gate work function adjusting metal oxide layer in the trench and filling the trench with a gate conductive layer after annealing and cleaning.

[0018] Optionally, when it is an NMOS transistor, the metal gate includes an N-type metal compound layer diffused into the high-dielectric-constant gate insulating layer and a gate metal layer or intrinsic gate polysilicon layer filling the groove. The material of the N-type metal compound layer includes one or a combination of titanium aluminum nitride, tantalum carbide, rhenium oxide, and tantalum nitride. When it is a PMOS transistor, the metal gate includes a P-type metal compound layer diffused into the high-dielectric-constant gate insulating layer and a gate metal layer or intrinsic gate polysilicon layer filling the groove. The material of the P-type metal compound layer includes one or a combination of titanium nitride, tungsten, tungsten nitride, molybdenum nitride, aluminum oxide, and aluminum molybdenum nitride. The material of the gate metal layer filling the groove includes tungsten, aluminum, or a combination thereof.

[0019] Optionally, the gate insulating layer includes one or a combination of ZrO2 layer, ZrON layer, ZrSiON layer, HfZrO layer, HfZrON layer, HfON layer, HfO2 layer, HfAlO layer, HfAlON layer, HfSiO layer, HfSiON layer, HfLaO layer, and HfLaON layer.

[0020] Optionally, the step of forming the semiconductor substrate includes:

[0021] A semiconductor substrate is provided, wherein a gate insulating layer and a polysilicon gate are sequentially formed on the surface of the semiconductor substrate from bottom to top;

[0022] A hard mask layer is formed on the surface of the polysilicon gate, the hard mask layer comprising a nitride hard mask layer and an oxide hard mask layer stacked from bottom to top;

[0023] Photolithography is used to form a polysilicon virtual gate;

[0024] A gate sidewall is formed on the side of the polysilicon virtual gate;

[0025] A contact hole etch stop layer composed of a nitride layer is formed, the contact hole etch stop layer covering the surface of the semiconductor substrate between the hard mask layer, the gate sidewall, and the polysilicon dummy gate.

[0026] Optionally, the semiconductor substrate includes a Si substrate, an SOI substrate, or a SiGe substrate.

[0027] As described above, the method for fabricating the metal gate structure of the present invention adds a nitride stop layer after forming the first oxide layer, and then forms a second oxide layer on the nitride stop layer. Thus, in the chemical mechanical polishing (CMP) step, the nitride stop layer can serve as a stop layer for subsequent CMP. Since the hardness of the second oxide layer is greater than that of the first oxide layer, the harder silicon oxide layer is removed in the CMP step, which can significantly improve the depression problem of the oxide layer. Furthermore, since the hard mask etch-back and POP CMP steps are not required during the fabrication process, destructive processes (etching / polishing) and process steps can be reduced, costs can be reduced, efficiency can be improved, and the risk of defects can be reduced, thereby improving product quality. Attached Figure Description

[0028] Figure 1 The diagram shows a process flow diagram for preparing the metal gate structure in an embodiment of the present invention.

[0029] Figure 2 The diagram shown is a schematic representation of the structure of a semiconductor substrate in an embodiment of the present invention.

[0030] Figure 3 The diagram shown is a schematic representation of the structure after the formation of the first oxide layer in an embodiment of the present invention.

[0031] Figure 4 The diagram shown is a schematic representation of the structure after the formation of the nitrided stop layer in an embodiment of the present invention.

[0032] Figure 5 The diagram shown is a schematic representation of the structure after the formation of the second oxide layer in an embodiment of the present invention.

[0033] Figure 6The diagram shows the structure after the nitrided stop layer has been exposed using a chemical mechanical polishing method with high-precision endpoint detection capability in an embodiment of the present invention.

[0034] Figure 7 The diagram shows the structure after the polysilicon virtual gate is exposed by etching in an embodiment of the present invention.

[0035] Component designation explanation

[0036] 100 Semiconductor substrate

[0037] 101 Semiconductor Substrate

[0038] 102 STI isolation structure

[0039] 103 Gate insulating layer

[0040] 104 polysilicon gate

[0041] 105 Nitride Hard Mask Layer

[0042] 106 Oxide Hard Mask Layer

[0043] 107 Gate sidewall

[0044] 108 Contact Hole Etching Stop Layer

[0045] 201 First Oxide Layer

[0046] 202 Second Oxide Layer

[0047] 300 Nitrided Stop Layer

[0048] Steps S1 to S6 Detailed Implementation

[0049] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0050] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0051] For ease of description, spatial relation terms such as "below," "below," "lower than," "below," "above," and "upper" may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may be one or more layers in between. Wherein, when an element is referred to as being "fixed to" or "set on" another element, it may be directly on or indirectly on the other element. When an element is referred to as being "connected to" another element, it may be directly connected to or indirectly connected to the other element.

[0052] The text may use expressions such as "between..." to indicate that both endpoints are included, and may also use expressions such as "multiple" to indicate two or more, unless otherwise explicitly specified. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of that feature.

[0053] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0054] like Figure 1 As shown, this embodiment provides a method for fabricating a metal gate structure, including the following steps:

[0055] S1: Provide a semiconductor substrate, the semiconductor substrate including a polysilicon dummy gate;

[0056] S2: A first oxide layer is formed on the semiconductor substrate;

[0057] S3: A nitriding stop layer is formed on the first oxide layer;

[0058] S4: A second oxide layer is formed on the nitriding stop layer, and the hardness of the second oxide layer is greater than that of the first oxide layer;

[0059] S5: The second oxide layer is removed by grinding to expose the nitriding stop layer;

[0060] S6: The polysilicon virtual gate is exposed by etching.

[0061] The method for fabricating the metal gate structure in this embodiment adds a step of fabricating the nitride stop layer after forming the first oxide layer, and then forms the second oxide layer on the nitride stop layer. Thus, in the chemical mechanical polishing step, the nitride stop layer can serve as a stop layer for subsequent polishing. Since the hardness of the second oxide layer is greater than that of the first oxide layer, the harder second silicon oxide layer is removed in the polishing step, which can significantly improve the depression problem of the oxide layer. In addition, since the hard mask etch-back and POP CMP steps are not required during the fabrication process, destructive processes (etching / polishing) and process steps can be reduced, costs can be reduced, efficiency can be improved, and the risk of defects can be reduced, thus improving product quality.

[0062] The following is in conjunction with the appendix Figures 2-7 The fabrication method of the aforementioned metal gate structure is further described.

[0063] See Figure 2 First, step S1 is performed to provide a semiconductor substrate 100, which includes a polysilicon dummy gate.

[0064] Specifically, in this embodiment, as Figure 2 The semiconductor substrate 100 may include a semiconductor substrate 101, an STI isolation structure 102 located in the semiconductor substrate 101, a gate insulating layer 103 located on the semiconductor substrate 101, a polysilicon gate 104 located on the gate insulating layer 103 to form the polysilicon dummy gate, a nitride hard mask layer 105 and an oxide hard mask layer 106 located on the polysilicon gate 104, a gate sidewall 107 located around the gate insulating layer 103 and the polysilicon gate 104, and a contact hole etch stop layer 108 composed of a nitride layer covering the semiconductor substrate 101, the gate sidewall 107 and the oxide hard mask layer 106. Of course, the structure of the semiconductor substrate 100 can be adapted as needed, and no excessive limitation is made here.

[0065] As an example, the steps of forming the semiconductor substrate 100 may include:

[0066] The semiconductor substrate 101 is provided, and the gate insulating layer 103 and the polysilicon gate 104 are sequentially formed from bottom to top on the surface of the semiconductor substrate 101.

[0067] A hard mask layer is formed on the surface of the polysilicon gate 104, the hard mask layer including the nitride hard mask layer 105 and the oxide hard mask layer 106 stacked from bottom to top;

[0068] Photolithography is used to form a polysilicon virtual gate;

[0069] The gate sidewall 107 is formed on the side of the polysilicon virtual gate;

[0070] A contact hole etch stop layer 108 composed of a nitride layer is formed, which covers the surface of the semiconductor substrate 101 between the hard mask layer, the gate sidewall 107, and the polysilicon dummy gate.

[0071] The STI isolation structure 102 can be formed by first forming an STI trench in the semiconductor substrate 101 through photolithography after the gate insulating layer 103 is formed, and then forming an STI dielectric material to fill the STI trench to form the STI isolation structure 102. However, the preparation method of the STI isolation structure 102 is not limited to this and can be selected as needed.

[0072] Specifically, the semiconductor substrate 101 may include a Si substrate, an SOI substrate, or a SiGe substrate, which can be selected as needed. The materials and thicknesses of the STI isolation structure 102, the gate insulating layer 103, the polysilicon gate 104, the hard mask layer, the gate sidewall 107, and the contact hole etch stop layer 108 can all be selected as needed, and no excessive restrictions are imposed here.

[0073] Next, refer to Figures 3-5 Steps S2 to S4 are executed to sequentially form the first oxide layer 201, the nitride stop layer 300, and the second oxide layer 202 on the semiconductor substrate 100.

[0074] As an example, the first oxide layer includes a silicon oxide layer formed using HARP; the second oxide layer 202 includes a silicon oxide layer formed using HDP.

[0075] Specifically, High Aspect Ratio Processing (HARP) has good gap-filling capabilities, but the HARP interlayer dielectric layer formed by HARP is usually relatively loose and soft. During planarization processes such as chemical mechanical polishing (CMP), it is prone to depression defects, making it difficult to provide a flat surface for subsequent metal gate fabrication. This can lead to defects such as short circuits in the fabricated metal gate. High-Density Plasma Processing (HDP), on the other hand, can form a material layer with higher hardness. In this embodiment, a first oxide layer 201 with good gap-filling properties is first formed using HARP. Then, a nitrided stop layer 300 is formed on the first oxide layer 201, and a harder second oxide layer 202 is formed on the nitrided stop layer 300. In subsequent processes, after grinding away the second oxide layer 202 using the nitrided stop layer 300 as a stop layer, a surface with good flatness can be formed, thus significantly improving the depression problem.

[0076] In this embodiment, for ease of process control, the first oxide layer 201 is a silicon oxide layer, the second oxide layer 202 is a silicon oxide layer, and the nitriding stop layer 300 is a silicon nitride layer. However, the materials of the first oxide layer 201, the second oxide layer 202, and the nitriding stop layer 300 are not limited to these and can be selected as needed. No excessive restrictions are imposed here.

[0077] Next, refer to Figure 6 Step S5 is executed, in which the second oxide layer 202 is removed by grinding to expose the nitrided stop layer.

[0078] Specifically, the grinding method may include chemical mechanical polishing (CMP) with high-precision endpoint detection capability, but is not limited to this. For example, physical polishing or a combination of physical polishing and CMP may also be used. No excessive limitation is made here.

[0079] Next, refer to Figure 7 Step S6 is executed, and the polysilicon virtual gate is exposed by etching.

[0080] Specifically, the etching method may include dry etching, and the removal of the nitride and oxide layers on the polysilicon dummy gate can be achieved by controlling the process parameters to expose the polysilicon gate 104 in the polysilicon dummy gate. Since a relatively flat surface has been formed after step S5, this step can expose the polysilicon dummy gate by etching and has good flatness, thus eliminating the need for etching back the hard mask layer and polishing the top of the polysilicon dummy gate (Poly Opening Nitride Polish CMP, POP CMP). This reduces the destructive processes of etching and polishing, reduces process steps, thereby reducing costs, improving efficiency, reducing defect risk, and improving product quality.

[0081] Furthermore, after step S6, the method further includes the step of removing the polysilicon virtual gate to form a trench using an etching method, and the step of forming a gate work function adjusting metal oxide layer in the trench and filling the trench with a gate conductive layer after annealing and cleaning.

[0082] As an example, when it is an NMOS transistor, the metal gate includes an N-type metal compound layer diffused into the high-dielectric-constant gate insulating layer and a gate metal layer or intrinsic gate polysilicon layer filling the groove. The material of the N-type metal compound layer includes one or a combination of titanium aluminum nitride, tantalum carbide, rhenium oxide, and tantalum nitride. When it is a PMOS transistor, the metal gate includes a P-type metal compound layer diffused into the high-dielectric-constant gate insulating layer and a gate metal layer or intrinsic gate polysilicon layer filling the groove. The material of the P-type metal compound layer includes one or a combination of titanium nitride, tungsten, tungsten nitride, molybdenum nitride, aluminum oxide, and aluminum molybdenum nitride. The material of the gate metal layer filling the groove includes tungsten, aluminum, or a combination thereof. Specific choices can be made as needed and are not limited here.

[0083] As an example, the gate insulating layer may include one or a combination of ZrO2 layer, ZrON layer, ZrSiON layer, HfZrO layer, HfZrON layer, HfON layer, HfO2 layer, HfAlO layer, HfAlON layer, HfSiO layer, HfSiON layer, HfLaO layer, and HfLaON layer, which can be selected as needed and is not limited here.

[0084] In summary, the method for fabricating the metal gate structure of the present invention, after forming the first oxide layer, adds the preparation of a nitride stop layer, and then forms a second oxide layer on the nitride stop layer. Thus, in the chemical mechanical polishing (CMP) step, the nitride stop layer can serve as a stop layer for subsequent CMP. Since the hardness of the second oxide layer is greater than that of the first oxide layer, the harder silicon oxide layer is removed in the polishing step, which can significantly improve the depression problem of the oxide layer after CMP. Furthermore, since the hard mask etch-back and POP CMP steps are not required during the fabrication process, destructive processes (etching / polishing) and process steps can be reduced, costs can be reduced, efficiency can be improved, defect risks can be reduced, and product quality can be improved.

[0085] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a metal gate structure, characterized in that, Includes the following steps: A semiconductor substrate is provided, the semiconductor substrate including a polysilicon dummy gate; A first oxide layer is formed on the semiconductor substrate, and the first oxide layer covers the polysilicon virtual gate; A nitriding stop layer is formed on the first oxide layer; A second oxide layer is formed on the nitriding stop layer, and the hardness of the second oxide layer is greater than that of the first oxide layer; The second oxide layer is removed by grinding to expose the nitriding stop layer. After the second oxide layer is removed by grinding the nitriding stop layer as a stop layer, a surface with good flatness is formed, thereby significantly improving the depression problem. The polysilicon virtual gate is exposed by etching.

2. The method for fabricating a metal gate structure according to claim 1, characterized in that: The first oxide layer includes a silicon oxide layer formed using HARP; the second oxide layer includes a silicon oxide layer formed using HDP.

3. The method for fabricating a metal gate structure according to claim 1, characterized in that: The nitrided stop layer includes a silicon nitride layer.

4. The method for fabricating a metal gate structure according to claim 1, characterized in that: The grinding method includes chemical mechanical grinding.

5. The method for fabricating a metal gate structure according to claim 1, characterized in that: An STI isolation structure is also formed in the semiconductor substrate, the polysilicon virtual gate includes a polysilicon virtual gate with a gate insulating layer with a high dielectric constant, and the side of the polysilicon virtual gate includes a gate sidewall.

6. The method for fabricating a metal gate structure according to claim 1, characterized in that: It also includes the steps of removing the polysilicon virtual gate to form a trench using an etching method, and forming a gate work function adjusting metal oxide layer in the trench and filling the trench with a gate conductive layer after annealing and cleaning.

7. The method for fabricating a metal gate structure according to claim 6, characterized in that: When the transistor is an NMOS transistor, the metal gate includes an N-type metal compound layer diffused into a high-dielectric-constant gate insulating layer and a gate metal layer or an intrinsic gate polysilicon layer filling the groove. The material of the N-type metal compound layer includes one or a combination of titanium aluminum nitride, tantalum carbide, rhenium oxide, and tantalum nitride. When the transistor is a PMOS transistor, the metal gate includes a P-type metal compound layer diffused into a high-dielectric-constant gate insulating layer and a gate metal layer or an intrinsic gate polysilicon layer filling the groove. The material of the P-type metal compound layer includes one or a combination of titanium nitride, tungsten, tungsten nitride, molybdenum nitride, aluminum oxide, and aluminum molybdenum nitride. The material of the gate metal layer filling the groove includes tungsten, aluminum, or a combination thereof.

8. The method for fabricating a metal gate structure according to claim 5, characterized in that: The gate insulating layer includes one or a combination of ZrO2 layer, ZrON layer, ZrSiON layer, HfZrO layer, HfZrON layer, HfON layer, HfO2 layer, HfAlO layer, HfAlON layer, HfSiO layer, HfSiON layer, HfLaO layer, and HfLaON layer.

9. The method for fabricating a metal gate structure according to claim 1, characterized in that: The steps for forming the semiconductor substrate include: A semiconductor substrate is provided, wherein a gate insulating layer and a polysilicon gate are sequentially formed on the surface of the semiconductor substrate from bottom to top; A hard mask layer is formed on the surface of the polysilicon gate, the hard mask layer comprising a nitride hard mask layer and an oxide hard mask layer stacked from bottom to top; Photolithography is used to form a polysilicon virtual gate; A gate sidewall is formed on the side of the polysilicon virtual gate; A contact hole etch stop layer composed of a nitride layer is formed, the contact hole etch stop layer covering the surface of the semiconductor substrate between the hard mask layer, the gate sidewall, and the polysilicon dummy gate.

10. The method for fabricating a metal gate structure according to claim 9, characterized in that: The semiconductor substrate includes a Si substrate, an SOI substrate, or a SiGe substrate.

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