Semiconductor element with a bonding wire and method for manufacturing the same

Abstract

A semiconductor device includes a semiconductor substrate having a bond pad, and a first dielectric layer disposed on the semiconductor substrate. A portion of the bond pad is exposed by the first dielectric layer. The semiconductor device also includes a metal oxide layer disposed on the portion of the bond pad, and a bond wire that penetrates the metal oxide layer to bond to the bond pad. The portion of the bond pad is completely covered by the metal oxide layer and the bond wire.

Description

[0001] Cross-referencing

[0002] This application claims priority and benefits from U.S. Official Application No. 17 / 493,820, filed October 4, 2021, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure provides a semiconductor element and a method for fabricating the same, and particularly relates to a semiconductor element with bonding wires and a method for fabricating the same. Background Technology

[0004] Semiconductor components are indispensable for many modern applications. With the development of electronic technology, semiconductor components are becoming increasingly smaller while offering more functions and incorporating more integrated circuits. Due to the miniaturization of semiconductor components, wafer-level chip-scale packaging (WLCSP) is widely used because of its low cost and relatively simple process. Furthermore, many fabrication operations can be performed within such small semiconductor components.

[0005] However, the fabrication and assembly of semiconductor devices involves many complex steps and operations. The increasing complexity of semiconductor device fabrication and assembly can lead to defects. Therefore, continuous improvement of semiconductor device processes is necessary to address these issues.

[0006] The above description of "prior art" provides background information only and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art of this disclosure, and no description of the above "prior art" should be considered part of this disclosure. Summary of the Invention

[0007] One embodiment of this disclosure provides a semiconductor device, comprising: a semiconductor substrate having a bonding pad; a first dielectric layer disposed on the semiconductor substrate, wherein a portion of the bonding pad is exposed by the first dielectric layer; a metal oxide layer disposed on the portion of the bonding pad; and a wire bond penetrating the metal oxide layer and bonded to the bonding pad. The portion of the bonding pad is completely covered by the metal oxide layer and the wire bond.

[0008] In some embodiments, the bonding pad comprises copper (Cu).

[0009] In some embodiments, the metal oxide layer includes tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), or a combination thereof.

[0010] In some embodiments, the metal oxide layer includes a sputtering structure protruding from a top surface of the metal oxide layer, and a bottom surface of the bonding wire is surrounded by and in direct contact with the sputtering structure of the metal oxide layer.

[0011] In some embodiments, the semiconductor device further includes a second dielectric layer disposed on the first dielectric layer and a third dielectric layer disposed on the second dielectric layer. The first dielectric layer, the second dielectric layer, and the third dielectric layer each have substantially aligned sidewalls.

[0012] In some embodiments, the semiconductor device further includes a polymer layer to cover a top surface of the third dielectric layer and the sidewalls of the first dielectric layer, the second dielectric layer, and the third dielectric layer.

[0013] In some embodiments, the polymer layer is in direct contact with the metal oxide layer and the bonding wire.

[0014] Another embodiment of this disclosure provides a semiconductor device, comprising: a semiconductor substrate having a bonding pad; a dielectric stack disposed on the semiconductor substrate; a bonding wire physically bonded to a top surface of the bonding pad; and a metal oxide layer disposed on the top surface of the bonding pad. The top surface of the bonding pad is exposed by the dielectric stack. The metal oxide layer is in direct contact with a bottom surface of the bonding wire and a sidewall of the dielectric stack.

[0015] In some embodiments, the metal oxide layer surrounds and mechanically supports the bottom surface of the bonding wire.

[0016] In some embodiments, the bonding pad comprises copper (Cu), and the metal oxide layer comprises tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), or a combination thereof.

[0017] In some embodiments, the dielectric stack includes a first dielectric layer, a second dielectric layer disposed on the first dielectric layer, and a third dielectric layer disposed on the second dielectric layer, wherein the first dielectric layer and the second dielectric layer are made of different materials.

[0018] In some embodiments, the interface between the first dielectric layer and the second dielectric layer is above the topmost surface of the metal oxide layer.

[0019] In some embodiments, the semiconductor device further includes a polymer layer disposed between the bonding wire and the dielectric stack. The polymer layer is in direct contact with a top surface of the metal oxide layer.

[0020] In some embodiments, the polymer layer comprises polyimide.

[0021] In another embodiment of this disclosure, a method for fabricating a semiconductor device is provided, comprising: providing a semiconductor substrate having a bonding pad; forming a first dielectric layer on the bonding pad; etching the first dielectric layer to expose a top surface of the bonding pad; selectively depositing a metal oxide layer on the top surface of the bonding pad; and bonding a bonding wire to the semiconductor substrate, wherein the bonding wire penetrates the metal oxide layer and makes physical contact with the bonding pad.

[0022] In some embodiments, the metal oxide layer is selectively deposited using an atomic layer deposition (ALD) process.

[0023] In some embodiments, before exposing the top surface of the bonding pad, the method further includes forming a second dielectric layer on the first dielectric layer; forming a third dielectric layer on the second dielectric layer; forming a patterned mask on the third dielectric layer; and using the patterned mask as an etching mask to etch the first dielectric layer, the second dielectric layer, and the third dielectric layer to expose the top surface of the bonding pad.

[0024] In some embodiments, before bonding the bonding wire to the semiconductor substrate, the method further includes depositing a polymer layer to cover the first dielectric layer and the metal oxide layer; and etching the polymer layer to expose the top surface of the metal oxide layer.

[0025] In some embodiments, the bonding wire is separated from the first dielectric layer by the polymer layer.

[0026] In some embodiments, after exposing the top surface of the metal oxide layer, the method further includes etching the metal oxide layer using a polymer layer as an etching mask; and removing the polymer layer before the bonding wire is bonded to the semiconductor substrate.

[0027] This disclosure provides a semiconductor device with bonding wires and a method for fabricating the same. In some embodiments, the semiconductor device includes a metal oxide layer disposed on a bonding pad and bonding wires penetrating the metal oxide layer to be bonded to the bonding pad. After the bonding process, the bonding pad is completely covered by the metal oxide layer and the bonding wires. This protects the bonding pad from oxidation and contamination, and the metal oxide layer provides mechanical support to the bottom surface of the bonding wires. Furthermore, the metal oxide layer is selectively deposited on the bonding pad without performing an oxidation process, thus preventing adverse effects on device performance. Therefore, the performance of the semiconductor device can be improved.

[0028] The technical features and advantages of this disclosure have been broadly summarized above, thus enabling a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of the disclosed claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the same purpose as this disclosure can be achieved quite readily by utilizing the concepts and specific embodiments disclosed below to modify or design other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the concept and scope of this disclosure as defined by the disclosed claims. Attached Figure Description

[0029] A more comprehensive understanding of the disclosure can be obtained by referring to the accompanying drawings in conjunction with the embodiments and the disclosed claims, wherein the same element symbols in the drawings refer to the same elements.

[0030] Figure 1 This is a cross-sectional view illustrating semiconductor elements according to some embodiments of the present disclosure.

[0031] Figure 2 This is a cross-sectional view illustrating semiconductor elements according to some embodiments of the present disclosure.

[0032] Figure 3 This is a cross-sectional view illustrating semiconductor elements according to some embodiments of the present disclosure.

[0033] Figure 4 The flowchart illustrates a method for fabricating a semiconductor element according to some embodiments of this disclosure.

[0034] Figure 5 This is a cross-sectional view illustrating intermediate stages in the fabrication of semiconductor elements according to some embodiments of the present disclosure, to provide a semiconductor substrate with bonding pads.

[0035] Figure 6 This is a cross-sectional view illustrating intermediate stages in the fabrication of semiconductor elements according to some embodiments of the present disclosure, to form a dielectric stack on a semiconductor substrate and bonding pads.

[0036] Figure 7 This is a cross-sectional view illustrating an intermediate stage in the fabrication of a semiconductor element according to some embodiments of the present disclosure, to form a patterned mask on a dielectric stack.

[0037] Figure 8 This is a cross-sectional view illustrating an intermediate stage in the fabrication of a semiconductor element according to some embodiments of the present disclosure, in which a patterned mask is used as an etch mask to etch a dielectric stack to expose the top surface of the bonding pad.

[0038] Figure 9 This is a cross-sectional view illustrating an intermediate stage in the fabrication of a semiconductor element according to some embodiments of the present disclosure, to selectively deposit a metal oxide layer on the top surface of a bonding pad.

[0039] Figure 10 This is a cross-sectional view illustrating an intermediate stage in the fabrication of a semiconductor element according to some embodiments of the present disclosure, in which a polymer layer is deposited to cover the dielectric stack and the metal oxide layer.

[0040] Figure 11 This is a cross-sectional view illustrating an intermediate stage in the fabrication of a semiconductor element according to some embodiments of the present disclosure, to form a patterned mask on a polymer layer.

[0041] Figure 12 This is a cross-sectional view illustrating an intermediate stage in the fabrication of a semiconductor element according to some embodiments of the present disclosure, in which a patterned mask is used as an etch mask to etch a polymer layer to expose the top surface of a metal oxide layer.

[0042] Figure 13 This is a cross-sectional view illustrating an intermediate stage in the fabrication of a semiconductor element according to some embodiments of the present disclosure, to remove a patterned mask.

[0043] Figure 14 This is a cross-sectional view illustrating an intermediate stage in the fabrication of a semiconductor element according to some embodiments of the present disclosure, in order to align the bonding wires with the bonding pads.

[0044] Figure 15 This is a cross-sectional view illustrating an intermediate stage in the fabrication of a semiconductor element according to some embodiments of the present disclosure, in which a patterned mask is used as an etching mask to etch a metal oxide layer to form grooves in the metal oxide layer.

[0045] Figure 16 This is a cross-sectional view illustrating an intermediate stage in the fabrication of a semiconductor element according to some embodiments of the present disclosure, in order to remove a patterned mask and a polymer layer.

[0046] Figure 17 These are enlarged views illustrating some embodiments of this disclosure. Figure 16 Part of the structure shown.

[0047] Figure 18 This is a cross-sectional view illustrating an intermediate stage in the fabrication of a semiconductor element according to some embodiments of the present disclosure, where a patterned mask is used as an etching mask to form grooves on a metal oxide layer and a bonding pad.

[0048] Figure 19 This is a cross-sectional view illustrating an intermediate stage in the fabrication of a semiconductor element according to some embodiments of the present disclosure, in order to remove a patterned mask and a polymer layer.

[0049] Figure 20 These are enlarged views illustrating some embodiments of this disclosure. Figure 19 Part of the structure shown.

[0050] Explanation of reference numerals in the attached figures:

[0051] 10: Preparation method

[0052] 100A: Semiconductor Components

[0053] 100B: Semiconductor Components

[0054] 100C: Semiconductor Components

[0055] 101: Semiconductor substrate

[0056] 103: Bonding Pad

[0057] 103T: Top surface

[0058] 103': Recessed bonding pad

[0059] 103'T: Top surface

[0060] 105: First dielectric layer

[0061] 107: Second dielectric layer

[0062] 109: Third dielectric layer

[0063] 111: Patterned Masking

[0064] 120: Opening

[0065] 130: Opening

[0066] 133: Metal oxide layer

[0067] 133T: Top surface

[0068] 133': Recessed metal oxide layer

[0069] 133'T: Top surface

[0070] 135: Polymer layer

[0071] 137: Patterned Masking

[0072] 140: Opening

[0073] 150: Opening

[0074] 160: Groove

[0075] 170: Groove

[0076] 181: Bond wire

[0077] 181B: Bottom surface

[0078] A: Part

[0079] B: Part

[0080] D1: Distance

[0081] D2: Distance

[0082] S1: Splash structure

[0083] S2: Splash structure

[0084] S3: Splash structure

[0085] S4: Splash structure

[0086] S11: Steps

[0087] S13: Steps

[0088] S15: Steps

[0089] S17: Steps

[0090] S19: Steps

[0091] S21: Steps

[0092] S23: Steps

[0093] S25: Steps

[0094] S27: Steps

[0095] W1: Width

[0096] W2: Width

[0097] W3: Maximum width Detailed Implementation

[0098] The following description of this disclosure, accompanied by the accompanying drawings which are incorporated in and form part of this specification, illustrates embodiments of the disclosure; however, the disclosure is not limited to these embodiments. Furthermore, the following embodiments may be appropriately integrated to complete another embodiment.

[0099] Terms such as “an embodiment,” “an embodiment,” “an exemplary embodiment,” “another embodiment,” and “another embodiment” indicate that the embodiments described in this disclosure may include specific features, structures, or characteristics; however, not every embodiment must include that specific feature, structure, or characteristic. Furthermore, repeated use of the phrase “in an embodiment” does not necessarily refer to the same embodiment, but may refer to the same embodiment.

[0100] The following disclosure provides numerous different embodiments or examples of various features as implementations of this disclosure. Specific embodiments or examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to impose limitations. For example, the dimensions of an element are not limited to the disclosed range or values, but may depend on process conditions and / or the desired properties of the element. Furthermore, the description of a first feature being formed "above" or "on" a second feature in the following description can include embodiments in which the first and second features are formed in direct contact, and can also include embodiments in which additional features may be formed within the range of the first and second features, thereby potentially preventing direct contact between the first and second features. For simplicity and clarity, various features can be drawn at any scale. In the drawings, some layers / features may be omitted for simplicity.

[0101] Figure 1 This is a cross-sectional view illustrating a semiconductor device 100A according to some embodiments of the present disclosure. In some embodiments, the semiconductor device 100A includes a semiconductor substrate 101 having bonding pads 103 and a dielectric stack disposed on the semiconductor substrate 101. In some embodiments, the dielectric stack includes a first dielectric layer 105, a second dielectric layer 107 disposed on the first dielectric layer 105, and a third dielectric layer 109 disposed on the second dielectric layer 107.

[0102] In some embodiments, the sidewalls of the first dielectric layer 105, the second dielectric layer 107, and the third dielectric layer 109 are substantially aligned. Within the scope of this disclosure, the term "substantially" means preferably at least 90%, more preferably 95%, even more preferably 98%, and most preferably 99%. In some embodiments, at least a portion of the top surface 103T of the bonding pad 103 is exposed by the dielectric stack.

[0103] In some embodiments, the first dielectric layer 105 and the second dielectric layer 107 are made of different materials. In some embodiments, one of the first dielectric layer 105 and the second dielectric layer 107 has tensile stress, while the other of the first dielectric layer 105 and the second dielectric layer 107 has compressive stress, thus creating zero or near-zero stress between them.

[0104] In some embodiments, the semiconductor device 100A further includes a metal oxide layer 133 disposed on the top surface 103T of the bonding pad 103, and a polymer layer 135 covering the dielectric stack and the metal oxide layer 133. In some embodiments, the metal oxide layer 133 is in direct contact with the top surface 103T of the bonding pad 103. In some embodiments, the top surface and sidewalls of the third dielectric layer 109, the sidewalls of the second dielectric layer 107, and the sidewalls of the first dielectric layer 105 are covered by the polymer layer 135. Furthermore, in some embodiments, the polymer layer 135 is in direct contact with the top surface 133T of the metal oxide layer 133.

[0105] In some embodiments, bonding pad 103 comprises copper (Cu) or another suitable conductive material. In some embodiments, metal oxide layer 133 comprises tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), or combinations thereof. Additionally, metal oxide layer 133 may comprise other materials, such as oxides of aluminum (Al), hafnium (Hf), zirconium (Zr), nickel (Ni), zinc (Zn), or combinations thereof. It should be understood that metal oxide layer 133 can be used to prevent ions from migrating from bonding pad 103 to adjacent areas. Furthermore, according to some embodiments, polymer layer 135 comprises polyimide (PI).

[0106] In some embodiments, the semiconductor element 100A further includes a bonding wire 181 penetrating the metal oxide layer 133 to physically contact the bonding pad 103. It should be understood that the thickness of the metal oxide layer 133 is selected based on the downward force applied when the bonding wire 181 is bonded to the semiconductor substrate 101. In some embodiments, the bonding wire 181 is in direct contact with the bonding pad 103, the metal oxide layer 133, and the polymer layer 135. In some embodiments, the metal oxide layer 133 is in direct contact with the sidewalls of the first dielectric layer 105 and the bottom surface 181B of the bonding wire 181.

[0107] Furthermore, according to some embodiments, the metal oxide layer 133 includes a sputtering structure S1 protruding from the top surface 133T of the metal oxide layer 133, and the bottom surface 181B of the bonding wire 181 is surrounded by and in direct contact with the sputtering structure S1. In some embodiments, the bonding wire 181 is separated from the dielectric stack by a polymer layer 135. In some embodiments, this portion of the bonding pad 103 exposed by the dielectric stack is completely covered by the metal oxide layer 133 and the bonding wire 181. That is, the top surface 103T of the bonding pad 103 is not exposed to air or moisture in the environment, thus preventing oxidation or contamination.

[0108] Figure 2This is a cross-sectional view illustrating a semiconductor element 100B according to some embodiments of the present disclosure. Semiconductor element 100B may be similar to semiconductor element 100A, wherein the same reference numerals refer to the same elements, and certain details or descriptions of the same elements are not repeated. Some differences will be pointed out below. In semiconductor element 100B, no polymer layer is sandwiched between the bonding wire 181 and the dielectric stack.

[0109] Furthermore, according to some embodiments, the metal oxide layer 133' in the semiconductor element 100B includes a sputtering structure S2 protruding from the top surface 133'T of the metal oxide layer 133', and the bottom surface 181B of the bonding wire 181 is surrounded by and in direct contact with the sputtering structure S2.

[0110] In semiconductor device 100A, there is a distance D1 between the topmost surface of sputtered structure S1 and the top surface 133T of the metal oxide layer 133 covered by polymer layer 135. In semiconductor device 100B, there is a distance D2 between the topmost surface of sputtered structure S2 and the top surface 133'T of the metal oxide layer 133' near the first dielectric layer 105. In some embodiments, distance D1 is greater than distance D2.

[0111] Figure 3 This is a cross-sectional view illustrating a semiconductor element 100C according to some embodiments of the present disclosure. Semiconductor element 100C may be similar to semiconductor element 100A, wherein the same reference numerals refer to the same element, and certain details or descriptions of the same element are not repeated. Some differences will be pointed out below. In semiconductor element 100C, no polymer layer is sandwiched between the bonding wire 181 and the dielectric stack.

[0112] Furthermore, in the semiconductor device 100C, according to some embodiments, the bonding pad 103' includes a sputtering structure S3 protruding from the top surface 103'T of the bonding pad 103', the metal oxide layer 133' includes a sputtering structure S4 protruding from the top surface 133'T of the metal oxide layer 133', and the bottom surface 181B of the bonding wire 181 is surrounded and directly contacted by the sputtering structures S3 and S4. In some embodiments, the bottom surface 181B of the bonding wire 181 is located below the top surface 103'T of the bonding pad 103'.

[0113] Figure 4 The flowchart illustrates a method 10 for fabricating semiconductor devices (e.g., semiconductor devices 100A, 100B, and 100C) according to some embodiments of the present disclosure. According to some embodiments, the fabrication method 10 includes steps S11, S13, S15, S17, S19, S21, S23, S25, and S27. Figure 4Steps S11 to S27 will be explained in conjunction with the following figures.

[0114] Figures 5 to 14 This is a cross-sectional view illustrating intermediate stages in the fabrication of semiconductor device 100A according to some embodiments of this disclosure. Figure 5 As shown, a semiconductor substrate 101 with bonding pads 103 is provided. The corresponding steps are shown in... Figure 4 Step S11 of preparation method 10.

[0115] The semiconductor substrate 101 may be a semiconductor wafer, such as a silicon wafer. Additionally, the semiconductor substrate 101 may include elementary semiconductor materials, compound semiconductor materials, and / or alloy semiconductor materials. Elementary semiconductor materials may include, for example, but are not limited to, crystalline silicon, polycrystalline silicon, amorphous silicon, germanium, and / or diamond. Compound semiconductor materials may include, for example, but are not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. Alloy semiconductor materials may include, for example, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP.

[0116] Semiconductor substrate 101 may include a variety of passive and active microelectronic components, such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (pFETs), n-type field-effect transistors (nFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bicarrier junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high-voltage transistors, high-frequency transistors, fin field-effect transistors (FinFETs), other suitable integrated circuit (IC) components, or combinations thereof.

[0117] Furthermore, the semiconductor substrate 101 may include various material layers (e.g., dielectric layers, semiconductor layers, and / or conductive layers) configured to form IC features (e.g., doped regions, isolation features, gate features, source / drain features, interconnect features, other features, or combinations thereof). For example, bonding pads 103 are electrically connected to conductive layers within the semiconductor substrate 101. For clarity, the semiconductor substrate 101 has been simplified. It should be understood that additional features may be added to the semiconductor substrate 101, and some of the features described below may be replaced, modified, or eliminated in other embodiments.

[0118] In some embodiments, the bonding pad 103 comprises copper (Cu) or another suitable conductive material. Furthermore, according to some embodiments, the semiconductor substrate 101 has more than one bonding pad, the material of which includes copper (Cu).

[0119] Secondly, according to some embodiments, the dielectric stack is formed on the semiconductor substrate 101, such as... Figure 6 As shown. In some embodiments, a first dielectric layer 105, a second dielectric layer 107, and a third dielectric layer 109 are sequentially formed on a semiconductor substrate 101, and the bonding pad 103 is covered by the dielectric stack. The corresponding steps are shown in Figure 4 Step S13 of preparation method 10.

[0120] The materials of the first dielectric layer 105, the second dielectric layer 107, and the third dielectric layer 109 may include silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, and / or combinations thereof. In some embodiments, the first dielectric layer 105 and the second dielectric layer 107 are made of different materials. For example, one of the first dielectric layer 105 and the second dielectric layer 107 has tensile stress, while the other of the first dielectric layer 105 and the second dielectric layer 107 has compressive stress, thus creating zero or near-zero stress between them.

[0121] Furthermore, the first dielectric layer 105, the second dielectric layer 107, and the third dielectric layer 109 can be fabricated using deposition processes. Deposition processes may include chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), other suitable processes, and / or combinations thereof.

[0122] Then, according to some embodiments, a patterned mask 111 with openings 120 is formed on the dielectric stack, such as... Figure 7 As shown. In some embodiments, the opening 120 of the patterned mask 111 exposes a top surface of the third dielectric layer 109. In some embodiments, the opening 120 of the patterned mask 111 has a width W1.

[0123] Subsequently, according to some embodiments, a patterned mask 111 is used as an etching mask to perform an etching process on the dielectric stack, thus forming an opening 130 in the dielectric stack, such as... Figure 8 As shown. In some embodiments, the top surface 103T of the bonding pad 103 is at least partially exposed by the opening 130. The corresponding steps are shown in Figure 4 Step S15 of preparation method 10.

[0124] In some embodiments, the etching process performed on the dielectric stack includes a dry etching process, a wet etching process, or a combination thereof. After the etching process, the first dielectric layer 105, the second dielectric layer 107, and the third dielectric layer 109 have substantially aligned sidewalls (i.e., the sidewalls of the opening 130).

[0125] Furthermore, in some embodiments, the width of the opening 130 is substantially equal to the width W1. After the top surface 103T of the bonding pad 103 is exposed by the opening 130, the patterned mask 111 can be removed. In some embodiments, the patterned mask 111 is removed by a stripping process, an ashing process, an etching process, or another suitable process.

[0126] Secondly, according to some embodiments, a metal oxide layer 133 is deposited on the top surface 103T of the bonding pad 103 using a selective deposition process, such as... Figure 9 As shown. The corresponding steps are shown in Figure 4 Step S17 of preparation method 10. In some embodiments, the selective deposition process is an ALD process. It should be understood that after selectively depositing the metal oxide layer 133, the sidewalls of the dielectric stack are exposed. That is, the sidewalls of the dielectric stack are not covered by the metal oxide layer 133.

[0127] In some embodiments, in a selective deposition process, Figure 8 The structure (with or without patterned mask 111) is exposed to the metal precursor and alcohol, respectively. In some embodiments, the metal precursor includes tantalum (Ta), titanium (Ti), aluminum (Al), hafnium (Hf), zirconium (Zr), nickel (Ni), zinc (Zn), or combinations thereof. In some embodiments, the alcohol includes methanol, ethanol, isopropanol, tert-butanol, or combinations thereof. It should be understood that the thickness of the metal oxide layer 133 is relatively small, and the sidewalls of the first dielectric layer 105 are not substantially covered by the metal oxide layer 133.

[0128] Then, according to some embodiments, a polymer layer 135 is deposited to cover the dielectric stack and the metal oxide layer 113, such as Figure 10 As shown. The corresponding steps are shown in Figure 4 Step S19 of preparation method 10. In some embodiments, a polymer layer 135 is formed to cover the top surface and sidewalls of the third dielectric layer 109, the sidewalls of the second dielectric layer 107, and the sidewalls of the first dielectric layer 105.

[0129] In some embodiments, opening 130 (see...) Figure 9The polymer layer 135 is filled with polymer 135. In some embodiments, polymer layer 135 comprises polyimide. Furthermore, polymer layer 135 can be fabricated using deposition processes such as CVD, PVD, ALD, or other suitable deposition processes.

[0130] Subsequently, according to some embodiments, a patterned mask 137 with openings 140 is formed on the polymer layer 135, such as... Figure 11 As shown. In some embodiments, the opening 140 of the patterned mask 137 exposes a top surface of the polymer layer 135. In some embodiments, the opening 140 of the patterned mask 137 has a width W2.

[0131] Secondly, according to some embodiments, a patterned mask 137 is used as an etching mask to perform an etching process on the polymer layer 135, thus forming an opening 150 in the polymer layer 135, such as... Figure 12 As shown. In some embodiments, the top surface 133T of the metal oxide layer 133 is partially exposed by the opening 150. The corresponding steps are shown in Figure 4 Step S21 of preparation method 10.

[0132] In some embodiments, the etching process performed on the polymer layer 135 includes a dry etching process, a wet etching process, or a combination thereof. Following the etching process, according to some embodiments, the top surface and sidewalls of the dielectric stack are completely covered by the polymer layer 135, while a portion of the metal oxide layer 133 is covered by the polymer layer 135. Furthermore, in some embodiments, the width of the opening 150 is substantially equal to the width W2.

[0133] After the top surface 133T of the metal oxide layer 133 is exposed by the opening 150, according to some embodiments, the patterned mask 137 is removed, such as... Figure 13 As shown. In some embodiments, the patterned mask 137 is removed by a stripping process, an ashing process, an etching process, or another suitable process. In some embodiments, the width W2 of the opening 150 in the polymer layer 135 is smaller than the width W1 of the opening 130 in the dielectric stack.

[0134] After removing the patterned mask 137, according to some embodiments, the bonding wire 181 is aligned with the opening 150, exposing the top surface 133T of the metal oxide layer 133, such as... Figure 14 As shown. In some embodiments, the bonding wire 181 comprises copper (Cu), tungsten (W), or other suitable materials. In some embodiments, the bonding wire 181 is bonded to the semiconductor substrate 101 by applying a downward force.

[0135] Then, according to some embodiments, bonding wire 181 is bonded to semiconductor substrate 101, such as... Figure 1 As shown. In some embodiments, the bonding wire 181 penetrates the metal oxide layer 133 to make physical contact with the bonding pad 103. The corresponding steps are shown in Figure 4 Step S27 of preparation method 10 in the process. After bonding wire 181 is bonded to bonding pad 103, semiconductor device 100A is obtained.

[0136] As described above, in the bonding process, around the bonding wire 181 and the opening 150 (see...) Figure 14 A sputtering structure S1 is formed in the metal oxide layer 133. In some embodiments, the sputtering structure S1 is fabricated using the material of the metal oxide layer 133, and the bottom surface 181B of the bonding wire 181 is surrounded by and in direct contact with the sputtering structure S1. In some embodiments, a gap exists between the sputtering structure S1 of the metal oxide layer 133 and the bonding wire 181.

[0137] In semiconductor device 100A, bonding pad 103 is completely covered by metal oxide layer 133 and bonding wire 181 after the bonding process. That is, bonding pad 103 is not exposed to air. This protects bonding pad 103 from oxidation and contamination, and metal oxide layer 133 provides mechanical support for bonding wire 181. Furthermore, the material of metal oxide layer 133 is selected to prevent ions from migrating from bonding pad 103 to adjacent areas. Moreover, metal oxide layer 133 is selectively deposited on bonding pad 103 without oxidation, thus preventing adverse effects on device performance. Therefore, the performance of semiconductor device 100A can be improved.

[0138] Figure 15 and Figure 16 This is a cross-sectional view illustrating some embodiments of this disclosure, from... Figure 12 The structure shown continues the intermediate stage of fabricating semiconductor device 100B. According to some embodiments, after the etching process of polymer layer 135, a patterned mask 137 is used as an etching mask to etch metal oxide layer 133, thus forming a groove 160 in the recessed metal oxide layer 133', as... Figure 15 As shown. The corresponding steps are shown in Figure 4 Step S23 of preparation method 10.

[0139] In some embodiments, the etching process performed on the metal oxide layer 133 includes a dry etching process, a wet etching process, or a combination thereof. Following the etching process, according to some embodiments, the bonding pad 103 remains covered by the recessed metal oxide layer 133'. Furthermore, in some embodiments, the width of the groove 160 is substantially equal to the width W2.

[0140] After the recessed metal oxide layer 133' is formed, according to some embodiments, the patterned mask 137 and the polymer layer 135 are removed, such as... Figure 16 As shown. Figure 17 These are enlarged views illustrating some embodiments of this disclosure. Figure 16 Part A of the structure shown. The corresponding steps are shown in Figure 4 Step S25 of preparation method 10.

[0141] Some of the processes used to remove the polymer layer 135 are similar to or the same as those used to remove the patterned mask 137, and their details will not be repeated here. After the polymer layer 135 is removed, according to some embodiments, the top surface 133'T of the metal oxide layer 133' is fully exposed by the opening 150 and the groove 160.

[0142] Subsequently, according to some embodiments, bonding wire 181 is bonded to semiconductor substrate 101, such as... Figure 2 As shown. In some embodiments, the bonding wire 181 penetrates the metal oxide layer 133' to physically contact the bonding pad 103. The corresponding steps are shown in Figure 4 Step S27 of preparation method 10.

[0143] After the bonding wire 181 is bonded to the bonding pad 103, a semiconductor device 100B is obtained. In some embodiments, the bonding wire 181 has a maximum width W3, and the maximum width W3 is less than or substantially equal to the groove 160 (see...). Figure 17 The width W2 of ).

[0144] As described above, in the bonding process, the sputtering structure S2 is formed around the bonding wire 181 and the opening 150 and the groove 160 (see...). Figure 16 In some embodiments, the sputtering structure S2 is fabricated using the material of the metal oxide layer 133', while the bottom surface 181B of the bonding wire 181 is surrounded by and in direct contact with the sputtering structure S2.

[0145] In some embodiments, since the metal oxide layer 133 is etched prior to the bonding process to form a recessed metal oxide layer 133' with grooves 160, a space is reserved for accommodating the sputtering structure S2 formed during the bonding process. Figure 2 The distance D2 is less than Figure 1 The distance D1. Therefore, it can prevent the formation of unexpected electrical connections between adjacent bonding pads.

[0146] Figure 18 and Figure 19 This is a cross-sectional view illustrating some embodiments of this disclosure, from... Figure 12The structure shown continues the intermediate stage of fabricating semiconductor device 100C. According to some embodiments, after the etching process of polymer layer 135, a patterned mask 137 is used as an etching mask to etch the metal oxide layer 133 and bonding pad 103, thus forming grooves 170 in the recessed metal oxide layer 133' and the recessed bonding pad 103', as... Figure 18 As shown. The corresponding steps are shown in Figure 4 Step S23 of preparation method 10.

[0147] In some embodiments, the etching process performed on the metal oxide layer 133 and the bonding pad 103 includes a dry etching process, a wet etching process, or a combination thereof. In some embodiments, the groove 170 penetrates the metal oxide layer 133', exposing the bonding pad 103. Furthermore, in some embodiments, the width of the groove 170 is substantially equal to the width W2.

[0148] According to some embodiments, after the recessed metal oxide layer 133' and the recessed bonding pad 103' are formed, the patterned mask 137 and the polymer layer 135 are removed, such as... Figure 19 As shown. Figure 20 These are enlarged views of specific parts, illustrating some embodiments of this disclosure. Figure 19 Part B of the structure shown. The corresponding steps are shown in Figure 4 Step S25 of preparation method 10. After removing the polymer layer 135, according to some embodiments, the top surface 133'T of the metal oxide layer 133' is completely exposed by the opening 150 and the groove 170.

[0149] Secondly, according to some embodiments, bonding wire 181 is bonded to semiconductor substrate 101, such as... Figure 3 As shown. In some embodiments, the bonding wire 181 makes physical contact with the metal oxide layer 133' and the bonding pad 103'. The corresponding steps are shown in Figure 4 Step S27 of preparation method 10.

[0150] After the bonding wire 181 is bonded to the bonding pad 103', a semiconductor device 100C is obtained. In some embodiments, the bonding wire 181 has a maximum width W3, and the maximum width W3 is less than or substantially equal to the groove 170 (see...). Figure 20 The width W2 of ).

[0151] As described above, in the bonding process, sputtering structures S3 and S4 are formed around the bonding wire 181 and in the opening 150 and the groove 170 (see...). Figure 19In some embodiments, the sputtering structure S3 is fabricated using the material of the metal oxide layer 133', while the sputtering structure S4 is fabricated using the material of the bonding pad 103', and the bottom surface 181B of the bonding wire 181 is surrounded by and in direct contact with the sputtering structures S3 and S4.

[0152] In some embodiments, since the metal oxide layer 133 and the bonding pad 103 are etched prior to the bonding process to form a metal oxide layer 133' with recesses and a bonding pad 103' with recesses, the sputtering structures S3 and S4 formed in the bonding process retain a receiving space, which can prevent the formation of unexpected electrical connections between adjacent bonding pads.

[0153] This disclosure provides a semiconductor device with bonding wires and a method for fabricating the same. The semiconductor device includes a metal oxide layer (e.g., metal oxide layer 133 or 133') disposed on a bonding pad (e.g., bonding pad 103 or 103'), and bonding wires (e.g., bonding wire 181) penetrating the metal oxide layer to bond to the bonding pad. After the bonding process, the bonding pad is completely covered by the metal oxide layer and the bonding wires. That is, the bonding pad is not exposed to air. This protects the bonding pad from oxidation and contamination, and the metal oxide layer provides mechanical support for the bonding wire junction.

[0154] Furthermore, the material of the metal oxide layer can be selected to prevent ions from migrating from the bonding pads to adjacent areas. Additionally, the metal oxide layer is selectively deposited on the bonding pads (e.g., using an ALD process) without performing an oxidation process, thus preventing adverse effects on device performance. Therefore, the performance of the semiconductor device can be improved.

[0155] One embodiment of this disclosure provides a semiconductor device, comprising: a semiconductor substrate having a bonding pad; a first dielectric layer disposed on the semiconductor substrate, wherein a portion of the bonding pad is exposed by the first dielectric layer; a metal oxide layer disposed on the portion of the bonding pad; and a wire bond penetrating the metal oxide layer and bonded to the bonding pad. The portion of the bonding pad is completely covered by the metal oxide layer and the wire bond.

[0156] Another embodiment of this disclosure provides a semiconductor device, comprising: a semiconductor substrate having a bonding pad; a dielectric stack disposed on the semiconductor substrate; a bonding wire physically bonded to a top surface of the bonding pad; and a metal oxide layer disposed on the top surface of the bonding pad. The top surface of the bonding pad is exposed by the dielectric stack. The metal oxide layer is in direct contact with a bottom surface of the bonding wire and a sidewall of the dielectric stack.

[0157] In another embodiment of this disclosure, a method for fabricating a semiconductor device is provided, comprising: providing a semiconductor substrate having a bonding pad; forming a first dielectric layer on the bonding pad; etching the first dielectric layer to expose a top surface of the bonding pad; selectively depositing a metal oxide layer on the top surface of the bonding pad; and bonding a bonding wire to the semiconductor substrate, wherein the bonding wire penetrates the metal oxide layer and makes physical contact with the bonding pad.

[0158] The embodiments of this disclosure have several advantageous features. By forming a metal oxide layer covering the bonding pads prior to the bonding process, oxidation and contamination of the bonding pads can be prevented before and after the bonding process, and the metal oxide layer can provide mechanical support for the bonding wires. Therefore, the performance of the semiconductor device can be improved.

[0159] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives can be made without departing from the concept and scope of this disclosure as defined by the published claims. For example, many of the processes described above can be implemented in different ways, and many of the processes described above can be replaced by other processes or combinations thereof.

[0160] Furthermore, the scope of this disclosure is not limited to the specific embodiments of the processes, machinery, manufacturing, material compositions, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure that existing or future processes, machinery, manufacturing, material compositions, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used according to this disclosure. Accordingly, such processes, machinery, manufacturing, material compositions, means, methods, or steps are included within the scope of the claims disclosed in this disclosure.

Claims

1. A semiconductor element, comprising: A semiconductor substrate having a bonding pad; A first dielectric layer is disposed on the semiconductor substrate, wherein a portion of the bonding pad is exposed by the first dielectric layer; A metal oxide layer is disposed on this portion of the bonding pad; A bonding wire penetrates the metal oxide layer and bonds to the bonding pad, wherein this portion of the bonding pad is completely covered by the metal oxide layer and the bonding wire; and A polymer layer covers the sidewalls of the first dielectric layer and is in direct contact with the metal oxide layer and the bonding wire.

2. The semiconductor device of claim 1, wherein the bonding pad comprises copper.

3. The semiconductor device of claim 1, wherein the metal oxide layer includes a sputtering structure protruding from a top surface of the metal oxide layer, and a bottom surface of the bonding wire is surrounded by and in direct contact with the sputtering structure of the metal oxide layer.

4. The semiconductor device of claim 1, further comprising: A second dielectric layer is disposed on the first dielectric layer; as well as A third dielectric layer is disposed on the second dielectric layer, wherein the first dielectric layer, the second dielectric layer and the third dielectric layer each have substantially aligned sidewalls.

5. The semiconductor device of claim 4, further comprising: The polymer layer covers a top surface of the third dielectric layer and the sidewalls of the second and third dielectric layers.

6. A semiconductor element, comprising: A semiconductor substrate having a bonding pad; A dielectric stack is disposed on the semiconductor substrate, wherein a top surface of the bonding pad is exposed by the dielectric stack; A bonding wire is physically bonded to the top surface of the bonding pad; A metal oxide layer is disposed on the top surface of the bonding pad, wherein the metal oxide layer is in direct contact with a bottom surface of the bonding wire and a sidewall of the dielectric stack. as well as A polymer layer is disposed between the bonding wire and the dielectric stack, wherein the polymer layer is in direct contact with a top surface of the metal oxide layer, the polymer layer covers the sidewalls of the dielectric stack, and is in direct contact with the bonding wire.

7. The semiconductor element of claim 6, wherein the metal oxide layer surrounds and mechanically supports the bottom surface of the bonding wire.

8. The semiconductor element of claim 6, wherein the bonding pad comprises copper.

9. The semiconductor device of claim 6, wherein the dielectric stack comprises a first dielectric layer, a second dielectric layer disposed on the first dielectric layer, and a third dielectric layer disposed on the second dielectric layer, and wherein the first dielectric layer and the second dielectric layer are made of different materials.

10. The semiconductor device of claim 9, wherein the interface between the first dielectric layer and the second dielectric layer is above the topmost surface of the metal oxide layer.

11. The semiconductor device of claim 6, wherein the polymer layer comprises polyimide.

12. A method for fabricating a semiconductor device, comprising: Provide a semiconductor substrate with a bonding pad; A first dielectric layer is formed on the bonding pad; The first dielectric layer is etched to expose a top surface of the bonding pad; A metal oxide layer is selectively deposited on the top surface of the bonding pad; A polymer layer is deposited to cover the first dielectric layer and the metal oxide layer; The polymer layer is etched to expose the top surface of the metal oxide layer; as well as A bonding wire is bonded to the semiconductor substrate, wherein the bonding wire penetrates the metal oxide layer and makes physical contact with the bonding pad. The polymer layer covers the sidewalls of the first dielectric layer and is in direct contact with the bonding line.

13. The method for fabricating a semiconductor device as described in claim 12, wherein the metal oxide layer is selectively deposited by an atomic layer deposition process.

14. The method of fabricating a semiconductor device as claimed in claim 12, further comprising, before exposing the top surface of the bonding pad: A second dielectric layer is formed on the first dielectric layer; A third dielectric layer is formed on the second dielectric layer; A patterned mask is formed on the third dielectric layer; as well as Using the patterned mask as an etching mask, the first dielectric layer, the second dielectric layer, and the third dielectric layer are etched to expose the top surface of the bonding pad.

15. The method for fabricating a semiconductor element as claimed in claim 12, wherein the bonding wire is separated from the first dielectric layer by the polymer layer.

16. The method of fabricating a semiconductor device as claimed in claim 12, wherein after exposing the top surface of the metal oxide layer, the method further comprises: A polymer layer is used as an etching mask to etch the metal oxide layer; as well as The polymer layer is removed before the bonding wire is bonded to the semiconductor substrate.

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