Semiconductor package

Abstract

This disclosure provides a semiconductor package. The semiconductor package has a semiconductor die, a package substrate, and a plurality of bonding lines. The semiconductor die has a plurality of input / output pads disposed on an active side. The package substrate has a first side and a second side, the first side being attached to the active side of the semiconductor die, the second side being opposite to the semiconductor die, and having an opening that passes through the package substrate. The plurality of input / output pads overlap with the opening. The width of the opening on the second side of the package substrate is greater than the width of the opening on the first side of the package substrate. The plurality of bonding lines connect the plurality of input / output pads to the second side of the package substrate through the opening in the package substrate.

Description

[0001] This invention claims priority and benefits to U.S. Patent Application No. 17 / 492,093 (priority date: October 1, 2021), the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] This disclosure relates to a semiconductor package and a method for fabricating the same. More particularly, it relates to a ball-grid array (BGA) semiconductor package and a method for fabricating the same. Background Technology

[0003] BGA (Browser Grid Array) packaging is a surface-mount package used in electronic products to mount multiple integrated circuits. In a BGA package, the interconnecting pins are arranged in the form of solder balls. These solder balls provide multiple short connection paths to a printed circuit board (PCB), thus reducing impedance between them. Compared to dual in-line or planar semiconductor packages where only the peripheral area is used for interconnecting pins, the entire lower surface of a BGA package can be used for interconnecting pins (e.g., solder balls). Therefore, a BGA package can provide more connections within a given area.

[0004] To shorten the connection between the chip and the package substrate in a BGA package, the chip can be attached to the package substrate face-down. A flip chip bonding process is used to achieve this face-down bonding. However, flip chip bonding is not perfect. At least, compared to wire bonding or other bonding technologies, flip chip bonding is not a cost-effective method.

[0005] The above description of "prior art" provides background information only and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art of this disclosure, and no description of the above "prior art" should be considered part of the invention. Summary of the Invention

[0006] One embodiment of this disclosure provides a semiconductor package. The semiconductor package includes a semiconductor die having a plurality of input / output pads disposed on an active side of the semiconductor die; a package substrate having a first side attached to the active side of the semiconductor die and a second side facing away from the semiconductor die, and having an opening passing through the package substrate, wherein the plurality of input / output pads overlap with the opening, and the width of the opening on the second side of the package substrate is greater than the width of the opening on the first side of the package substrate; and a plurality of bonding wires connecting the plurality of input / output pads to the second side of the package substrate via the opening of the package substrate.

[0007] Another embodiment of this disclosure provides a semiconductor package. The semiconductor package includes a semiconductor die having a plurality of input / output pads disposed on an active side of the semiconductor die; a package substrate having a first side attached to the active side of the semiconductor die and a second side facing away from the semiconductor die and laterally surrounding an opening, wherein the plurality of input / output pads overlap the opening, the opening having a plurality of long sides and a plurality of short sides, a width across the plurality of long sides of the opening on the second side of the package substrate being greater than a width across the plurality of long sides of the opening on the first side of the package substrate; and a plurality of bonding wires crossing the plurality of long sides of the opening to connect the plurality of input / output pads to the second side of the package substrate.

[0008] Another embodiment of this disclosure provides a semiconductor package. The semiconductor package includes a semiconductor die having a plurality of input / output pads disposed on an active side of the semiconductor die; a package substrate having a first side attached to the active side of the semiconductor die and a second side facing away from the semiconductor die, and having an opening passing through the package substrate, wherein the plurality of input / output pads overlap with the opening, and a width of the opening on the second side of the package substrate is greater than a width of the opening on the first side of the package substrate; a plurality of bonding wires connecting the plurality of input / output pads to the second side of the package substrate via the opening; a first encapsulation laterally encapsulating the semiconductor die; and a second encapsulation filling the opening and extending to the second side of the package substrate.

[0009] The technical features and advantages of this disclosure have been summarized quite extensively above to provide a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure through modifications or design of other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the appended claims. Attached Figure Description

[0010] The disclosure of the present invention can be more fully understood by referring to the accompanying drawings in conjunction with the embodiments and claims, wherein the same element symbols in the drawings refer to the same elements.

[0011] Figure 1A This is a cross-sectional schematic diagram illustrating a semiconductor package according to some embodiments of the present disclosure.

[0012] Figure 1BThis is a planar schematic diagram illustrating the active side of a semiconductor package according to some embodiments of the present disclosure.

[0013] Figure 1C This is a plan view illustrating some embodiments of the present disclosure, for example. Figure 1A The bottom side of the semiconductor package shown.

[0014] Figure 1D This is an enlarged schematic diagram illustrating the opening of the packaging substrate in a semiconductor package according to some embodiments of the present disclosure.

[0015] Figure 1E This is a cross-sectional schematic diagram illustrating a semiconductor package viewed along the Y direction in some embodiments of the present disclosure.

[0016] Figure 2 This is a flowchart illustrating a method for preparing a semiconductor package according to some embodiments of this disclosure.

[0017] Figures 3A to 3H This is a sectional view, exemplified in... Figure 2 The intermediate structures along direction X at different stages during the preparation process shown.

[0018] Figure 4A This is a cross-sectional schematic diagram illustrating a semiconductor package according to some embodiments of the present disclosure.

[0019] Figure 4B This is an enlarged schematic diagram, exemplified as follows: Figure 4A The opening in the packaging substrate of the semiconductor package shown.

[0020] Figure 5A This is a cross-sectional schematic diagram illustrating a semiconductor package according to some embodiments of the present disclosure.

[0021] Figure 5B This is an enlarged schematic diagram, exemplified as follows: Figure 5A The opening of the packaging substrate 10-2 in the semiconductor package shown.

[0022] Figure 6A This is a cross-sectional schematic diagram illustrating a semiconductor package according to some embodiments of the present disclosure.

[0023] Figure 6B This is an enlarged schematic diagram, exemplified as follows: Figure 6A The opening in the packaging substrate of the semiconductor package shown.

[0024] Figure 7 This is a cross-sectional schematic diagram illustrating a semiconductor package according to some embodiments of the present disclosure.

[0025] The attached figures are labeled as follows:

[0026] 10: Semiconductor Packaging

[0027] 10-1: Semiconductor Packaging

[0028] 10-2: Semiconductor Packaging

[0029] 10-3: Semiconductor Packaging

[0030] 10-4: Semiconductor Packaging

[0031] 100: Semiconductor die

[0032] 102: Input / Output Pads

[0033] 104: Packaging substrate

[0034] 104-1: Packaging substrate

[0035] 104-2: Packaging substrate

[0036] 104-3: Packaging substrate

[0037] 104-4: Packaging substrate

[0038] 106: Encapsulated Input / Output

[0039] 106a: Solder paste

[0040] 106b: Tin ball

[0041] 108: Adhesive

[0042] 110: Connection line

[0043] 112: Conductive pad

[0044] 114: Encapsulated body

[0045] 116: Encapsulated body

[0046] 300: Initial packaging substrate

[0047] 300e: Edge section

[0048] 302: Joining tool

[0049] 304: Mold

[0050] 306: Chamber

[0051] 308: Chamber

[0052] 310: Entrance

[0053] 312: Entrance

[0054] 314: Encapsulated body

[0055] AS: Active side

[0056] A S1 :angle

[0057] A S1’ :angle

[0058] A S2 :angle

[0059] A S2’ :angle

[0060] BS: Backside

[0061] CR: Central Area

[0062] E S2 :edge

[0063] LS: Long side

[0064] L S1 First length

[0065] L S2 Second length

[0066] MR: Memory Array

[0067] S1: First side

[0068] S2: Second side

[0069] S11: Steps

[0070] S13: Steps

[0071] S15: Steps

[0072] S17: Steps

[0073] S19: Steps

[0074] S21: Steps

[0075] S23: Steps

[0076] S25: Steps

[0077] SP1: Lateral Space

[0078] SP2: Lateral Space

[0079] SS: Short side

[0080] SW1: Sidewall

[0081] SW1C: Sidewall

[0082] SW1N: Sidewall

[0083] SW1S: Sidewall

[0084] SW1V: Sidewall

[0085] SW2: Sidewall

[0086] TH: Opening

[0087] TH': Open

[0088] TH-1: Opening

[0089] TH-2: Opening

[0090] TH-3: Opening

[0091] TH-4: Opening

[0092] W S1 First width

[0093] W S2 Second width

[0094] X: Direction

[0095] Y: direction Detailed Implementation

[0096] The following describes specific examples of components and configurations to simplify embodiments of this disclosure. Of course, these embodiments are merely illustrative and are not intended to limit the scope of this disclosure. For example, in the description, a first component is formed on top of a second component, which may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components do not directly contact each other. Furthermore, reference numerals and / or letters may be repeated in many examples of embodiments of this disclosure. These repetitions are for simplicity and clarity and, unless specifically stated herein, do not in themselves represent a specific relationship between the various embodiments and / or the configurations discussed.

[0097] Furthermore, for ease of explanation, spatial relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship between one element or feature shown in the figures and another element or feature. These spatial relative terms are intended to encompass different orientations of the elements in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein can be interpreted accordingly.

[0098] Figure 1A This is a cross-sectional schematic diagram illustrating a semiconductor package 10 according to some embodiments of the present disclosure.

[0099] Please refer to Figure 1AA semiconductor die 100 is mounted in a semiconductor package 10. The semiconductor die 100 is one of a plurality of wafers monolithically formed from a device wafer. In some embodiments, the semiconductor die 100 is a semiconductor die, such as a double data rate fourth generation (DDR4) dynamic random access memory (DRAM) die. Multiple integrated circuits (e.g., memory circuits) may be formed on a front surface of a semiconductor substrate in the semiconductor die 100, and the integrated circuits formed on one side of the semiconductor die 100 may be described as an active side AS. Multiple input / output (I / O) pads 102 are formed on the active side AS and serve as the respective inputs / outputs of the integrated circuits. Multiple signals may be provided to or output from the semiconductor die 100 via the multiple input / output pads 102.

[0100] Figure 1B This is a planar schematic diagram illustrating the active side AS of a semiconductor package 100 according to some embodiments of the present disclosure.

[0101] Please refer to Figure 1A and Figure 1B In some embodiments, multiple input / output pads 102 are disposed within a central region CR of the active side AS. For example, the multiple input / output pads 102 may be disposed along two columns in the central region CR. In embodiments where the semiconductor die 100 is a memory die, multiple memory arrays MR in the semiconductor die 100 may be disposed on opposite sides of the multiple input / output pads 102 and routed to the multiple input / output pads 102. Furthermore, multiple drive circuits (not shown) for assisting the operation of the multiple memory arrays MR may be disposed around the multiple memory arrays MR and connected to the multiple memory arrays MR and the multiple input / output pads 102. Since the multiple memory arrays MR are embedded in the semiconductor die 100, they are in Figure 1B The diagram is schematically shown in dashed lines. Furthermore, the multiple input / output pads 102 and the multiple memory arrays MR can be cross-configured into other possible architectures, and this disclosure is not limited to the architecture of the multiple input / output pads 102 and the multiple memory arrays MR.

[0102] Please refer to Figure 1AA semiconductor die 100 is attached to a package substrate 104. Although not shown, the package substrate 104 may include multiple wires embedded in a stack of multiple isolation layers. The multiple wires are configured to outroute multiple input / output pads 102 of the semiconductor die 100. In some embodiments, the package substrate 104 has a dielectric core, and multiple isolation layers and multiple wires are formed on one side or opposite sides of the dielectric core. In other embodiments, the package substrate 104 is a core-less package substrate, and multiple isolation layers are stacked without an intermediate dielectric core. Furthermore, multiple package inputs / outputs 106 are disposed on the side of the package substrate 104 opposite to the semiconductor die 100. The multiple input / output pads 102 of the semiconductor die 100 may be connected to the multiple package inputs / outputs 106 via multiple wires in the package substrate 104. In some embodiments, the semiconductor package 10 is a ball-grid-array (BGA) package. In these embodiments, the plurality of packaged inputs / outputs 106 may include a plurality of solder pastes 106a and a plurality of solder balls 106b.

[0103] Semiconductor die 100 can be bonded to package substrate 104 via an active side AS. In some embodiments, an adhesive 108 may be disposed between the active side AS of semiconductor die 100 and package substrate 104 to facilitate bonding between semiconductor die 100 and package substrate 104. Adhesive 108 may be provided on an area where the active side AS of semiconductor die 100 overlaps with package substrate 104, or on a portion of the package substrate 104 and semiconductor die 100 that are bonded. Multiple input / output pads 102 of the active side AS of semiconductor die 100 may be laterally surrounded by adhesive 108. In embodiments where multiple input / output pads 102 are formed within a central region CR of the active side AS of semiconductor die 100 (see reference...), this adhesive 108 may be used to further enhance bonding. Figure 1B The adhesive 108 may have a central opening that overlaps with a plurality of input / output pads 102 and covers the remaining area of ​​the active side of the semiconductor die 100.

[0104] Similar to the adhesive 108 used in some embodiments, the package substrate 104 has an opening TH that overlaps with a plurality of input / output pads 102. The opening TH extends from a first side S1 where the package substrate 104 is bonded to the semiconductor die 100, through the package substrate 104, to a second side S2 where a plurality of package inputs / outputs 106 are formed. In other words, the package substrate 104 laterally surrounds the opening TH. The plurality of input / output pads 102 of the semiconductor die 100 are wired to the second side S2 of the package substrate 104 via a plurality of bonding wires 110 passing through the opening TH of the package substrate 104. In some embodiments, the plurality of bonding wires 110 connect the plurality of input / output pads 102 to a plurality of conductive pads 112 formed on the second side S2 of the package substrate 104. The plurality of conductive pads 112 may be disposed around the opening TH of the package substrate 104 and wired to the plurality of package inputs / outputs 106 via a plurality of wires in the package substrate 104. In other words, the multiple input / output pads 102 of the semiconductor die 100 can be wired to the multiple package inputs / outputs 106 via multiple bonding lines 110, multiple conductive pads 112 on the second side S2 of the package substrate 104, and multiple lines embedded in the package substrate 104.

[0105] Figure 1C This is a plan view illustrating some embodiments of the present disclosure, for example. Figure 1A The bottom side of the semiconductor package 10 shown.

[0106] Please refer to Figure 1A and Figure 1C A plurality of input / output pads 102 of the semiconductor die 100 are disposed within a boundary of an opening TH of the package substrate 104. Furthermore, a plurality of conductive pads 112 outside the opening TH may be disposed along the boundary of the opening TH. In some embodiments, the plurality of input / output pads 102 and the plurality of conductive pads 112 are disposed along each long side LS of the opening TH, and a plurality of bonding lines 110 extending between one of the input / output pads 102 and the corresponding conductive pad 112 may extend across one of the long sides LS of the opening TH. Figure 1CIn the illustrated embodiment, the opening TH is formed into a rectangular shape, and a first row of multiple input / output pads 102 and a first row of multiple conductive pads 112 are arranged along a left long side LS of the opening TH, while a second row of multiple input / output pads 102 and a second row of multiple conductive pads 112 are arranged along a right long side LS of the opening TH. Alternatively, the short sides SS of the opening TH may not be lined with multiple conductive pads 112. In other embodiments, multiple conductive pads 112 may be arranged along the long sides LS and short sides SS of the opening TH. In these other embodiments, some bonding lines 110 may extend across the multiple long sides LS of the opening TH, while other bonding lines 110 may extend across the multiple short sides SS of the opening TH. Furthermore, in yet another embodiment, the opening TH is formed into a rectangular shape with rounded ends, so that the multiple short sides SS curve rather than... Figure 1C The straight line shown. Although not described in detail, the openings TH of the package substrate 104 can intersect to form any other shape, as long as the openings TH overlap with the plurality of input / output pads 102.

[0107] like Figure 1C As shown, multiple long sides LS can extend along a direction Y, while multiple short sides SS can extend along a direction X, with direction X perpendicular to direction Y. Furthermore, Figure 1A It is a cross-sectional view along direction X.

[0108] Please refer to this again. Figure 1C Multiple packaged inputs / outputs 106 may be distributed on the second side S2 of the package substrate 104, surrounding the opening TH but not occupied by the multiple conductive pads 112. In some embodiments, the multiple conductive pads 112 are disposed between the opening TH and the multiple packaged inputs / outputs 106. Figure 1C In the example shown, a first row of multiple conductive pads 112 is positioned between a left long side LS of the opening TH and a first array of multiple package inputs / outputs 106, while a second row of multiple conductive pads 112 is positioned between a right long side LS of the opening TH and a second array of multiple package inputs / outputs 106. Furthermore, if the space between each short side SS of the opening TH and an outer boundary of the package substrate 104 is sufficiently large, the multiple package inputs / outputs 106 can also be positioned between each short side SS of the opening TH and the outer boundary of the package substrate 104.

[0109] Figure 1D This is an enlarged schematic diagram illustrating the opening TH of the packaging substrate 104 in some embodiments of this disclosure.

[0110] Please refer to Figure 1C and Figure 1D The opening TH of the packaging substrate 104 has a first width W S1And a second width W S2 And the first width W S1 At the first side S1 of the packaging substrate 104, the second width W S2 Then at the second side S2 of the packaging substrate 104. The first and second widths W S1 W S2 Measured along a direction that intersects the long sides LS of the opening TH. In embodiments where the multiple long sides LS of the opening TH extend along the direction Y, the first and second widths W S1 W S2 Measured along direction X. The second width WS2 is designed to be greater than the first width WS1, in order to connect the multiple bonding lines 110 to the opening TH at the edge E of the second side S2 of the package substrate 104. S2 Sufficiently spaced apart. Therefore, during the formation of the multiple bonding lines 110, it is possible to avoid overlap between the multiple bonding lines 110 and the multiple edges E of the opening TH. S2 The physical contact between them. This physical contact may cause damage to multiple bonding lines 110, and therefore may damage the electrical connection between the semiconductor die 100 and the package substrate 104. In other words, by the second width W of the opening TH S2 Designed to be larger than the first width W S1 This further ensures a good connection between the semiconductor die 100 and the package substrate 104. Furthermore, by properly aligning the multiple edges E of the package substrate 104... S2 The multiple edges E of the encapsulation substrate 104 are spaced apart from the multiple extension paths of the multiple bonding lines 110. S2 This avoids collisions with a bonding tool during the formation of multiple bonding lines 110. Therefore, potential damage to the package substrate 104 during the formation of multiple bonding lines 110 can be effectively avoided. In some embodiments, the second width W S2 For the first width W S1 The ratio is between 1.25 and 1.3. For example, the second width W S2 It can be between 1000μm and 1300μm, while the first width W S1 It can be between 800μm and 1000μm.

[0111] Furthermore, since multiple edges E of the package substrate 104 can be... S2A safe distance is maintained between the multiple bonding lines 110, so that the multiple input / output pads 102 serving as the boundaries of the multiple bonding lines 110 can be positioned closer to the multiple long sides LS of the opening TH. In some embodiments, the lateral space SP1 between each input / output pad 102 and the nearest edge of the opening TH at the first side S1 of the package substrate 104 is between 100 and 400 μm. By having multiple input / output pads 102 closer to the multiple long sides LS of the opening TH, the lateral space SP2 between the rows of the multiple input / output pads 102 can be increased. In other words, a larger area between the rows of the multiple input / output pads 102 can be used for additional multiple input / output pads. In some embodiments, the lateral space SP2 is between 100 and 400 μm.

[0112] In some embodiments, the multiple long sides of the opening TH are defined by multiple sloping sidewalls SW1. The multiple sloping sidewalls SW1 can penetrate the package substrate 104. In other words, the multiple sloping sidewalls SW1 extend from a first side S1 of the package substrate 104 to a second side S1 of the package substrate 104 (or from the second side S2 to the first side S1). Because the opening TH is designed with a second width W... S2 Greater than the first width W S1 Therefore, there is an angle A between each sidewall SW1 and the second side S2 of the packaging substrate 104. S2 The angle can be greater than 90 degrees, and the angle A between each sidewall SW1 and the first side S1 of the packaging substrate 104 is also greater than 90 degrees. S1 It can be less than 90 degrees. In some embodiments, angle A S2 Between 91 degrees and 165 degrees, and angle A S1 Between 15 and 90 degrees.

[0113] Figure 1E This is a cross-sectional schematic diagram illustrating a semiconductor package 10 viewed along direction Y in some embodiments of the present disclosure.

[0114] Please refer to Figure 1C and Figure 1E The opening TH of the encapsulation substrate 104 has a first length L S1 And a second length L S2 First length L S1 Located at the first side S1 of the packaging substrate 104, while the second length L S2 Located at the second side S2 of the packaging substrate 104. First and second lengths L S1 L S2 Measurements are taken along a direction that intersects multiple short sides SS of the opening TH (e.g., direction Y). In embodiments where no joining lines extend across multiple short sides SS, the opening TH need not be designed to have a second length L.S2 Greater than the first length L S1 In the first and second lengths L S1 L S2 They can be roughly the same. Furthermore, the multiple sidewalls SW2 of the multiple short sides SS that define the opening TH can be roughly perpendicular to the first and second sides S1, S2 of the package substrate 104.

[0115] Please refer to Figure 1A and Figure 1E The semiconductor die 100 is encapsulated by an encapsulant 114. The encapsulant 114 is provided at a first side S1 of the package substrate 104 and laterally surrounds the semiconductor die 100. In embodiments where the semiconductor die 100 is attached to the package substrate 104 via an adhesive 108, the adhesive 108 may laterally contact the encapsulant 114. Furthermore, in some embodiments, the semiconductor die 100 is overmolded by the encapsulant 114. In these embodiments, a back side BS of the semiconductor die 100 may be covered by the encapsulant 114, and the back side BS is the active side AS opposite to the semiconductor die 100. Additionally, the thickness of the encapsulant 114 may be greater than the thickness of the semiconductor die 100.

[0116] Furthermore, the opening TH of the package substrate 104 is filled by the encapsulation 116. Accordingly, a plurality of input / output pads 102 disposed within the opening TH are filled by the encapsulation 116, and the active side AS of the semiconductor die 100 contacts the encapsulation 116 around a portion of the plurality of input / output pads 102. Additionally, the sidewalls SW1, SW2 defining the plurality of long sides LS and the plurality of short sides SS of the opening TH laterally contact the encapsulation 116. In some embodiments, the opening TH is filled by the encapsulation 116, and the encapsulation 116 also extends onto a second side S2 of the package substrate 104. Figure 1A As shown, a plurality of conductive pads 112 at the second side S2 of the package substrate 104 and surrounding the opening TH are covered by a capsule 116. However, the capsule 116 may not extend to the plurality of package inputs / outputs 106 and maintain an appropriate space with them. Furthermore, to avoid the plurality of package inputs / outputs 106 from making contact with other packaged components, the height of the capsule 116 protruding from the second side S2 of the package substrate 104 should be less than the height of the plurality of package inputs / outputs 106.

[0117] like Figure 1D As shown, a portion of the capsule 116 filling the opening TH has a shape defined by the opening TH. Accordingly, the width of this portion of the capsule 116 at the first side S1 of the encapsulation substrate 104 is approximately equal to the width W of the opening TH. S1The width of this portion of the encapsulation 116 at the second side S2 of the encapsulation substrate 104 is approximately equal to the width W of the opening TH. S2 As mentioned above, the width W S2 Greater than width W S1 .

[0118] Furthermore, such as Figure 1E As shown, the length of this portion of the encapsulation body 116 at the first side S1 of the encapsulation substrate 104 is approximately equal to the length L of the opening TH. S1 The length of the portion of the encapsulation 116 on the second side S2 of the encapsulation substrate 104 is approximately equal to the length L of the opening TH. S2 As described above, in some embodiments, the length L S2 Approximately equal to length L S1 .

[0119] When the package substrate 104 has an opening TH, the semiconductor die 100 can be attached to the package substrate 104 face-down without using a flip-chip bonding process. Instead of using a flip-chip bonding process, a more cost-effective wire bonding process is used to establish the electrical connection between the semiconductor die 100 and the package substrate 104. In some embodiments, the opening TH of the package substrate 104 is positioned with a plurality of input / output pads 102 of the semiconductor die 100, and a plurality of bonding lines 110 passing through the opening TH connect the plurality of input / output pads 102 to the other side of the package substrate 104. Furthermore, the opening TH is designed with a narrow end and a wide end, the narrow end being located on a first side S1 of the package substrate 104 facing the semiconductor die 100, and the wide end being located on a second side S2 of the package substrate 104 away from the semiconductor die 100. As a result of this design, the edge E of the opening TH at the second side S2 of the package substrate 104... S2 A sufficient distance can be maintained between the multiple bonding lines 110. Therefore, the multiple bonding lines 110 can be prevented from being obstructed by multiple edge E during the formation of the multiple bonding lines 110. S2 The package substrate 104 is protected from damage and is protected from impact by the bonding tool used to form the multiple bonding lines 110. Furthermore, when the multiple bonding lines 110 can be safely kept separated from the edge ES2, the multiple input / output pads 102 can be positioned closer to the opening TH for convenience, so that more areas of the active side AS of the semiconductor die 100 can obtain additional input / output pads.

[0120] Figure 2 This is a flowchart illustrating a method for preparing a semiconductor package 10 according to some embodiments of this disclosure. Figures 3A to 3H This is a sectional view, exemplified in... Figure 2The intermediate structures along direction X at different stages during the preparation process shown.

[0121] Please refer to Figure 2 and Figure 3A This involves performing a step and providing an initial packaging substrate 300. The initial packaging substrate 300 will be molded and singulated to form a shape such as... Figure 1A as well as Figures 1C to 1E The described package substrate 104. In other words, the initial package substrate 300 includes a plurality of lines embedded in a stack of a plurality of isolation layers and has a first side S1 and a second side S2, wherein the first side S1 is attached to the semiconductor die 100 and the second side S2 is opposite to the first side S1. In some embodiments, the initial package substrate 300 is provided with an opening TH' that passes through the initial package substrate 300. The opening TH' is similar to... Figure 1A and Figures 1C to 1E The described opening TH, except that opening TH' may have a width approximately equal to the width of the first side S1 and the second side S2 of the package substrate 104.

[0122] Please refer to Figure 2 and Figure 3B Step S13 is performed, and the initial package substrate 300 is shaped. During shaping, multiple edge portions 300e extending along the long sides LS of the opening TH' of the initial package substrate 300 are removed, and the opening TH' is transformed into the shape shown in the figure. Figure 1A and Figures 1C to 1E The opening TH is described. In embodiments where the opening TH has multiple inclined sidewalls SW1 along multiple long sides LS, the multiple removed edge portions 300e may each be wedge-shaped. Furthermore, in some embodiments, the multiple edge portions 300e of the initial package substrate 300 are removed by cutting the initial package substrate 300 from the second side S2 of the initial package substrate 300. For example, a method of cutting the initial package substrate 300 may include a wet etching process and a dry etching process using a tile rotating substrate.

[0123] In other embodiments, the additional molding step is omitted, and the initial encapsulation substrate 300 is provided with an opening TH instead of an opening TH'.

[0124] Please refer to Figure 2 and Figure 3CStep S15 is performed, and the semiconductor die 100 is attached to a first side S1 of the initial package substrate 300. The initial package substrate 300 is flipped over so that the first side S1 of the initial package substrate 300 faces upward, and the semiconductor die 100 is attached to the initial package substrate 300 from above. Furthermore, during attachment, a plurality of input / output pads 102 at the active side AS of the semiconductor die 100 are positioned relative to the opening TH of the initial package substrate 300 so that the plurality of input / output pads 102 are exposed within the opening TH after attachment. In some embodiments, the semiconductor die 100 is attached to the initial package substrate 300 via an adhesive 108. In these embodiments, the adhesive 108 may be provided on the active side AS of the semiconductor die 100 prior to attachment. Alternatively, the adhesive 108 may be provided on the first side S1 of the initial package substrate 300 prior to attachment.

[0125] Please refer to Figure 2 and Figure 3D Step S17 is executed, and a plurality of conductive pads 112 are formed on the second side S2 of the initial encapsulation substrate 300. Prior to the formation of the plurality of conductive pads 112, as... Figure 3C The package structure shown can be flipped so that the second side S2 of the initial package substrate 300 faces upward. Furthermore, the package structure can be supported from below the semiconductor die 100.

[0126] Please refer to Figure 2 and Figure 3E Step S19 is performed, and a plurality of bonding lines 110 are formed. In some embodiments, a bonding tool 302 is used to form the plurality of bonding lines 110. Although not shown in the figures, the bonding tool 302 has an aperture extending into the bonding tool 302 from a capillary tip. The formation of a bonding line 110 may begin with a microwire that is screwed through the aperture. The protruding line is then heated by an electrical spark and rolled back to form a sphere larger than a diameter of the aperture. The sphere is then pressed onto an input / output pad 102 under the application of heat (thermopressing), ultrasonic energy (ultrasound), or both (thermosound) to establish a bond with the input / output pad 102. The bonding tool 302 then moves toward a target conductive pad 112, and a portion of the bonding line 110 is formed along this path. Because the opening TH is designed with a width at the second side S2 of the initial package substrate 300 that is greater than a width at the first side S1 of the initial package substrate 300, the bonding line 110 can avoid contact with the edge E. S2 Solid contact, and edge E S2This avoids collisions with the bonding tool 302. When this portion of the bonding line 110 reaches the conductive pad 112, it is bonded to the conductive pad 112 via a process that also establishes a bond with the input / output pads 102. Thus, the bonding line 110 is formed.

[0127] Please refer to Figure 2 , Figure 3F and Figure 3G Step S21 is performed, and the capsules 114 and 116 are formed. In some embodiments, such as Figure 3F As shown, the current package structure is placed in a mold 304 having chambers 306 and 308, which define spaces filled with molding materials. A portion of the package structure at a first side S1 of the initial package substrate 300, including a semiconductor die 100 and an adhesive 108, is accommodated in chamber 306. On the other hand, an opening TH of the initial package substrate 300 communicates with chamber 308, and multiple input / output pads 102, multiple bonding lines 110, and multiple conductive pads 112 are accommodated in chamber 308. Once the package structure is placed in the mold 304, molding materials are supplied to chamber 306 via an inlet hole 310, which communicates with chamber 306. Similarly, molding materials are supplied to chamber 308 via an inlet 312, which communicates with chamber 308. The molding material in chamber 306 can be heated and cured to form a capsule 314, which can then be monolithized to form a capsule-like structure. Figure 1A , Figure 1D and Figure 1E The described capsule 114. On the other hand, the molding material in chamber 308 can be heated and cured to form, as... Figure 1A , Figure 1D and Figure 1E The described encapsulation body 116. In encapsulation bodies 314, 116 (as...) Figure 3G After the mold (as shown) is formed, the mold 304 is removed.

[0128] Please refer to Figure 2 and Figure 3H Step S23 is performed, and the current package structure is single-piece. Before single-piece processing, the current package structure can be flipped so that the second side S2 of the initial package substrate 300 faces upward, and the package structure can be supported from the side of the encapsulation body 314 opposite to the initial package substrate 300. During single-piece processing, the initial package substrate 300 and the encapsulation body 314 are cut into multiple pieces, including as follows: Figure 1A and Figures 1C to 1EThe encapsulation substrate 104 and the capsule 114 are described. In some embodiments, the sidewalls of the encapsulation substrate 104 are substantially coplanar with the sidewalls of the capsule 114.

[0129] Please refer to Figure 2 and Figure 1A Step S25 is executed, and a plurality of package inputs / outputs 106 are formed. In embodiments where the plurality of package inputs / outputs 106 include a plurality of solder pastes 106a and a plurality of solder balls 106b, the plurality of solder pastes 106a are formed on the second side S2 of the package substrate 104, and then the plurality of solder balls 106b are provided on the plurality of solder pastes 106a. Furthermore, the plurality of solder pastes 106a and the plurality of solder balls 106b may be subjected to at least heat treatment to form a desired shape.

[0130] Thus far, based on some embodiments of this disclosure, the following has been formed: Figures 1A to 1E The semiconductor package 10 is described. In other embodiments, multiple package inputs / outputs 106 (e.g., Figure 2 and Figure 1A The described step S25) involves a single-particle step (e.g. Figure 2 and Figure 3H (as described in step S23). Furthermore, in some embodiments, the formed semiconductor package 10 can also be attached to other package elements (e.g., a printed circuit board) via multiple package inputs / outputs 106.

[0131] Figure 4A This is a cross-sectional schematic diagram illustrating a semiconductor package 10-1 according to some embodiments of the present disclosure. Figure 4B This is an enlarged schematic diagram, exemplified as follows: Figure 4A The opening TH-1 of the packaging substrate 104-1 in the semiconductor package 10-1 shown.

[0132] Please refer to Figure 4A and Figure 4B Semiconductor packaging 10-1 is similar to... Figures 1A to 1E Similarly, the semiconductor package 10-1 described herein has a package substrate 104-1 with an opening TH-1, and is also designed with a width W at the second side S2 of the package substrate 104-1. S2 A width W greater than that at the first side S1 of the package substrate 104-1 S1 Because it is different from... Figures 1A to 1E The semiconductor package 10 described has a package substrate 104, so each long side of the opening TH-1 in the package substrate 104-1 is connected to a side wall SW1. N and one side wall SW1 S Defined. Sidewall SW1 N It can extend from the first side S1 of the packaging substrate 104-1 to the sidewall SW1N SW1 S At one junction, the sidewall SW1S can extend from the second side S2 of the package substrate 104-1 to the junction. N An angle A between the first side S1 of the packaging substrate 104-1 and the packaging substrate 104-1 S1’ It can be less than or equal to 90 degrees. On the other hand, the sidewall SW1 S It can be an inclined sidewall, and in sidewall SW1 S An angle A between the second side S2 of the packaging substrate 104-1 and the packaging substrate 104-1 S2’ Greater than 90 degrees. In some embodiments, angle A S2’ Between 91 and 165 degrees.

[0133] Figure 5A This is a cross-sectional schematic diagram illustrating a semiconductor package 10-2 according to some embodiments of the present disclosure. Figure 5B This is an enlarged schematic diagram, exemplified as follows: Figure 5A The opening TH-2 of the packaging substrate 10-2 in the semiconductor package 104-2 shown.

[0134] Please refer to Figure 5A and Figure 5B Semiconductor packaging 10-2 is similar to... Figures 1A to 1E Similarly, the semiconductor package 10-2 described herein has a package substrate 104-2 with an opening TH-2, which is also designed to have a width W at the second side S2 of the package substrate 104-2. S2 A width W greater than that at the first side S1 of the package substrate 104-2 S1 Because it is different from... Figures 1A to 1E The semiconductor package 10 described has a package substrate 104, so each long side LS of the opening TH-2 in the package substrate 104-2 is connected by a curved sidewall SW1. C Defined. Curved sidewall SW1 C It can be a concave surface that arches into the packaging substrate 104-2 and can extend from the first side S1 of the packaging substrate 104-2 to the second side S2 (or vice versa).

[0135] Figure 6A This is a cross-sectional schematic diagram illustrating a semiconductor package 10-3 according to some embodiments of the present disclosure. Figure 6B This is an enlarged schematic diagram, exemplified as follows: Figure 6A The opening TH-3 of the packaging substrate 104-3 in the semiconductor package 10-3 shown.

[0136] Please refer to Figure 6A and Figure 6B Semiconductor packaging 10-3 is similar to... Figures 1A to 1ESimilarly, the semiconductor package 10-3 described herein has a package substrate 104-3 with an opening TH-3, which is also designed to have a width W at the second side S2 of the package substrate 104-3. S2 A width W greater than that at the first side S1 of the package substrate 104-3 S1 Because it is different from... Figures 1A to 1E The semiconductor package 10 described has a package substrate 104, so each long side LS of the opening TH-3 in the package substrate 104-3 is connected by a curved sidewall SW1. V Defined. The curved sidewall SW1V may be a convex surface that surrounds outward and may extend from the first side S1 of the package substrate 104-3 to the second side S2 (or vice versa).

[0137] Figure 7 This is a cross-sectional schematic diagram illustrating a semiconductor package 10-4 according to some embodiments of the present disclosure.

[0138] Semiconductor package 10-4 is similar to Figures 1A to 1E The described semiconductor package 10, except that an opening TH-4 in the package substrate 104-4 of the semiconductor package 10 is designed to have a length L at the second side S2 of the package substrate 104-4. S2 A length L greater than that at the first side S1 of the package substrate 104-4 S1 In addition, as described above, lengths LS1 and LS2 are measured along a direction that intersects multiple short sides SS of opening TH-4 (e.g., direction Y). Furthermore, each short side SS of opening TH-4 can be defined by a side wall SW2, which extends from the first side S1 of the package substrate 104-4 to the second side S2 (or vice versa). The side wall SW2 can be an inclined side wall, or similar to... Figure 5B The described sidewall SW1 C Or like Figure 6B The described sidewall SW1 V A curved sidewall. In yet another embodiment, each short side SS of the opening TH-4 is defined by a plurality of joined sidewalls, similar to... Figure 4B The described sidewall SW1 N SW1 S .

[0139] As described above, the semiconductor package according to various embodiments of this disclosure includes a package substrate having an opening. A semiconductor die can be attached to the package substrate in a face-down manner without using a flip-chip bonding process. Instead of using a flip-chip bonding process, a more cost-effective one-wire bonding process is used to establish the electrical connection between the semiconductor die and the package substrate. In some embodiments, the opening of the package substrate is positioned with a plurality of input / output pads on an active side of the semiconductor die, and a plurality of bonding traces passing through the opening connect the plurality of input / output pads to the other side of the package substrate. Furthermore, the opening is designed to have a narrow end and a wide end, the narrow end being located on a first side of the package substrate facing the semiconductor die, and the wide end being located on a second side of the package substrate away from the semiconductor die. As a result of this design, the plurality of edges of the opening on the second side of the package substrate can be kept at a sufficient distance from the plurality of bonding traces. Therefore, the plurality of bonding traces can be prevented from being damaged by the plurality of edges during the formation of such bonding traces, and the package substrate can be prevented from being collided with during a bonding operation used to form the plurality of bonding traces. Furthermore, since multiple bonding lines can be safely separated from multiple edges, multiple input / output pads can be positioned closer to the boundary of the opening, thus providing additional input / output pads to a larger area of ​​the active side of the semiconductor device.

[0140] One embodiment of this disclosure provides a semiconductor package. The semiconductor package includes a semiconductor die having a plurality of input / output pads disposed on an active side of the semiconductor die; a package substrate having a first side attached to the active side of the semiconductor die and a second side facing away from the semiconductor die, and having an opening passing through the package substrate, wherein the plurality of input / output pads overlap with the opening, and the width of the opening on the second side of the package substrate is greater than the width of the opening on the first side of the package substrate; and a plurality of bonding wires connecting the plurality of input / output pads to the second side of the package substrate via the opening of the package substrate.

[0141] Another embodiment of this disclosure provides a semiconductor package. The semiconductor package includes a semiconductor die having a plurality of input / output pads disposed on an active side of the semiconductor die; a package substrate having a first side attached to the active side of the semiconductor die and a second side facing away from the semiconductor die and laterally surrounding an opening, wherein the plurality of input / output pads overlap the opening, the opening having a plurality of long sides and a plurality of short sides, a width across the plurality of long sides of the opening on the second side of the package substrate being greater than a width across the plurality of long sides of the opening on the first side of the package substrate; and a plurality of bonding wires crossing the plurality of long sides of the opening to connect the plurality of input / output pads to the second side of the package substrate.

[0142] Another embodiment of this disclosure provides a semiconductor package. The semiconductor package includes a semiconductor die having a plurality of input / output pads disposed on an active side of the semiconductor die; a package substrate having a first side attached to the active side of the semiconductor die and a second side facing away from the semiconductor die, and having an opening passing through the package substrate, wherein the plurality of input / output pads overlap with the opening, and a width of the opening on the second side of the package substrate is greater than a width of the opening on the first side of the package substrate; a plurality of bonding wires connecting the plurality of input / output pads to the second side of the package substrate via the opening; a first encapsulation laterally encapsulating the semiconductor die; and a second encapsulation filling the opening and extending to the second side of the package substrate.

[0143] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives can be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and other processes or combinations thereof can be substituted for many of the processes described above.

[0144] Furthermore, the scope of this invention is not limited to the specific embodiments of the processes, machinery, manufacturing, material compositions, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this invention that existing or future processes, machinery, manufacturing, material compositions, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described in this invention can be used based on this disclosure. Accordingly, such processes, machinery, manufacturing, material compositions, means, methods, or steps are included within the scope of the claims of this invention.

Claims

1. A semiconductor package, comprising: A semiconductor die having multiple input / output pads disposed on an active side of the semiconductor die; A package substrate is attached to the active side of the semiconductor die on a first side and to the opposite side of the semiconductor die on a second side, and has an opening through which a plurality of input / output pads overlap with the opening, wherein a width of the opening on the second side of the package substrate is greater than a width of the opening on the first side of the package substrate. as well as Multiple bonding lines connect multiple input / output pads to the second side of the package substrate via the opening in the package substrate; The lateral space between each input / output pad and the nearest edge of the opening on the first side of the package substrate is between 100 μm and 400 μm. The opening has a first width and a second width, the first width being at a first side of the packaging substrate and the second width being at a second side of the packaging substrate, the ratio of the second width to the first width being between 1.25 and 1.

3. An angle greater than 90 degrees is defined between the second side of the encapsulation substrate and a set of bonding lines extending across one sidewall of the opening.

2. The semiconductor package of claim 1, wherein an angle defined between the first side of the package substrate and the sidewall of the opening is less than 90 degrees.

3. The semiconductor package of claim 2, wherein the sidewall of the opening is a sloping sidewall.

4. The semiconductor package of claim 1, wherein the sidewall of the opening extends from the second side of the package substrate to a junction with another sidewall shared by the opening, the other sidewall shared by the opening extending from the junction to the first side of the package substrate.

5. The semiconductor package of claim 4, wherein an angle defined between the first side of the package substrate and the sidewall of the opening extending from the junction to the first side of the package substrate is equal to or less than 90 degrees.

6. The semiconductor package of claim 1, wherein a set of bonding lines extending across a sidewall of the opening is a curved sidewall.

7. The semiconductor package of claim 6, wherein the sidewall arches into the package substrate.

8. The semiconductor package of claim 6, wherein the sidewall bends into the opening.

9. A semiconductor package, comprising: A semiconductor die having multiple input / output pads disposed on an active side of the semiconductor die; A package substrate is attached to the active side of the semiconductor die on a first side and to the semiconductor die on a second side away from the semiconductor die and laterally surrounds an opening, wherein a plurality of input / output pads overlap the opening, the opening having a plurality of long sides and a plurality of short sides, and a width across the plurality of long sides of the opening on the second side of the package substrate is greater than a width across the plurality of long sides of the opening on the first side of the package substrate; as well as Multiple bonding lines, spanning the multiple long sides of the opening, connect the multiple input / output pads to the second side of the package substrate; The lateral space between each input / output pad and the nearest edge of the opening on the first side of the package substrate is between 100 μm and 400 μm. The opening has a first width and a second width, the first width being at a first side of the packaging substrate and the second width being at a second side of the packaging substrate, the ratio of the second width to the first width being between 1.25 and 1.

3. An angle greater than 90 degrees is defined between the second side of the encapsulation substrate and a set of bonding lines extending across one sidewall of the opening.

10. The semiconductor package of claim 9, wherein a length of the plurality of short sides passing through the opening on the second side of the package substrate is equal to a length of the plurality of short sides passing through the opening on the first side of the package substrate.

11. The semiconductor package of claim 9, wherein a length spanning the plurality of short sides of the opening on the second side of the package substrate is greater than a length spanning the plurality of short sides of the opening on the first side of the package substrate.

12. The semiconductor package of claim 9, wherein each long side of the opening is defined by an inclined sidewall.

13. The semiconductor package of claim 9, wherein each short side of the opening is defined by a first sidewall and a second sidewall, and the second sidewall is connected to the first sidewall, wherein the first sidewall and the second sidewall extend in different directions.

14. The semiconductor package of claim 9, wherein each long side of the opening is defined by a curved sidewall.

15. A semiconductor package, comprising: A semiconductor die having multiple input / output pads disposed on an active side of the semiconductor die; A package substrate is attached to the active side of the semiconductor die on a first side and to the semiconductor die on a second side, and has an opening through which a plurality of the input / output pads overlap with the opening, and the width of the opening on the second side of the package substrate is greater than the width of the opening on the first side of the package substrate. Multiple bonding lines connect multiple input / output pads to the second side of the package substrate via the opening in the package substrate; A first encapsulation body laterally encapsulates the semiconductor die; as well as A second encapsulation body fills the opening and extends to the second side of the encapsulation substrate; The lateral space between each input / output pad and the nearest edge of the opening on the first side of the package substrate is between 100 μm and 400 μm. The opening has a first width and a second width, the first width being at a first side of the packaging substrate and the second width being at a second side of the packaging substrate, the ratio of the second width to the first width being between 1.25 and 1.

3. An angle greater than 90 degrees is defined between the second side of the encapsulation substrate and a set of bonding lines extending across one sidewall of the opening.

16. The semiconductor package of claim 15, wherein the second encapsulant filling a portion of the opening has a first width and a second width, the first width being on the first side of the package substrate, the second width being on the second side of the package substrate, and the second width being greater than the first width.

17. The semiconductor package of claim 15, further comprising: Multiple conductive pads are formed on the second side of the encapsulation substrate and connected to the multiple bonding lines.

18. The semiconductor package of claim 17, wherein the plurality of conductive pads are covered by the second encapsulation.

19. The semiconductor package of claim 17, wherein the opening has a plurality of long sides and a plurality of short sides, and the plurality of conductive pads are disposed along the plurality of long sides of the opening.

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