Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device according to an embodiment of the present application includes a substrate, a first epitaxial electrode layer disposed on the substrate, a ferroelectric epitaxial layer disposed on the first epitaxial electrode layer, a dielectric epitaxial layer disposed on the ferroelectric epitaxial layer, and a second epitaxial electrode layer disposed on the dielectric epitaxial layer. The ferroelectric epitaxial layer realizes a negative capacitance. Each of the first epitaxial electrode layer and the second epitaxial electrode layer includes a conductive pyrochlore oxide. The ferroelectric epitaxial layer and the dielectric epitaxial layer are electrically connected in series. A dielectric structure including the ferroelectric epitaxial layer and the dielectric epitaxial layer is non-ferroelectric.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Application No. 10-2021-0132006, filed on October 5, 2021, with the Korean Intellectual Property Office under 35 U.SC §119(a), which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure generally relates to a semiconductor device, and more specifically, to a semiconductor device including an epitaxial electrode layer and a dielectric epitaxial layer, and a method for manufacturing the same. Background Technology

[0004] As the feature size of semiconductor chips decreases, the size of capacitor devices disposed within them also decreases. However, the capacitance required for the dielectric layer constituting the capacitor device must be maintained at a minimum predetermined reference value to ensure reliable device operation. Therefore, increasing the capacitance of such capacitor devices is advantageous, and various methods are being investigated to increase the capacitance of the dielectric layer used in capacitor devices.

[0005] As representative examples of various methods, approaches to applying high-k materials to the dielectric layer of capacitor devices and methods to reduce the thickness of the dielectric layer have been studied. However, as the size of capacitor devices continues to shrink, the industry demands that capacitor devices meet the requirements for higher capacitance reference values ​​while maintaining low leakage current and high breakdown voltage. Summary of the Invention

[0006] A semiconductor device according to an embodiment of the present invention includes: a substrate, a first epitaxial electrode layer disposed on the substrate, a ferroelectric epitaxial layer disposed on the first epitaxial electrode layer, a dielectric epitaxial layer disposed on the ferroelectric epitaxial layer, and a second epitaxial electrode layer disposed on the dielectric epitaxial layer. Each of the first epitaxial electrode layer and the second epitaxial electrode layer comprises a conductive pyrochlore oxide. The ferroelectric epitaxial layer and the dielectric epitaxial layer are connected in series. The dielectric structure including the ferroelectric epitaxial layer and the dielectric epitaxial layer is non-ferroelectric.

[0007] A semiconductor device according to another embodiment of the present invention includes: a substrate, a first epitaxial electrode layer disposed on the substrate, a dielectric epitaxial layer disposed on the first epitaxial electrode layer, a ferroelectric epitaxial layer disposed on the dielectric epitaxial layer, and a second epitaxial electrode layer disposed on the ferroelectric epitaxial layer. Each of the first epitaxial electrode layer and the second epitaxial electrode layer comprises a conductive pyrochlore oxide. The dielectric epitaxial layer and the ferroelectric epitaxial layer are connected in series. The dielectric structure including the dielectric epitaxial layer and the ferroelectric epitaxial layer is non-ferroelectric.

[0008] A semiconductor device according to another embodiment of the present disclosure includes a substrate and a capacitor disposed on the substrate. The capacitor includes: a storage node epitaxial electrode, a ferroelectric epitaxial layer disposed on the storage node epitaxial electrode, a dielectric epitaxial layer disposed on the ferroelectric epitaxial layer, and a plate epitaxial electrode disposed on the dielectric epitaxial layer. Each of the storage node epitaxial electrode and the plate epitaxial electrode comprises a conductive pyrochlore oxide. The ferroelectric epitaxial layer and the dielectric epitaxial layer are connected in series. The capacitor has non-ferroelectric properties. Attached Figure Description

[0009] Figure 1 This is a schematic diagram illustrating the polarization properties of a ferroelectric layer according to an embodiment of the present disclosure.

[0010] Figure 2 This is a schematic diagram illustrating the polarization properties of a dielectric layer according to an embodiment of the present disclosure.

[0011] Figure 3 This is a schematic diagram illustrating the circuit configuration of a dielectric structure according to an embodiment of the present disclosure.

[0012] Figure 4 This is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment of the present disclosure.

[0013] Figure 5 This is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present disclosure.

[0014] Figure 6 This is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present disclosure.

[0015] Figure 7 This is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present disclosure.

[0016] Figure 8A This is a schematic plan view of a memory cell of a semiconductor device according to an embodiment of the present disclosure.

[0017] Figure 8B It is along Figure 8A A cross-sectional view taken from line A-A' of the memory cell.

[0018] Figure 8C It is along Figure 8A A cross-sectional view of the memory cell taken by line B-B'.

[0019] Figure 9A and Figure 9B This is a schematic cross-sectional view of a capacitor in a semiconductor device according to an embodiment of the present disclosure.

[0020] Figure 10A and Figure 10B This is a schematic cross-sectional view of a capacitor according to another embodiment of the present disclosure.

[0021] Figure 11A and Figure 11B This is a schematic cross-sectional view of a capacitor according to another embodiment of the present disclosure. Detailed Implementation

[0022] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the drawings, the dimensions of the components (e.g., the width and thickness of the components) are enlarged to clearly illustrate the components of each device. The terms used herein may correspond to words chosen in the embodiments in consideration of their function, and those skilled in the art to which the embodiments pertain may interpret the meaning of the terms differently. If clearly defined in detail, these terms may be interpreted according to the definitions. Unless otherwise defined, the terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which the embodiments pertain.

[0023] Furthermore, the singular form of a word should be understood to include the plural form of that word unless explicitly used otherwise in the context. It should be understood that the terms “comprising,” “including,” or “having” are intended to specify the presence of a feature, quantity, step, operation, component, element, part, or combination thereof, but are not intended to exclude the possibility of the presence or addition of one or more other features, quantities, steps, operations, components, elements, parts, or combinations thereof.

[0024] Furthermore, when performing a method or manufacturing method, each process constituting the method may be performed in a manner different from the prescribed order, unless a specific order is explicitly described in the context. In other words, each process may be performed in the same manner as said in the order, and may be performed substantially simultaneously. Additionally, at least a portion of each of the above processes may be performed in the reverse order.

[0025] Figure 1 This is a schematic diagram illustrating the polarization properties of a ferroelectric layer according to an embodiment of the present disclosure. Specifically, curve 10 illustrates the polarization change in the ferroelectric layer when an electric field is applied to both ends of the ferroelectric layer. Figure 2 This is a schematic diagram illustrating the polarization properties of a dielectric layer according to an embodiment of the present disclosure. Specifically, curve 20 illustrates the polarization change in the dielectric layer when an electric field is applied to both ends of the dielectric layer.

[0026] See Figure 1Curve 10 shows that the ferroelectric layer can have a first remanent polarization Pr1 and a second remanent polarization Pr2, as well as a first coercive field Ec and a second coercive field -Ec. In the absence of an applied electric field, the first remanent polarization Pr1 and the second remanent polarization Pr2 can be polarizations maintained within the ferroelectric layer. The first coercive field Ec and the second coercive field -Ec can indicate the magnitude of the electric field required to switch the polarization orientation of the ferroelectric layer in opposite directions.

[0027] See Figure 1 Curve 10, as an example, shows that when the ferroelectric layer has a second remanent polarization Pr2 in its initial state, a positively polarized electric field can be applied to the ferroelectric layer to change its polarization. See also... Figure 1 An electric field can be applied to the ferroelectric layer while simultaneously increasing its intensity in a sweeping manner. When the electric field reaches the first coercive field Ec, the polarization of the ferroelectric layer can change to have a first polarization P1 after passing through the negative slope portion 10NC on curve 10. As another embodiment, when the ferroelectric layer has a first remanent polarization Pr1 in its initial state, a negatively polarized electric field can be applied to the ferroelectric layer to change its polarization. See also Figure 1 An electric field can be applied to the ferroelectric layer while increasing its intensity in a sweeping manner. When the electric field reaches the second coercive field -Ec, the polarization of the ferroelectric layer can change to have a second polarization P2 after passing through the negative slope portion 10NC on curve 10.

[0028] On curve 10, the capacitance of the ferroelectric layer can be proportional to the ratio ΔP / ΔE of the polarization change ΔP according to the electric field change ΔE. In the electric field region corresponding to the negative slope portion 10NC of curve 10 (i.e., in the electric field region where the ratio ΔP / ΔE of the polarization change ΔP according to the electric field change ΔE has a negative value), the ferroelectric layer may exhibit negative capacitance. That is, when polarization switching of the ferroelectric layer is performed under the first coercive field Ec, the polarization of the ferroelectric layer can change along the portion of curve 10 indicating negative capacitance. Conversely, in… Figure 1 In curve 10, the ferroelectric layer may exhibit positive capacitance in the remaining electric field intervals other than the electric field interval corresponding to the negative slope portion 10NC (i.e., in the electric field intervals where the ratio of polarization change ΔP to electric field change ΔE, ΔP / ΔE, is positive).

[0029] See Figure 2 Curve 20 illustrates the polarization behavior of the dielectric layer under an initial electric field. In this specification, unless otherwise stated, the dielectric layer may refer to a nonferroelectric layer. Therefore, in Figure 2 In this case, the dielectric layer does not exhibit any ferroelectric properties. As an example, the dielectric layer could be a paraelectric layer.

[0030] See Figure 2Curve 20 shows that when an electric field is applied to both ends of the dielectric layer while sweeping in the positive or negative direction, the polarization of the dielectric layer can increase from zero proportionally to the applied electric field. When the electric field is removed from the dielectric layer, the magnitude of the polarization may return to zero. That is, when no electric field is applied to the dielectric layer, the dielectric layer may not retain residual polarization.

[0031] Furthermore, on curve 20, the capacitance of the ferroelectric layer is proportional to the ratio ΔP / ΔE of the polarization change ΔP relative to the electric field change ΔE. Therefore, with Figure 2 The dielectric layer associated with curve 20 can be used throughout the entire electric field range (i.e., in relation to...). Figure 1 The negative slope portion (corresponding to the electric field interval of 10NC) has a positive capacitance.

[0032] While not bound by any particular theory, when a ferroelectric layer is combined with a dielectric layer to form a dielectric structure, the ferroelectric layer in the dielectric structure can exhibit negative capacitance in a more stable manner compared to the case where the ferroelectric layer is used without a dielectric layer. The dielectric structure formed by combining a ferroelectric layer and a dielectric layer may not exhibit ferroelectric properties overall. That is, the dielectric structure may not retain residual polarization after the applied electric field is removed. For example, the dielectric structure may exhibit paraelectric properties.

[0033] Figure 3 This is a schematic diagram illustrating the circuit configuration of a dielectric structure according to an embodiment of the present disclosure. See also Figure 3 The dielectric structure 30 may include a dielectric layer DE and a ferroelectric layer FE connected in series. When a voltage is applied to the two ends of the dielectric structure 30 through the power supply 35, the capacitance C of the dielectric structure 30 increases. T It can be calculated using the following equation (1).

[0034] 1 / (C T )=1 / (C DE )+1 / (C FE )-------------(1)

[0035] Here, C DE It is the capacitance of the dielectric layer DE, C FE It is the capacitance of the ferroelectric layer FE. When each of the dielectric layer DE and the ferroelectric layer FE has a positive capacitance, the capacitance C of the dielectric structure 30 is... T The capacitance C can be smaller than that of the dielectric layer DE and the ferroelectric layer FE, respectively. DE and C FE .

[0036] In one example, according to equation (1), within a certain voltage range, when the dielectric layer DE has a positive capacitance and the ferroelectric layer FE has a negative capacitance, the capacitance C of the dielectric structure 30 is... T The capacitance C of the dielectric layer DE can be compared. DE Large. Therefore, when the ferroelectric layer FE and the dielectric layer DE are connected in series to form the dielectric structure 30, the capacitance C of the dielectric structure 30 is large. T The capacitance C of the dielectric layer DE can be compared. DE big.

[0037] As described above, the configuration of the dielectric structure 30 can be applied to various embodiments of the present disclosure described below. That is, when the dielectric structure includes a dielectric layer DE and a ferroelectric layer FE electrically connected in series, the dielectric structure as a whole can have non-ferroelectric properties. Non-ferroelectric properties may mean that the dielectric material does not have remanent polarization and does not have a coercive field. For example, non-ferroelectric properties may mean paraelectricity. Furthermore, the dielectric structure can exhibit an increased capacitance C relative to the dielectric layer DE within a predetermined operating voltage range. T .

[0038] Figure 4 This is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment of the present disclosure. See also Figure 4 Semiconductor device 1 may include: a substrate 101, a first epitaxial electrode layer 110 disposed on the substrate 101, a ferroelectric epitaxial layer 120 disposed on the first epitaxial electrode layer 110, a dielectric epitaxial layer 130 disposed on the ferroelectric epitaxial layer 120, and a second epitaxial electrode layer 140 disposed on the dielectric epitaxial layer 130. The first epitaxial electrode layer 110, the ferroelectric epitaxial layer 120, the dielectric epitaxial layer 130, and the second epitaxial electrode layer 140 may be epitaxial growth layers.

[0039] In semiconductor device 1, the ferroelectric epitaxial layer 120 and the dielectric epitaxial layer 130 can be connected in series to form a non-ferroelectric dielectric structure 1000 between the first epitaxial electrode layer 110 and the second epitaxial electrode layer 140. That is, the dielectric structure 1000 including the ferroelectric epitaxial layer 120 and the dielectric epitaxial layer 130 is non-ferroelectric. In one example, the ferroelectric epitaxial layer 120 may exhibit a negative capacitance, while the dielectric epitaxial layer 130 may exhibit a positive capacitance.

[0040] In one embodiment, substrate 101 may have a fluorite-type crystal structure. In another embodiment, although... Figure 4 Although not shown, substrate 101 may include a buffer layer having a fluorite-type crystal structure.

[0041] In this specification, fluorite-type crystal structure may refer to fluorite crystal structure, or it may refer to crystal structure in which the occupancy sites of particles in the crystal lattice are similar to the occupancy sites of particles in fluorite crystal structure.

[0042] For example, a fluorite crystal structure can refer to the crystal structure of a compound with the chemical formula MX2, formed by ionic bonds. In this case, in the fluorite crystal structure, the cation M can occupy the regular sites of the face-centered cubic (FCC) structure, and the anion X can occupy the eight tetrahedral interstitial sites in the FCC structure. A representative example of a fluorite crystal structure is the crystal structure of calcium fluoride (CaF2).

[0043] Substrate 101 may comprise yttrium-stabilized zirconium oxide (hereinafter referred to as "YSZ") or strontium tin oxide (hereinafter referred to as "STO"). As an example, substrate 101 may be formed of YSZ or STO. Substrate 101 may serve as a seed substrate for forming the first epitaxial electrode layer 110 into an epitaxial layer. In another example not shown, substrate 101 may comprise a buffer layer comprising YSZ or STO. The buffer layer may form an interface with the first epitaxial electrode layer 110 and may serve as a seed layer for forming the first epitaxial electrode layer 110 into an epitaxial layer.

[0044] The first epitaxial electrode layer 110 may be disposed on the substrate 101. The first epitaxial electrode layer 110 may include conductive pyrochlore oxide. The conductive pyrochlore oxide may have a fluorite-type crystal structure. The first epitaxial electrode layer 110 may be an epitaxial layer formed on the substrate 101 by heteroepitaxialization. Heteroepitaxialization may include, for example, pulsed laser deposition (PLD), atomic layer deposition (ALD), chemical vapor deposition (CVD), etc.

[0045] In one embodiment, the conductive pyrochlore oxide may have the chemical formula A2B2O7 (where A and B are metals and O is oxygen) or A2B2O 7-δ (A and B are metals and O is oxygen, 0 < δ < 1). The metals A, B, and oxygen in a conductive pyrochlore oxide can be positioned at different locations within the lattice of a fluorite crystal structure. For example, a conductive pyrochlore oxide can have a structure in which at least one of metals A, B, and oxygen is vacant at some locations in the lattice.

[0046] Conductive pyrochlore oxides may include, for example, lead iridium oxide (Pb₂Ir₂O₇), lanthanum iridium oxide (La₂Ir₂O₇), cerium iridium oxide (Ce₂Ir₂O₇), praseodymium iridium oxide (Pr₂Ir₂O₇), neodymium iridium oxide (Nd₂Ir₂O₇), samarium iridium oxide (Sm₂Ir₂O₇), gadolinium iridium oxide (Gd₂Ir₂O₇), ytterbium iridium oxide (Yb₂Ir₂O₇), lanthanum ruthenium oxide (La₂Ru₂O₇), cerium ruthenium oxide (Ce₂Ru₂O₇), praseodymium ruthenium oxide (Pr₂Ru₂O₇), neodymium ruthenium oxide (Nd₂Ru₂O₇), samarium ruthenium oxide (Sm₂Ru₂O₇), gadolinium ruthenium oxide (Gd₂Ru₂O₇), ytterbium ruthenium oxide (Yb₂Ru₂O₇), and bismuth ruthenium oxide (Bi₂Ru₂O₇). 7-δ ,0<δ<1), lead ruthenium oxide (Pb2Ru2O) 7-δ ,0<δ<1), thallium ruthenium oxide (Tl2Ru2O) 7-δ ,0<δ<1), Bismuth iridium oxide (Bi2Ir2O) 7-δ ,0<δ<1), lead iridium oxide (Pb2Ir2O) 7-δ ,0<δ<1), thallium iridium oxide (Tl2Ir2O) 7-δ , 0<δ<1), or a combination of two or more of them.

[0047] See Figure 4 The ferroelectric epitaxial layer 120 can be disposed on the first epitaxial electrode layer 110. The ferroelectric epitaxial layer 120 can have a fluorite-type crystal structure. In one embodiment, the ferroelectric epitaxial layer 120 can have an orthorhombic crystal structure.

[0048] The ferroelectric epitaxial layer 120 can be formed on the first epitaxial electrode layer 110 using heteroepitaxial deposition. Heteroepitaxial deposition can include, for example, pulsed laser deposition (PLD), atomic layer deposition (ALD), chemical vapor deposition (CVD), etc. The ferroelectric epitaxial layer 120 can have a thickness of, for example, one to three nanometers (1 nm to 3 nm).

[0049] The ferroelectric epitaxial layer 120 can possess ferroelectric properties, which is combined with the above. Figure 1 The description is as follows. As an example, the ferroelectric epitaxial layer 120 may have remanent polarization and a coercive field. Furthermore, the ferroelectric epitaxial layer 120 may exhibit negative capacitance within a predetermined electric field range.

[0050] In one embodiment, the ferroelectric epitaxial layer 120 may comprise hafnium zirconium oxide. In another embodiment, the ferroelectric epitaxial layer 120 may comprise hafnium oxide doped with a dopant, or hafnium zirconium oxide doped with a dopant. Dopant may comprise, for example, carbon (C), silicon (Si), magnesium (Mg), aluminum (Al), yttrium (Y), nitrogen (N), germanium (Ge), tin (Sn), strontium (Sr), lead (Pb), calcium (Ca), barium (Ba), titanium (Ti), zirconium (Zr), gadolinium (Gd), and lanthanum (La), or combinations of two or more of these.

[0051] See Figure 4 The dielectric epitaxial layer 130 can be disposed on the ferroelectric epitaxial layer 120. The dielectric epitaxial layer 130 can have a fluorite-type crystal structure. In one embodiment, the dielectric epitaxial layer 130 can have a monoclinic or tetragonal crystal structure.

[0052] The dielectric epitaxial layer 130 can be formed on the ferroelectric epitaxial layer 120 using heteroepitaxial methods. Heteroepitaxial methods can include, for example, pulsed laser deposition (PLD), atomic layer deposition (ALD), chemical vapor deposition (CVD), etc. The dielectric epitaxial layer 130 can have a thickness of, for example, 1 nm to 3 nm.

[0053] The dielectric epitaxial layer 130 can have non-ferroelectric properties, as described above. Figure 2 As described, the dielectric epitaxial layer 130 can exhibit positive capacitance across the entire electric field range, such as... Figure 2 As described in curve 20. In one embodiment, the dielectric epitaxial layer 130 may include, for example, hafnium oxide, zirconium oxide, zirconium-doped hafnium zirconium oxide, or a combination of two or more thereof. As described above, although the dielectric epitaxial layer 130 may include the same metal as the ferroelectric epitaxial layer 120, it may have a different crystal structure than the ferroelectric epitaxial layer 120. The dielectric epitaxial layer 130 together with the ferroelectric epitaxial layer 120 may constitute the dielectric structure 1000.

[0054] See back Figure 4 The second epitaxial electrode layer 140 can be disposed on the dielectric epitaxial layer 130. The conductive pyrochlore oxide can have a fluorite-type crystal structure. The second epitaxial electrode layer 140 can be formed on the dielectric epitaxial layer 130 by heteroepitaxialization. Heteroepitaxialization can include, for example, pulsed laser deposition (PLD), atomic layer deposition (ALD), chemical vapor deposition (CVD), etc. In one embodiment, the second epitaxial electrode layer 140 can be formed of the same material as the first epitaxial electrode layer 110.

[0055] As described above, according to embodiments of this disclosure, a first epitaxial electrode layer, a ferroelectric epitaxial layer, a dielectric epitaxial layer, and a second epitaxial electrode layer are sequentially disposed on a substrate, and each stack can be formed by an epitaxial layer. Therefore, the defect density at the interfaces between the first epitaxial electrode layer and the ferroelectric epitaxial layer, between the ferroelectric epitaxial layer and the dielectric epitaxial layer, or between the dielectric epitaxial layer and the second epitaxial electrode layer can be reduced. Furthermore, the formation of the ferroelectric epitaxial layer and the dielectric epitaxial layer as epitaxial layers allows for improved polarization properties of both. Consequently, through the improvement of the interface characteristics and polarization characteristics described above, a semiconductor device with increased capacitance, increased breakdown voltage, and reduced leakage current can be provided.

[0056] Figure 5 This is a schematic cross-sectional view illustrating a semiconductor device according to another embodiment of the present disclosure. See also Figure 5 In semiconductor device 2, the positions of the ferroelectric epitaxial layer 120 and the dielectric epitaxial layer 130 of dielectric structure 2000 may differ from those of semiconductor device 2. Figure 4 The location of the semiconductor device 1. Apart from the structure related to the arrangement of the ferroelectric epitaxial layer 120 and the dielectric epitaxial layer 130, the remaining configuration can be... Figure 4 The structure of semiconductor device 1 is essentially the same.

[0057] See Figure 5 A first epitaxial electrode layer 110 may be disposed on a substrate 101. A dielectric epitaxial layer 130 may be disposed on the first epitaxial electrode layer 110. The dielectric epitaxial layer 130 may be formed on the first epitaxial electrode layer 110 using a heteroepitaxial method. Examples of heteroepitaxial methods may include, for example, pulsed laser deposition (PLD), atomic layer deposition (ALD), chemical vapor deposition (CVD), etc. The dielectric epitaxial layer 130 may have a thickness of, for example, 1 nm to 3 nm.

[0058] A ferroelectric epitaxial layer 120 can be disposed on a dielectric epitaxial layer 130. The ferroelectric epitaxial layer 120 can be an epitaxial layer formed on the dielectric epitaxial layer 130 by a heteroepitaxial method. Heteroepitaxial methods can include, for example, pulsed laser deposition (PLD), atomic layer deposition (ALD), chemical vapor deposition (CVD), etc. The ferroelectric epitaxial layer 120 can have a thickness of, for example, 1 nm to 3 nm.

[0059] The second epitaxial electrode layer 140 can be disposed on the ferroelectric epitaxial layer 120. The second epitaxial electrode layer 140 can be formed on the ferroelectric epitaxial layer 120 by heteroepitaxialization. Heteroepitaxialization can include, for example, pulsed laser deposition (PLD), atomic layer deposition (ALD), chemical vapor deposition (CVD), etc.

[0060] As described above, according to embodiments of this disclosure, a first epitaxial electrode layer, a dielectric epitaxial layer, a ferroelectric epitaxial layer, and a second epitaxial electrode layer are sequentially disposed on a substrate, all of which can be formed from epitaxial layers. Accordingly, the density of impurities or defects at the interfaces between the first epitaxial electrode layer and the dielectric epitaxial layer, between the dielectric epitaxial layer and the ferroelectric epitaxial layer, or between the ferroelectric epitaxial layer and the second epitaxial electrode layer is reduced. Furthermore, the formation of the ferroelectric epitaxial layer and the dielectric epitaxial layer as epitaxial layers allows for improved polarization properties of both. As a result, through the improvement of the aforementioned interface characteristics and polarization characteristics, a semiconductor device with increased capacitance, increased breakdown voltage, and reduced leakage current can be provided.

[0061] Figure 6 This is a schematic cross-sectional view illustrating a semiconductor device according to another embodiment of the present disclosure. See also Figure 6 ,and Figure 4 Compared to semiconductor device 1, semiconductor device 3 may further include a barrier insulating layer 210 disposed between ferroelectric epitaxial layer 120 and dielectric epitaxial layer 130. The barrier insulating layer 210 may include, for example, aluminum oxide, yttrium oxide, magnesium oxide, or a combination of two or more of them.

[0062] The barrier insulating layer 210 can suppress material exchange between the ferroelectric epitaxial layer 120 and the dielectric epitaxial layer 130. Therefore, changes in the material composition of the ferroelectric epitaxial layer 120 and the dielectric epitaxial layer 130 caused by direct contact can be prevented or suppressed. Thus, the ferroelectric properties of the ferroelectric epitaxial layer 120 can be stabilized, and the non-ferroelectric properties of the dielectric epitaxial layer 130 can be stabilized. As a result, the effect of increasing capacitance through the series electrical connection of the ferroelectric epitaxial layer 120 and the dielectric epitaxial layer 130 can be more reliably realized in the semiconductor device 3.

[0063] Furthermore, the barrier insulating layer 210 can have a larger bandgap energy than the ferroelectric epitaxial layer 120 and the dielectric epitaxial layer 130. Therefore, the barrier insulating layer 210 can form a barrier between the ferroelectric epitaxial layer 120 and the dielectric epitaxial layer 130. Thus, the barrier insulating layer 210 can reduce the leakage current generated at the interface between the ferroelectric epitaxial layer 120 and the dielectric epitaxial layer 130 during the operation of the semiconductor device 3. As a result, the breakdown voltage of the semiconductor device 3 can be increased.

[0064] In one embodiment, the barrier insulating layer 210 may have an amorphous structure. However, the thickness of the barrier insulating layer 210 may be thin enough that when the dielectric epitaxial layer 130 is formed on the barrier insulating layer 210, the dielectric epitaxial layer 130 grows epitaxially along the crystal structure of the ferroelectric epitaxial layer 120 beneath the barrier insulating layer 210. That is, even if the barrier insulating layer 210 is interposed between the dielectric epitaxial layers 130, the dielectric epitaxial layer 130 may still have a fluorite-type crystal structure. In one embodiment, the dielectric epitaxial layer 130 may have a monoclinic or tetragonal crystal structure.

[0065] In some embodiments, the barrier insulating layer 210 can be applied to Figure 5 The semiconductor device 2. That is, a layer substantially similar to the barrier insulating layer 210 can be disposed thereon. Figure 5 Between the dielectric epitaxial layer 130 and the ferroelectric epitaxial layer 120 in the dielectric structure 2000.

[0066] Figure 7 This is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present disclosure. Regarding the configuration of the barrier insulating layers 211, 212, and 213, Figure 7 The semiconductor device 4 can be used with a reference Figure 6 The semiconductor device 3 described is different. The remaining components of the semiconductor device 4 can be the same as those described. Figure 6 The semiconductor devices 3 are substantially the same, except for the blocking insulating layers 211, 212 and 213.

[0067] See Figure 7 The semiconductor device 4 may include a first barrier insulating layer to third barrier insulating layers 211, 212, and 213. The first barrier insulating layer may be connected to... Figure 6 The barrier insulating layer 210 of the semiconductor device 3 is substantially the same.

[0068] A second barrier insulating layer 212 may be disposed between the first epitaxial electrode layer 110 and the ferroelectric epitaxial layer 120. The second barrier insulating layer 212 can suppress material exchange between the first epitaxial electrode layer 110 and the ferroelectric epitaxial layer 120. Therefore, changes in the material composition of the ferroelectric epitaxial layer can be prevented or suppressed.

[0069] Furthermore, the bandgap energy of the second barrier insulating layer 212 can be greater than that of the ferroelectric epitaxial layer 120. Therefore, the second barrier insulating layer 212 can form a barrier between the first epitaxial electrode layer 110 and the ferroelectric epitaxial layer 120. Thus, the second barrier insulating layer 212 can reduce the leakage current generated at the interface between the first epitaxial electrode layer 110 and the ferroelectric epitaxial layer 120 during operation of the semiconductor device 4. As a result, the breakdown voltage of the semiconductor device 4 can be increased.

[0070] The second barrier insulating layer 212 may have an amorphous structure. However, the thickness of the second barrier insulating layer 212 may be thin enough that when the ferroelectric epitaxial layer 120 is formed on the second barrier insulating layer 212, the ferroelectric epitaxial layer 120 grows epitaxially under the influence of the crystal structure of the first epitaxial electrode layer 110 disposed beneath the second barrier insulating layer 212. That is, even if the second barrier insulating layer 212 is interposed between the ferroelectric epitaxial layer 120 and the first epitaxial electrode layer 110, the ferroelectric epitaxial layer 120 may still have a fluorite-type crystal structure. The ferroelectric epitaxial layer 120 may have an orthorhombic crystal structure. In one embodiment, the second barrier insulating layer 212 may include, for example, aluminum oxide, yttrium oxide, magnesium oxide, or a combination of two or more of these.

[0071] A third barrier insulating layer 213 may be disposed between the dielectric epitaxial layer 130 and the second epitaxial electrode layer 140. The third barrier insulating layer 213 can suppress material exchange between the dielectric epitaxial layer 130 and the second epitaxial electrode layer 140. Therefore, changes in the material composition of the dielectric epitaxial layer 130 can be prevented or suppressed.

[0072] Furthermore, the bandgap energy of the third barrier insulating layer 213 can be greater than that of the dielectric epitaxial layer 130. Therefore, the third barrier insulating layer 213 can form a barrier between the dielectric epitaxial layer 130 and the second epitaxial electrode layer 140. As a result, the third barrier insulating layer 213 can reduce the leakage current generated at the interface between the dielectric epitaxial layer 130 and the second epitaxial electrode layer 140 during operation of the semiconductor device 4. Consequently, the breakdown voltage of the semiconductor device 4 can be increased.

[0073] The third barrier insulating layer 213 may have an amorphous structure. However, the thickness of the third barrier insulating layer 213 may be thin enough that when the second epitaxial electrode layer 140 is formed on the third barrier insulating layer 213, the second epitaxial electrode layer 140 grows epitaxially under the influence of the crystal structure of the dielectric epitaxial layer 130 located below the third barrier insulating layer 213. That is, even if the third barrier insulating layer 213 is interposed between the second epitaxial electrode layer 140 and the dielectric epitaxial layer 130, the second epitaxial electrode layer 140 may still have a fluorite-type crystal structure. In one embodiment, the third barrier insulating layer 213 may include, for example, aluminum oxide, yttrium oxide, magnesium oxide, or a combination of two or more of them.

[0074] In some embodiments (not shown), one of the second barrier insulating layer 212 or the third barrier insulating layer 213 may be omitted. For example, the semiconductor device 4 may include a first barrier insulating layer 211 and a second barrier insulating layer 212, or the semiconductor device 4 may include a first barrier insulating layer 211 and a third barrier insulating layer 213.

[0075] In some embodiments (not shown), the combination of the first barrier insulating layer to the third barrier insulating layers 211, 212 and 213 can be similarly applied. Figure 5 Semiconductor device 2. For example, in semiconductor device 2, a first barrier insulating layer may be disposed between dielectric epitaxial layer 130 and ferroelectric epitaxial layer 120, a second barrier insulating layer may be disposed between first epitaxial electrode layer 110 and dielectric epitaxial layer 130, and a third barrier insulating layer may be disposed between ferroelectric epitaxial layer 120 and second epitaxial electrode layer 140.

[0076] Figure 8A This is a schematic plan view of a memory cell of a semiconductor device according to an embodiment of the present disclosure. Figure 8B It is along Figure 8A A cross-sectional view taken from line A-A' of the memory cell. Figure 8C It is along Figure 8A A cross-sectional view of the memory cell taken by line B-B'.

[0077] See Figures 8A to 8C Each of the memory cells 5 may include a cell transistor, which includes a buried word line 308, a bit line 314, and a capacitor 400.

[0078] Substrate 301 may include a semiconductor material. Substrate 301 may include a device isolation layer 303 and an active region 304. Active region 304 may be doped with n-type or p-type dopant. Each cell region of active region 304 may be doped with p-type dopant. Active region 304 may be defined as a region of substrate 301 separated by device isolation layer 303. Device isolation layer 303 may be formed by shallow trench isolation (STI) process and may be disposed in device isolation trench 302 formed in substrate 301.

[0079] See Figure 8C Word line trenches 306 can be formed in the substrate 301. A gate insulating layer 307 can be disposed on the inner surface of each word line trench 306. Buried word lines 308 can be disposed on the gate insulating layer 307. The buried word lines 308 can partially fill the word line trenches 306.

[0080] A word line overlay 309 may be disposed on the buried word line 308 in each word line trench 306. The upper surface 308S of the buried word line 308 may be located at a lower level than the surface 301S of the substrate 301. The buried word line 308 may include a conductive material. In one embodiment, the buried word line 308 may be a thin film structure comprising a titanium nitride layer and a tungsten layer. In another embodiment, the buried word line 308 may be made of a single titanium nitride layer or a single tungsten layer.

[0081] See Figure 8B and Figure 8C The first doped region 310 and the second doped region 311 can be formed in the active region 304 of the substrate 301. The first doped region 310 and the second doped region 311 can be spaced apart from each other by word line trenches 306. One of the first doped region 310 and the second doped region 311 can be the source region of a unit transistor, and the other can be the drain region of a unit transistor. For example, the first doped region 310 and the second doped region 311 can include n-type dopants such as arsenic (As) or phosphorus (P).

[0082] As described above, the unit transistor may include a buried word line 308 and a first doped region 310 and a second doped region 311. The buried word line 308 may be... Figure 8A It extends in the x direction.

[0083] See Figure 8B and Figure 8C Bit line contact plug 313 may be disposed on substrate 301. Bit line contact plug 313 may be electrically connected to first doped region 310. Bit line contact plug 313 may be disposed in bit line contact hole 312. Bit line contact hole 312 may be formed in substrate 301, and hard mask layer 305 may be disposed on substrate 301. Lower surface 313S of bit line contact plug 313 may be located at a lower level than upper surface 301S of substrate 301. Bit line contact plug 313 may include conductive material. Bit line structure BL may be disposed on bit line contact plug 313. Bit line structure BL may include bit line 314 in contact with bit line contact plug 313 and bit line hard mask 315 disposed on bit line 314.

[0084] See Figures 8A to 8C Viewed from the plane, bit line 314 may extend in one direction (e.g., the y-direction) to intersect with buried word line 308. Bit line 314 may be electrically connected to the first doped region 310 via bit line contact plug 313. Bit line 314 may include a conductive material. Bit line hard mask 315 may include an insulating material.

[0085] The bit line spacer 316 can be disposed on the sidewall of each bit line structure BL. For example... Figure 8A As shown, in this example, the bit line spacer 316 may extend to cover both sidewalls of the bit line contact plug 313. The bit line spacer 316 may comprise silicon oxide, silicon nitride, or a combination thereof. In another embodiment, the bit line spacer 316 may include an air gap. As an example, the bit line spacer 316 may have a nitride-air gap-nitride (NAN) structure with the air gap located between silicon nitride layers.

[0086] Storage node contact (SNC) plugs may be disposed between bit line structures BL. Storage node contact (SNC) plugs may be disposed within storage node contact vias 318. Storage node contact (SNC) plugs may be electrically connected to a second doped region 311. In one embodiment, the storage node contact (SNC) plug may include a lower plug 319 and an upper plug 321. The storage node contact (SNC) plug may also include an ohmic contact layer 320 between the lower plug 319 and the upper plug 321. In one embodiment, the upper plug 321 may include metal, the lower plug 319 may include doped silicon, and the ohmic contact layer 320 may include metal silicide.

[0087] See Figure 8C The plug separation layer 317 can be disposed on the hard mask layer 305. The plug separation layer 317 can be an insulating layer disposed between adjacent bit line structures BL. Through the plug separation layer 317 and the hard mask layer 305, the storage node contact hole 318 can be formed on the active region 304.

[0088] See Figures 8A to 8C The capacitor 400 can be disposed on the storage node contact (SNC) plug. The capacitor 400 can have... Figure 4 Semiconductor devices 1, Figure 5 Semiconductor devices 2, Figure 6 Semiconductor device 3 and Figure 7 The configuration of any one of the semiconductor devices 4. The following will refer to... Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11A and Figure 11B The configuration of capacitor 400 is described in more detail.

[0089] Figure 9A and Figure 9B This is a schematic cross-sectional view of a capacitor in a semiconductor device according to an embodiment of the present disclosure. Capacitors 401 and 402 can be applied to... Figures 8A to 8C The memory cell 5 has a capacitor 400.

[0090] See Figure 9A The capacitor 401 may include: a storage node epitaxial electrode 410a, a ferroelectric epitaxial layer 420a disposed on the storage node epitaxial electrode 410a, a dielectric epitaxial layer 430a disposed on the ferroelectric epitaxial layer 420a, and a plate epitaxial electrode 440a disposed on the dielectric epitaxial layer 430a. The storage node epitaxial electrode 410a may be disposed on the above reference. Figures 8A to 8C The memory cell 5 described is on the storage node contact (SNC) plug. The storage node epitaxial electrode 410a can be electrically connected to the second doped region 311 of the substrate 301.

[0091] See Figure 9A The storage node epitaxial electrode 410a may have an open cylindrical shape. The ferroelectric epitaxial layer 420a may be configured to cover both the inner and outer walls of the storage node epitaxial electrode 410a. The dielectric epitaxial layer 430a may be configured to cover the ferroelectric epitaxial layer 420a. The plate epitaxial electrode 440a may be configured to cover the dielectric epitaxial layer 430a.

[0092] In one embodiment, capacitor 401 may be a reference. Figure 4 The semiconductor device 1 described. As an example, the storage node epitaxial electrode 410a and the plate epitaxial electrode 440a of the capacitor 401 can correspond to the reference. Figure 4 The semiconductor device 1 described includes a first epitaxial electrode layer 110 and a second epitaxial electrode layer 140. Additionally, the ferroelectric epitaxial layer 420a and the dielectric epitaxial layer 430a of the capacitor 401 can correspond to the reference. Figure 4 The semiconductor device 1 described includes a ferroelectric epitaxial layer 120 and a dielectric epitaxial layer 130.

[0093] In another embodiment, capacitor 401 may be a reference. Figure 5 The semiconductor device 2 described. In Figure 5 In the semiconductor device 2, the arrangement of the ferroelectric epitaxial layer 120 and the dielectric epitaxial layer 130 can be consistent with... Figure 4 The arrangement of semiconductor device 1 is reversed.

[0094] Accordingly ( Figure 9A (Not shown in the figure) In capacitor 401, a dielectric epitaxial layer 430a can be disposed on storage node epitaxial electrode 410a, a ferroelectric epitaxial layer 420a can be disposed on dielectric epitaxial layer 430a, and a plate epitaxial electrode 440a can be disposed on ferroelectric epitaxial layer 420a.

[0095] In another embodiment, capacitor 401 may be a reference. Figure 6 The semiconductor device 3 described. With Figure 4 Compared to semiconductor device 1, Figure 6 The semiconductor device 3 may also include a barrier insulating layer 210. Accordingly ( Figure 9A (Not shown in the figure) In capacitor 401, a barrier insulating layer 210 may also be provided between the ferroelectric epitaxial layer 420a and the dielectric epitaxial layer 430a.

[0096] In another embodiment ( Figure 9A (Not shown in the image), capacitor 401 can be a reference. Figure 7 The semiconductor device 4 is described. (And...) Figure 4 Compared to semiconductor device 1, Figure 7The semiconductor device 4 may further include a first barrier insulating layer to third barrier insulating layers 211, 212, and 213. Accordingly, in the capacitor 401, the first barrier insulating layer may also be disposed between the ferroelectric epitaxial layer 420a and the dielectric epitaxial layer 430a, the second barrier insulating layer may also be disposed between the storage node epitaxial electrode 410a and the ferroelectric epitaxial layer 420a, and the third barrier insulating layer may also be disposed between the dielectric epitaxial layer 430a and the plate epitaxial electrode 440a.

[0097] The seed layer (not shown) can be set Figures 8A to 8C Storage Node Contact (SNC) plug and Figure 9A The seed layer is between the storage node epitaxial electrodes 410a. The seed layer can be a seed layer used to form the storage node epitaxial electrodes 410a. The seed layer can have a fluorite-type crystal structure.

[0098] See Figure 9B ,and Figure 9B Compared to capacitor 401, capacitor 402 may further include a support 450a connecting adjacent storage node epitaxial electrodes 410a to each other. The support 450a can be used to physically support the outer walls of the storage node epitaxial electrodes 410a. The support 450a can improve the structural stability of the storage node epitaxial electrodes 410a. The support 450a may include, for example, silicon nitride.

[0099] Figure 10A and Figure 10B This is a schematic cross-sectional view of a capacitor according to another embodiment of the present disclosure. Figure 10A and Figure 10B The capacitors 403 and 404 shown can be applied to Figures 8A to 8C The memory cell 5 has a capacitor 400.

[0100] See Figure 10A The capacitor 403 may include: a storage node epitaxial electrode 410b, a ferroelectric epitaxial layer 420b disposed on the storage node electrode 410b, a dielectric epitaxial layer 430b disposed on the ferroelectric epitaxial layer 420b, and a plate epitaxial electrode 440b disposed on the dielectric epitaxial layer 430b.

[0101] Regarding the shape of the storage node epitaxial electrode 410b, the capacitor 403 may be related to... Figure 9A The capacitor 401 is different. See [link / reference]. Figure 10A The storage node epitaxial electrode 410b can have the shape of a solid cylinder without inner sidewalls. Therefore, the ferroelectric epitaxial layer 420b can be configured to cover the outer wall surface of the storage node epitaxial electrode 410b.

[0102] The seed layer (not shown) can be set Figures 8A to 8CStorage Node Contact (SNC) plug and Figure 10A The seed layer is between the storage node epitaxial electrodes 410b. The seed layer can be a seed layer used to form the storage node epitaxial electrodes 410b. The seed layer can have a fluorite-type crystal structure.

[0103] See Figure 10B ,and Figure 10A Compared to capacitor 403, capacitor 404 may further include a support 450b connecting adjacent storage node epitaxial electrodes 410b to each other. The support 450b can be used to physically support the outer walls of the storage node epitaxial electrodes 410b. The support 450b can improve the structural stability of the storage node epitaxial electrodes 410b. The support 450b may include, for example, silicon nitride.

[0104] Figure 11A and Figure 11B This is a schematic cross-sectional view of a capacitor according to another embodiment of the present disclosure. Capacitors 405 and 406 can be applied to... Figures 8A to 8C The memory cell 5 has a capacitor 400.

[0105] See Figure 11A The capacitor 405 may include: a storage node epitaxial electrode 410c, a ferroelectric epitaxial layer 420c disposed on the storage node epitaxial electrode 410c, a dielectric epitaxial layer 430c disposed on the ferroelectric epitaxial layer 420c, and a plate epitaxial electrode 440c disposed on the dielectric epitaxial layer 430c.

[0106] Capacitor 405 can be used with Figure 9A The difference between capacitor 401 and capacitor 405 lies in the shape of the storage node epitaxial electrode 410c. Apart from the shape of the storage node epitaxial electrode 410c, the configuration of capacitor 405 can be similar to... Figure 9A The configuration of capacitor 401 is essentially the same. See also Figure 11A The shape of the storage node epitaxial electrode 410c can be Figure 9A The open cylinder shape of the storage node epitaxial electrode 410a shown in the figure and Figure 10A The combination of columnar shapes of the storage node epitaxial electrode 410b shown.

[0107] The seed layer (not shown) can be set Figures 8A to 8C Storage Node Contact (SNC) plug and Figure 11A The seed layer is used between the epitaxial electrodes 410c of the storage node. The seed layer can be a seed layer applied to form the epitaxial electrodes 410c of the storage node. The seed layer can have a fluorite-type crystal structure.

[0108] See Figure 11B ,and Figure 11ACompared to capacitor 405, capacitor 406 may further include a support 450c connecting the epitaxial electrodes 410c of the storage nodes to each other. The support 450c can be used to physically support the outer walls of adjacent epitaxial electrodes 410c of the storage nodes. The support 450c can improve the structural stability of the epitaxial electrodes 410c of the storage nodes. The support 450c may include, for example, silicon nitride.

[0109] Embodiments of this disclosure have been disclosed for illustrative purposes. Those skilled in the art will understand that various modifications, additions, and substitutions are possible without departing from the scope and spirit of this disclosure and the appended claims.

Claims

1. A semiconductor device, comprising: Substrate; A first epitaxial electrode layer is disposed on the substrate; A ferroelectric epitaxial layer is disposed on the first epitaxial electrode layer; A dielectric epitaxial layer disposed on the ferroelectric epitaxial layer; A second epitaxial electrode layer is disposed on the dielectric epitaxial layer; and A first barrier insulating layer is disposed between the ferroelectric epitaxial layer and the dielectric epitaxial layer. Each of the first epitaxial electrode layer and the second epitaxial electrode layer comprises a conductive pyrochlore oxide. The ferroelectric epitaxial layer and the dielectric epitaxial layer are connected in series and electrically. The dielectric structure comprising the ferroelectric epitaxial layer and the dielectric epitaxial layer is nonferroelectric.

2. The semiconductor device according to claim 1, wherein, The ferroelectric epitaxial layer has a negative capacitance.

3. The semiconductor device according to claim 1, wherein, The conductive pyrochlore oxide comprises at least one selected from the following: lead iridium oxide (Pb₂Ir₂O₇), lanthanum iridium oxide (La₂Ir₂O₇), cerium iridium oxide (Ce₂Ir₂O₇), praseodymium iridium oxide (Pr₂Ir₂O₇), neodymium iridium oxide (Nd₂Ir₂O₇), samarium iridium oxide (Sm₂Ir₂O₇), gadolinium iridium oxide (Gd₂Ir₂O₇), ytterbium iridium oxide (Yb₂Ir₂O₇), lanthanum ruthenium oxide (La₂Ru₂O₇), cerium ruthenium oxide (Ce₂Ru₂O₇), praseodymium ruthenium oxide (Pr₂Ru₂O₇), neodymium ruthenium oxide (Nd₂Ru₂O₇), samarium ruthenium oxide (Sm₂Ru₂O₇), gadolinium ruthenium oxide (Gd₂Ru₂O₇), ytterbium ruthenium oxide (Yb₂Ru₂O₇), and bismuth ruthenium oxide (Bi₂Ru₂O₇). 7-δ ,0<δ<1), lead ruthenium oxide (Pb2Ru2O) 7-δ ,0<δ<1), thallium ruthenium oxide (Tl2Ru2O) 7-δ ,0<δ<1), Bismuth Iridium Oxide (Bi2Ir2O) 7-δ ,0<δ<1), lead iridium oxide (Pb2Ir2O) 7-δ ,0<δ<1) and thallium iridium oxide (Tl2Ir2O 7-δ , 0 < δ < 1).

4. The semiconductor device according to claim 1, wherein, The ferroelectric epitaxial layer includes hafnium zirconium oxide.

5. The semiconductor device according to claim 4, wherein, The ferroelectric epitaxial layer includes a dopant doped in the hafnium zirconium oxide, and The dopant includes at least one selected from the following: carbon (C), silicon (Si), magnesium (Mg), aluminum (Al), yttrium (Y), nitrogen (N), germanium (Ge), tin (Sn), strontium (Sr), lead (Pb), calcium (Ca), barium (Ba), titanium (Ti), zirconium (Zr), gadolinium (Gd), and lanthanum (La).

6. The semiconductor device according to claim 1, wherein, The dielectric epitaxial layer comprises at least one selected from hafnium oxide, zirconium oxide, and zirconium-doped zirconium (Zr) oxide, and The dielectric epitaxial layer is nonferroelectric.

7. The semiconductor device according to claim 1, wherein, The ferroelectric epitaxial layer has an orthorhombic crystal structure, and The dielectric epitaxial layer has a monoclinic or tetragonal crystal structure.

8. The semiconductor device according to claim 1, wherein, Each of the ferroelectric epitaxial layer and the dielectric epitaxial layer has a thickness of 1 nanometer to 3 nanometers.

9. The semiconductor device according to claim 1, wherein, The first barrier insulating layer comprises at least one selected from aluminum oxide, yttrium oxide, and magnesium oxide.

10. The semiconductor device of claim 9, further comprising at least one of a second barrier insulating layer disposed between the first epitaxial electrode layer and the ferroelectric epitaxial layer and a third barrier insulating layer disposed between the dielectric epitaxial layer and the second epitaxial electrode layer.

11. The semiconductor device according to claim 1, wherein, The substrate comprises yttrium-stabilized zirconium oxide or strontium tin oxide.

12. A semiconductor device, comprising: Substrate; A first epitaxial electrode layer is disposed on the substrate; A dielectric epitaxial layer is disposed on the first epitaxial electrode layer; A ferroelectric epitaxial layer is disposed on the dielectric epitaxial layer; A second epitaxial electrode layer is disposed on the ferroelectric epitaxial layer; and A first barrier insulating layer is disposed between the ferroelectric epitaxial layer and the dielectric epitaxial layer. Each of the first epitaxial electrode layer and the second epitaxial electrode layer comprises a conductive pyrochlore oxide. Wherein, the dielectric epitaxial layer and the ferroelectric epitaxial layer are connected in series, and The dielectric structure comprising the dielectric epitaxial layer and the ferroelectric epitaxial layer is nonferroelectric.

13. The semiconductor device according to claim 12, wherein, The ferroelectric epitaxial layer has a negative capacitance.

14. The semiconductor device according to claim 12, wherein, The conductive pyrochlore oxide comprises at least one selected from the following: lead iridium oxide (Pb₂Ir₂O₇), lanthanum iridium oxide (La₂Ir₂O₇), cerium iridium oxide (Ce₂Ir₂O₇), praseodymium iridium oxide (Pr₂Ir₂O₇), neodymium iridium oxide (Nd₂Ir₂O₇), samarium iridium oxide (Sm₂Ir₂O₇), gadolinium iridium oxide (Gd₂Ir₂O₇), ytterbium iridium oxide (Yb₂Ir₂O₇), lanthanum ruthenium oxide (La₂Ru₂O₇), cerium ruthenium oxide (Ce₂Ru₂O₇), praseodymium ruthenium oxide (Pr₂Ru₂O₇), neodymium ruthenium oxide (Nd₂Ru₂O₇), samarium ruthenium oxide (Sm₂Ru₂O₇), gadolinium ruthenium oxide (Gd₂Ru₂O₇), ytterbium ruthenium oxide (Yb₂Ru₂O₇), and bismuth ruthenium oxide (Bi₂Ru₂O₇). 7-δ ,0<δ<1), lead ruthenium oxide (Pb2Ru2O) 7-δ ,0<δ<1), thallium ruthenium oxide (Tl2Ru2O) 7-δ ,0<δ<1), Bismuth Iridium Oxide (Bi2Ir2O) 7-δ ,0<δ<1), lead iridium oxide (Pb2Ir2O) 7-δ ,0<δ<1) and thallium iridium oxide (Tl2Ir2O 7-δ , 0 < δ < 1).

15. The semiconductor device according to claim 12, wherein, The ferroelectric epitaxial layer includes hafnium zirconium oxide.

16. The semiconductor device according to claim 15, wherein, The ferroelectric epitaxial layer includes a dopant doped in the hafnium zirconium oxide, and The dielectric epitaxial layer is nonferroelectric.

17. The semiconductor device of claim 12, further comprising at least one of a second barrier insulating layer disposed between the first epitaxial electrode layer and the ferroelectric epitaxial layer and a third barrier insulating layer disposed between the dielectric epitaxial layer and the second epitaxial electrode layer.

18. A semiconductor device, comprising: Substrate; as well as A capacitor, which is disposed on the substrate, The capacitor includes: Storage node epitaxial electrodes; A ferroelectric epitaxial layer is disposed on the epitaxial electrode of the storage node; A dielectric epitaxial layer disposed on the ferroelectric epitaxial layer; Epitaxial electrodes, disposed on the dielectric epitaxial layer; and A first barrier insulating layer is disposed between the ferroelectric epitaxial layer and the dielectric epitaxial layer. Each of the storage node epitaxial electrode and the plate epitaxial electrode comprises a conductive pyrochlore oxide. The ferroelectric epitaxial layer and the dielectric epitaxial layer are connected in series and electrically. The capacitor in question has non-ferroelectric properties.

19. The semiconductor device according to claim 18, wherein, The ferroelectric epitaxial layer achieves negative capacitance.

20. The semiconductor device of claim 18, further comprising a field-effect transistor disposed on the substrate and electrically connected to the capacitor.

21. The semiconductor device of claim 18, further comprising at least one of a second barrier insulating layer disposed between the storage node epitaxial electrode and the ferroelectric epitaxial layer and a third barrier insulating layer disposed between the dielectric epitaxial layer and the plate epitaxial electrode.

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