Semiconductor structure and integrated circuit layout

Abstract

A semiconductor structure includes first and second cells arranged adjacent to each other along a column direction and having first and second cell heights, respectively. Each cell includes at least one semiconductor active region extending longitudinally along a row direction perpendicular to the column direction. The structure further includes an array of metal traces over the first and second cells. The metal traces are formed by a lithographic process having a half-pitch resolution R row along the row direction. A first pitch of the metal traces along the row direction is greater than or equal to 2R row . At least three rows of the metal traces are located in a region directly over the first and second cells and having a height equal to a sum of the first and second cell heights. A row of the metal traces is disposed across a cell boundary of the first and second cells. Embodiments of the present application relate to integrated circuit layouts.

Description

Technical Field

[0001] Some embodiments of this application relate to semiconductor structures and integrated circuit layouts. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of IC development, functional density (i.e., the number of interconnect devices per chip area) has increased, while geometry (i.e., the smallest component (or line) that can be produced using manufacturing processes) has decreased. This scaling down process typically provides benefits by increasing production efficiency and reducing associated costs. This scaling down also increases the complexity of handling and manufacturing ICs.

[0003] For example, ICs typically use multilayer interconnects to connect various devices (such as transistors) on a chip. Multilayer interconnects include metal traces (or metal lines) and metal vias. When designing these metal traces, some methods focus on directly reducing the metal pitch (the interval at which the metal trace repeats along its width) to meet area budgets. However, small metal pitches make photolithography difficult and thus require double or multiple patterning processes. Therefore, this approach can increase process complexity and cost. Improvements to metal trace design are needed. Summary of the Invention

[0004] Some embodiments of this application provide a semiconductor structure including: a first unit and a second unit, arranged adjacent to each other along a column direction, each of the first unit and the second unit including at least one semiconductor active region extending longitudinally along a row direction perpendicular to the column direction, the first unit having a first unit height along the column direction, and the second unit having a second unit height along the column direction; and an array of metal traces located above the first unit and the second unit, wherein the array of metal traces is arranged in rows and columns, and includes a half-pitch resolution R along the row direction. row The metal traces are formed by a photolithography process, wherein the first spacing along the row direction is greater than or equal to 2R. row At least three rows of the metal traces are located in a region directly above the first unit and the second unit and have a height equal to the sum of the heights of the first unit and the second unit, and one of the rows of the metal traces is configured to span a unit boundary shared by the first unit and the second unit.

[0005] Other embodiments of this application provide a semiconductor structure including: a first cell and a second cell arranged along a column direction and sharing a cell boundary, each of the first cell and the second cell including at least one of an NMOSFET, a PMOSFET, and a CMOSFET, the first cell having a first cell height along the column direction, and the second cell having a second cell height along the column direction; and an array of metal traces located above the first cell and the second cell, wherein the array of metal traces is arranged in rows and columns and formed by a manufacturing process of printing a pattern corresponding to the array of metal traces using a single exposure, at least three rows of the metal traces being located in a region directly above the first cell and the second cell and having a height equal to the sum of the heights of the first cell and the second cell.

[0006] Further embodiments of this application provide an integrated circuit layout, including: a first unit and a second unit, arranged adjacent to each other along a column direction, each of the first unit and the second unit including at least one active region extending longitudinally along a row direction perpendicular to the column direction, the first unit and the second unit having a first unit height and a second unit height respectively along the column direction; and an array of metal traces located above the first unit and the second unit, wherein the array of metal traces is arranged in rows and columns, and includes a half-pitch resolution R along the row direction. row The metal traces are formed by a photolithography process, wherein the first spacing along the row direction is greater than or equal to 2R. row The metal traces in the same column are spaced apart by column spacing, and the sum of the height of any metal trace and the column spacing is in the range of one-half to two-thirds of the average of the height of the first unit and the height of the second unit. Attached Figure Description

[0007] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0008] Figure 1 It is a perspective view of a semiconductor structure having metal traces designed according to aspects of the present invention;

[0009] Figure 2 An embodiment of the present invention is shown. Figure 1 Cross-sectional view of multiple layers of the semiconductor structure shown;

[0010] Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 ,and Figure 9 According to various embodiments of the present invention Figure 1 A top view of the metal traces in the semiconductor structure;

[0011] Figure 10 A flowchart of a method according to various embodiments of the present invention is shown. Detailed Implementation

[0012] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0013] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to readily describe the relationship between one element or component and another (or other) element or component as shown in the figures. In addition to the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly. Furthermore, when numbers or ranges of numbers are described using terms such as “approximately,” “about,” etc., unless otherwise stated, the term is intended to cover numbers within certain variations (e.g., + / - 10% or other variations) based on the knowledge of those skilled in the art disclosed herein. For example, the term “about 5 nm” may cover size ranges of 4.5 nm to 5.5 nm, 4.0 nm to 5.0 nm, etc.

[0014] This application generally relates to semiconductor structures and manufacturing processes, and more specifically to metal traces used in advanced semiconductor manufacturing.

[0015] Technological competitiveness in semiconductor manufacturing rests on four closely related key parameters—performance, power, area, and cost. Semiconductor manufacturers sometimes trade one parameter for another during their manufacturing process to meet the growing demand for smaller, faster electronic devices capable of simultaneously supporting more complex and sophisticated functions. For example, when designing metal traces (or metal lines) in multilayer interconnects, some approaches focus on directly reducing the metal pitch (the interval at which the metal trace repeats along its width) to meet area budgets. However, small metal pitches make photolithography difficult and thus require double or multiple patterning processes. Therefore, this approach typically increases process complexity and cost.

[0016] In this invention, the scaling of metal traces takes on different dimensions. Compared to methods requiring double or multiple patterning, embodiments of this invention do not reduce the metal pitch and width along the width direction of the metal trace, but rather reduce the length of the metal trace and increase the metal pitch. By reducing the length of the metal trace, more metal traces can be arranged along the longitudinal direction within the geometry of a standard cell. Therefore, this invention still provides sufficient metal traces for wiring standard cells, such as AND, NAND, OR, NOR, inverters, etc., which provide building blocks for ICs. Furthermore, because the metal pitch is larger than in other methods, this invention can be implemented using a single patterning (or single exposure) lithography process, eliminating the need for double or multiple patterning, thus reducing process complexity and cost. Additionally, the metal traces of this invention can be wider than those in other methods (for standard cells of the same size), thereby reducing resistance and IR drop, improving semiconductor device performance, and increasing the process margin for via landing.

[0017] Figure 1 A perspective view of a semiconductor structure 100 (e.g., integrated circuit 100) constructed according to various aspects of the present invention is shown. Reference Figure 1 The semiconductor structure 100 includes a substrate 102 and a wiring layer 104 formed above the substrate 102. The wiring layer 104 includes metal traces (or metal lines) 105 (indicated by dashed lines) and vias (…). Figure 1 Not shown in, but in Figures 2-4 The diagram shows a via 106. In one embodiment, metal traces 105 form an array with rows and columns. Multiple metal traces 105 and vias 106 form an interconnect structure connecting active devices (e.g., transistors) and / or passive devices (e.g., resistors) in the semiconductor structure 100. It should be noted that in various embodiments, the semiconductor structure 100 may include any number of wiring layers 104, such as four, five, six, seven, or even more wiring layers.

[0018] In one embodiment, substrate 102 comprises a silicon substrate (e.g., a wafer). Alternatively, substrate 102 may comprise other elemental semiconductors, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. In yet another alternative, substrate 102 is a semiconductor-on-insulator (SOI). Substrate 102 includes active devices, such as p-type field-effect transistors (PFETs), n-type FETs (NFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), p-type MOSFETs (PMOSFETs), n-type MOSFETs (NMOSFETs), complementary MOSFETs (CMOSFETs), bipolar transistors, high-voltage transistors, and high-frequency transistors. Transistors may be planar transistors or multi-gate transistors, such as FinFETs and gate-all-around (GAA) transistors. Substrate 102 may also include passive devices, such as resistors, capacitors, and inductors.

[0019] Wiring layer 104 includes a dielectric material, with metal traces 105 and vias 106 embedded therein. In embodiments, the dielectric material may include a low-k dielectric material, such as an oxide formed from tetraethyl orthosilicate (TEOS), undoped silicate glass, or doped silicon oxide such as borosilicate glass (BPSG), fluorosilicone glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG), and / or other suitable dielectric materials. In embodiments, each metal trace 105 may each include an outer conductive metal diffusion barrier layer and an inner metal conductor. For example, the metal diffusion barrier layer may include tantalum (Ta) or tantalum nitride (TaN), while the metal conductor may include copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), silver (Ag), gold (Au), and other suitable metals. Similarly, each via 106 may each include an outer metal diffusion barrier layer and an inner metal plug.

[0020] Figure 2 A cross-sectional view of a semiconductor structure 100 is shown, illustrating multiple layers therein, including a substrate 102, a well (or diffusion layer) 204, an isolation structure 230, an active region (e.g., a semiconductor fin) 215, a gate structure 240, a Via0 layer, first to sixth metal layers (M1, M2, M3, M4, M5, and M6), and first to fifth via layers (Via1, Via2, Via3, Via4, and Via5). The semiconductor structure 100 may include... Figure 2 Other layers or structures not shown, such as vias and dielectric layers embedded in metal layers. Figure 1The metal trace 105 shown represents a metal trace in any one of the metal layers M1, M2, M3, M4, M5, and M6. Additionally, any one of the metal layers M1, M2, M3, M4, M5, and M6 is connected to an adjacent (below or above) metal layer or transistor terminal (e.g., gate, source, drain) through a via layer having via 106.

[0021] A well 204 is formed in or on substrate 102. Well 204 includes a p-type doped region for an n-type transistor and an n-type doped region for a p-type transistor. In the depicted embodiment, active region 215 includes fin-like semiconductor material (or fins) protruding from substrate 202. In alternative embodiments, active region 215 may include a planar semiconductor region for a planar transistor or a stacked channel layer for a full-ring gate transistor. In one embodiment, active region 215 for an NMOSFET includes monocrystalline silicon or intrinsic silicon or other suitable semiconductor material; while active region 215 for a PMOSFET may include silicon, germanium, silicon-germanium, or other suitable semiconductor material. Isolation structure 230 isolates active region 215. Isolation structure 230 may include silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation materials (e.g., including silicon, oxygen, nitrogen, carbon, or other suitable isolation materials), or combinations thereof. The isolation structure 230 may include different structures, such as shallow trench isolation (STI) structures and / or deep trench isolation (DTI) structures.

[0022] The gate structure 240 includes a gate dielectric layer and a gate electrode layer. The gate dielectric layer may include silicon dioxide, silicon oxynitride, and / or materials such as HfO2, HfSiO, HfSiO4, HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, and HfAlO. x High-k dielectric materials include ZrO, ZrO2, ZrSiO2, AlO, AlSiO, Al2O3, TiO, TiO2, LaO, LaSiO, Ta2O3, Ta2O5, Y2O3, SrTiO3, BaZrO, BaTiO3 (BTO), (Ba,Sr)TiO3 (BST), Si3N4, hafnium dioxide-alumina (HfO2-Al2O3) alloys, other suitable high-k dielectric materials, or combinations thereof. High-k dielectric materials generally refer to dielectric materials with a high dielectric constant (e.g., greater than the dielectric constant of silicon oxide (k≈3.9)). The gate electrode layer may include titanium, aluminum, tantalum carbide, tantalum carbide-nitride, silicon tantalum nitride, titanium nitride, tantalum nitride, ruthenium, molybdenum, tungsten, platinum, tungsten, cobalt, copper, and / or other suitable materials.

[0023] Through-hole layer ( Figure 2 Via0 to Via5) and metal layer ( Figure 2 Each of M1 to M6 may include titanium, tantalum, tungsten, cobalt, molybdenum, ruthenium, or conductive nitrides such as titanium nitride, aluminum titanium nitride, tungsten nitride, tantalum nitride, or combinations thereof.

[0024] In one embodiment, the metal layer and the via layer directly beneath it are formed using a dual damascene process. Taking layers M2 and Via1 as examples, after the dielectric layer stack is formed above layer M1, a process can be used to etch the upper dielectric layer in the stack to form a trench corresponding to the metal trace 105 in layer M2. Another process can then be used to etch additional dielectric layers in the stack and within the trench to form vias corresponding to the vias 106 in layer Via1. One or more metal layers are then filled into the vias and trenches to simultaneously form vias 106 and metal traces 105. Subsequently, a chemical mechanical planarization process is used to remove excess metal and planarize the dielectric and metal layers. This process is repeated for each metal layer and the via layer directly beneath it.

[0025] In various embodiments of the semiconductor structure 100, numerous metal layers and via layers may be present. Therefore, the metal layers need to be optimized given several key metrics. One key metric is the size of the metal traces 105, such as their thickness, width, and length, which affects power consumption, parasitic capacitance, and IR drop. Another key metric is the density of the metal traces 105, i.e., the number of metal traces 105 per unit area. It is generally desirable to have as many metal traces 105 as possible per unit area to provide sufficient wiring for the underlying devices (e.g., transistors). Yet another key metric is manufacturing complexity and cost.

[0026] Some methods aim to directly reduce the metal pitch (the interval at which the metal traces 105 repeat along their width) to increase the density of the metal traces. However, small metal pitches can make photolithography difficult. For example, any photolithography process has certain resolution limitations, which depend in part on the wavelength of the light used for lithography. The minimum feature size that a projection system in a photolithography process can print is approximately given by the following formula:

[0027]

[0028] Where CD is the minimum feature size (also known as the critical size), k1 is a coefficient of packaging process-related factors, λ is the wavelength of the light used, and NA is the numerical aperture of the lens visible from the wafer. When the metal pitch is smaller than the resolution limit of a given lithography process (e.g., CD), the metal traces can no longer be reliably printed in a single exposure, thus requiring dual patterning or multiple patterning processes. Dual patterning divides the mask pattern corresponding to the metal traces into two subsets and prints these two subsets onto the wafer using two separate lithography processes. Similarly, multiple patterning uses two or more lithography processes to print the mask pattern corresponding to the metal traces. Therefore, dual or multiple patterning processes typically increase manufacturing complexity and cost compared to single patterning processes.

[0029] Instead of reducing the spacing and width of the metal traces, embodiments of the present invention reduce the length of the metal traces while maintaining the spacing of the metal traces equal to or greater than the resolution limit of the photolithography process selected for manufacturing the semiconductor structure 100. In other words, the metal traces of the present invention can be manufactured using a single patterning (single exposure) process, thereby reducing manufacturing complexity and cost. Embodiments of the present invention can produce high-density metal traces without incurring the manufacturing complexity and cost required for dual or multiple patterning processes.

[0030] refer to Figure 3 The diagram shows a top view of an array of metal traces 105 designed according to an embodiment of the invention. The metal traces 105 are disposed above a plurality of unit cells 110, wherein two unit cells 110-1 and 110-2 are shown in dashed boxes. Along the Y direction, unit cell 110-1 has a height H1, while unit cell 110-2 has a height H2. In this embodiment, H1 is equal to H2. In alternative embodiments, H1 may be less than or greater than H2. Unit cells 110-1 and 110-2 share a common cell boundary. Figure 3In the depicted embodiment, unit cells 110-1 and 110-2 have the same width along the X direction. A plurality of such unit cells 110 arranged in columns (along the Y direction) and rows (along the X direction) may exist in the semiconductor structure 100. Each unit cell 110 may include one or more standard logic cells, such as AND, NOR, OR, NAND, inverters, etc. Height H1 is large enough that unit cell 110-1 includes one or more NMOSFETs, one or more PMOSFETs, or one or more CMOSFETs. Similarly, height H2 is large enough that unit cell 110-2 includes one or more NMOSFETs, one or more PMOSFETs, or one or more CMOSFETs. For example, each of unit cells 110-1 and 110-2 includes at least one semiconductor active region 215 (also visible in…). Figure 2 An NMOSFET, PMOSFET, or CMOSFET is established on the semiconductor active region 215. At least one semiconductor active region 215 extends longitudinally along the X direction and has a width along the Y direction, which is less than its respective heights H1 and H2. In one embodiment, the height H1 is less than 250 nm, the height H2 is less than 250 nm, and the spacing between the active regions 215 is approximately 25 nm. In such an embodiment, up to 10 active regions 215 may exist in each of cells 110-1 and 110-2.

[0031] The metal traces 105 are arranged in an array having columns (along the Y direction) and rows (along the X direction). Each metal trace 105 extends longitudinally along the Y direction and laterally along the X direction. It should be noted that... Figure 3 The X and Y directions shown in the diagram are for ease of description only and can represent any two orthogonal directions. It should also be noted that... Figure 3 The illustrated metal trace 105 can be located in any metal layer (e.g., M1 to M6 layers) in the semiconductor structure 100, and the metal trace 105 in the metal layer directly above or below can extend longitudinally along the X direction and laterally along the Y direction.

[0032] exist Figure 3 In the depicted embodiment, all metal traces 105 in the array have the same length (or height) L along the Y direction. m and the same width W along the X direction m Additionally, the length L m Less than height H1 and less than height H2. Along the X direction (row direction), the metal trace 105 is spaced between two adjacent edges by a row spacing (or edge-to-edge spacing) S. row Spacing out. Additionally, along the X direction, the metal trace 105 is spaced at intervals P. mSeparately spaced. Figure 3 Spacing P m The diagram illustrates the distance between the centerlines of the metal trace 105. In an alternative embodiment, the spacing P... m This is the edge-to-edge distance of the metal trace 105. Along the Y direction (column direction), the metal trace 105 is spaced at column spacing (or end-to-end spacing) S between two adjacent ends. col Separately spaced.

[0033] In this embodiment, the array of metal traces 105 is fabricated or will be fabricated using a single exposure lithography process. The lithography process has a half-pitch resolution R along the X direction. x (or R) row and half-pitch resolution R along the Y direction y (or R) col For example, R row It can be in the range of approximately 5nm to approximately 30nm, and R col It can be in the range of approximately 5nm to approximately 30nm. In this embodiment, the width W m Equal to or greater than R row And the spacing S row Equal to or greater than R row Therefore, the spacing P m Equal to or greater than 2R row For example, the spacing P m For R row Approximately 2.0 to 2.5 times. In some embodiments, it is desirable to increase the spacing P. m The design is made as small as possible while providing sufficient process margin for the photolithography process to form patterns corresponding to all metal traces 105 in a single exposure.

[0034] In addition, the spacing S col Equal to or greater than R col And length L m Equal to or greater than R col Additionally, in one embodiment, the length L m Designed for spacing P m The length is approximately 0.45 to 0.95 times, for example, approximately 0.7 times. Such a length allows for a large number of metal traces per average unit area of ​​105.

[0035] In one embodiment, length L m and spacing S col The sum is designed to be less than or equal to the average unit height H. avg = two-thirds (2 / 3) of (H1+H2) / 2. For example, length L m and spacing S col The sum is designed as the average unit height Havg = Approximately one-half (1 / 2) to two-thirds (2 / 3) of (H1+H2) / 2. In other words:

[0036] L m +S col =a*H avg Where a is approximately 0.5 to 0.667. (Equation 2)

[0037] Since H1 equals H2 in this embodiment, the average unit height H avg Equal to H1. In one embodiment, the average cell height H avg Less than 250 nm or less than 10 times the spacing of the active region 215. Equation 2 also applies to embodiments with more than two unit cells 110. In those embodiments, the average cell height... The length and spacing shown in Equation 2 allow for the encapsulation of a large number of metal traces 105 per average cell area, providing sufficient metal trace density for wiring cells 110.

[0038] exist Figure 3 In the illustrated embodiment, three rows of metal traces 105 exist in a region directly above the two unit cells 110-1 and 110-2 and having a height equal to H1 + H2. This region is also referred to as a dual-height region. In this embodiment, four metal traces 105 exist in each row. Additionally, one row of metal traces 105 extends across the common boundary between units 110-1 and 110-2. In alternative embodiments (e.g., in...) Figure 8 In the middle), four lines of metal traces 105 can exist in the dual-height region.

[0039] exist Figure 3 In the depicted embodiment, due to the spacing P m Equal to or greater than 2R row Therefore, the metal trace 105 can be fabricated using a single patterning (i.e., a single exposure) process, thereby reducing manufacturing complexity and cost. Corresponding to Figure 3 The mask pattern of the array of metal traces 105 is contained (or included) in a single photomask used by the photolithography process. Furthermore, because the metal traces 105 are designed to be shorter than the average cell height (see Equation 2 above), many metal traces 105 can be packaged per unit cell. For example, three or more rows of metal traces 105 can be placed in a dual-height region.

[0040] Figure 3 Example vias 106 connected to some metal traces 105 are also depicted. The vias 106 are located in a via layer directly below or above the metal layer containing the metal traces 105. Some vias 106 have a width equal to or less than the metal width W. mWidth W v The spacing of the through holes 106 is equal to or greater than the metal spacing P. m Therefore, the through hole 106 can also be manufactured using a single patterning process.

[0041] Figure 3 (as well as Figures 4-9 Each of them can be considered as depicting a metal trace 105 in a manufactured semiconductor structure 100. Figure 3 (as well as Figures 4-9 Each of the figures can also be viewed as depicting a layout of the semiconductor structure 100 to be manufactured. In this case, the metal trace 105 (and the other structures in those figures) is a pattern (or layout pattern) in the layout. Through a mask manufacturing process, the layout pattern is converted into a mask pattern in a photomask. Then, through various manufacturing processes (e.g., photolithography, etching, and deposition), the mask pattern is transferred to a wafer, thereby forming the metal trace 105 in the semiconductor structure 100.

[0042] Figure 4 A top view of an array of metal traces 105 designed according to another embodiment of the present invention is shown. Figure 3 In the middle, due to the width W m and spacing S row All equal to or greater than R row Therefore, the width W m Approaching the distance P m Approximately 0.4 to 0.6 times. In Figure 4 In the middle, the width W of the metal trace 105 m Designed with spacing P m Approximately 0.55 times to approximately 0.75 times, for example, approximately 0.65 times. In this case, the width W m Lenience Figure 3 The width in the middle allows for a width of W. v Similarly, scale up to achieve better circuit performance or to provide additional process margin for via landing. Figure 4 Other aspects of the embodiments in Figure 3 Those aspects are the same as those in the embodiments.

[0043] In addition to metal trace 105 and unit 110 Figure 5 A gate structure 240 (or gate 240 or gate line 240) is also depicted. In this embodiment, the gate structure 240 extends longitudinally along the Y direction. Some gate structures 240 are coupled to active regions 215 to form NMOSFETs, PMOSFETs, or CMOSFETs. The gate structures 240 are spaced apart from each other by a pitch P along the X direction. g In one embodiment, the spacing P gIt is approximately 60nm or smaller, for example, in the range of 10nm to 60nm.

[0044] In this embodiment, the spacing P g Basically equal to the spacing P m Additionally, from a top view, each column of metal traces 105 is positioned directly above the gate structure 240. In another embodiment (not shown), from a top view, each column of metal traces 105 is not positioned directly above the gate structure 240, but rather offset from the gate structure 240. However, in both embodiments, the number of columns of metal traces 105 and the number of gate structures 240 are the same within cell 110-1 (or cell 110-2). Figure 5 Other aspects of the embodiments in Figure 3 Those aspects are the same as those in the embodiments.

[0045] Figure 6 A top view of an array of metal traces 105 designed according to another embodiment of the present invention is shown. In this embodiment, the height H1 is less than the height H2 and greater than the length L of the metal traces 105. m . Figure 6 Other aspects of the embodiments in Figure 3 Those aspects are the same as in the embodiments. For example, all metal traces 105 have the same length L. m Furthermore, three rows of metallic traces 105 exist in a region directly above the two unit cells 110-1 and 110-2 and with a height equal to H1+H2. Additionally, the second row of metallic traces 105 (starting from the top) extends across the boundary between the two unit cells 110-1 and 110-2. Furthermore, the length L... m and spacing S col The sum is designed to be less than or equal to the average unit height H. avg = two-thirds (2 / 3) of (H1+H2) / 2. For example, length and L m and spacing S col The sum is designed as the average unit height H avg = Approximately one-half (1 / 2) to two-thirds (2 / 3) of (H1+H2) / 2. In one embodiment, the average cell height H avg Less than 250nm, or less than 215nm in the active region ( Figure 6 Not shown in the text, but can be seen in Figure 3 , Figure 5 , Figure 7 The spacing is 10 times that of the distance between the two points. Additionally, the spacing P... m Equal to or greater than 2R row .

[0046] Figure 7A top view of an array of metal traces 105 designed according to another embodiment of the present invention is shown. In this embodiment, the height H1 is less than the height H2 and less than the length L of the metal traces 105. m Due to length L m The height is greater than H1, so the first row of metal traces 105 extends beyond the boundary between the two cells 110-1 and 110-2. This configuration improves the sharing of metal traces 105 between cells 110. Figure 7 Other aspects of the embodiments in Figure 3 Those aspects are the same as in the embodiments. For example, all metal traces 105 have the same length L. m Furthermore, three rows of metallic traces 105 exist in a region directly above the two unit cells 110-1 and 110-2 and with a height equal to H1+H2. Additionally, the length L... m and spacing S col The sum is designed to be less than or equal to the average unit height H. avg = two-thirds (2 / 3) of (H1+H2) / 2. For example, length and L m and spacing S col The sum is designed as the average unit height H avg = Approximately one-half (1 / 2) to two-thirds (2 / 3) of (H1+H2) / 2. In one embodiment, the average cell height H avg Less than 250nm, or less than 10 times the spacing of the active region 215. Additionally, the spacing P... m Equal to or greater than 2R row .

[0047] Figure 8 A top view of an array of metal traces 105 designed according to another embodiment of the present invention is shown. In this embodiment, all metal traces 105 have the same length L. m It is smaller than height H1 and smaller than height H2. Additionally, the length L... m and spacing S col The sum is designed as the average unit height H avg = Approximately one-half (1 / 2) of (H1+H2) / 2. In one embodiment, the average unit height H avg Less than 250nm or less than 215nm of active region Figure 8 Not shown in the text, but can be seen in Figure 3 , Figure 5 , Figure 7The spacing is 10 times that of the distance between the two heights. In this embodiment, four rows of metal traces 105 exist in the dual-height region. When heights H1 and H2 are approximately the same, two rows of metal traces 105 exist directly above each of units 110-1 and 110-2. In alternative embodiments where height H1 is less than height H2, such as... Figure 6 or Figure 7 In that case, the number of rows of metal traces 105 directly above cell 110-2 may be more than the number directly above cell 110-1. Figure 8 Other aspects of the embodiments in Figure 3 Those aspects are the same as those in the embodiments. For example, the spacing P m Equal to or greater than 2R row .

[0048] Figure 9 A top view of an array of metal traces 105 designed according to another embodiment of the present invention is shown. In this embodiment, the height H1 is less than the height H2. Three rows of metal traces 105 exist directly above the area occupied by the two cells 110-1 and 110-2. Not all metal traces 105 have the same length. In particular, each metal trace 105 in the first row (starting from the top) has a length L1. m The metal trace 105 has a length L2 in each of the other two rows. m Length L1 m The height H1 is less than the length L2m, and the length L2m is less than the height H2. Additionally, the length L1... m and spacing S col The sum is designed as the average unit height H avg = Approximately one-half (1 / 2) to two-thirds (2 / 3) of (H1+H2) / 2, and the length L2 m and spacing S col The sum is designed as the average unit height H avg = Approximately one-half (1 / 2) to two-thirds (2 / 3) of (H1+H2) / 2. In one embodiment, the average cell height H avg Less than 250nm or less than 215nm of active region Figure 9 Not shown in the text, but can be seen in Figure 3 , Figure 5 , Figure 7 The spacing is 10 times that of L1. Additionally, in one embodiment, the ratio of H1 to H2 is equal to that of L1. m and L2 m The ratios are approximately the same. This embodiment allows the length of the metal trace 105 to be adjusted based on the height of the unit 110, increasing design flexibility. Figure 9 Other aspects of the embodiments in Figure 3Those aspects are the same as in the embodiments. For example, the middle row of the metal trace 105 extends across the common boundary between cells 110-1 and 110-2, and the spacing P m Equal to or greater than 2R row .

[0049] Even if not shown, the gate structure 240 can be in Figure 3 , Figure 4 , Figure 6 , Figure 7 , Figure 8 ,and Figure 9 Each of the embodiments shown is implemented, for example, with Figure 5 The same implementation method is shown in the embodiment. Additionally, for simplicity, the active region 215 is not shown. Figure 4 , Figure 6 , Figure 8 ,and Figure 9 middle.

[0050] Figure 10 A flowchart of a method 300 for designing and manufacturing a metal trace 105 according to an embodiment of the present invention is shown. Method 300 is merely an example and is not intended to limit the invention beyond the scope expressly stated in the claims. Additional operations may be provided before, during, and after method 300, and some of the operations described may be replaced, removed, or moved for other embodiments of the method. The following is in conjunction with... Figures 3 to 9 Description method 300.

[0051] In operation 302, method 300 ( Figure 10 To obtain the resolution constraints of the target manufacturing process. For example, in photolithography, the resolution constraint may include the half-pitch resolution R along the X direction. x (or R) row and half-pitch resolution R along the Y direction y (or R) col ).

[0052] In operation 304, method 300 ( Figure 10 Obtain the trace spacing P for the metal trace 105. m For example, the spacing P m Equal to or greater than 2R row For example, R row Approximately 2.0 to 2.5 times that.

[0053] In operation 306, method 300 ( Figure 10 Obtain the trace length (or trace height) L for the metal trace 105. m In one embodiment, the length L m According to the trace spacing Pm It is determined by the average unit height. For example, the length L m Designed with spacing P m Approximately 0.4 to 0.6 times, for example, approximately 0.5 times. Additionally, the length L of the metal trace 105... m and end-to-end spacing S col The sum is designed to be less than or equal to two-thirds (2 / 3) of the average unit height. For example, length L m and spacing S col The sum is designed as the average unit height H avg Approximately one-half (1 / 2) to two-thirds (2 / 3) of the average unit height H. avg It is the average height of the unit below the metal trace 105.

[0054] In operation 308, method 300 ( Figure 10 A single mask (or photomask) is provided, comprising a mask pattern corresponding to all metal traces above at least two adjacent cells. Method 300 then uses the mask to perform a target manufacturing process to form metal traces 105 on the wafer.

[0055] While not intended to be limiting, embodiments of the invention offer one or more of the following advantages. For example, embodiments of the invention provide a semiconductor structure with an array of metal traces. The array of metal traces can be arranged above standard cells and shared between standard cells. The length and end-to-end spacing of the metal traces are scaled based on the average height of the standard cells. Therefore, a sufficient number of metal traces can be packaged per unit cell area. The spacing of the metal traces is designed so that all metal traces can be formed using a single exposure process, thereby reducing manufacturing complexity and cost. Embodiments of the invention can be easily integrated into existing semiconductor manufacturing processes.

[0056] In one example aspect, the present invention relates to a semiconductor structure. The semiconductor structure includes first and second cells arranged adjacent to each other along a column direction. Each of the first and second cells includes at least one semiconductor active region extending longitudinally along a row direction perpendicular to the column direction. The first cell has a first cell height along the column direction, and the second cell has a second cell height along the column direction. The semiconductor structure also includes an array of metal traces located above the first and second cells. The array of metal traces is arranged in rows and columns, and includes a resolution R with half-pitch along the row direction. row The photolithography process forms the manufacturing process. The first spacing of the metal traces along the row direction is greater than or equal to 2R. rowAt least three rows of metallic traces are located in an area directly above the first and second cells, and have a height equal to the sum of the heights of the first and second cells. One of the rows of metallic traces is configured to span a cell boundary shared by the first and second cells.

[0057] In one embodiment of the semiconductor structure, the height of the first cell is equal to the height of the second cell. In another embodiment, the height of the first cell is less than the height of the second cell.

[0058] In one embodiment, the semiconductor structure further includes a gate structure extending longitudinally along the column direction, wherein the second spacing of the gate structure along the row direction is substantially equal to the first spacing.

[0059] In one embodiment, the array of metal traces has the same height along the column direction. In another embodiment, the metal traces in the same column are spaced apart by column spacing, and the sum of the height of any metal trace and the column spacing is less than or equal to two-thirds of the average of the height of the first unit and the height of the second unit.

[0060] In one embodiment, one of the rows of metal traces extends directly above the first cell and has a height greater than the height of the first cell. In another embodiment, the mask pattern corresponding to the array of metal traces is included in a single photomask used in the photolithography process. In yet another embodiment, the first cell and the second cell have a common width along the row direction.

[0061] In another example aspect, the present invention relates to a semiconductor structure. The semiconductor structure includes a first cell and a second cell arranged along a column direction and sharing a cell boundary. Each of the first and second cells includes at least one of an NMOSFET, a PMOSFET, and a CMOSFET. The first cell has a first cell height along the column direction. The second cell has a second cell height along the column direction. The semiconductor structure also includes an array of metal traces located above the first and second cells. The array of metal traces is arranged in rows and columns and formed by a manufacturing process that prints a pattern corresponding to the array of metal traces using a single exposure. At least three rows of metal traces are located in a region directly above the first and second cells and have a height equal to the sum of the heights of the first and second cells.

[0062] In one embodiment of the semiconductor structure, one of the rows of metal traces is configured to span the cell boundary. In another embodiment, metal traces in the same column are spaced apart by a column pitch, and the height of any metal trace and the sum of the column pitch are in the range of one-half to two-thirds of the average of the height of the first cell and the height of the second cell.

[0063] In one embodiment, the manufacturing process has a half-pitch resolution R along the row direction perpendicular to the column direction. row And the metal traces along the first spacing in the row direction at R row The range is 2.0 to 2.5 times. In another embodiment, the array of metal traces has the same height along the column direction, and the same height is about half of the first spacing.

[0064] In another embodiment, one of the rows of metal traces extends directly above the first unit and has a height greater than the height of the first unit.

[0065] In another example, the present invention relates to an integrated circuit (IC) layout. The IC layout includes first and second cells arranged adjacent to each other along a column direction. Each of the first and second cells includes at least one active region extending longitudinally along a row direction perpendicular to the column direction. The first and second cells have a first cell height and a second cell height, respectively, along the column direction. The IC layout also includes an array of metal traces located above the first and second cells. The array of metal traces is arranged in rows and columns and includes a resolution R with a half-pitch along the row direction. row The photolithography process forms the manufacturing process. The first spacing of the metal traces along the row direction is greater than or equal to 2R. row Metal traces within the same column are spaced apart by column spacing. The sum of the height of any metal trace and the column spacing is between one-half and two-thirds of the average of the height of the first and second units.

[0066] In one embodiment of the IC layout, the first spacing is in R row The range is 2.0 to 2.5 times. In another embodiment, one of the rows of metal traces extends directly above the first unit and has a height greater than the height of the first unit.

[0067] In one embodiment, the photolithography process has a half-pitch resolution R along the column direction. col And the column spacing is greater than R col In another embodiment, the IC layout also includes gate lines extending longitudinally along the column direction, wherein the second spacing of the gate lines along the row direction is substantially equal to the first spacing.

[0068] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages as this disclosure. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor structure, comprising: A first unit and a second unit are arranged adjacent to each other along a column direction. Each of the first unit and the second unit includes at least one semiconductor active region extending longitudinally along a row direction perpendicular to the column direction. The first unit has a first unit height along the column direction, and the second unit has a second unit height along the column direction. as well as An array of metal traces is located above the first and second units, wherein the array of metal traces is arranged in rows and columns, and includes a half-pitch resolution R along the row direction. row The metal traces are formed by a photolithography process, wherein the first spacing along the row direction is greater than or equal to 2R. row At least three rows of the metal traces are located in a region directly above the first unit and the second unit and have a height equal to the sum of the heights of the first unit and the second unit, and one of the rows of the metal traces is configured to span a unit boundary shared by the first unit and the second unit.

2. The semiconductor structure according to claim 1, wherein, The height of the first unit is equal to the height of the second unit.

3. The semiconductor structure according to claim 1, wherein, The height of the first unit is smaller than the height of the second unit.

4. The semiconductor structure according to claim 1, further comprising: A gate structure extending longitudinally along the column direction, wherein a second spacing of the gate structure along the row direction is equal to the first spacing.

5. The semiconductor structure according to claim 1, wherein, The array of metal traces has the same height along the column direction.

6. The semiconductor structure according to claim 1, wherein, The metal traces in the same column are spaced apart by column spacing, and the sum of the height of any metal trace and the column spacing is less than or equal to two-thirds of the average of the height of the first unit and the height of the second unit.

7. The semiconductor structure according to claim 1, wherein, One of the rows of the metal traces extends directly above the first unit and has a height greater than the height of the first unit.

8. The semiconductor structure according to claim 1, wherein, The mask pattern corresponding to the array of metal traces is included in a single photomask used in the photolithography process.

9. The semiconductor structure according to claim 1, wherein, The first unit and the second unit have a common width along the row direction.

10. A semiconductor structure comprising: A first unit and a second unit are arranged along a column direction and share a unit boundary. Each of the first unit and the second unit includes at least one of an NMOSFET, a PMOSFET, and a CMOSFET. The first unit has a first unit height along the column direction, and the second unit has a second unit height along the column direction. as well as An array of metal traces is located above the first and second units, wherein the array of metal traces is arranged in rows and columns and formed by a manufacturing process that prints a pattern corresponding to the array of metal traces using a single exposure, the single exposure having a half-pitch resolution R along a row direction perpendicular to the column direction. row The first spacing of the metal traces along the row direction is greater than or equal to 2R. row At least three rows of the metal traces are located in a region directly above the first unit and the second unit, and have a height equal to the sum of the heights of the first unit and the second unit.

11. The semiconductor structure according to claim 10, wherein, One of the rows of the metal trace is configured to span the cell boundary.

12. The semiconductor structure according to claim 10, wherein, The metal traces in the same column are spaced apart by column spacing, and the sum of the height of any one of the metal traces and the column spacing is in the range of one-half to two-thirds of the average of the height of the first unit and the height of the second unit.

13. The semiconductor structure according to claim 10, wherein, The manufacturing process has a half-pitch resolution R along the row direction perpendicular to the column direction. row And the metal traces along the first spacing in the row direction at R row The range is 2.0 to 2.5 times.

14. The semiconductor structure according to claim 13, wherein, The array of metal traces has the same height along the column direction, and the same height is half of the first spacing.

15. The semiconductor structure according to claim 10, wherein, One of the rows of the metal traces extends directly above the first unit and has a height greater than the height of the first unit.

16. An integrated circuit layout, comprising: The first unit and the second unit are arranged adjacent to each other along the column direction. Each of the first unit and the second unit includes at least one active area extending longitudinally along the row direction perpendicular to the column direction. The first unit and the second unit have a first unit height and a second unit height, respectively, along the column direction. as well as An array of metal traces is located above the first and second units, wherein the array of metal traces is arranged in rows and columns, and includes a half-pitch resolution R along the row direction. row The metal traces are formed by a photolithography process, wherein the first spacing along the row direction is greater than or equal to 2R. row The metal traces in the same column are spaced apart by column spacing, and the sum of the height of any metal trace and the column spacing is in the range of one-half to two-thirds of the average of the height of the first unit and the height of the second unit.

17. The integrated circuit layout according to claim 16, wherein, The first spacing is in R row The range is 2.0 to 2.5 times.

18. The integrated circuit layout according to claim 16, wherein, One of the rows of the metal traces extends directly above the first unit and has a height greater than the height of the first unit.

19. The integrated circuit layout according to claim 16, wherein, The photolithography process has a half-pitch resolution R along the column direction. col And the column spacing is greater than R col .

20. The integrated circuit layout according to claim 16, further comprising: Gate lines extend longitudinally along the column direction, wherein the second spacing of the gate lines along the row direction is equal to the first spacing.

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