An active device chip

Abstract

This invention provides an active device chip, comprising a substrate, active devices, and metal interconnects. Each active device includes multiple transistors. The metal interconnects include a first metal interconnect, a second metal interconnect, and a third metal interconnect. The substrate has a center point, through which external circuitry provides power and signal transmission to the active device chip. All active devices are radially distributed around the center point, with each active device equidistant from the center point and arranged at equal intervals. Each RF input terminal extends to the center point via a first metal interconnect of equal length. Each RF output terminal extends to the center point via a second metal interconnect of equal length. Each bias voltage feed point extends to the center point via a third metal interconnect of equal length. Compared with related technologies, the power amplifier using the active device chip of this invention has higher efficiency.

Description

Technical Field

[0001] This invention relates to the field of chip layout technology, and more particularly to an active device chip. Background Technology

[0002] With the rapid development of wireless communication technology, radio frequency (RF) power amplifiers need to emit higher power while achieving higher efficiency. Among them, the active components of the RF power amplifier are an important part of the chip.

[0003] In related technologies, the active components of RF power amplifiers typically use multiple transistors connected in parallel to increase output power. Please refer to [reference needed]. Figure 1 As shown, Figure 1 This is a schematic diagram of the chip layout for the related technology. The active device consists of 36 transistors connected in parallel, arranged in 6 rows and 6 columns. This arrangement can effectively utilize the chip area.

[0004] However, in the active devices of related chips, for each transistor, due to the non-central symmetry of their arrangement with respect to the DC bias feed point, or the different distances between each transistor and the DC bias feed point Vb, the parasitic resistance generated on the transmission line connected to the transistor's base causes a certain difference in the base voltage received by each transistor, resulting in non-identical operating states for each transistor. Furthermore, for radio frequency signals, the flow of radio frequency current through the base and collector of the transistors generates phase differences between transistors in different rows and columns, for example... Figure 1 The base input current I of each column is indicated in the middle. b1 I b2 I b3 and I b4 and collector output current I C1 I C2 and I C3 There is a certain phase difference between them. Therefore, during power combining, phase misalignment occurs, which reduces the efficiency of the RF power amplifier in the chip.

[0005] Therefore, it is necessary to provide a new chip to solve the above problems. Summary of the Invention

[0006] To address the shortcomings of the existing technologies, this invention proposes a high-efficiency active device chip for power amplifiers.

[0007] To address the aforementioned technical problems, embodiments of the present invention provide an active device chip, comprising a substrate and a plurality of active devices and metal interconnects respectively disposed on the substrate. Each active device includes a plurality of transistors, which are connected in parallel to form a radio frequency (RF) input terminal, an RF output terminal, and a bias voltage feed point of the active device. The metal interconnects include a first metal interconnect, a second metal interconnect, and a third metal interconnect disposed on different layers and isolated from each other. The substrate has a center point, through which external circuitry provides power and signal transmission to the active device chip. All active devices are radially distributed with the center point as the center, and each active device is equidistant from the center point and arranged at equal intervals. Each RF input terminal extends to the center point through a first metal interconnect of the same length. Each RF output terminal extends to the center point through a second metal interconnect of the same length. Each bias voltage feed point extends to the center point through a third metal interconnect of the same length.

[0008] Preferably, the transistor is a bipolar junction transistor (BJT). The collectors of all the BJTs in the same active device are interconnected and serve as the radio frequency (RF) input terminal. The emitters of all the BJTs in the same active device are interconnected and serve as the RF output terminal. The bases of all the BJTs in the same active device are interconnected and serve as the bias voltage feed point.

[0009] Preferably, there are M active devices, where M ≥ 3 and M is a positive integer; each active device includes N transistors, where N ≥ 2 and N is an even number.

[0010] Preferably, the number M of active devices in the active device chip is determined based on the total number S of transistors, and satisfies the following formula:

[0011] M*N=S.

[0012] Preferably, the total number of transistors S = 36, the number of active devices M = 6, and each active device includes N = 6 transistors; the six active devices are distributed in an equilateral hexagon with the center point as the center.

[0013] Preferably, the six transistors of each active device are arranged in a matrix of 3 rows and 2 columns.

[0014] Preferably, the transistor is a MOS transistor, the sources of all the MOS transistors in the same active device are interconnected and serve as the RF input terminal, the drains of all the MOS transistors in the same active device are interconnected and serve as the RF output terminal, and the gates of all the MOS transistors in the same active device are interconnected and serve as the bias voltage feed point.

[0015] Preferably, the width of the third metal connection is greater than the width of the first metal connection and the width of the second metal connection.

[0016] Preferably, the width of the second metal connection is greater than the width of the first metal connection.

[0017] Compared with related technologies, the active device chip of the present invention sets a center point on the substrate, and then distributes all active devices radially around the center point. Each active device is equidistant from the center point and is arranged at equal intervals. Each RF input terminal extends to the center point via a first metal interconnect of equal length; each RF output terminal extends to the center point via a second metal interconnect of equal length; and each bias voltage feed point extends to the center point via a third metal interconnect of equal length. This structure ensures that all active devices in the active device chip of the present invention are centrally symmetrically distributed around the center point. Therefore, the distance between the bias voltage feed point of each active device and the center point is equal, greatly reducing the differences in state between different active devices. Furthermore, when the RF current flows through each active device, the length of each first metal interconnect, each second metal interconnect, and each third metal interconnect is the same, avoiding the phase difference problem of RF current between different transistors in the layout of related technology chips. Therefore, the difference in operating state between each active device in the active device chip can be greatly reduced, and the phase difference generated when the radio frequency current flows through each active device can be greatly reduced, so that the output power of each active device is more in phase, thereby making the power amplifier of the active device chip of the present invention highly efficient. Attached Figure Description

[0018] The present invention will now be described in detail with reference to the accompanying drawings. The above and other aspects of the present invention will become clearer and more readily understood through the detailed description following the accompanying drawings. In the drawings,

[0019] Figure 1 This is a schematic diagram of the chip layout for related technologies;

[0020] Figure 2 This is a schematic diagram of the layout of the active device chip of the present invention. Detailed Implementation

[0021] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0022] The specific embodiments / examples described herein are specific implementations of the present invention, used to illustrate the concept of the invention, and are illustrative and exemplary, and should not be construed as limiting the implementation methods or scope of the present invention. In addition to the embodiments described herein, those skilled in the art can employ other obvious technical solutions based on the content disclosed in the claims and specification of this application. These technical solutions include those that make any obvious substitutions and modifications to the embodiments described herein, all of which are within the protection scope of the present invention.

[0023] This invention provides an active device chip 100.

[0024] Please refer to Figure 2 As shown, Figure 2 This is a schematic diagram of the circuit structure of the active device chip 100 in the related technology.

[0025] Specifically, the active device chip 100 includes a substrate 1 and a plurality of active devices 2 and metal interconnects 3 respectively disposed on the substrate 1.

[0026] The substrate 1 supports the structure of the active device chip 100. The substrate 1 has a center point A. External circuitry provides power and signal transmission to the active device chip 100 through the position of the center point A. All active devices 2 are radially distributed with the center point A as the center, and each active device 2 is equidistant from the center point A and arranged at equal intervals. This structure ensures that all active devices 2 of the active device chip 100 are centrally symmetrically distributed with the center point A as the center, which can significantly reduce the difference in operating state between each active device 2 in the active device chip 100, and also significantly reduce the phase difference generated when the radio frequency current flows through each active device 2.

[0027] Specifically, each of the active devices 2 includes a plurality of transistors 21.

[0028] Multiple transistors 21 are connected in parallel to form the RF input terminal 22, RF output terminal 23, and bias voltage feed point 24 of the active device 2.

[0029] In this embodiment, transistor 21 is a bipolar transistor. The collectors of all the bipolar transistors in the same active device 2 are interconnected and serve as the radio frequency input terminal 22. The emitters of all the bipolar transistors in the same active device 2 are interconnected and serve as the radio frequency output terminal 23. The bases of all the bipolar transistors in the same active device 2 are interconnected and serve as the bias voltage feed point 24.

[0030] Of course, this is not the only embodiment. In another embodiment, the transistor 21 is a MOS transistor. The sources of all the MOS transistors in the same active device 2 are interconnected and serve as the RF input terminal 22. The drains of all the MOS transistors in the same active device 2 are interconnected and serve as the RF output terminal 23. The gates of all the MOS transistors in the same active device 2 are interconnected and serve as the bias voltage feed point 24.

[0031] In this embodiment, the transistor 21 further includes a ballast resistor and a DC blocking capacitor disposed on the transistor.

[0032] The metal interconnect 3 includes a first metal interconnect 31, a second metal interconnect 32 and a third metal interconnect 33 respectively disposed on different layers and isolated from each other.

[0033] Each of the RF input terminals 22 extends to the center point A via a first metal interconnect 31 of the same length. Each of the RF output terminals 23 extends to the center point A via a second metal interconnect 32 of the same length. Each of the bias voltage feed points 24 extends to the center point A via a third metal interconnect 33 of the same length. This structure ensures that the distance between the bias voltage feed point 24 of each active device 2 and the center point A is equal, thereby greatly reducing the state differences between different active devices 2. In addition, when the RF current flows through each active device 2, it passes through each first metal 22 for the same length, each second metal 23 for the same length, and each third metal 24 for the same length, thus avoiding the phase difference problem of RF current between different transistors in the chip layout of related technologies. Therefore, the difference in operating state between each active device 2 in the active device chip 100 can be greatly reduced, and the phase difference generated when the radio frequency current flows through each active device 2 can be greatly reduced, so that the output power of each active device 2 is more in phase, thereby making the power amplifier of the active device chip 100 of the present invention highly efficient.

[0034] The number of active devices 2 is M. M ≥ 3 and M is a positive integer.

[0035] Each of the active devices 2 comprises N transistors 21. N ≥ 2 and N is an even number.

[0036] Multiple active devices 2 are connected to form an RF power amplifier 4. The number M of active devices 2 in the active device chip 100 is determined according to the total number S of transistors 21, and satisfies the following formula:

[0037] M*N=S.

[0038] In this embodiment, the total number of transistors 21 is S = 36, the number of active devices 2 is M = 6, and each active device 2 includes N = 6 transistors 21. The six active devices 2 are arranged in an equilateral hexagon with the center point A as the center. Specifically, the six transistors 21 of each active device 2 are arranged in a 3x2 matrix. This structure is easy to implement, occupies a small layout area, and ensures that the distances between the bias voltage feed points 24 of the six active devices 2 and the center point A are equal, the distances between the RF input terminals 22 of the six active devices 2 and the center point A are equal, and the distances between the RF output terminals 23 of the six active devices 2 and the center point A are equal.

[0039] In this embodiment, the width of the third metal interconnect 33 is greater than the width of the first metal interconnect 31 and the width of the second metal interconnect 32. This structure results in low resistance of the RF current flowing through the base of the transistor 21, making it easier to ensure that the distance between the bias voltage feed point 24 of the active device 2 and the center point A is equal.

[0040] In this embodiment, the width of the second metal interconnect 32 is greater than the width of the first metal interconnect 31. This structure facilitates the entry of the transistor 21 into the working state, thereby improving reliability.

[0041] It should be noted that the transistors, capacitors, resistors and power amplifiers used in this invention are all commonly used components in the field. The specific indicators and parameters are adjusted according to the actual application, and will not be described in detail here.

[0042] Compared with related technologies, the active device chip of the present invention sets a center point on the substrate, and then distributes all active devices radially around the center point. Each active device is equidistant from the center point and is arranged at equal intervals. Each RF input terminal extends to the center point via a first metal interconnect of equal length; each RF output terminal extends to the center point via a second metal interconnect of equal length; and each bias voltage feed point extends to the center point via a third metal interconnect of equal length. This structure ensures that all active devices in the active device chip of the present invention are centrally symmetrically distributed around the center point. Therefore, the distance between the bias voltage feed point of each active device and the center point is equal, greatly reducing the differences in state between different active devices. Furthermore, when the RF current flows through each active device, the length of each first metal interconnect, each second metal interconnect, and each third metal interconnect is the same, avoiding the phase difference problem of RF current between different transistors in the layout of related technology chips. Therefore, the difference in operating state between each active device in the active device chip can be greatly reduced, and the phase difference generated when the radio frequency current flows through each active device can be greatly reduced, so that the output power of each active device is more in phase, thereby making the power amplifier of the active device chip of the present invention highly efficient.

[0043] It should be noted that the various embodiments described above with reference to the accompanying drawings are merely illustrative of the present invention and not intended to limit its scope. Those skilled in the art should understand that any modifications or equivalent substitutions made to the present invention without departing from its spirit and scope should be included within the scope of the present invention. Furthermore, unless the context otherwise requires, words appearing in the singular include those in the plural, and vice versa. Additionally, unless specifically stated otherwise, all or part of any embodiment may be used in conjunction with all or part of any other embodiment.

Claims

1. An active device chip, comprising a substrate and a plurality of active devices and metal interconnects respectively disposed on the substrate, each active device comprising a plurality of transistors, the plurality of transistors being arranged in parallel to form a radio frequency input terminal, a radio frequency output terminal, and a bias voltage feed point of the active device; the metal interconnects comprising a first metal interconnect, a second metal interconnect, and a third metal interconnect respectively disposed on different layers and isolated from each other; characterized in that, The substrate has a center point, through which the external circuit provides power and signal transmission to the active device chip; all the active devices are radially distributed with the center point as the center, and the distance from each active device to the center point is the same and the active devices are arranged at equal intervals. Each of the radio frequency input terminals extends to the center point via the first metal wire of the same length. Each of the aforementioned radio frequency output terminals extends to the center point via a second metal wire of the same length. Each of the bias voltage feed points extends to the center point via the third metal connection of the same length.

2. The active device chip according to claim 1, characterized in that, The transistor is a bipolar junction transistor (BJT). The collectors of all the BJTs in the same active device are interconnected and serve as the radio frequency (RF) input terminal. The emitters of all the BJTs in the same active device are interconnected and serve as the RF output terminal. The bases of all the BJTs in the same active device are interconnected and serve as the bias voltage feed point.

3. The active device chip of claim 1, wherein, The number of active devices is M, where M ≥ 3 and M is a positive integer; Each of the active devices comprises N transistors, where N ≥ 2 and N is an even number.

4. The active device chip of claim 3, wherein, The number M of active devices in the active device chip is determined based on the total number S of transistors, and satisfies the following formula: M*N=S.

5. The active device chip of claim 4, wherein, The total number of transistors S = 36, the number of active devices M = 6, and the number of transistors in each active device N = 6; the six active devices are distributed in an equilateral hexagon with the center point as the center.

6. The active device chip of claim 5, wherein, The six transistors of each active device are arranged in a 3x2 matrix.

7. The active device chip of claim 1, wherein, The transistor is a MOS transistor. The sources of all the MOS transistors in the same active device are interconnected and serve as the radio frequency input terminal. The drains of all the MOS transistors in the same active device are interconnected and serve as the radio frequency output terminal. The gates of all the MOS transistors in the same active device are interconnected and serve as the bias voltage feed point.

8. The active device chip of claim 1, wherein, The width of the third metal connection is greater than the width of the first metal connection and the width of the second metal connection.

9. The active device chip of claim 8, wherein, The width of the second metal connection is greater than the width of the first metal connection.

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