Display device

Abstract

The present invention provides a display device comprising: a first transistor having an oxide semiconductor layer, a gate wiring, and a gate insulating layer; at least one first insulating layer disposed on the first transistor, having a first contact hole disposed outside the gate wiring; a planarization film disposed on the first insulating layer, having a second contact hole overlapping the first contact hole; a first transparent conductive layer disposed on the planarization film, including a region overlapping the gate wiring; a second insulating layer disposed on the first transparent conductive layer, covering the side of the second contact hole; a second transparent conductive layer disposed on the second insulating layer, contacting the oxide semiconductor layer through the first and second contact holes; a first resin disposed on the second transparent conductive layer, filling the interior of the first and second contact holes; and a third transparent conductive layer disposed on the second transparent conductive layer and the first resin.

Description

Technical Field

[0001] One embodiment of the present invention relates to a display device. In particular, one embodiment of the present invention relates to a display device using transistors having an oxide semiconductor structure. Background Technology

[0002] Conventionally, display devices are known to have a configuration in which a transistor using low-temperature polysilicon (LTPS) as the channel is incorporated within the pixel circuit of each pixel. Furthermore, in this display device, the pixel electrode is formed of a light-transmitting conductive film. However, if the LPS is simply directly connected to the light-transmitting pixel electrode, the connection resistance becomes high, making it difficult to achieve the desired result. Therefore, the LPS needs to be connected to the pixel electrode via a conductive metal layer. However, depending on the location of the conductive metal layer, this can be a major cause of a decrease in the pixel aperture ratio.

[0003] Furthermore, in recent years, with the increasing sophistication of display devices, there has been a push towards miniaturization of pixel sizes. As pixel sizes shrink, it is desirable for wiring widths and transistor sizes to also decrease, but designing them to be smaller in line with pixel miniaturization is not easy. As a result, the area occupied by wiring and transistors within a pixel becomes relatively larger, ultimately leading to a smaller aperture ratio for each pixel.

[0004] Therefore, the development of transistors using an oxide semiconductor layer in the channel for pixel circuits is underway. This oxide semiconductor layer can achieve characteristics sufficient to drive pixel circuits even with a small transistor size (e.g., Japanese Patent Application Laid-Open Nos. 2014-146819 and 2015-159315). In such a display device, the pixel electrode, which serves as a transparent conductive layer, can be directly connected to the oxide semiconductor layer through contact holes, eliminating the need for a metal layer for connection. Therefore, the reduction in aperture ratio can be suppressed.

[0005] Existing technical documents

[0006] Patent documents

[0007] Patent Document 1: Japanese Patent Application Publication No. 2014-146819

[0008] Patent Document 2: Japanese Patent Application Publication No. 2015-159315 Summary of the Invention

[0009] The technical problem that the invention aims to solve

[0010] However, even in transistors that use an oxide semiconductor layer in the channel for pixel circuits, if the unevenness caused by the aforementioned contact holes and the like becomes significant in each pixel region, it is difficult to control the liquid crystal molecules within that unevenness. Ultimately, this will hinder the improvement of the pixel aperture ratio (transmittance).

[0011] One of the objectives of one embodiment of the present invention is to increase the aperture ratio in miniaturized pixels in a display device.

[0012] Solutions for solving technical problems

[0013] An embodiment of the present invention relates to a display device comprising: a first transistor having an oxide semiconductor layer, a gate wiring opposite to the oxide semiconductor layer, and a gate insulating layer between the oxide semiconductor layer and the gate wiring; at least one first insulating layer disposed on the first transistor, having a first contact hole disposed outside the gate wiring; a planarization film disposed on the first insulating layer, having a second contact hole overlapping the first contact hole; a first transparent conductive layer disposed on the planarization film, including a region overlapping the gate wiring; a second insulating layer disposed on the first transparent conductive layer, covering the side of the second contact hole; a second transparent conductive layer disposed on the second insulating layer, contacting the oxide semiconductor layer through the first contact hole and the second contact hole; a first resin disposed on the second transparent conductive layer, filling the interior of the first contact hole and the second contact hole; and a third transparent conductive layer disposed on the second transparent conductive layer and the first resin. Attached Figure Description

[0014] Figure 1 This is a cross-sectional view showing an outline of a display device according to an embodiment of the present invention.

[0015] Figure 2 This is a top view showing an outline of a display device according to an embodiment of the present invention.

[0016] Figure 3 This is a top view illustrating the layout of each layer in a display device according to an embodiment of the present invention.

[0017] Figure 4 This is a top view illustrating the layout of each layer in a display device according to an embodiment of the present invention.

[0018] Figure 5 This is a top view illustrating the layout of each layer in a display device according to an embodiment of the present invention.

[0019] Figure 6 This is a top view illustrating the layout of each layer in a display device according to an embodiment of the present invention.

[0020] Figure 7 This is a top view illustrating the layout of each layer in a display device according to an embodiment of the present invention.

[0021] Figure 8 This is a top view illustrating the layout of each layer in a display device according to an embodiment of the present invention.

[0022] Figure 9 This is a top view illustrating the layout of each layer in a display device according to an embodiment of the present invention.

[0023] Figure 10 This is a top view illustrating the layout of each layer in a display device according to an embodiment of the present invention.

[0024] Figure 11 This is a top view illustrating the layout of each layer in a display device according to an embodiment of the present invention.

[0025] Figure 12 This is a top view illustrating the layout of each layer in a display device according to an embodiment of the present invention.

[0026] Figure 13 This is a top view illustrating the layout of each layer in a display device according to an embodiment of the present invention.

[0027] Figure 14 This is a top view illustrating the layout of each layer in a display device according to an embodiment of the present invention.

[0028] Figure 15 This is a top view illustrating the layout of each layer in a display device according to an embodiment of the present invention.

[0029] Figure 16 This is a top view illustrating the layout of each layer in a display device according to an embodiment of the present invention.

[0030] Figure 17 This is a top view showing an outline of a display device according to an embodiment of the present invention.

[0031] Figure 18 This is a block diagram illustrating the circuit configuration of a display device according to an embodiment of the present invention.

[0032] Figure 19 This is a circuit diagram illustrating the pixel circuit of a display device according to an embodiment of the present invention. Detailed Implementation

[0033] The various embodiments of the present invention will now be described with reference to the accompanying drawings. The following disclosure is merely illustrative. Configurations readily conceived by those skilled in the art, while maintaining the spirit of the invention, through appropriate modifications to the embodiments, are of course included within the scope of the invention. For clarity, the drawings may sometimes schematically represent the width, thickness, shape, etc., of various parts compared to the actual embodiments. However, the shapes illustrated are merely examples and do not limit the interpretation of the invention. In this specification and the drawings, for elements identical to those described in previously presented drawings, letters may be appended after the same reference numerals, and detailed descriptions may be appropriately omitted.

[0034] In various embodiments of the present invention, the direction from the substrate toward the oxide semiconductor layer is referred to as "up" or "above". Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as "down" or "below". For ease of explanation, the terms "up" or "below" are used, but for example, the substrate and oxide semiconductor layer may be arranged in a manner opposite to the illustration. In the following description, the phrase "e.g., oxide semiconductor layer on the substrate" is used only to describe the vertical relationship between the substrate and oxide semiconductor layer as described above; other components may also be arranged between the substrate and oxide semiconductor layer. "Up" or "below" refers to the stacking order in a structure with multiple layers. When described as a pixel electrode above a transistor, it may also refer to the non-overlapping position of the transistor and pixel electrode when viewed from above. On the other hand, when described as a pixel electrode vertically above a transistor, it refers to the overlapping position of the transistor and pixel electrode when viewed from above.

[0035] "Display device" refers to a structure that displays images using an electro-optic layer. For example, the term "display device" sometimes refers to a display panel that includes an electro-optic layer, or sometimes to a structure on which other optical components (e.g., polarizing components, backlights, touch panels, etc.) are mounted to the display unit. The "electro-optic layer" can include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, or an electrophoretic layer, provided there is no technical inconsistency. Therefore, in the embodiments described later, a liquid crystal display device including a liquid crystal layer will be used as an example, but the structure in this embodiment can be applied to display devices including other electro-optic layers mentioned above.

[0036] In this specification, statements such as "α includes A, B, or C," "α includes any one of A, B, and C," and "α includes one of the groups selected from A, B, and C," unless otherwise expressly stated, do not exclude the possibility that α includes multiple combinations of A to C. Furthermore, these statements do not exclude the possibility that α includes other elements.

[0037] It should be noted that the following implementation methods can be combined with each other as long as there is no technical contradiction.

[0038] [1. First Implementation Method]

[0039] [1-1. Configuration of the display device 10]

[0040] use Figures 1 to 16 The configuration of a display device 10 according to an embodiment of the present invention will be described. Figure 1 This is a cross-sectional view showing an outline of a display device according to an embodiment of the present invention.

[0041] like Figure 1 As shown, the display device 10 includes a substrate SUB, transistors Tr1 and Tr2, wiring W, pixel electrodes PTCO1 and PTCO2, a common auxiliary electrode CMTL, a common electrode CTCO1, and a common electrode CTCO2. It should be noted that TCO is short for Transparent Conductive Oxide. Transistor Tr1 is a transistor included in the pixel circuit of the display device 10. Transistor Tr2 is a transistor included in the peripheral circuit. The peripheral circuit is the circuit that drives the pixel circuit; details will be described later. Figure 1 The cross-sectional view is a diagram used to illustrate the layer structure of the display device 10, showing that the peripheral circuitry and pixel circuitry are adjacent. In fact, the pixel circuitry is disposed within the display area, and the peripheral circuitry is disposed in the border area outside the display area; it is self-evident that these circuits are disposed separately from each other. The display area refers to the area where pixels form an image, that is, the area where the user can visually perceive the light from the pixels. Furthermore, especially... Figure 1 In the pixel circuit, the diagram is shown centered on the periphery of the contact hole in the pixel region. Only a portion of the transmissive area (opening area) within the pixel region, which actually contributes to the display, is shown. It should be noted that for this transmissive area, in... Figure 2 As shown in the image.

[0042] [1-2. Structure of transistor Tr1]

[0043] Transistor Tr1 has an oxide semiconductor layer OS, a gate insulating layer GI1, and a gate electrode GL1 (also called a gate wiring). The gate electrode GL1 is opposite to the oxide semiconductor layer OS. The gate insulating layer GI1 is disposed between the oxide semiconductor layer OS and the gate electrode GL1. In this embodiment, a top-gate transistor is shown with the oxide semiconductor layer OS disposed on the substrate SUB side of the gate electrode GL1, but a bottom-gate transistor with the gate electrode GL1 and the oxide semiconductor layer OS in the opposite positional relationship can also be used.

[0044] The oxide semiconductor layer OS includes oxide semiconductor layers OS1 and OS2. Oxide semiconductor layer OS1 is the region of the oxide semiconductor layer that overlaps with the gate electrode GL1 when viewed from above. Oxide semiconductor layer OS1 functions as a semiconductor layer, switching between a conducting and non-conducting state depending on the voltage supplied to the gate electrode GL1. That is, oxide semiconductor layer OS1 functions as the channel of transistor Tr1. Oxide semiconductor layer OS2 functions as a conductive layer. Oxide semiconductor layers OS1 and OS2 are layers formed from the same oxide semiconductor layer. For example, oxide semiconductor layer OS2 is an oxide semiconductor layer whose resistance is reduced by doping impurities into a layer with the same physical properties as oxide semiconductor layer OS1.

[0045] An insulating layer IL2 is disposed on the gate electrode GL1. A wiring W1 is disposed on the insulating layer IL2. The wiring W1 is connected to the oxide semiconductor layer OS2 through an opening WCON (also called a contact hole) disposed on the insulating layer IL2 and the gate insulating layer GI1. The area in the oxide semiconductor layer OS2 that contacts the wiring W1 is called the second contact area CON2. The wiring W1 contacts the oxide semiconductor layer OS2 in the second contact area CON2 that does not overlap with the gate electrode GL1 when viewed from above. Data signals related to the grayscale of the pixel are transmitted to the wiring W1. An insulating layer IL3 is disposed on the insulating layer IL2 and the wiring W1. An opening ACON (first contact hole) is disposed on the gate insulating layer GI1, the insulating layer IL2, and the insulating layer IL3.

[0046] An insulating layer IL4 is disposed on the insulating layer IL3. The insulating layer IL4 softens the steps formed by the structure disposed in the layer below the insulating layer IL4. The insulating layer IL4 is sometimes referred to as a planarization film. An opening PCON (also called a second contact hole) is disposed on the insulating layer IL4. The opening PCON is disposed at a position that does not overlap with the gate electrode GL1. A common auxiliary electrode CMTL is disposed on the insulating layer IL4. A common electrode CTCO1 is disposed on the common auxiliary electrode CMTL. The common auxiliary electrode CMTL and the common electrode CTCO1 have different planar patterns, which will be described in detail later. The common auxiliary electrode CMTL is a metal layer. The resistance of the common auxiliary electrode CMTL is lower than that of the common electrode CTCO1. In addition, the common auxiliary electrode CMTL also functions as a light-shielding layer, for example, by blocking light from adjacent pixels, color mixing can be suppressed.

[0047] An insulating layer IL5 is provided on the common electrode CTCO1. The insulating layer IL5 is also provided on the sidewall of the opening PCON, which is located within the insulating layer IL4. The pixel electrode PTCO1 reaches the oxide semiconductor layer OS2 through the openings ACON provided in the gate insulating layer GI1, insulating layers IL2 and IL3, and the peripheral wall of the opening PCON provided in the insulating layer IL4, and is in direct contact with the oxide semiconductor layer OS2. The opening ACON is located inside the opening PCON. The pixel electrode PTCO1 is in contact with the sidewalls of the insulating layers IL5, IL2, and IL3, and the sidewall of the gate insulating layer GI1, all located on the sidewall of the opening PCON. The area where the pixel electrode PTCO1 contacts the oxide semiconductor layer OS2 is referred to as the first contact area CON1.

[0048] Here, for example, if a transparent conductive layer such as an ITO layer is formed in contact with a semiconductor layer such as a silicon layer, the surface of the semiconductor layer will be oxidized by the process gas and oxygen ions during ITO film formation. Since the oxide layer formed on the surface of the semiconductor layer has high resistance, the contact resistance between the semiconductor layer and the transparent conductive layer becomes high, resulting in poor electrical contact between the two. On the other hand, even if the transparent conductive layer is formed in contact with an oxide semiconductor layer, a high-resistivity oxide layer as described above will not form on the surface of the oxide semiconductor layer, so poor electrical contact will not occur between the oxide semiconductor layer and the transparent conductive layer.

[0049] In the display device 10, the oxide semiconductor layer OS can be directly connected to the pixel electrode PTCO1. It is not necessary to connect the oxide semiconductor layer OS to the pixel electrode PTCO1 through a conductive metal layer. Therefore, the aperture ratio of the pixels can be improved.

[0050] The peripheral walls of openings ACON and PCON are covered by pixel electrode PTCO1 and filled with resin layer LEV. It should be noted that pixel electrode PTCO1 does not need to completely cover the peripheral walls of openings ACON and PCON; it can cover at least a portion. By using resin layer LEV to fill openings ACON and PCON on pixel electrode PTCO1, the steps formed by openings ACON and PCON can be mitigated. Furthermore, the surface of pixel electrode PTCO2 disposed on pixel electrode PTCO1 can be planarized, thus stabilizing the switching of liquid crystal molecules. Moreover, unevenness in the thickness of insulating layer IL6 disposed on pixel electrode PTCO2 can be suppressed, resulting in uniform coating. Additionally, by using a light-transmitting resin as resin layer LEV, the transmittance loss at openings PCON and ACON can be reduced, thus improving transmittance. In addition, by making the material of the resin layer LEV the same as that of the insulating layer IL4, or by making the refractive index of the resin layer LEV approximately the same as that of the insulating layer IL4, the loss of light transmittance caused by the difference in refractive index between the resin layer LEV and the insulating layer IL4 can be reduced.

[0051] A pixel electrode PTCO2 is disposed on a pixel electrode PTCO1 and a resin layer LEV. Pixel electrode PTCO2 is in contact with pixel electrode PTCO1. An insulating layer IL6 is disposed on pixel electrode PTCO2. A common electrode CTCO2 is disposed on insulating layer IL6. A holding capacitor Cs1 can be formed by a common auxiliary electrode CMTL, a common electrode CTCO1, an insulating layer IL5, pixel electrodes PTCO1 and PTCO2.

[0052] A common electrode CTCO2 is disposed on the insulating layer IL6. The common electrode CTCO2 is a transparent conductive layer. The common electrode CTCO2 is disposed throughout the entire display area, with a portion having an opening OP (in... Figure 1 (Not shown in the diagram). Furthermore, a holding capacitor Cs2 can be formed by the common electrode CTCO2, the insulating layer IL6, and the pixel electrodes PTCO1 and PTCO2. When viewed from above, the common electrode CTCO2 has an area overlapping with the common electrode CTCO1. Additionally, the common electrode CTCO2 is electrically connected to the common electrode CTCO1 in its peripheral region.

[0053] A spacer SP is provided on the common electrode CTCO2. The spacer SP is located in the area overlapping with the common auxiliary electrode CMTL, the common electrode CTCO1, the pixel electrodes PTCO1, PTCO2, and the common electrode CTCO2.

[0054] The spacer SP is set for a subset of pixels. For example, the spacer SP can be set for any one of the blue, red, and green pixels. However, the spacer SP can also be set on all pixels. The height of the spacer SP is half the height of the cell gap. It should be noted that spacers are also set on the opposing substrate, and the spacers on the opposing substrate overlap with the aforementioned spacers SP when viewed from above.

[0055] A light-shielding layer LS is provided between transistor Tr1 and substrate SUB. In this embodiment, light-shielding layers LS1 and LS2 are provided as light-shielding layers LS. However, the light-shielding layer LS may be formed only by light-shielding layer LS1 or only by light-shielding layer LS2. When viewed from above, the light-shielding layer LS is provided in the region where gate electrode GL1 overlaps with oxide semiconductor layer OS. That is, when viewed from above, the light-shielding layer LS is provided in the region where it overlaps with oxide semiconductor layer OS1. The light-shielding layer LS suppresses light incident from the substrate SUB side from reaching oxide semiconductor layer OS1. When a conductive layer is used as light-shielding layer LS, a voltage can also be applied to light-shielding layer LS to control oxide semiconductor layer OS1. When a voltage is applied to light-shielding layer LS, light-shielding layer LS and gate electrode GL1 can also be connected in the peripheral region of pixel circuit. It should be noted that when viewed from above, the aforementioned second contact region CON2 and first contact region CON1 are provided in regions that do not overlap with light-shielding layer LS and gate electrode GL1. In addition, when viewed from above, the spacer SP overlaps with the gate electrode GL1 and the light-shielding layer LS1.

[0056] [1-3. Structure of transistor Tr2]

[0057] Transistor Tr2 has a p-type transistor Tr2-1 and an n-type transistor Tr2-2.

[0058] Both the p-type transistor Tr2-1 and the n-type transistor Tr2-2 have a gate electrode GL2 (also called a gate wiring), a gate insulating layer GI2, and a semiconductor layer S. The gate electrode GL2 is opposite to the semiconductor layer S. The gate insulating layer GI2 is disposed between the semiconductor layer S and the gate electrode GL2. In this embodiment, a bottom-gate transistor is shown with the gate electrode GL2 disposed on the substrate SUB side of the semiconductor layer S, but a top-gate transistor with the opposite positional relationship between the semiconductor layer S and the gate electrode GL2 can also be used.

[0059] The semiconductor layer S of the p-type transistor Tr2-1 includes semiconductor regions S1 and S2. The semiconductor layer S of the n-type transistor Tr2-2 includes semiconductor regions S1, S2, and S3. Semiconductor region S1 is the region that overlaps with the gate electrode GL2 when viewed from above. Semiconductor region S1 functions as the channel of transistor Tr2-1. Semiconductor region S2 functions as a conductor. Semiconductor region S3 functions as a conductor with higher resistance than semiconductor region S2. Semiconductor region S3 suppresses hot carrier degradation by attenuating hot carriers entering semiconductor region S1.

[0060] An insulating layer IL1 and a gate insulating layer GI1 are disposed on the semiconductor layer S. In transistor Tr2, the gate insulating layer GI1 functions only as an interlayer film. A wiring W2 is disposed on these insulating layers. The wiring W2 is connected to the semiconductor layer S through openings in the insulating layers IL1 and GI1. An insulating layer IL2 is disposed on the wiring W2. A wiring W1 is disposed on the insulating layer IL2. The wiring W1 is connected to the wiring W2 through an opening WCON in the insulating layer IL2.

[0061] Gate electrode GL2 and light-shielding layer LS2 are on the same layer. Wiring W2 and gate electrode GL1 are on the same layer. Here, "same layer" means that multiple components are formed by patterning a single layer.

[0062] [1-4. Planar layout of display device 10]

[0063] use Figures 2 to 15 The planar layout of the pixels in the display device 10 will be described. Figure 2 The common auxiliary electrode CMTL, common electrodes CTCO1 and CTCO2, and spacer SP are omitted. The planar layout of the common auxiliary electrode CMTL and common electrodes CTCO1 and CTCO2 are respectively in... Figures 12-15 As shown in [the image / document]. Additionally, in [the image / document]... Figures 2 to 15 In the diagram, the locations where openings are provided are shown for the gate insulating layer GI1 and insulating layers IL1 to IL6.

[0064] like Figure 2 and Figure 3 As shown, the light-shielding layer LS extends in the first direction D1. The light-shielding layer LS may also have different shapes depending on the pixel. In this embodiment, a protrusion PJT is provided that protrudes from a portion of the light-shielding layer LS extending in the first direction D1 into the second direction D2.

[0065] like Figure 2 and Figure 4 As shown, the oxide semiconductor layer OS extends in the second direction D2. The gate electrode GL1 extends in the first direction D1 in a manner that intersects with the oxide semiconductor layer OS.

[0066] like Figure 2 and Figure 5 As shown, the pattern of the gate electrode GL1 is disposed inside the pattern of the light-shielding layer LS. (As...) Figure 5 As shown, the light-shielding layer LS is configured to include the area where the gate electrode GL1 overlaps with the oxide semiconductor layer OS when viewed from above. It should be noted that the gate electrode GL1 is also referred to as the "gate wiring".

[0067] like Figure 2 and Figure 6 As shown, the opening WCON is in Figure 6 The opening WCON is located near the top of the pattern of the oxide semiconductor layer OS. The opening WCON is located in the gate insulating layer GI1 and the insulating layer IL2. The opening WCON is located in the region that overlaps with the pattern of the oxide semiconductor layer OS but does not overlap with the gate electrode GL1.

[0068] like Figure 2 and Figure 7 As shown, multiple wirings W1 extend in the second direction D2. Wirings W1 are disposed in the region (second contact region CON2) within the opening WCON that overlaps with the oxide semiconductor layer OS. When it is necessary to distinguish and describe adjacent wirings separately, adjacent wirings W1 are referred to as wiring W1-1 (first wiring) and wiring W1-2 (second wiring). In this case, the main portion of the oxide semiconductor layer OS extends in the second direction D2 between wirings W1-1 and W1-2, intersecting with the gate electrode GL1. The main portion of the pattern of the oxide semiconductor layer OS extends in the second direction D2 between adjacent wirings W1. Furthermore, the remaining portion of the pattern of the oxide semiconductor layer OS extends from this main portion toward the region of the opening WCON in a direction inclined relative to the first direction D1 and the second direction D2.

[0069] like Figure 2 and Figure 8 As shown, the opening ACON is set in Figure 8 The opening ACON is located near the lower end of the pattern of the oxide semiconductor layer OS. The opening ACON is located in the gate insulating layer GI1, insulating layers IL2, and IL3. The opening ACON is located in the region that overlaps with the pattern of the oxide semiconductor layer OS but does not overlap with the gate electrode GL1.

[0070] like Figure 2 and Figure 9 As shown, the opening PCON is set in Figure 9 Near the lower end of the pattern of the oxide semiconductor layer OS. An opening PCON is disposed in the insulating layer IL4. Furthermore, the opening PCON overlaps with the opening ACON. In other words, the opening ACON is disposed inside the opening PCON.

[0071] like Figure 10 As shown, the common auxiliary electrode CMTL extends along the first direction D1 and has a portion that overlaps with the gate electrode GL1. Additionally, the common auxiliary electrode CMTL has a portion that overlaps with the wiring W1 along the second direction D2. An example is shown where the common auxiliary electrode CMTL is not connected to a common auxiliary electrode CMTL adjacent in the second direction D2, but this is not a limitation. The common auxiliary electrode CMTL may also be connected to a common auxiliary electrode CMTL adjacent in the second direction D2. Furthermore, a cutout CO extending from the center of the pixel in the D2 direction is provided at one end of each common auxiliary electrode CMTL. Figure 10 In this configuration, a cutout CO extending from the center of the pixel toward the direction D2 is provided at the lower end of each common auxiliary electrode CMTL. The common auxiliary electrode CMTL overlaps with wiring W1 and at least a portion of the opening WCON.

[0072] like Figure 11 As shown, a common electrode CTCO1 extends along a first direction D1 on a common auxiliary electrode CMTL. The common electrode CTCO1 is arranged to intersect with wirings W1-1 and W1-2 extending in a second direction D2. In this embodiment, the configuration of having a common electrode CTCO1 on a common auxiliary electrode CMTL has been described, but this embodiment of the present invention is not limited to this. A configuration in which a common auxiliary electrode CMTL is provided on a common electrode CTCO1 is also possible.

[0073] Figure 12 An opening PCON is shown, which is disposed in insulating layer IL4. An insulating layer IL5 is disposed on the sidewall of the opening PCON.

[0074] like Figure 2 and Figure 13 As shown, the pixel electrode PTCO1 extends along the second direction D2. The pixel electrode PTCO1 overlaps with the gate electrode GL1 and the oxide semiconductor layer OS. For the pixel electrode PTCO1, the portion of the oxide semiconductor layer OS that contacts the pixel electrode PTCO1 through the openings ACON and PCON that overlap with the gate electrode GL1 is referred to as the first contact region CON1. ​​Furthermore, the pixel electrode PTCO1 overlaps with the common electrode CTCO1 across the insulating layer IL5. The region where the pixel electrode PTCO1 overlaps with the common electrode CTCO1 across the insulating layer IL5 functions as a holding capacitor Cs1 (see reference). Figure 1 Additionally, on the pixel electrode PTCO1, the interiors of openings ACON and PCON are filled with a resin layer LEV. The surface of the resin layer LEV is planarized along the surface of the pixel electrode PTCO1.

[0075] like Figure 2 and Figure 14 As shown, pixel electrode PTCO2 overlaps with pixel electrode PTCO1 and resin layer LEV. In other words, pixel electrode PTCO2 is in direct contact with pixel electrode PTCO1 outside the area where resin layer LEV is disposed. Pixel electrode PTCO2 overlaps with gate electrode GL1 and oxide semiconductor layer OS. Pixel electrode PTCO2 extends along the second direction D2. The area of ​​pixel electrode PTCO2 is larger than the area of ​​pixel electrode PTCO1. An insulating layer IL6 is disposed on pixel electrode PTCO2.

[0076] like Figure 2 and Figure 15 As shown, the common electrode CTCO2 is provided for multiple pixels and has an opening OP. The opening OP has multiple shapes extending in a first direction D1 and a shape that bends along the bend of the pixel electrode PTCO1 in a second direction D2. More specifically, the opening OP has three transverse openings OPW extending in the D1 direction and a longitudinal opening OPL extending in the D2 direction, the longitudinal opening OPL and one end of the three transverse openings OPW (at...) Figure 15 (The middle part is the left end) is connected. In addition, the outer edge of the pixel electrode PTCO1 overlaps with the vertical opening OPL, thus, a portion of the vertical opening OPL (in Figure 15 The middle section (left end side) does not overlap with the pixel electrode PTCO1. Here, the common electrode CTCO2 overlaps with the pixel electrodes PTCO1 and PTCO2 through the insulating layer IL6. The area where the common electrode CTCO2 overlaps with the pixel electrodes PTCO1 and PTCO2 through the insulating layer IL6 functions as a holding capacitor Cs2 (see reference). Figure 1 ).

[0077] In a display device according to one embodiment of the present invention, the transistor Tr1, which serves as the pixel circuit, is a transistor with an oxide semiconductor layer used as the channel. The interiors of contact holes ACON and PCON, which connect the oxide semiconductor layer to the pixel electrode PTCO1, are filled with a resin layer LEV. Furthermore, the surface of the resin layer LEV is planarized along the surface of the pixel electrode PTCO1. Therefore, due to the reduction in unevenness caused by contact holes ACON and PCON, the liquid crystal molecules are well controlled within the contact holes, thereby improving the pixel aperture ratio (transmittance).

[0078] [1-5. Materials of the components of the display device 10]

[0079] As a substrate SUB, rigid substrates that are transparent but not flexible, such as glass substrates, quartz substrates, and sapphire substrates, can be used. On the other hand, when flexibility is required for the substrate SUB, flexible substrates containing resin and being flexible, such as polyimide substrates, acrylic substrates, siloxane boards, or fluororesin substrates, can be used. To improve the heat resistance of the substrate SUB, impurities can also be introduced into the aforementioned resins.

[0080] Common metallic materials can be used as gate electrodes GL1, GL2, wiring W1, W2, light-shielding layer LS, and common auxiliary electrode CMTL. For example, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), and their alloys or compounds can be used as these components. These materials can be used as a single layer or in a stacked configuration.

[0081] For example, a Ti / Al / Ti stacked structure is used as the gate electrode GL1. In this embodiment, the cross-sectional shape of the patterned end of the gate electrode GL1 in the above-described stacked structure is a positive cone shape.

[0082] Common insulating materials can be used as gate insulating layers GI1, GI2 and insulating layers IL1 to IL6. For example, silicon oxide (SiO2) can be used as insulating layers IL1 to IL3, IL5 and IL6. x ), silicon oxynitride (SiO) x N y ), silicon nitride (SiN) x ), silicon oxynitride (SiN) x O y ), aluminum oxide (AlO) x ), aluminum oxynitride (AlO) x N y ), aluminum oxynitride (AlN) x O y ), aluminum nitride (AlN) x Inorganic insulating layers such as IL4, IL4, and LEV are used. Insulating layers with few defects can be used as these insulating layers. Organic insulating materials such as polyimide resin, acrylic resin, epoxy resin, silicone resin, fluoropolymer resin, or siloxane resin can be used as insulating layer IL4 and resin layer LEV. Here, it is preferable that the same organic insulating material is used for insulating layer IL4 and resin layer LEV. It should be noted that the above-mentioned organic insulating materials can also be used as gate insulating layers GI1, GI2 and insulating layers IL1-IL3, IL5, and IL6. As the above components, the above materials can be used as a single layer or in a stacked manner.

[0083] It should be noted that, as an example of the aforementioned insulating layer, GI1, a SiO2 layer with a thickness of 100 nm, is used as the gate insulating layer. x Furthermore, SiO₂ with a total thickness of 600 nm to 700 nm is used as the insulating layer IL1. x / SiN x / SiO x The structure is a stacked layer. As the gate insulating layer GI2, SiO₂ with a total thickness of 60–100 nm is used. x / SiN x The structure is a stacked structure. As the insulating layer IL2, SiO₂ with a total thickness of 300nm–500nm is used. x / SiN x / SiO x The structure is a stacked structure. As the insulating layer IL3, SiO₂ with a total thickness of 200 nm to 500 nm is used. x (single-layer), SiN x (Single layer) or their stacked structures. As insulating layer IL4, an organic layer with a thickness of 2 μm to 4 μm is used. As insulating layer IL5, SiN with a thickness of 50 nm to 150 nm is used. x (Single layer). As the insulating layer IL6, SiN with a thickness of 50nm–150nm is used. x (Single layer)

[0084] The above SiO x N y and AlO x N y It consists of silicon and aluminum compounds containing nitrogen (N) in a ratio less than that of oxygen (O) (x>y). Additionally, SiN... x O y and AlN x O y It consists of silicon and aluminum compounds containing oxygen in a ratio less than that of nitrogen (x>y).

[0085] As the oxide semiconductor layer OS, a metal oxide with semiconductor properties can be used. The oxide semiconductor layer OS is transparent. For example, an oxide semiconductor containing indium (In), gallium (Ga), zinc (Zn), and oxygen (O) can be used. In particular, an oxide semiconductor having a composition ratio of In:Ga:Zn:O = 1:1:1:4 can be used. However, the oxide semiconductor containing In, Ga, Zn, and O used in this embodiment is not limited to the above composition, and oxide semiconductors with different compositions can also be used. For example, in order to improve mobility, the In ratio can be made larger than that described above. In addition, in order to increase the band gap and reduce the effect caused by light irradiation, the Ga ratio can be made larger than that described above.

[0086] Other elements can also be added to oxide semiconductors containing In, Ga, Zn, and O. For example, metal elements such as Al and Sn can also be added to the oxide semiconductor. In addition to the oxide semiconductors mentioned above, oxide semiconductors containing In and Ga (IGO), oxide semiconductors containing In and Zn (IZO), oxide semiconductors containing In, Sn, and Zn (ITZO), and oxide semiconductors containing In and W can also be used as oxide semiconductor layers OS. The oxide semiconductor layer OS can be amorphous or crystalline. The oxide semiconductor layer OS can also be a mixture of amorphous and crystalline phases.

[0087] A transparent conductive layer is used as the common electrodes CTCO1 and CTCO2 and the pixel electrodes PTCO1 and PTCO2. This transparent conductive layer can be a mixture of indium oxide and tin oxide (ITO) or a mixture of indium oxide and zinc oxide (IZO). Other materials can also be used as this transparent conductive layer.

[0088] As described above, according to the display device 10 of this embodiment, conduction between the oxide semiconductor layer OS of transistor Tr1 and pixel electrode PTCO1 can be ensured by making them directly contacted. Therefore, it is not necessary to provide a metal layer between the oxide semiconductor layer OS and pixel electrode PTCO1. As a result, light is not blocked at the openings ACON and PCON, thus suppressing the reduction of the aperture ratio. In addition, the layer exposed in the display area is an oxide semiconductor layer OS that is transparent and does not easily generate uneven transmitted light like silicon layers, thus suppressing the occurrence of display unevenness.

[0089] The display device 10 increases the holding capacitance by overlapping the holding capacitors Cs1 and Cs2, thus providing good image quality. Furthermore, by overlapping the holding capacitors Cs1 and Cs2, moisture diffusion from the lower layer can be suppressed.

[0090] Furthermore, as the pixel size of display devices shrinks, the pixel electrodes become more susceptible to capacitive coupling caused by signal lines. If the shrunk pixels are to be driven at high speeds, the crosstalk caused by the pixel electrode potential changing according to the signal line potential can become significant.

[0091] In a display device 10 according to an embodiment of the present invention, a common electrode CTCO1 is provided in a manner that intersects with wirings W1-1 and W1-2 extending in the second direction D2. The common electrode CTCO1 is provided along the first direction D1 in a manner that crosses multiple pixels. As a result, the common electrode CTCO1 can shield the wirings W1-1 and W1-2 from the pixel electrodes. Therefore, capacitive coupling between the wirings W1-1 and W1-2 and the pixel electrodes can be reduced. In addition, in the display area of ​​the pixel, a holding capacitance based on the pixel electrode PTCO1, the insulating layer IL6, and the common electrode CTCO2 can be added to the holding capacitance based on the pixel electrode PTCO1, the insulating layer IL5, and the common electrode CTCO1. As a result, the holding capacitance can be increased, and thus the effect of capacitive coupling on the potential can be reduced. In this way, in the display device 10, in the miniaturized pixels, the effect of capacitive coupling on the potential can be reduced, and thus crosstalk can be reduced.

[0092] In addition, such as Figure 13 As shown, the width of the pixel electrode PTCO1 in the first direction D1 can be approximately the same as, smaller than, or larger than the width of the opening PCON in the first direction D1. Preferably, the width of the pixel electrode PTCO1 in the first direction D1 is larger than the width of the opening PCON in the first direction D1. The arrangement of the pixel electrode PTCO1 is offset relative to the arrangement of the opening PCON in the first direction D1. In other words, there may be a region in the opening PCON where the insulating layer IL5 does not contact the pixel electrode PTCO1. That is, the pixel electrode PTCO1 may also contact the insulating layer IL5 provided in the opening PCON. By offsetting the arrangement of the pixel electrode PTCO1 relative to the arrangement of the opening PCON in the first direction D1, it is possible to suppress the pixel electrode PTCO1 from being interrupted by the opening PCON in the second direction D2. Therefore, the potential applied to the pixel electrode PTCO1 can be made uniform.

[0093] It should be noted that, as Figure 16 As shown, the pixel electrode PTCO1 can also be configured such that its arrangement is not disjoint with the arrangement of the opening PCON in the first direction D1. In other words, there can be multiple areas in the opening PCON where the insulating layer IL5 does not contact the pixel electrode PTCO1. That is, the pixel electrode PTCO1 can also have multiple areas that contact the insulating layer IL5 disposed in the opening PCON.

[0094] [2. Second Implementation]

[0095] use Figures 17-19 The overall configuration of the display device 20 described in the first embodiment will be explained.

[0096] [2-1. Overview of display device 20]

[0097] Figure 17 This is a top view showing an outline of a display device 20 according to an embodiment of the present invention. Figure 17 As shown, the display device 20 includes an array substrate 300, a sealing portion 400, an opposing substrate 500, a flexible printed circuit board 600 (FPC 600), and an IC chip 700. The array substrate 300 and the opposing substrate 500 are bonded together by the sealing portion 400. In the liquid crystal region 22 surrounded by the sealing portion 400, a plurality of pixel circuits 310 are arranged in a matrix. The liquid crystal region 22 is the region that overlaps with the liquid crystal element 410 described later when viewed from above.

[0098] The sealing region 24, where the sealing portion 400 is provided, is the area surrounding the liquid crystal region 22. The FPC 600 is disposed in the terminal region 26. The terminal region 26 is the area where the array substrate 300 is exposed from the opposing substrate 500, and is disposed outside the sealing region 24. It should be noted that the outside of the sealing region 24 refers to the area where the sealing portion 400 is provided and the area surrounded by the sealing portion 400. The IC chip 700 is disposed on the FPC 600. The IC chip 700 supplies signals for driving each pixel circuit 310.

[0099] [2-2. Circuit configuration of display device 20]

[0100] Figure 18 This is a block diagram illustrating the circuit configuration of a display device according to an embodiment of the present invention. Figure 18 As shown, a source driver circuit 320 is disposed adjacent to the liquid crystal region 22 where the pixel circuit 310 is disposed in the first direction D1 (row direction). Additionally, a gate driver circuit 330 is disposed adjacent to the liquid crystal region 22 in the second direction D2 (column direction). The source driver circuit 320 and the gate driver circuit 330 are disposed in the aforementioned sealed region 24. The region where the source driver circuit 320 and the gate driver circuit 330 are disposed is not limited to the sealed region 24; it can be any region outside the region where the pixel circuit 310 is disposed.

[0101] Source wiring 321 extends from source driver circuit 320 toward a second direction D2 and is connected to a plurality of pixel circuits 310 arranged in the second direction D2. Gate wiring 331 extends from gate driver circuit 330 toward a first direction D1 and is connected to a plurality of pixel circuits 310 arranged in the first direction D1.

[0102] A terminal section 333 is provided in the terminal area 26. The terminal section 333 is connected to the source driver circuit 320 via a connection wire 341. Similarly, the terminal section 333 is connected to the gate driver circuit 330 via a connection wire 341. An external device connected to the FPC 600 is connected to the display device 20 via the terminal section 333, and the pixel circuits 310 provided in the display device 20 are driven according to the signals from the external device.

[0103] The transistor Tr1 shown in the first and second embodiments is used in the pixel circuit 310. The transistor Tr2 shown in the first and second embodiments is applied to the transistors included in the source driver circuit 320 and the gate driver circuit 330.

[0104] [2-3. Pixel circuit 310 of display device 20]

[0105] Figure 19 This is a circuit diagram illustrating the pixel circuitry of a display device 20 according to an embodiment of the present invention. Figure 19 As shown, the pixel circuit 310 includes components such as a transistor 800, a holding capacitor 890, and a liquid crystal element 410. The transistor 800 has a first gate electrode 810, a first source electrode 830, and a first drain electrode 840. The first gate electrode 810 is connected to the gate wiring 331. The first source electrode 830 is connected to the source wiring 321. The first drain electrode 840 is connected to the holding capacitor 890 and the liquid crystal element 410. The transistor Tr1 shown in the first and second embodiments is applied to... Figure 19 The transistor 800 is shown. It should be noted that, in this embodiment, for ease of explanation, 830 is referred to as the source electrode and 840 as the drain electrode, but the functions of each electrode as the source and as the drain can be interchanged.

[0106] As embodiments of the present invention, the above embodiments can be appropriately combined and implemented as long as they do not contradict each other. In addition, any device that adds, deletes, or modifies the constituent elements, or adds, omits, or changes the conditions of a process, based on the display device of each embodiment, is included within the scope of the present invention as long as it possesses the spirit of the present invention.

[0107] Even if other effects are different from those achieved by the above-described embodiments, effects that are obvious according to the description in this specification or effects that are easily foreseen by those skilled in the art are of course also understood to be effects brought about by the present invention.

Claims

1. A display device comprising: The first transistor includes an oxide semiconductor layer, a gate wiring opposite to the oxide semiconductor layer, and a gate insulating layer between the oxide semiconductor layer and the gate wiring. At least one first insulating layer is disposed on the first transistor, and a first contact hole is disposed on the outside of the gate wiring; A planarization film is disposed on the first insulating layer and has a second contact hole that overlaps with the first contact hole; A first transparent conductive layer is disposed on the planarization film, including a region overlapping with the gate wiring; A second insulating layer is disposed on the first transparent conductive layer, covering the side of the second contact hole; The second transparent conductive layer is disposed on the second insulating layer and is in contact with the oxide semiconductor layer through the first contact hole and the second contact hole; A first resin is disposed on the second transparent conductive layer, filling the interior of the first contact hole and the second contact hole; A third transparent conductive layer is disposed on the second transparent conductive layer and the first resin; as well as A third insulating layer is disposed on the third transparent conductive layer. A fourth transparent conductive layer is disposed on the third insulating layer, the fourth transparent conductive layer having an opening pattern that overlaps with the first resin.

2. The display device according to claim 1, further comprising: A conductive layer is disposed between the planarization film and the first transparent conductive layer, including a region that overlaps with the gate wiring.

3. The display device according to claim 1, further comprising: A conductive layer is disposed between the first transparent conductive layer and the second insulating layer, including a region that overlaps with the gate wiring.

4. The display device according to claim 1, wherein, The third transparent conductive layer overlaps with the first transparent conductive layer through the second transparent conductive layer.

5. The display device according to claim 1, wherein, The refractive index of the planarization film is approximately the same as that of the first resin.

6. The display device according to claim 1, wherein, When viewed from above, the fourth transparent conductive layer overlaps with the first transparent conductive layer, the second transparent conductive layer, and the third transparent conductive layer.

7. The display device according to claim 1, wherein, When viewed from above, the gate wiring is arranged along a first direction. The second transparent conductive layer and the third transparent conductive layer are disposed along a second direction intersecting the first direction. The third transparent conductive layer has a region at the second contact hole that contacts the second insulating layer.

8. The display device according to claim 1, wherein, The third transparent conductive layer overlaps with the first transparent conductive layer without being separated by the second transparent conductive layer.

9. The display device according to claim 6, wherein, At least a portion of the opening pattern does not overlap with the third transparent conductive layer.

10. The display device according to claim 9, wherein, The opening pattern has one or more horizontal openings and a vertical opening connected to the horizontal openings, a portion of which does not overlap with the third transparent conductive layer.

11. The display device according to claim 2, wherein, The conductive layer has a cutout that overlaps with the oxide semiconductor layer.

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