High electron mobility transistor devices

Abstract

This invention provides a high electron mobility transistor device, including a substrate, a semiconductor stacked layer, a gate, a source, a drain, and a first Schottky electrode. The semiconductor stacked layer is disposed on the substrate. The gate is disposed on the semiconductor stacked layer. The source and drain are electrically connected to the semiconductor stacked layer. The source, gate, and drain are arranged sequentially along a first direction. The first Schottky electrode has a Schottky contact with the semiconductor stacked layer and is electrically connected to the source. The gate and the first Schottky electrode are arranged along a second direction, which is perpendicular to the first direction. By integrating the high electron mobility transistor with a Schottky diode, the overall performance of the high electron mobility transistor device can be improved.

Description

Technical Field

[0001] The present invention relates to a high electron mobility transistor device, and more particularly to a high electron mobility transistor device including a Schottky electrode. Background Technology

[0002] A high electron mobility transistor (HEMT) is a type of transistor. HEMTs consist of a heterojunction formed by two semiconductor materials with different band gaps. The heterojunction can generate a two-dimensional electron gas or a two-dimensional hole gas, which can serve as the conductive path of the HEMT. Due to its advantages such as low resistance, high breakdown voltage, and fast switching frequency, HEMTs are widely used in high-power electronic components.

[0003] HEMTs can be classified into depletion mode or enhancement mode HEMTs based on whether the channel is normally open or normally closed. Enhancement mode transistors have gained considerable attention in the industry due to the additional security they provide and their ease of control with simple, low-cost driver circuits. Summary of the Invention

[0004] This invention provides a high electron mobility transistor device that improves the overall performance of the high electron mobility transistor device by integrating a HEMT with a Schottky Barrier Diode (SBD).

[0005] At least one embodiment of the present invention provides a high electron mobility transistor device, including a substrate, a semiconductor stacked layer, a gate, a source, a drain, and a first Schottky electrode. The semiconductor stacked layer is disposed on the substrate and includes a first isolation structure. The gate is disposed on the semiconductor stacked layer. The source and drain are electrically connected to the semiconductor stacked layer. The source, gate, and drain are arranged sequentially along a first direction. The first Schottky electrode has a Schottky contact with the semiconductor stacked layer and is electrically connected to the source. The gate and the first Schottky electrode are arranged along a second direction, wherein the first and second directions are parallel to the surface of the substrate, and the second direction is perpendicular to the first direction. The first Schottky electrode and the semiconductor stacked layer constitute a first Schottky diode, the first Schottky diode is electrically connected to the source and drain, and the first isolation structure is laterally located between the first Schottky electrode and the gate, and between the first Schottky electrode and the source.

[0006] In some embodiments, the first isolation structure electrically isolates the semiconductor stacked layer below the first Schottky electrode from the semiconductor stacked layer below the gate, and the first isolation structure electrically isolates the semiconductor stacked layer below the first Schottky electrode from the semiconductor stacked layer below the source.

[0007] In some embodiments, the high electron mobility transistor device further includes a field-effect electrode. The field-effect electrode is electrically connected to the gate and is located above the gate and the first Schottky electrode.

[0008] In some embodiments, in the first direction, the distance between the gate and the drain is equal to the distance between the first Schottky electrode and the drain.

[0009] In some embodiments, the high electron mobility transistor device further includes a first ohmic electrode and a second Schottky electrode. The first ohmic electrode has an ohmic contact with the semiconductor stack and is electrically connected to the gate, wherein the gate, the first Schottky electrode, and the first ohmic electrode are arranged along a second direction. The second Schottky electrode has a Schottky contact with the semiconductor stack. The source and the second Schottky electrode are arranged along the second direction. A second Schottky diode, formed by the second Schottky electrode and the semiconductor stack, is included between the source and the gate.

[0010] In some embodiments, the semiconductor stack includes a second isolation structure. The second isolation structure is laterally located between the first ohmic electrode and the gate, and between the first ohmic electrode and the drain, and laterally located between the second Schottky electrode and the source. The second isolation structure electrically isolates the semiconductor stack below the first ohmic electrode from the semiconductor stack below the gate, and electrically isolates the semiconductor stack below the first ohmic electrode from the semiconductor stack below the drain, and electrically isolates the semiconductor stack below the second Schottky electrode from the semiconductor stack below the source.

[0011] In some embodiments, the second Schottky diode is electrically connected to the source and the gate.

[0012] In some embodiments, there is an ohmic contact between the source and the semiconductor stack, and an ohmic contact between the drain and the semiconductor stack.

[0013] At least one embodiment of the present invention provides a high electron mobility transistor device, including a substrate, a semiconductor stacked layer, a gate, a source, a drain, a first ohmic electrode, and a first Schottky electrode. The semiconductor stacked layer is disposed on the substrate, wherein the semiconductor stacked layer includes a first isolation structure. The gate is disposed on the semiconductor stacked layer. The source and drain are electrically connected to the semiconductor stacked layer, respectively. The source, gate, and drain are arranged sequentially along a first direction. The first ohmic electrode has an ohmic contact with the semiconductor stacked layer. The first ohmic electrode is electrically connected to the gate. The first ohmic electrode and the gate are arranged along a second direction, wherein the first and second directions are parallel to the surface of the substrate, and the second direction is perpendicular to the first direction. The first isolation structure is laterally located between the first ohmic electrode and the gate, and between the first ohmic electrode and the drain. The first Schottky electrode has a Schottky contact with the semiconductor stacked layer. The source and the first Schottky electrode are arranged along the second direction. A first Schottky diode, formed by the first Schottky electrode and the semiconductor stacked layer, is included between the source and the gate. The first isolation structure is laterally located between the first Schottky electrode and the source.

[0014] In some embodiments, the first isolation structure electrically isolates the semiconductor stacked layer below the first ohmic electrode from the semiconductor stacked layer below the gate, the first isolation structure electrically isolates the semiconductor stacked layer below the first ohmic electrode from the semiconductor stacked layer below the drain, and the first isolation structure electrically isolates the semiconductor stacked layer below the first Schottky electrode from the semiconductor stacked layer below the source.

[0015] In some embodiments, the first Schottky diode is electrically connected to the source and the gate.

[0016] In some embodiments, there is an ohmic contact between the source and the semiconductor stack, and an ohmic contact between the drain and the semiconductor stack.

[0017] In some embodiments, the high electron mobility transistor device further includes a field-effect electrode. The field-effect electrode is electrically connected to the gate and is located above the gate and the first ohmic electrode.

[0018] In some embodiments, the high electron mobility transistor device further includes a second ohmic electrode and a second Schottky electrode. The second ohmic electrode has an ohmic contact with the semiconductor stack and is electrically connected to the first Schottky electrode. The second Schottky electrode has a Schottky contact with the semiconductor stack. The second Schottky electrode and the semiconductor stack constitute a second Schottky diode. The first Schottky diode and the second Schottky diode are connected in series between the source and the gate.

[0019] In some embodiments, the second ohmic electrode is located between the first ohmic electrode and the gate.

[0020] In some embodiments, the source, the first Schottky electrode, and the second Schottky electrode are arranged along a second direction, and the first ohmic electrode, the second ohmic electrode, and the gate are arranged along a second direction.

[0021] Based on the above, by integrating HEMT with SBD, the efficiency loss of reverse conduction mode and / or component failure caused by electrostatic discharge (ESD) can be reduced. Attached Figure Description

[0022] The accompanying drawings are included to further illustrate the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0023] Figure 1A This is a top view schematic diagram of a high electron mobility transistor device according to an embodiment of the present invention.

[0024] Figure 1B It is along Figure 1A A schematic diagram of the cross section of line a-a'.

[0025] Figure 1C It is along Figure 1A A schematic diagram of the cross section of line b-b'.

[0026] Figure 1D It is along Figure 1A A cross-sectional view of line c-c'.

[0027] Figure 1E yes Figure 1A A circuit diagram of a high electron mobility transistor device.

[0028] Figure 2A This is a top view schematic diagram of a high electron mobility transistor device according to an embodiment of the present invention.

[0029] Figure 2B It is along Figure 2A A schematic diagram of the cross section of line a-a'.

[0030] Figure 2C It is along Figure 2A A schematic diagram of the cross section of line b-b'.

[0031] Figure 2D It is along Figure 2A A cross-sectional view of line c-c'.

[0032] Figure 2E yes Figure 2A A circuit diagram of a high electron mobility transistor device.

[0033] Figure 3A This is a top view schematic diagram of a high electron mobility transistor device according to an embodiment of the present invention.

[0034] Figure 3B It is along Figure 3A A schematic diagram of the cross sections of lines d-d' and e-e'.

[0035] Figure 3C yes Figure 3A A circuit diagram of a high electron mobility transistor device.

[0036] Figure 4A This is a top view schematic diagram of a high electron mobility transistor device according to an embodiment of the present invention.

[0037] Figure 4B yes Figure 4A A circuit diagram of a high electron mobility transistor device.

[0038] Figure 5A This is a schematic cross-sectional view of a high electron mobility transistor according to an embodiment of the present invention.

[0039] Figure 5B This is a schematic cross-sectional view of a Schottky diode according to an embodiment of the present invention.

[0040] Figure 6 This is a schematic cross-sectional view of a Schottky diode according to an embodiment of the present invention.

[0041] Explanation of icon numbers

[0042] 10, 20, 30: High electron mobility transistor devices;

[0043] 100: Substrate;

[0044] 102: Nucleation layer;

[0045] 104: Buffer layer;

[0046] 106: Channel layer;

[0047] 108: Barrier layer;

[0048] 110: Semiconductor stacked layer;

[0049] 120: Dielectric structure;

[0050] 210: Gate;

[0051] 220: Source pole;

[0052] 220B, 230B, 320B: Bottom surface;

[0053] 230: Drain;

[0054] 240: P-type gallium nitride layer;

[0055] 310, 350: Conductive structure;

[0056] 320a, 320b, 320ba, 320bb, 320bc: Schottky electrodes;

[0057] 330a, 330b, 330c: Isolation structure;

[0058] 340, 340a, 340b, 340c: Ohmic electrodes;

[0059] 360a, 360b: Conductive structure;

[0060] a-a',b-b',c-c',d-d',e-e': line;

[0061] D1: First direction;

[0062] D2: Second direction;

[0063] Id,Ir: direction;

[0064] FP: Field-effect circuit board;

[0065] HEMT: High Electron Mobility Transistor;

[0066] SBD1, SBD2, SBD2a, SBD2b, SBD2c: Schottky diodes;

[0067] V1,V2,V2a,V3,V4,V4a: Distance. Detailed Implementation

[0068] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element symbols are used in the drawings and description to denote the same or similar parts.

[0069] Figure 1A This is a top view schematic diagram of a high electron mobility transistor device according to an embodiment of the present invention.

[0070] Figure 1B It is along Figure 1A A schematic diagram of the cross section of line a-a'. Figure 1C It is along Figure 1A A schematic diagram of the cross section of line b-b'.

[0071] Figure 1D It is along Figure 1A A cross-sectional view of line c-c'.

[0072] Please refer to Figures 1A to 1E The high electron mobility transistor device 10 includes a substrate 100, a semiconductor stack 110, a gate 210, a source 220, a drain 230, and a Schottky electrode 320a.

[0073] In some embodiments, substrate 100 includes a semiconductor substrate or a semiconductor-on-insulator (SOI) substrate, wherein the semiconductor material in the semiconductor substrate or SOI substrate may include elemental semiconductors, alloy semiconductors, or compound semiconductors. For example, elemental semiconductors may include Si or Ge. Alloy semiconductors may include SiGe, SiGeC, etc. Compound semiconductors may include SiC, III-V semiconductor materials, or II-VI semiconductor materials. III-V semiconductor materials may include GaN, GaP, GaAs, AlN, AlP, AlAs, InN, InP, InAs, GaNP, GaNAs, GaPAs, AlNP, AlNAs, AlPAs, InNP, InNAs, InPAs, GaAlNP, GaAlNAs, GaAlPAs, GaInNP, GaInNAs, GaInPAs, InAlNP, InAlNAs, or InAlPAs. Group II-VI semiconductor materials may include CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, HgS, HgSe, HgTe, CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, CdZnSeS, CdZnSeTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe, or HgZnSTe. Furthermore, the semiconductor material may be doped to a first conductivity type or a second conductivity type complementary to the first conductivity type. For example, the first conductivity type can be N-type, while the second conductivity type can be P-type.

[0074] The semiconductor stacked layer 110 is disposed on the substrate 100 and includes a nucleation layer 102, a buffer layer 104, a channel layer 106, and a barrier layer 108.

[0075] A channel layer 106 is disposed above the substrate 100. In one embodiment, the material of the channel layer 106 includes a group III nitride, such as a group III-V compound semiconductor material. In some embodiments, the material of the channel layer 106 includes GaN. The channel layer 106 may be a doped or undoped layer. In some embodiments, the channel layer 106 has a two-dimensional electron gas (2DEG) located below the interface between the channel layer 106 and the overlying barrier layer 108.

[0076] Nucleation layer 102 and buffer layer 104 may be disposed between substrate 100 and channel layer 106 to reduce stress caused by differences in lattice constants and / or coefficients of thermal expansion between substrate 100 and channel layer 106. More specifically, nucleation layer 102 is in contact with the upper surface of substrate 100, and buffer layer 104 is disposed between nucleation layer 102 and channel layer 106. In one embodiment, the material of nucleation layer 102 includes group III nitrides, such as group III-V compound semiconductor materials. In one embodiment, the material of nucleation layer 102 includes AlN, GaN, AlGaN, or combinations thereof. In one embodiment, the material of buffer layer 104 includes group III nitrides, such as group III-V compound semiconductor materials, and may have a single-layer or multi-layer structure. In one embodiment, the material of buffer layer 104 includes AlN, GaN, AlGaN, InGaN, AlInN, AlGaInN, or combinations thereof.

[0077] A barrier layer 108 is disposed on the channel layer 106. In one embodiment, the barrier layer 108 is made of a group III nitride, such as a group III-V compound semiconductor material, and may have a single-layer or multi-layer structure. In one embodiment, the barrier layer 108 comprises AlGaN, AlInN, AlN, or AlGaInN, or a combination thereof. The barrier layer 108 may be a doped or undoped layer.

[0078] Gate 210 is disposed on semiconductor stack 110. In one embodiment, the material of gate 210 includes metal or metal nitride (e.g., Ta, TaN, Ti, TiN, W, Pd, Ni, Au, Al or combinations thereof), metal silicide (e.g., WSix), or other materials that can form a Schottky contact with a III-V compound semiconductor.

[0079] In this embodiment, a p-type gallium nitride (GaN) layer 240 is disposed between the gate 210 and the barrier layer 108. The p-type gallium nitride layer 240 is used to form a disconnected region of a two-dimensional electron gas or a region with a relatively low electron density; therefore, the material of the p-type gallium nitride layer 240 is gallium nitride doped with a dopant (e.g., magnesium). In some embodiments, in order to suppress the redistribution of the dopant in the p-type gallium nitride layer 240, a low-temperature aluminum nitride layer (not shown) is disposed under the p-type gallium nitride layer 240. The term "low-temperature" aluminum nitride layer refers to an aluminum nitride layer formed at an epitaxial temperature lower than the temperature typically used for HEMT device epitaxial processes (e.g., over 1000 degrees Celsius), such as an aluminum nitride layer formed at an epitaxial temperature between 700°C and 800°C.

[0080] Source 220 and drain 230 are electrically connected to semiconductor stack 110. Source 220 and drain 230 are disposed on barrier layer 108. However, the present invention is not limited thereto. In one embodiment, at least one of source 220 and / or drain 230 may extend into channel layer 106 and be electrically connected to two-dimensional electron gas. In one embodiment, the materials of source 220 and drain 230 include metals (e.g., Al, Ti, Ni, Au, or alloys thereof), or other materials capable of forming ohmic contacts with III-V compound semiconductors. In other words, source 220 and semiconductor stack 110 have ohmic contacts, and drain 230 and semiconductor stack 110 have ohmic contacts, but the present invention is not limited thereto. In other embodiments, source 220 and drain 230 may also be selected from materials capable of forming Schottky contacts with III-V compound semiconductors.

[0081] A Schottky electrode 320a is disposed on the barrier layer 108, and a Schottky contact is formed between the Schottky electrode 320a and the semiconductor stack layer 110. In some embodiments, the material of the Schottky electrode 320a includes a metal or metal nitride (e.g., Ta, TaN, Ti, TiN, W, Pd, Ni, Au, Al or combinations thereof), a metal silicide (e.g., WSix), or other materials capable of forming a Schottky contact with a III-V compound semiconductor. In some embodiments, the Schottky electrode 320a and the gate 210 comprise the same material, but this is not a limitation of the invention.

[0082] The Schottky electrode 320a is electrically connected to the source 220. In this embodiment, the source 220 is electrically connected to the Schottky electrode 320a via a conductive structure 310. In some embodiments, the material of the conductive structure 310 includes a metal, a metal nitride, a metal oxide, or other suitable material.

[0083] In this embodiment, the Schottky electrode 320a and the semiconductor stack 110 constitute a Schottky diode SBD1. The Schottky diode SBD1 is located between the source 220 and the drain 230, and is electrically connected to the source 220 and the drain 230. The HEMT includes a source 220, a gate 210, and a drain 230. Figure 1E The circuit diagram is shown below.

[0084] The field-effect electrode FP is electrically connected to the gate 210. In some embodiments, the field-effect electrode FP comprises a conductive material, such as a metal, metal nitride, metal oxide, or other suitable material. In some embodiments, the field-effect electrode FP, the source 220, and the drain 230 extend along a second direction D2 and are separated from each other. The field-effect electrode FP is located above the gate 210 and the Schottky electrode 320a, and extends from above the gate 210 and the Schottky electrode 320a toward the drain 230 to cover a portion of the semiconductor stack 110 between the gate 210 and the drain 230 and a portion of the semiconductor stack 110 between the Schottky electrode 320a and the drain 230.

[0085] Dielectric structure 120 is located on semiconductor stack layer 110. It should be noted that, for ease of explanation, Figures 1B to 1C The dielectric structure 120 is omitted from the drawing and is depicted as a single-layer structure; however, in practice, the dielectric structure 120 may include a single or multiple insulating layers. For example, the dielectric structure 120 includes silicon nitride, silicon oxide, aluminum oxide, hafnium oxide, or other insulating materials, or stacked layers of the above materials. In some embodiments, the gate 210, source 220, drain 230, conductive structure 310, Schottky electrode 320a, and field-effect plate FP each include a single or multiple layer structure and are distributed in or on the dielectric structure 120.

[0086] In this embodiment, the semiconductor stack 110 includes an isolation structure 330a. The isolation structure 330a extends downward from the top surface of the semiconductor stack 110 beyond the two-dimensional electron gas.

[0087] The isolation structure 330a is laterally located between the Schottky electrode 320a and the gate 210, thereby preventing current from flowing directly through the semiconductor stack 110 below the Schottky electrode 320a and below the gate 210. In other words, the isolation structure 330a electrically isolates the semiconductor stack 110 below the Schottky electrode 320a from the semiconductor stack 110 below the gate 210. Furthermore, the isolation structure 330a is laterally located between the Schottky electrode 320a and the source 220, thereby allowing current to flow through the Schottky electrode 320a into the semiconductor stack 110 below the Schottky electrode 320a, without directly flowing from the semiconductor stack 110 below the source 220 into the semiconductor stack 110 below the Schottky electrode 320a. In other words, the isolation structure 330a electrically isolates the semiconductor stack 110 below the Schottky electrode 320a from the semiconductor stack 110 below the source electrode 220.

[0088] In this embodiment, the isolation structure 330a is located between the vertical projection of the Schottky electrode 320a onto the semiconductor stacked layer 110 and the vertical projection of the gate 210 onto the semiconductor stacked layer 110, and also between the vertical projection of the Schottky electrode 320a onto the semiconductor stacked layer 110 and the vertical projection of the source 220 onto the semiconductor stacked layer 110, and along the first direction D1. The isolation structure 330a is not located between the vertical projection of the Schottky electrode 320a onto the semiconductor stacked layer 110 and the vertical projection of the drain 230 onto the semiconductor stacked layer 110.

[0089] In some embodiments, the isolation structure 330a includes an insulating material. For example, a recess is formed in the semiconductor stack 110, and the recess is filled with insulating material to form the isolation structure 330a. For example, during the formation of the dielectric structure 120, a portion of the insulating material is filled into the recess in the semiconductor stack 110 to form the isolation structure 330a. In other embodiments, a doping process (e.g., by ion implantation) is performed on the semiconductor stack 110 to form an isolation structure 330a in which carriers are not easily transmitted.

[0090] In this embodiment, the source 220, gate 210 and drain 230 are arranged sequentially along the first direction D1, and in this embodiment, the source 220, Schottky electrode 320a and drain 230 are arranged along the first direction D1.

[0091] In the forward conduction mode of the high electron mobility transistor device 10, a positive voltage is applied to the drain 230, and current flows along direction Id from the drain 230 through the semiconductor stack layer 110 below the gate 210 and reaches the source 220. At this time, the Schottky diode SBD1 is reverse biased, and current is more difficult to pass through the Schottky diode SBD1. The HEMT (such as a high electron mobility transistor device) containing the source 220, gate 210, and drain 230... Figure 1E The transistors in the transistors are functioning normally.

[0092] In the reverse conduction mode of the high electron mobility transistor device 10, a negative voltage is applied to the drain 230 or a positive voltage is applied to the source 220. At this time, the Schottky diode SBD1 is forward biased, and current can flow through the Schottky diode SBD1. The current flows along direction Ir from the Schottky electrode 320a through the semiconductor stack layer 110 below the Schottky electrode 320a and reaches the drain 230. Therefore, regardless of whether the HEMT is in the on-state or off-state, current can flow from the source 220 to the drain 230 through the Schottky electrode 320a.

[0093] Based on the above, the current in the reverse conduction mode can be channeled through the Schottky diode SBD1, thereby increasing the efficiency of the high electron mobility transistor device 10 in the reverse conduction mode.

[0094] In this embodiment, the gate 210 and the Schottky electrode 320a are arranged along a second direction D2, and the second direction D2 is perpendicular to the first direction D1. Since the gate 210 and the Schottky electrode 320a are arranged along the second direction D2, a HEMT (such as a source 220, gate 210, and drain 230) is constructed. Figure 1E The breakdown voltage of the transistor in the high electron mobility transistor device 10 is close to or equal to the breakdown voltage of the Schottky diode SBD1. In some embodiments, the distance V1 between the gate 210 and the drain 230 in the first direction D1 is equal to the distance V2 between the Schottky electrode 320a and the drain 230 in the first direction D1, thereby making it easier to control the breakdown voltage of the high electron mobility transistor device 10.

[0095] Furthermore, since the gate 210 and the Schottky electrode 320a are arranged along the second direction D2, the field-effect plate FP can shield not only the electric field of the HEMT but also the electric field of the Schottky diode SBD1, thereby enabling the Schottky diode SBD1 to achieve reliability similar to that of the HEMT. In some embodiments, the distance V3 between the side of the field-effect plate FP near the drain 230 and the gate 210 in the first direction D1 is equal to the distance V4 between the side of the field-effect plate FP near the drain 230 and the Schottky electrode 320a in the first direction D1.

[0096] Furthermore, since the gate 210 and the Schottky electrode 320a are in the second direction D2, the width of the high electron mobility transistor device 10 in the first direction D1 can be reduced.

[0097] Figure 2A This is a top view schematic diagram of a high electron mobility transistor device according to an embodiment of the present invention.

[0098] Figure 2B It is along Figure 2A A schematic diagram of the cross section of line a-a'. Figure 2C It is along Figure 2A A schematic diagram of the cross section of line b-b'.

[0099] Figure 2D It is along Figure 2A A cross-sectional view of line c-c'. Figure 2E yes Figure 2A A circuit diagram of a high electron mobility transistor device.

[0100] It must be stated here that, Figures 2A to 2E The embodiments follow Figures 1A to 1E The component reference numerals and partial contents of the embodiments are described below, wherein the same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted. For explanations of the omitted parts, please refer to the foregoing embodiments, and will not be repeated here.

[0101] Please refer to Figures 2A to 2E In this embodiment, a Schottky diode SBD2 is provided between the source 220 and the gate 210 of the high electron mobility transistor device 20, and the Schottky diode SBD2 is electrically connected to the source 220 and the gate 210.

[0102] The high electron mobility transistor device 20 includes a substrate 100, a semiconductor stack 110, a gate 210, a source 220, a drain 230, an ohmic electrode 340, and a Schottky electrode 320b.

[0103] A semiconductor stacked layer 110 is disposed on a substrate 100. A gate 210 is disposed on the semiconductor stacked layer 110. A source 220 and a drain 230 are electrically connected to the semiconductor stacked layer 110, respectively.

[0104] A source 220, a gate 210, and a drain 230 are disposed on a semiconductor stack 110 and arranged sequentially along a first direction D1. The HEMT includes a source 220, a gate 210, and a drain 230. In some embodiments, an ohmic contact is formed between the source 220 and the semiconductor stack 110, and an ohmic contact is formed between the drain 230 and the semiconductor stack 110, but this is not a limitation of the invention. In other embodiments, the source 220 and the drain 230 may also be made of materials capable of forming Schottky contacts with III-V compound semiconductors.

[0105] An ohmic electrode 340 is disposed on the semiconductor stack 110 and has an ohmic contact with the semiconductor stack 110. The ohmic electrode 340 is electrically connected to the gate 210 through a conductive structure 350. In some embodiments, the material of the conductive structure 350 includes a metal. In some embodiments, the ohmic electrode 340, the source 220, and the drain 230 are all made of materials that can form an ohmic contact with the semiconductor stack 110; therefore, the ohmic electrode 340, the source 220, and the drain 230 can be formed together, thereby saving production costs.

[0106] In some embodiments, the distance V1 between the gate 210 and the drain 230 in the first direction D1 is equal to the distance V2a between the ohmic electrode 340 and the drain 230 in the first direction D1, but the present invention is not limited thereto.

[0107] A Schottky electrode 320b is disposed on the semiconductor stack 110 and has a Schottky contact with the semiconductor stack 110. The Schottky electrode 320b is electrically connected to the source 220 through a conductive structure 310. In this embodiment, the conductive structure 310 extends along a second direction D2. The Schottky electrode 320b, the ohmic electrode 340, and the drain 230 are arranged sequentially along a first direction D1.

[0108] In this embodiment, the ohmic electrode 340 and the gate electrode 210 are arranged along the second direction D2, and the source electrode 220 and the Schottky electrode 320b are also arranged along the second direction D2. This reduces the width of the high electron mobility transistor device 20 in the first direction D1.

[0109] In this embodiment, the Schottky electrode 320b and the semiconductor stack 110 constitute a Schottky diode SBD2. One end of the Schottky diode SBD2 is electrically connected to the source 220, and the other end of the Schottky diode SBD2 is electrically connected to the gate 210 through the ohmic electrode 340 and the conductive structure 350, as shown below. Figure 2E The circuit diagram is shown below.

[0110] The field-effect plate FP is electrically connected to the gate 210. In some embodiments, the field-effect plate FP comprises a conductive material, such as a metal, metal nitride, metal oxide, or other suitable material. In some embodiments, the field-effect plate FP, the conductive structure 310, and the drain 230 extend along a second direction D2 and are separated from each other. The field-effect plate FP is located above the gate 210 and the ohmic electrode 340, and extends from above the gate 210 and the ohmic electrode 340 toward the drain 230 to cover a portion of the semiconductor stack layer 110 between the gate 210 and the drain 230 and a portion of the semiconductor stack layer 110 between the ohmic electrode 340 and the drain 230. In this embodiment, the field-effect plate FP also covers a portion of the semiconductor stack layer 110 between the ohmic electrode 340 and the Schottky electrode 320b, thereby improving the reliability of the Schottky diode SBD2.

[0111] In some embodiments, the gate 210, source 220, drain 230, conductive structure 310, Schottky electrode 320b, ohmic electrode 340, conductive structure 350, and field-effect plate FP each comprise a single-layer or multi-layer structure and are distributed within or on the dielectric structure 120. In this embodiment, a portion of the dielectric structure 120 is selectively disposed between the field-effect plate FP and the ohmic electrode 340. For example, the dielectric structure 120 is sandwiched between the conductive structure 350 above the ohmic electrode 340 and the field-effect plate FP.

[0112] In some embodiments, the distance V3 between the side of the field-effect plate FP near the drain 230 and the gate 210 in the first direction D1 is equal to the distance V4a between the side of the field-effect plate FP near the drain and the ohmic electrode 340 in the first direction D1.

[0113] In this embodiment, the semiconductor stack 110 includes an isolation structure 330b. The isolation structure 330b extends downward from the top surface of the semiconductor stack 110 beyond the two-dimensional electron gas.

[0114] The isolation structure 330b is laterally located between the ohmic electrode 340 and the gate 210, thereby preventing current from being directly transferred through the semiconductor stack 110 below the ohmic electrode 340 and the semiconductor stack 110 below the gate 210. In other words, the isolation structure 330b electrically isolates the semiconductor stack 110 below the ohmic electrode 340 from the semiconductor stack 110 below the gate 210. Furthermore, the isolation structure 330b is laterally located between the ohmic electrode 340 and the drain 230, thereby preventing the Schottky diode SBD2 from being directly connected to the drain 230. In other words, the isolation structure 330b electrically isolates the semiconductor stack 110 below the ohmic electrode 340 from the semiconductor stack 110 below the drain 230. Furthermore, the isolation structure 330b is laterally located between the Schottky electrode 320b and the source 220, thereby preventing current from being directly transferred through the semiconductor stack 110 below the Schottky electrode 320b and below the source 220. In other words, the isolation structure 330b electrically isolates the semiconductor stack 110 below the Schottky electrode 320b from the semiconductor stack 110 below the source 220.

[0115] In this embodiment, the isolation structure 330b is located between the vertical projection of the ohmic electrode 340 onto the semiconductor stacked layer 110 and the vertical projection of the gate 210 onto the semiconductor stacked layer 110, and between the vertical projection of the ohmic electrode 340 onto the semiconductor stacked layer 110 and the vertical projection of the drain 230 onto the semiconductor stacked layer 110. Furthermore, in the second direction D2, the isolation structure 330b is located between the vertical projection of the Schottky electrode 320b onto the semiconductor stacked layer 110 and the vertical projection of the source 220 onto the semiconductor stacked layer 110. In some embodiments, the isolation structure 330a is not located between the vertical projection of the Schottky electrode 320b onto the semiconductor stacked layer 110 and the vertical projection of the ohmic electrode 340 onto the semiconductor stacked layer 110.

[0116] In some embodiments, the isolation structure 330b includes an insulating material. For example, a recess is formed in the semiconductor stack 110, and the recess is filled with insulating material to form the isolation structure 330b. For example, during the formation of the dielectric structure 120, a portion of the insulating material is filled into the recess in the semiconductor stack 110 to form the isolation structure 330a. In other embodiments, a doping process (e.g., by ion implantation) is performed on the semiconductor stack 110 to form an isolation structure 330b in which carriers are not easily transmitted.

[0117] In this embodiment, the anode of the Schottky diode SBD2 is electrically connected to the source 220, and the cathode is electrically connected to the gate 210. This enables effective discharge of static electricity, improves the gate electrostatic protection capability of the HEMT, and reduces component failure caused by electrostatic discharge.

[0118] Figure 3A This is a top view schematic diagram of a high electron mobility transistor device according to an embodiment of the present invention. Figure 3B It is along Figure 3A A schematic diagram of the cross sections of lines d-d' and e-e'. Figure 3C yes Figure 3A A circuit diagram of a high electron mobility transistor device.

[0119] It must be stated here that, Figures 3A to 3C The embodiments follow Figures 2A to 2E The component reference numerals and partial contents of the embodiments are described below, wherein the same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted. For explanations of the omitted parts, please refer to the foregoing embodiments, and will not be repeated here.

[0120] Please refer to Figures 3A to 3C In this embodiment, the source 220 and gate 210 of the high electron mobility transistor device 30 include a plurality of Schottky diodes SBD2a, SBD2b, and SBD2c connected in series.

[0121] Ohmic electrodes 340a, 340b, and 340c are disposed on the semiconductor stacked layer 110 and have ohmic contacts with the semiconductor stacked layer 110, respectively. In this embodiment, ohmic electrodes 340b and 340c are located between the first ohmic electrode 340a and the gate 210.

[0122] Schottky electrodes 320ba, 320bb, and 320bc are disposed on the semiconductor stacked layer 110 and have Schottky contacts with the semiconductor stacked layer 110 respectively.

[0123] In this embodiment, the source electrode 220, the Schottky electrodes 320ba, 320bb, and 320bc are arranged along the second direction D2, and the ohmic electrodes 340a, 340b, and 340c are arranged along the second direction D2 with the gate electrode 210, thereby reducing the width of the high electron mobility transistor device 30 in the first direction D1.

[0124] In this embodiment, gate 210 is electrically connected to ohmic electrode 340a via conductive structure 350 (and other signal lines not shown in the figures). In some embodiments, gate 210 is electrically connected to other gates (not shown) via conductive structure 350, and multiple gates are electrically connected to ohmic electrode 340a. In other words, ohmic electrode 340a can be electrically connected to the gates of multiple HEMTs, and the number of HEMTs can be adjusted as needed, meaning that the present invention does not limit the gate of only one HEMT to be electrically connected to ohmic electrode 340a.

[0125] The ohmic electrode 340a is electrically connected to the Schottky electrode 320ba, forming a Schottky diode SBD2a with the semiconductor stack layer 110. The Schottky electrode 320ba is electrically connected to the ohmic electrode 340b through the conductive structure 360a. The ohmic electrode 340b is electrically connected to the Schottky electrode 320bb, forming a Schottky diode SBD2b with the semiconductor stack layer 110. The Schottky electrode 320bb is electrically connected to the ohmic electrode 340c through the conductive structure 360b. The ohmic electrode 340c is electrically connected to the Schottky electrode 320bc, forming a Schottky diode SBD2c with the semiconductor stack layer 110. The Schottky electrode 320bc is electrically connected to the source electrode 220 through the conductive structure 310.

[0126] In this embodiment, Schottky diodes SBD2a, SBD2b, and SBD2c are connected in series. In this embodiment, three Schottky diodes SBD2a, SBD2b, and SBD2c are connected in series between the gate 210 and the source 220, but this invention is not limited to this. Two or more Schottky diodes may be connected in series between the gate 210 and the source 220. In other words, the number of Schottky diodes connected in series can be adjusted as needed. By connecting the Schottky diodes in series, the electrostatic discharge of the high electron mobility transistor device 30 can be better controlled.

[0127] In this embodiment, the field-effect electrode FP is superimposed on the gate 210 and the ohmic electrodes 340a, 340b, and 340c. The field-effect electrode FP is superimposed on the semiconductor stack layer 110 between the gate 210 and the drain 230, and on the semiconductor stack layer 110 between the ohmic electrodes 340a, 340b, and 340c and the Schottky electrodes 320ba, 320bb, and 320bc. The field-effect electrode FP is electrically connected to the conductive structure 350, for example, through a conductive via C, but the invention is not limited thereto.

[0128] In this embodiment, the semiconductor stack 110 includes an isolation structure 330c. The isolation structure 330c extends downward from the top surface of the semiconductor stack 110 beyond the two-dimensional electron gas.

[0129] The isolation structure 330c is laterally located between the ohmic electrodes 340a, 340b, and 340c, thereby preventing current from being directly transferred through the semiconductor stack 110 below the ohmic electrode 340a, the semiconductor stack 110 below the ohmic electrode 340b, and the semiconductor stack 110 below the ohmic electrode 340c. Furthermore, the isolation structure 330c is laterally located between the Schottky electrodes 320ba, 320bb, and 320bc, thereby preventing current from being directly transferred through the semiconductor stack 110 below the Schottky electrode 320ba, the semiconductor stack 110 below the Schottky electrode 320bb, and the semiconductor stack 110 below the Schottky electrode 320bc. In other words, the isolation structure 330c electrically isolates the semiconductor stack 110 below the ohmic electrodes 340a, 340b, and 340c from each other. Furthermore, the isolation structure 330c is laterally located between the Schottky electrode 320bc and the source 220, thereby preventing current from being directly transferred through the semiconductor stack 110 below the Schottky electrode 320bc and below the source 220. In other words, the isolation structure 330c electrically isolates the semiconductor stack 110 below the Schottky electrode 320bc from the semiconductor stack 110 below the source 220.

[0130] Figure 4A This is a top view schematic diagram of a high electron mobility transistor device according to an embodiment of the present invention. Figure 4B yes Figure 4A A circuit diagram of a high electron mobility transistor device.

[0131] It must be stated here that, Figure 4A and Figure 4B The embodiments follow Figures 1A to 1E Implementation examples and Figures 2A to 2E The component reference numerals and partial contents of the embodiments are described below, wherein the same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted. For explanations of the omitted parts, please refer to the foregoing embodiments, and will not be repeated here.

[0132] Please refer to Figure 4A and Figure 4B The high electron mobility transistor device 40 includes a substrate 100, a semiconductor stack 110, a gate 210, a source 220, a drain 230, a Schottky electrode 320a, a Schottky electrode 320b, and an ohmic electrode 340.

[0133] The ohmic electrode 340 is disposed on the semiconductor stack 110 and has an ohmic contact with the semiconductor stack 110. The ohmic electrode 340 is electrically connected to the gate 210 through the conductive structure 350.

[0134] Schottky electrodes 320a and 320b are disposed on the semiconductor stacked layer 110 and have Schottky contacts with the semiconductor stacked layer 110 respectively. The Schottky electrodes 320a and 320b are electrically connected to the source electrode 220 through the conductive structure 310.

[0135] Schottky electrode 320a and semiconductor stack 110 constitute Schottky diode SBD1. Schottky diode SBD1 is electrically connected to the source 220 and drain 230. Schottky electrode 320b and semiconductor stack 110 constitute Schottky diode SBD2. Schottky diode SBD2 is electrically connected to the source 220 and electrically connected to the gate 210 through ohmic electrode 340 and conductive structure 350, as shown below. Figure 4B The circuit diagram is shown below.

[0136] In this embodiment, the ohmic electrode 340, the gate electrode 210, and the Schottky electrode 320a are arranged along the second direction D2, and the source electrode 220 and the Schottky electrode 320b are also arranged along the second direction D2. This reduces the width of the high electron mobility transistor device 40 in the first direction D1.

[0137] In this embodiment, the number of gates 210 between the ohmic electrode 340 and the Schottky electrode 320a can be adjusted according to actual needs. In other words, multiple HEMTs can share Schottky diode SBD1 and Schottky diode SBD2, but the present invention is not limited thereto.

[0138] In some embodiments, the distance V1 between the gate 210 and the drain 230 in the first direction D1 is equal to the distance V2 between the Schottky electrode 320a and the drain 230 in the first direction D1, thereby making it easier to control the breakdown voltage of the device. In some embodiments, the distance V2a between the ohmic electrode 340 and the drain 230 in the first direction D1 is also equal to the distance V1 between the gate 210 and the drain 230 in the first direction D1, but the present invention is not limited thereto.

[0139] In this embodiment, since the gate 210 and the Schottky electrode 320a are arranged along the second direction D2, the field-effect plate FP can shield not only the electric field of the HEMT but also the electric field of the Schottky diode SBD1, thereby enabling the Schottky diode SBD1 to achieve reliability similar to that of the HEMT. Furthermore, in this embodiment, the field-effect plate FP is also superimposed on the semiconductor stack layer 110 between the ohmic electrode 340 and the Schottky electrode 320b, thus also increasing the reliability of the Schottky diode SBD2.

[0140] In some embodiments, the distance V3 between the side of the field-effect plate FP near the drain 230 and the gate 210 in the first direction D1 is equal to the distance V4 between the side of the field-effect plate FP near the drain 230 and the Schottky electrode 320a in the first direction D1. In some embodiments, the distance V4a between the side of the field-effect plate FP near the drain and the ohmic electrode 340 in the first direction D1 is also equal to the distance V3 between the side of the field-effect plate FP near the drain 230 and the gate 210 in the first direction D1, but the present invention is not limited thereto.

[0141] In this embodiment, the semiconductor stack 110 includes an isolation structure 330a. The isolation structure 330a is laterally located between the Schottky electrode 320a and the gate 210, thereby preventing current from directly flowing through the semiconductor stack 110 below the Schottky electrode 320a and below the gate 210. Furthermore, the isolation structure 330a is laterally located between the Schottky electrode 320a and the source 220, thereby allowing current to flow through the Schottky electrode 320a into the semiconductor stack 110 below the Schottky electrode 320a, without directly flowing from the source 220 into the semiconductor stack 110 below the Schottky electrode 320a.

[0142] In this embodiment, the semiconductor stack 110 also includes an isolation structure 330b. The isolation structure 330b is laterally located between the ohmic electrode 340 and the gate 210, thereby preventing current from being directly transmitted through the semiconductor stack 110 between the semiconductor stack 110 below the ohmic electrode 340 and the semiconductor stack 110 below the gate 210. Furthermore, the isolation structure 330b is laterally located between the ohmic electrode 340 and the drain 230, thereby preventing the Schottky diode SBD2 from being directly connected to the drain 230. Additionally, the isolation structure 330b is laterally located between the Schottky electrode 320b and the source 220, thereby preventing current from being directly transmitted through the semiconductor stack 110 between the semiconductor stack 110 below the Schottky electrode 320b and the semiconductor stack 110 below the source 220.

[0143] Figure 5A This is a schematic cross-sectional view of a high electron mobility transistor according to an embodiment of the present invention. Figure 5B This is a schematic cross-sectional view of a Schottky diode according to an embodiment of the present invention.

[0144] It must be stated here that, Figure 5A and Figure 5B The embodiments follow Figures 1A to 1EThe component reference numerals and partial contents of the embodiments are described below, wherein the same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted. For explanations of the omitted parts, please refer to the foregoing embodiments, and will not be repeated here.

[0145] Please refer to Figure 5A In this embodiment, source 220 and drain 230 are electrically connected to semiconductor stack 110. Source 220 and drain 230 extend into channel layer 106 and are electrically connected to a two-dimensional electron gas. In one embodiment, the materials of source 220 and drain 230 include metals (e.g., Al, Ti, Ni, Au, or alloys thereof), or other materials capable of forming ohmic contacts with III-V compound semiconductors. In other words, source 220 and semiconductor stack 110 have ohmic contacts, and drain 230 and semiconductor stack 110 have ohmic contacts.

[0146] In some embodiments, at least one of the source 220 and drain 230 comprises a multilayer structure. For example, the source 220 comprises a multilayer structure, wherein the lowest layer in contact with the semiconductor stack 110 has an ohmic contact with the semiconductor stack 110, while other layers not in contact with the semiconductor stack 110 may comprise a material different from the aforementioned lowest layer. Similarly, the drain 230, for example, comprises a multilayer structure, wherein the lowest layer in contact with the semiconductor stack 110 has an ohmic contact with the semiconductor stack 110, while other layers not in contact with the semiconductor stack 110 may comprise a material different from the aforementioned lowest layer.

[0147] In this embodiment, the bottom surface 220B of the source electrode 220 and / or the bottom surface 230B of the drain electrode 230 are located on different horizontal planes from the bottom surface 320B of the Schottky electrode 320a, but the present invention is not limited thereto.

[0148] Figure 6 This is a schematic cross-sectional view of a high electron mobility transistor device according to an embodiment of the present invention.

[0149] It must be stated here that, Figure 6 The embodiments follow Figure 5A and Figure 5B The component reference numerals and partial contents of the embodiments are described below, wherein the same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted. For explanations of the omitted parts, please refer to the foregoing embodiments, and will not be repeated here.

[0150] Please refer to Figure 6 In this embodiment, the Schottky electrode 320a is directly connected to the source electrode 220. In other words, in this embodiment, the conductive structure 310 can be omitted (see reference). Figure 5B This setting reduces manufacturing costs.

[0151] In summary, by integrating HEMT and SBD, this invention can reduce efficiency loss in reverse conduction mode and / or component failure caused by electrostatic discharge.

[0152] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A high electron mobility transistor device, characterized by, Comprising: a substrate; a semiconductor stack disposed on the substrate, wherein the semiconductor stack includes a first isolation structure therein; a gate disposed on the semiconductor stack; a source and a drain respectively electrically connected to the semiconductor stack, and the source, the gate and the drain are sequentially arranged along a first direction; and a first Schottky electrode having a Schottky contact with the semiconductor stack and electrically connected to the source, wherein the gate and the first Schottky electrode are arranged along a second direction, wherein the first direction and the second direction are parallel to a surface of the substrate, and the second direction is perpendicular to the first direction, wherein the first Schottky electrode and the semiconductor stack form a first Schottky diode, the first Schottky diode electrically connects the source and the drain, and the first isolation structure is laterally between the first Schottky electrode and the gate and between the first Schottky electrode and the source.

2. The high electron mobility transistor device of claim 1, wherein, The first isolation structure electrically isolates the semiconductor stack under the first Schottky electrode from the semiconductor stack under the gate, and the first isolation structure electrically isolates the semiconductor stack under the first Schottky electrode from the semiconductor stack under the source.

3. The high electron mobility transistor device of claim 1, wherein, Further comprising: a field plate electrically connected to the gate and located above the gate and the first Schottky electrode.

4. The high electron mobility transistor device of claim 1, wherein, A distance between the gate and the drain in the first direction is equal to a distance between the first Schottky electrode and the drain in the first direction.

5. The high electron mobility transistor device of claim 1, wherein, Further comprising: a first ohmic electrode having an ohmic contact with the semiconductor stack and electrically connected to the gate, wherein the gate, the first Schottky electrode and the first ohmic electrode are arranged along the second direction; and a second Schottky electrode having a Schottky contact with the semiconductor stack, wherein the source and the second Schottky electrode are arranged along the second direction, and wherein the source and the gate include a second Schottky diode formed by the second Schottky electrode and the semiconductor stack.

6. The high electron mobility transistor device of claim 5, wherein, The semiconductor stack further includes a second isolation structure, and the second isolation structure is laterally between the first ohmic electrode and the gate and between the first ohmic electrode and the drain, and wherein the second isolation structure is laterally between the second Schottky electrode and the source, wherein the second isolation structure electrically isolates the semiconductor stack under the first ohmic electrode from the semiconductor stack under the gate, and the second isolation structure electrically isolates the semiconductor stack under the first ohmic electrode from the semiconductor stack under the drain, and wherein the second isolation structure electrically isolates the semiconductor stack under the second Schottky electrode from the semiconductor stack under the source.

7. The high electron mobility transistor device of claim 5, wherein: the second Schottky diode is electrically connected to the source and the gate.

8. The high electron mobility transistor device of claim 1, wherein, The source has an ohmic contact with the semiconductor stack, and the drain has an ohmic contact with the semiconductor stack.

9. A high electron mobility transistor device, characterized by, Further comprising: a substrate; a semiconductor stack disposed on the substrate, wherein the semiconductor stack includes a first isolation structure therein; a gate disposed on the semiconductor stack; a source and a drain respectively electrically connected to the semiconductor stack, and the source, the gate and the drain are sequentially arranged along a first direction; a first ohmic electrode having an ohmic contact with the semiconductor stack and electrically connected to the gate, wherein the first ohmic electrode and the gate are arranged along a second direction, wherein the first direction and the second direction are parallel to a surface of the substrate, and the second direction is perpendicular to the first direction, wherein the first isolation structure is laterally between the first ohmic electrode and the gate and between the first ohmic electrode and the drain; and a first Schottky electrode having a Schottky contact with the semiconductor stack, wherein the source and the first Schottky electrode are arranged along the second direction, and wherein a first Schottky diode is included between the source and the gate, the first Schottky diode comprising the first Schottky electrode and the semiconductor stack, and wherein the first isolation structure is laterally between the first Schottky electrode and the source.

10. The high electron mobility transistor device of claim 9, wherein, The first isolation structure electrically isolates the semiconductor stack under the first ohmic electrode from the semiconductor stack under the gate, the first isolation structure electrically isolates the semiconductor stack under the first ohmic electrode from the semiconductor stack under the drain, and the first isolation structure electrically isolates the semiconductor stack under the first Schottky electrode from the semiconductor stack under the source.

11. The high electron mobility transistor device of claim 9, wherein, The first Schottky diode is electrically connected to the source and the gate.

12. The high electron mobility transistor device of claim 9, wherein, The source has an ohmic contact with the semiconductor stack, and the drain has an ohmic contact with the semiconductor stack.

13. The high electron mobility transistor device of claim 9, wherein, Further comprising: a field plate electrically connected to the gate and located above the gate and the first ohmic electrode.

14. The high electron mobility transistor device of claim 9, wherein, Further comprising: a second ohmic electrode having an ohmic contact with the semiconductor stack and electrically connected to the first Schottky electrode; and a second Schottky electrode having a Schottky contact with the semiconductor stack, wherein the second Schottky electrode and the semiconductor stack form a second Schottky diode, the first Schottky diode and the second Schottky diode are connected in series between the source and the gate. The second ohmic electrode is between the first ohmic electrode and the gate.

15. The high electron mobility transistor device of claim 14, wherein, The source, the first Schottky electrode and the second Schottky electrode are arranged along the second direction, and the first ohmic electrode, the second ohmic electrode and the gate are arranged along the second direction.

16. The high electron mobility transistor device of claim 14, wherein, ​

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