silicon carbide semiconductor devices

Abstract

A silicon carbide semiconductor device includes a semiconductor element having a first conductivity type region (4), a gate trench structure, an interlayer insulating film (9), a first electrode (10), and a recess (12). The gate trench structure has a gate trench (6). The first electrode includes a metal layer (10a), a blocking metal (10b), an electrode layer (10c), and protrusions (10bc). The protrusions have a first protrusion and a second protrusion respectively disposed on both sides of the gate trench. The electrode layer has a portion embedded in the recess. The distance (W1) between the tip of the first protrusion and the tip of the second protrusion in the width direction of the gate trench is less than the width (W2) of the portion of the electrode layer below the protrusion.

Description

Technical Field

[0001] This disclosure relates to a silicon carbide (SiC) semiconductor device including a semiconductor element having a trench-gate structure made of silicon carbide. Background Technology

[0002] JP 2019-3967 A discloses a SiC semiconductor device with a trench gate structure that reduces cell pitch without increasing on-resistance. In this SiC semiconductor device, an interlayer insulating film and a barrier metal are embedded in the gate electrode within the gate trench to flatten the surface, and a source electrode with the barrier metal and electrode layer is formed on said surface by forming an electrode layer. Using this structure, since it is not required to expose the interlayer insulating film to the top surface of the SiC, it is possible to form contacts across the entire top surface, and there are fewer restrictions on cell pitch due to mask misalignment during contact hole formation. Therefore, it is possible to further reduce the cell pitch. Summary of the Invention

[0003] When a semiconductor device, such as a metal-oxide-semiconductor field-effect transistor (MOSFET), operates, its temperature repeatedly rises and falls. Because the different types of constituent materials in a semiconductor device have different coefficients of linear expansion, stress is repeatedly applied to the interfaces between these materials due to the temperature fluctuations. Therefore, if the MOSFET has a trench gate structure, the source electrode may be stripped.

[0004] In SiC semiconductor devices as described in JP 2019-3967 A, when the surface of the gate electrode within a gate trench structure having an embedded interlayer insulating film and an embedded barrier metal is planarized and the electrode layer is formed on this surface, the anchoring effect may be reduced due to the lower surface roughness. In other words, if the surface has roughness, the lateral misalignment between the electrode layer and the underlying layer is suppressed by the inhomogeneity caused by the roughness. However, if the surface has low roughness, lateral misalignment between the electrode layer and the underlying layer may occur, potentially causing the source electrode to be stripped.

[0005] When the source electrode is stripped, the resistance increases when current is applied. This causes a temperature rise due to heat generation, and the component may break down.

[0006] One object of this disclosure is to provide a SiC semiconductor that suppresses electrode stripping on a trench gate structure and suppresses device breakdown due to heat generation.

[0007] According to one aspect of this disclosure, a SiC semiconductor includes a semiconductor element having a substrate, a drift layer, a channel layer, a first conductivity type region, a gate trench structure, an interlayer insulating film, a first electrode, a second electrode, and a recess. The substrate is made of silicon carbide and is of either a first conductivity type or a second conductivity type. The drift layer is of the first conductivity type and is disposed on the substrate, and the drift layer has a lower impurity concentration than the substrate. The channel layer is of the second conductivity type and is disposed on the drift layer, and the channel layer has a surface layer portion with a contact region disposed thereon. The first conductivity type region is of the first conductivity type and has a higher impurity concentration than the drift layer. The first conductivity type region is disposed on the channel layer at a location different from the contact region. The gate trench structure has a gate trench, a gate insulating film, and a gate electrode. The gate trench penetrates the first conductivity type region and the channel layer. The gate insulating film is disposed on the inner wall surface of the gate trench. The gate electrode is disposed on the gate insulating film. The interlayer insulating film covers the gate electrode within the gate trench. The first electrode is electrically connected to the contact area and the first conductivity type area. The second electrode is disposed on the side closer to the back side of the substrate. The recess is provided by a step between the top surface of the interlayer insulating film and the top surface of the first conductivity type area. The first electrode includes a metal layer, a barrier metal, and an electrode layer. The metal layer is disposed on the surface of each of the contact area and the first conductivity type area. The barrier metal is disposed on the metal layer and within the recess. The electrode layer is disposed on the barrier metal layer. The barrier metal includes a first barrier metal portion and a second barrier metal portion. The first barrier metal portion is disposed within the recess. The second barrier metal portion is disposed on the metal layer. A step is provided between the first barrier metal portion and the second barrier metal portion. The first electrode also includes a protrusion disposed at the second barrier metal portion and projecting toward the interior of the gate trench in the width direction of the gate trench. The protrusion has a first protrusion and a second protrusion respectively disposed on both sides in the width direction of the gate trench. The electrode layer has a portion embedded in the recess below the protrusion. The distance between the tip of the first protrusion and the tip of the second protrusion in the width direction of the grid groove is less than the width of the portion of the electrode layer below the protrusion in the width direction of the grid groove.

[0008] According to the above structure, a step is formed between the first blocking metal portion and the second blocking metal portion. That is, the base surface of the electrode layer has a surface roughness. The second blocking metal portion includes a protrusion that projects in an eaves shape toward the inner side of the gate trench in the width direction. The distance between the tips of the first protrusion and the tips of the second protrusion, located on opposite sides of the gate trench, is less than the width of the portion of the electrode layer embedded in the recess below the protrusion. Therefore, the electrode layer can have an anchoring effect. Even when the temperature repeatedly rises and falls during semiconductor device operation, the electrode layer is unlikely to peel off from the underlying blocking metal. Therefore, peeling of the source electrode can be prevented. The increase in resistance and the temperature rise caused by heat generation when current is applied can be suppressed, and device breakdown can be prevented. Attached Figure Description

[0009] The above-described objects, features, and advantages of this disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. In the drawings:

[0010] Figure 1 This is a cross-sectional view of the SiC semiconductor device according to the first embodiment;

[0011] Figure 2 It is a cross-sectional view showing the structure of the source electrode;

[0012] Figure 3 This is a cross-sectional view of the source electrode structure when the blocking metal is made of a stacked structure;

[0013] Figure 4 This is a flowchart illustrating the formation of the trench gate structure and the source electrode in a SiC semiconductor device according to the first embodiment;

[0014] Figure 5A This is an example in Figure 4 A cross-sectional view of the state after the grid trenches have been formed;

[0015] Figure 5B This is an example in Figure 4 Cross-sectional view of the state after back-etching;

[0016] Figure 5C This is an example in Figure 4 A cross-sectional view of the state after the interlayer insulating film has been formed;

[0017] Figure 5D This is an example in Figure 4 Cross-sectional view of the back side of the interlayer insulating film after etching;

[0018] Figure 5E This is an example in Figure 4 A cross-sectional view of the state after the metal film has formed in the middle;

[0019] Figure 5F This is an example in Figure 4 A cross-sectional view of the state after the metal film has been removed;

[0020] Figure 5G This is an example in Figure 4 A cross-sectional view of the state after the formation of the blocking metal;

[0021] Figure 5H This is an example in Figure 4 A cross-section of the state after the electrode layer has been formed;

[0022] Figure 6A It is a cross-sectional view of the gate electrode with an embedded interlayer insulating film and a gate trench containing barrier metal, where the surface is planarized.

[0023] Figure 6B This is a cross-sectional view illustrating the stripping of the source electrode;

[0024] Figure 7 This is a cross-sectional view illustrating the structure of the source electrode of the SiC semiconductor device in a modified example of the first embodiment;

[0025] Figure 8 This is a flowchart illustrating the formation of the trench gate structure and source electrode in a SiC semiconductor device according to the second embodiment;

[0026] Figure 9A This is an example in Figure 8 A cross-sectional view of the state after the interlayer insulating film has been formed;

[0027] Figure 9B This is an example in Figure 8 Cross-sectional view of the back side of the interlayer insulating film after etching;

[0028] Figure 9C This is an example in Figure 8 A cross-sectional view of the state after the metal film has formed in the middle;

[0029] Figure 9D This is an example in Figure 8 A cross-sectional view of the state after the metal film has been removed;

[0030] Figure 9E This is an example in Figure 8 A cross-sectional view of the state after the gate contact hole is formed;

[0031] Figure 9F This is an example in Figure 8 A cross-sectional view of the state after the formation of the blocking metal; and

[0032] Figure 9G This is an example in Figure 8A cross-sectional view of the state after the electrode layer has been removed. Detailed Implementation

[0033] Several embodiments of this disclosure will now be described with reference to the accompanying drawings. In the following embodiments, the same or equivalent parts are denoted by the same reference numerals.

[0034] (First Embodiment)

[0035] The first embodiment is described below. A SiC semiconductor device according to the first embodiment is described below. This embodiment describes an example of a SiC semiconductor device formed from a MOSFET, which is a semiconductor element having a trench gate structure.

[0036] The SiC semiconductor device according to this embodiment includes, for example, Figure 1 The figure shows a vertical MOSFET with a trench gate structure. Vertical MOSFETs are formed in the cell region of a SiC semiconductor device, and the semiconductor device is fabricated by forming a high breakdown voltage structure around the cell region; however, only vertical MOSFETs are shown in the figure. In the following description, [the following will be used to describe...]. Figure 1 The horizontal direction is taken as the width direction of the SiC semiconductor device, and the vertical direction is taken as the thickness or depth direction of the SiC semiconductor device.

[0037] In SiC semiconductor devices, n-type semiconductors made of SiC are used. + Type 1 substrate is used as a semiconductor substrate. For example... Figure 2 As shown, n made of SiC is used + - A type substrate 1 is used to form SiC semiconductor devices. In n + On the main surface of type substrate 1, n - --type drift layer 2, p-type base region 3 and n + - The source pole region 4 is made of SiC and grown sequentially epitaxially.

[0038] The p-type base region 3 is the portion where the channel region is formed. The p-type base region 3 forms a p-type contact region 3a, in which the p-type contact region 3a, in conjunction with n… + The concentration of p-type impurities increases locally in the surface layer portion at different locations of the p-type source region 4. + -Type source region 4 has a higher density than n - The p-type drift layer 2 has a higher impurity concentration. The p-type base region 3 can also be called the channel layer. + - The source region 4 can also be called the first conductivity type region.

[0039] In addition, a gate trench 6 is formed to penetrate the p-type base region 3 and n-type base region 4. +-Type source pole region 4 and reach n - p-type drift layer 2. p-type base region 3 and n + The source region 4 is arranged to contact the side surface of the gate trench 6. The gate trench 6 is provided in a linear arrangement. Figure 1 The horizontal direction is used as the horizontal or width direction. Figure 1 The normal direction of a view is taken as the longitudinal or length direction, and the direction perpendicular to the lateral and longitudinal directions is taken as the depth direction. Although in Figure 1 Only one gate trench 6 is shown in the image, but in Figure 2 Multiple gate trenches 6 are arranged at regular intervals in the transverse direction. Although the width of the gate trenches 6 is arbitrary, the width of the gate trenches 6 can be twice or more the thickness of the blocking metal 10b, and is in the range of 0.3 to 1 micrometer (μm). For example, the width of the gate trenches 6 is set to 1 μm.

[0040] The portion of the p-type base region 3 located on the side surface of the gate trench 6 is connected to n when the vertical MOSFET is operating. + -Type source pole region 4 and n - The gate trench 6 has a channel region in the type-2 drift layer. A gate insulating film 7 is formed on the inner wall surface of the gate trench 6, including the channel region. A gate electrode 8 made of polysilicon is formed on the surface of the gate insulating film 7. The gate electrode 8 is n-type doped or p-type doped. An interlayer insulating film 9 is formed on the gate insulating film 7 and the gate electrode 8 to form a trench gate structure. The gate trench 6 is not completely filled by the gate insulating film 7, the gate electrode 8, and the interlayer insulating film, but is filled with... Figure 2 A portion of the barrier metal 10ba and electrode layer 10c described below are shown.

[0041] The top surface of the gate electrode 8 is lower than n, which is included in the inlet of the gate trench 6. + - The top surface of the source region 4, and the top surface of the gate electrode 8 with n + A step is formed between the top surfaces of the source region 4, causing the gate electrode 8 to be formed in a recessed shape. A portion of the interlayer insulating film 9, the barrier metal 10ba, and the electrode layer 10c are arranged in a recessed shape to fill the step, thereby filling the gate trench 6. Even after the interlayer insulating film 9 is formed on the gate electrode 8, the recessed shape is maintained, forming a recess 12 with a depth in the range of 40 to 300 nanometers (nm) (e.g., around 200 nm). Therefore, a portion of the barrier metal 10ba and a portion of the electrode layer 10c are formed to fill the recess 12 contained in the recessed shape. In other words, the bottom surface of the barrier metal 10ba is located within the recess formed by the n... +Below the SiC surface, the p-type source region 4 and the p-type contact region 3a are formed. A barrier metal 10ba is formed as a filled recess 12, and the top surface of the barrier metal 10ba is located below the SiC surface. Subsequently, a portion of the barrier metal 10ba and a portion of the electrode layer 10c are embedded in the recess 12.

[0042] Furthermore, a source electrode 10 and a gate wiring layer (not shown) are formed, for example, on the interlayer insulating film 9. The source electrode 10 corresponds to the first electrode. The source electrode 10 is connected to the n electrode through a contact hole in the interlayer insulating film 9. + --type source region 4 and p-type contact region 3a are in contact. The gate wiring portion is in contact with... Figure 1 The cross-sections shown are in contact with the gate electrode 8 in different cross-sections.

[0043] like Figure 2 As shown, the source electrode 10 includes a metal silicide layer 10a, a barrier metal 10b, and an electrode layer 10c.

[0044] The metal silicide layer 10a is an ohmic contact layer that undergoes a silicide reaction with SiC. With the formation of the metal silicide layer 10a, an ohmic contact with low contact resistance is formed between the source electrode 10 and the SiC. The metal silicide layer 10a is made of silicides of high-melting-point metals or noble metals, such as nickel silicide (Ni), titanium silicide (Ti), tantalum silicide (Ta), tungsten silicide (W), and molybdenum silicide (Mo). The metal contained in the metal silicide layer 10a can be of a single type or multiple types. For example, the type of metal contained in the metal silicide layer 10a can differ between n-type SiC and p-type SiC. For example, in this embodiment, the metal silicide layer 10a is made of nickel silicide. Although the thickness of the metal silicide layer 10a is arbitrary, it is set in the range of 10 to 100 nm, for example, approximately 50 nm.

[0045] The barrier metal 10b includes a barrier metal 10ba formed on the interlayer insulating film 9 and a barrier metal 10bb formed on the metal silicide layer 10a. The barrier metal 10ba corresponds to a first barrier metal or a first barrier metal portion, and the barrier metal 10bb corresponds to a second barrier metal or a second barrier metal portion. The barrier metal 10ba inhibits, for example, the diffusion of metal elements from the side closer to the source electrode 10 to the interlayer insulating film 9 and the gate electrode 8. The barrier metal 10bb inhibits, for example, the diffusion of metal elements from the metal silicide layer 10a in the source electrode 10 to the electrode layer 10c. When the metal silicide layer 10a is made of nickel silicide, the barrier metal 10ba inhibits the diffusion of Ni to the interlayer insulating film 9 and the gate electrode 8, and the barrier metal 10bb inhibits the diffusion of Ni to the electrode layer 10c. The barrier metal 10b is made of a metal that satisfies the above functions, such as titanium (Ti) or titanium nitride (TiN). Although Figure 2 The example illustrates that the barrier metal 10b is made of a single-layer structure; the barrier metal 10b can also be made of, for example... Figure 3 The structure shown is made of a stacked structure containing multiple metals such as Ti and TiN. The stacked structure can also be called a layered structure.

[0046] Although the barrier metals 10ba and 10bb are formed simultaneously, they are not formed on the same plane. A step is formed between the barrier metals 10ba and 10bb, such that the top surface of the barrier metal 10bb is above the top surface of the barrier metal 10ba. Furthermore, the barrier metals 10ba and 10bb are separated from each other. Although the thickness of the barrier metal 10b is arbitrary, it is less than or equal to the depth of the recess 12. In the case where the barrier metal 10b is made of a stacked structure having Ti and TiN, Ti has a thickness in the range of 30 to 100 nm, for example, 50 nm; and TiN has a thickness in the range of 50 to 100 nm, for example, 100 nm.

[0047] Because the thickness of the blocking metal 10b is less than or equal to the depth of the recess 12, the blocking metal 10ba is positioned below the SiC surface, and the hollow portion of the recess 12 remains even with the blocking metal 10ba disposed therein. In other words, the depth D1 of the recess 12 is greater than the thickness D2 of the blocking metal 10ba. Therefore, when a rough surface exists on the SiC, an electrode layer 10c is formed, and a portion of the electrode layer 10c is embedded in the recess 12. In this embodiment, the SiC is exposed at its top position on the side closer to the gate trench 6, and a portion of the electrode layer 10c is in contact with the SiC.

[0048] The barrier metal 10bb has a protrusion 10bc that protrudes from the metal silicide layer 10a toward the inside of the gate trench 6 in the width direction of the gate trench 6. The distance W1 between adjacent tips of the protrusion 10bc on both sides in the width direction of the gate trench 6 is smaller than the width W2 of the portion of the electrode layer 10c embedded below the protrusion 10bc. The protrusion amount of the protrusion 10bc can be adjusted according to the film formation conditions of the barrier metal 10b. The protrusion 10bc can protrude to the same level as the thickness of the portion of the barrier metal 10b formed on the metal silicide layer 10a. In this embodiment, the protrusion amount of the protrusion 10bc is set to half or more of the thickness of the portion of the barrier metal 10b formed on the metal silicide layer 10a. The protrusion 10bc can also be simply referred to as a protrusion, and the protrusion has a first protrusion and a second protrusion on both sides of the gate trench 6, respectively. In other words, the distance W1 between the tip of the first protrusion and the tip of the second protrusion in the width direction is smaller than the width W2 of the portion of the electrode layer 10c embedded below the protrusion 10bc.

[0049] Electrode layer 10c is a portion included in the pad portion of source electrode 10. Electrode layer 10c is made of a metal including aluminum (Al), such as aluminum silicon (AlSi). Electrode layer 10c is formed to be thicker than metal silicide layer 10a and barrier metal 10b. Electrode layer 10c is embedded in gate trench 6, including the portion below protrusion 10bc, through a gap of size W1. Because electrode layer 10c is embedded in the portion below protrusion 10bc, it can have an anchoring effect.

[0050] This embodiment describes the electrode layer 10c as being made of a single-layer structure. However, the electrode layer 10c can be made of a stacked structure by electroplating the surface with nickel (Ni) or gold (Au).

[0051] In addition, with electrical connection to n + The drain electrode 11 corresponding to the second electrode of the type substrate 1 is formed on n + On the back side of substrate 1, a vertical MOSFET with an n-channel inverted type trench-gate structure is provided using this structure. A cell region is formed by placing the aforementioned vertical MOSFET cells. A SiC semiconductor device is provided by forming an external voltage-resistant structure, such as a guard ring (not shown) or the like, around the cell region in which such a vertical MOSFET is formed.

[0052] The following reference Figure 4 The flowchart and corresponding process in manufacturing Figures 5A to 5HThe cross-sectional view in the figure illustrates a method for manufacturing a SiC semiconductor device according to this embodiment. Since devices other than the gate electrode 8 can be formed in any manner, the method for forming the gate electrode 8 will be mainly described below.

[0053] First, n-type silicon wafers made of SiC and formed into wafer shape are prepared. + -Type substrate 1, then in n + n is epitaxially grown on the main surface of type substrate 1. - p-type drift layer 2. p-type base region 3 and n + -Type source region 4 is formed on n through epitaxial growth or ion implantation. - - On type drift layer 2. In n + A mask (not shown) is formed on the main surface of the p-type source region 4, and a p-type contact region 3a is formed by ion implantation of p-type impurities. Next, a mask (not shown) is arranged on the surfaces of the p-type base region 3 and the n+-type source region 4, and the mask has apertures located in the regions where the trench gate structure is to be formed. These apertures correspond to openings.

[0054] Subsequently, as Figure 4 As shown, gate trench 6 is formed. For example, anisotropic etching, such as reactive ion etching (RIE), is performed using a mask to form a trench as shown. Figure 5A The gate trench 6 in the middle. After removing the mask, as... Figure 4 As shown, a gate insulating film 7 is formed. For example, a silicon oxide film is formed by chemical vapor deposition (CVD), and a thermal oxide film is formed by thermal oxidation. Thus, a gate insulating film 7 is formed.

[0055] Subsequently, as Figure 4 As shown, polysilicon formation and back-side etching are performed to form the gate electrode 8 within the gate trench 6, as... Figure 5B As shown. In other words, after forming a polysilicon film on the surface of the gate insulating film 7 by, for example, CVD to fill the gate trench 6, the polysilicon is back-etched by dry etching to remove the portion formed outside the gate trench 6. At this time, the polysilicon is back-etched until the interior of the gate trench 6 is recessed, so that the interior of the gate trench 6 is not completely filled by the gate electrode 8.

[0056] Subsequently, when Figure 4 As shown, during the formation of the interlayer insulating film 9, the interlayer insulating film 9 is formed on the gate electrode 8 to fill the interior of the gate trench 6, as... Figure 5C As shown in the figure. For example, an interlayer insulating film 9 can be formed by, for example, low-pressure CVD. (Performance) Figure 4 The back side of the interlayer insulating film 9 shown is etched. (As shown) Figure 5DAs shown, the interlayer insulating film 9 is exposed to expose the SiC surface by, for example, dry etching, while leaving the interlayer insulating film 9 on the gate electrode 8. Simultaneously, the back side of the interlayer insulating film 9 is etched by, for example, dry etching to form the recessed shape of the recess 12. Although the depth of the recess 12 is arbitrary, for example, the depth of the recess 12 is approximately 200 nm.

[0057] Subsequently, as Figure 4 As shown, the process involves forming a metal film and a silicide through heat treatment. Figure 5E As shown, a metal film 20 for forming a metal silicide layer 10a is formed. A Ni film is formed by Ni sputtering. At this time, since the recess 12 is maintained in the gate trench 6, a step is formed at the metal film 20 between the position on the gate trench and the outside of the gate trench 6 when the metal film 20 is formed.

[0058] A heat treatment is performed in the range of 600 to 800 degrees Celsius (e.g., 700 degrees Celsius) to induce a silicide reaction between the metal contained in the metal film 20 and the Si inside the SiC. As a result, the metal film 20 undergoes a silicide reaction on the SiC surface, while the metal film 20 on the interlayer insulating film 9 remains without undergoing a silicide reaction.

[0059] Subsequently, as Figure 4 As shown, the metal film 20 is removed to remove the metal film 20 retained on the interlayer insulating film 9, as follows. Figure 5F For example, the metal film 20 is removed by wet etching. As a result, the metal silicide layer 10a remains only on the SiC surface. Even on the SiC surface, not all of the metal film 20 undergoes silicide reaction; the metal film 20 may remain on the metal silicide layer 10a. In this case, the metal film 20 retained on the metal silicide layer 10a is also removed simultaneously. The metal silicide layer 10a is formed by the above heat treatment. If the temperature of the heat treatment is increased at this time, the metal elements contained in the metal film 20 can diffuse into the interlayer insulating film 9. For this purpose, the above heat treatment can be maintained at a relatively low temperature of 800 degrees Celsius or lower, and high-temperature annealing can be performed in the range of 900 to 1000 degrees Celsius (e.g., 950 degrees Celsius) after the metal film 20 is removed. Therefore, the contact resistance between the metal silicide layer 10a and SiC can be further reduced.

[0060] In addition, the execution of such Figure 4 The formation of the barrier metal 10b is shown. For example, the barrier metal 10b can be selectively deposited on the metal silicide layer 10a and the interlayer insulating film 9 by sputtering. In this embodiment, the barrier metal 10b is formed by sequentially sputtering Ti and TiN. However, for example, a monolayer film such as Ti or TiN and other types of materials can be sputtered to form the barrier metal 10b. As a result, as Figure 5GAs shown, barrier metal 10b is formed on metal silicide layer 10a and interlayer insulating film 9. Barrier metal 10bb on metal silicide layer 10a is formed to be distributed in the lateral direction and surround the interior of gate trench 6, and protrusions 10bc are formed in an eaves shape. As the energy decreases, for example during sputtering, barrier metal 10b can be deposited more isotropically, thus the size of protrusions 10bc can be adjusted by controlling the energy during sputtering.

[0061] At this point, since a step is formed between the interlayer insulating film 9 and the metal silicide layer 10a, this step is further inherited by the barrier metal 10b formed on the metal silicide layer 10a and the interlayer insulating film 9. In this embodiment, the depth D1 of the recess 12 is greater than the thickness D2 of the barrier metal 10b. Therefore, the barrier metal 10ba on the interlayer insulating film 9 and the barrier metal 10bb on the metal silicide layer 10a are formed separately. The protrusion 10bc can be formed into a stable eaves shape without forming the barrier metal 10b on the SiC surface of the separated portion.

[0062] Subsequently, the execution was as follows Figure 4 The electrode layer 10c is shown to be formed. For example, AlSi is sputtered. As a result, the electrode layer 10c is formed on the barrier metal 10b, such as... Figure 5H As shown in the diagram, electrode layer 10c is also formed around the lower portion of protrusion 10bc, and a portion of electrode layer 10c is inserted into recess 12. Source electrode 10 is formed by patterning electrode layer 10c and blocking metal 10b using a mask (not shown).

[0063] Additionally, in n + A drain electrode 11 is formed on the back side of a substrate 1. Thus, a SiC semiconductor device with a vertical MOSFET according to this embodiment is completed.

[0064] In the SiC semiconductor device according to this embodiment, a step is formed between the barrier metal 10ba formed on the surface of the interlayer insulating film 9 and the barrier metal 10bb formed on the metal silicide layer 10a. That is, the surface of the base of the electrode layer 10c has a surface roughness. The barrier metal 10bb includes a protrusion 10bc formed in an eaves shape inside the trench and protruding in the width direction of the gate trench 6, such that the dimension W1 is smaller than the dimension W2. A portion of the electrode layer 10c is located below the protrusion 10bc. Therefore, the SiC semiconductor device according to this embodiment differs from the SiC semiconductor device disclosed in JP 2019-3967A. The electrode layer 10c in this embodiment is capable of having an anchoring effect.

[0065] In the SiC semiconductor device described in JP 2019-3967 A, an interlayer insulating film J3 and a barrier metal J4 are embedded in the gate electrode J2 to planarize the surface inside the gate trench J1, as shown below. Figure 6A As shown. The stacked film J5 has Ni and Ti films, and the electrode layer J6 is made of AlSi. When the stacked film J5 and the electrode layer J6 are formed on the barrier metal J4 and the SiC surface, a source electrode including the barrier metal J4, the stacked film J5, and the electrode layer J6 is formed. Using this structure, since a flat surface with low roughness is formed through the SiC surface and the barrier metal J4, there are no steps included, for example, in the electrode layer J6. Therefore, as... Figure 6B As shown, for example, electrode layer J6 is peeled off at the interface with stacked film J5, thereby the source electrode is peeled off.

[0066] In contrast, in the SiC semiconductor device according to this embodiment, the surface of the electrode layer 10c base is roughened, and a portion of the electrode layer 10c is embedded beneath the protrusion 10bc. Therefore, the electrode layer 10c can have an anchoring effect. Even with repeated temperature increases and decreases during semiconductor device operation, the electrode layer 10c is unlikely to peel off from the underlying barrier metal 10b. Therefore, peeling of the source electrode 10 can be prevented. Temperature rise caused by increased resistance and heat generation when current is applied can be suppressed, and device breakdown can be prevented.

[0067] Furthermore, the following effects can be obtained in the SiC semiconductor of this embodiment.

[0068] In the SiC semiconductor device according to this embodiment, an electrode layer 10c is formed in a state where the recess 12 is held at the gate trench 6 by making the depth D1 greater than the thickness D2 (in other words, in a state where there is roughness at the SiC surface), and a portion of the electrode layer 10c moves into the recess 12. Therefore, a portion of the electrode layer 10c penetrates deeper, and a higher anchoring effect can be obtained. Thus, the above-mentioned effects can be further obtained.

[0069] The barrier metal 10ba on the interlayer insulating film 9 and the barrier metal 10bb on the SiC surface are not made into flat surfaces, but are made into a step between the barrier metal 10ba and the barrier metal 10bb. Because the residual stress of the barrier metal 10b can be dissipated, SiC semiconductor devices that suppress the effects caused by residual stress and warpage of the wafer can be manufactured.

[0070] In the SiC semiconductor device described in JP 2019-3967 A, since the barrier metal is made of Ti or TiN, the Ni film and Ti film used to form the metal silicide are formed sequentially by sputtering, thus increasing the number of sputtering operations. Conversely, in the SiC semiconductor device according to this embodiment, only the metal film 20 used to form the metal silicide layer 10a and the barrier metal 10b are formed by sputtering. Since sputtering is typically performed via single-wafer processing, the number of sputtering operations increases the manufacturing cost of the SiC semiconductor device. If the number of sputtering operations can be reduced in the SiC semiconductor device according to this embodiment, the manufacturing process of the SiC semiconductor device can be simplified, and the manufacturing cost can be further reduced.

[0071] (Modification of the first embodiment)

[0072] The first embodiment describes that the blocking metal 10ba and the blocking metal 10bb are separated from each other, and they can be as follows: Figure 7 The connection is shown. In this case, since the barrier metal 10b is more easily formed on the metal silicide layer 10a compared to the SiC surface, the protrusion 10bc is formed at the tip of the metal silicide layer 10a.

[0073] In the first embodiment, the recess 12 remains recessed even after the barrier metal 10ba is formed. However, the surface of the barrier metal 10ba can be flush with the SiC surface, or the surface of the barrier metal 10ba can protrude from the SiC surface.

[0074] In other words, there is a step between the blocking metal 10ba and the blocking metal 10bb, and a protrusion 10bc is formed at the blocking metal 10bb. As long as the distance W1 between adjacent tips of the protrusion 10bc is shorter than the width W2 of the portion of the electrode layer 10c embedded below the protrusion 10bc, the same effect as in the first embodiment can be obtained even with this structure.

[0075] (Second Embodiment)

[0076] The second embodiment is described below. This embodiment differs from the first embodiment in the formation of the gate wiring portion; the other parts are the same as the first embodiment. Therefore, only the differences from the first embodiment are described.

[0077] In this embodiment, refer to Figure 8 , 9A The description up to 9G describes, for example, the formation of a gate trench structure at the tip of the gate electrode 8 in the longitudinal direction, which is connected to the gate wiring portion. Figures 9A to 9G These are cross-sectional views of each process step. Figures 9A to 9G The left image for each is a cross-sectional view of a vertical MOSFET, and Figures 9A to 9GThe right figure for each of them is a cross-sectional view of a location other than the vertical MOSFET, for example, the gate wiring portion formed in the connection region between the cell region and the peripheral high-breakdown structure.

[0078] Figure 8 The formation of the gate trench 6, the gate insulating film 7, and the silicon film shown are the same as in the first embodiment. In this case, the gate insulating film 7 is formed on the SiC surface, and the polysilicon film is also formed on the gate insulating film 7 at the location where the gate wiring portion is formed. Subsequently, the polysilicon film is patterned by back-side etching, and the gate electrode 8 is formed inside the gate trench 6, as shown. Figure 9A As shown, a gate wiring layer 31 is formed within a portion of the gate wiring portion at another location. In the formation of the interlayer insulating film 9, the interlayer insulating film 9 is formed to be embedded in the gate electrode 8 inside the gate trench 6 and to cover the gate wiring layer 31. Perform as follows... Figure 8 The back side etching of the interlayer insulating film 9 is shown. At this time, the cell region where the vertical MOSFET is formed has apertures, and a mask (not shown) covering the area other than the cell region is formed on the interlayer insulating film 9 for back side etching. Figure 9B In this process, the gate wiring layer 31 is covered by the interlayer insulating film 9, and the interlayer insulating film 9 is only kept inside the gate trench 6 in the cell region.

[0079] Subsequently, the formation of the metal film 20 is performed, through... Figure 8 The heat treatment process illustrates the formation of silicides and the removal of the metal film 20. As a result, the metal film 20 is formed on the SiC surface and the interlayer insulating film 9 and undergoes silicide formation, as shown. Figure 9C As shown. After siliconization, as Figure 9D As shown, the metal film 20 on the interlayer insulating film 9 is removed to form a metal silicide layer 10a on the SiC surface. Since the gate wiring layer 31 is covered by the interlayer insulating film 9, the gate wiring layer 31 is still covered by the interlayer insulating film 9 even if the metal film 20 on the interlayer insulating film 9 is removed.

[0080] Subsequently, as Figure 8 As shown, photolithography is performed on the gate wiring portion. In the photolithography process, after the mask (not shown) has apertures at locations corresponding to the gate wiring layer 31, etching is performed to form apertures in the interlayer insulating film 9 at the gate contact apertures 9a connected to the gate wiring layer 31, as shown. Figure 9E As shown in the image. Furthermore, execution is as follows: Figure 8 The barrier metal 10b shown is formed, for example, by sequentially sputtering Ti and TiN. At this time, as... Figure 9FAs shown, since the gate contact hole 9a is formed, the blocking metal 10b is formed to contact the gate wiring layer 31.

[0081] Furthermore, if metals are used as materials undergoing silicide reactions, then in performing processes such as... Figure 8 During the heat treatment shown, metal silicide is formed at the contact portion between the gate wiring layer 31 and the barrier metal 10b, thereby forming an ohmic contact layer. For example, the heat treatment is performed in the range of 600 to 800 degrees Celsius, for example at a temperature of 700 degrees Celsius. As a result, the metal forming the barrier metal 10b and the polysilicon forming the gate wiring layer 31 undergo a silicide reaction to form a metal silicide layer. As a result, for example, Ti can be used together to form the barrier metal 10b and to form the ohmic contact layer with the gate wiring layer 31.

[0082] Furthermore, the barrier properties of TiN can be improved by oxidation or annealing. Therefore, when using TiN as the barrier metal 10b, TiN can be oxidized by exposing the sample to the atmosphere after the TiN film is formed. During oxidation, exposure to the atmosphere allows oxidation without increasing process costs. Annealing TiN using the aforementioned heat treatment can further improve its barrier properties.

[0083] Subsequently, the following is performed via sputtering, for example, AlSi. Figure 8 The electrode layer 10c shown is formed. As a result, the electrode layer 10c is formed on the barrier metal 10b, as... Figure 9G As shown in the figure. When the electrode layer 10c and the barrier metal 10b are patterned using a mask (not shown), the source electrode 10 is formed; and a gate wiring portion including the gate wiring layer 31 and the barrier metal 10b connected to the gate wiring layer 31 and the electrode layer 10c is formed.

[0084] Finally, in n + A drain electrode 11 is formed on the back side of a substrate 1. Thus, a SiC semiconductor device having a vertical MOSFET and a gate wiring portion according to this embodiment is completed.

[0085] As described above, when forming the source electrode 10 in a vertical MOSFET, the gate wiring portion can be formed by using a barrier metal 10b and an electrode layer 10c. When a metal is used for silicide reaction with the barrier metal 10b, an ohmic contact layer can be obtained by performing heat treatment. When TiN is used for the barrier metal 10b, the barrier performance can be improved by exposure to the atmosphere or heat treatment.

[0086] (Other embodiments)

[0087] Although this disclosure has been described with reference to the embodiments described above, this disclosure is not limited to these embodiments and includes various modifications and equivalent modifications. Furthermore, while various elements are shown in various exemplary combinations and configurations, other combinations and configurations including more, fewer, or only a single element are also within the spirit and scope of this disclosure.

[0088] The above embodiments describe a vertical MOSFET with a trench gate structure. However, other structures can also use a vertical MOSFET as the basic structure. For example, when a p-type deep layer is included below the trench gate structure, various structures can be provided, such as structures for suppressing the rise of the equipotential line to the trench gate structure to improve the breakdown voltage.

[0089] Each of the above embodiments has described a structure in which a metal silicide layer 10a is formed on the SiC surface as a metal layer; and a barrier metal 10bb and an electrode layer 10c are sequentially arranged on the metal silicide layer 10a. However, metals other than the metal silicide layer 10a can be arranged as metal layers.

[0090] In the above embodiments, an n-channel vertical MOSFET in which the first conductivity type is n-type and the second conductivity type is p-type has been described as an example. Optionally, the conductivity type of each element can be reversed to form a p-channel vertical MOSFET. In the above description, a vertical MOSFET has been described as an example of a semiconductor element with a trench gate structure. Optionally, this disclosure can be applied to IGBTs having a similar trench gate structure. In the case of an n-channel IGBT, in each of the above embodiments, n + The conductivity type of substrate 1 is changed from n-type substrate to p-type substrate, and the structure and manufacturing method are the same as those in each of the above embodiments, except that n + The conductivity type of substrate 1 changes from that of an n-type substrate to that of a p-type substrate.

Claims

1. A silicon carbide semiconductor device, comprising: Semiconductor devices, including A substrate made of silicon carbide and of a first or second conductivity type; a drift layer of the first conductivity type disposed on the substrate; the drift layer having a lower impurity concentration than the substrate. A channel layer, which is of the second conductivity type, is disposed on the drift layer, the channel layer having a surface layer portion, and a contact area is disposed on the surface layer portion. A first conductivity type region, which is of the first conductivity type and has a higher impurity concentration than the drift layer, is disposed on the channel layer at a different location than the contact region. A gate trench structure has a gate trench, a gate insulating film, and a gate electrode. The gate trench penetrates the first conductivity type region and the channel layer. The gate insulating film is disposed on the inner wall surface of the gate trench, and the gate electrode is disposed on the gate insulating film. An interlayer insulating film covers the gate electrode inside the gate trench. A first electrode is electrically connected to the contact area and the first conductivity type area. The second electrode is disposed on a side closer to the back surface of the substrate, and The recess is provided by a step between the top surface of the interlayer insulating film and the top surface of the first conductivity type region. The first electrode includes: A metal layer is disposed on the surface of each of the contact area and the first conductivity type area; A blocking metal, disposed on the metal layer and within the recess; and An electrode layer, which is disposed on the barrier metal, The blocking metal includes: A first blocking metal portion disposed within the recess; and The second blocking metal portion is arranged on the metal layer. A step is provided between the first blocking metal part and the second blocking metal part. The first electrode further includes a protrusion disposed at the second blocking metal portion and protruding toward the interior of the gate trench in the width direction of the gate trench. The protrusion has a first protrusion and a second protrusion respectively arranged on both sides of the width direction of the grid groove. The electrode layer has a portion embedded in the recess below the protrusion, and Wherein, the distance (W1) between the tip of the first protrusion and the tip of the second protrusion in the width direction of the gate groove is less than the width (W2) of the portion of the electrode layer below the protrusion in the width direction of the gate groove.

2. The silicon carbide semiconductor device according to claim 1, in, The metal layer is a metal silicide layer.

3. The silicon carbide semiconductor device according to claim 1, in, The first blocking metal part and the second blocking metal part are separate from each other, and The depth (D1) of the recess is greater than the thickness (D2) of the first blocking metal portion.

4. The silicon carbide semiconductor device according to claim 1, in, The first blocking metal part and the second blocking metal part are connected, and Wherein, when the protrusion is arranged at the end of the metal layer, the distance between the tip of the first protrusion and the tip of the second protrusion in the width direction of the gate trench is less than the width of the portion of the electrode layer below the protrusion in the width direction of the gate trench.

5. The silicon carbide semiconductor device according to any one of claims 1 to 4, in, The barrier metal is made of either titanium or titanium nitride, or of a stacked structure having both titanium and titanium nitride.

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