Asymmetrically laterally doped negative capacitance junctionless gate transistor and method of fabrication thereof

Abstract

The application discloses an asymmetric lateral Gaussian-doped negative capacitance junctionless gate transistor and a preparation method. The application forms a global lateral Gaussian-doped concentration distribution form by performing lateral Gaussian doping along a channel direction on the whole channel and drain extension region. The application forms a length and concentration distribution asymmetric negative capacitance junctionless gate transistor structure by adjusting the length of the source / drain extension region on the basis of the global lateral Gaussian doping, so as to reduce the subthreshold swing of the device, improve the on-off current ratio and effectively inhibit the drain-induced barrier lowering effect caused by the short channel effect.

Description

Technical Field

[0001] This invention belongs to the field of field-effect transistors in novel nano-semiconductor devices, specifically relating to an asymmetric lateral doping method for improving the performance of a negative capacitance junctionless ring-gate transistor by performing lateral Gaussian doping on the channel and drain extension regions, and its fabrication method. Background Technology

[0002] For nearly half a century, with the rapid development of semiconductor technology, the scale of complementary metal-oxide-semiconductor (CMOS) integrated circuits, as a component of the modern electronic information industry, has continued to expand. This is mainly due to the continuous shrinking of the feature size of CMOS devices, with the most advanced 5nm semiconductor process already in mass production. However, with the continuous increase in integration density, the continuous increase in power consumption of integrated circuit chips has become a challenge for the development of integrated circuits; moreover, due to the short-channel effect, the miniaturization of traditional CMOS devices will reach its physical limit.

[0003] To continue Moore's Law and maintain device performance, the chip industry began transitioning from planar transistors to three-dimensional FinFETs in 2012. However, as transistor spacing has gradually approached the atomic level, the pace of FinFET process innovation has slowed. Among multi-gate structures, the Gate-Around Field-Effect Transistor (GAAFET) possesses extremely strong gate control capabilities due to its unique fully enclosed gate structure. Both academia and industry have clearly identified GAAFETs as the next generation of nanoscale CMOS device structures after FinFETs. Introducing negative capacitance materials into GAAFETs can overcome the Boltzmann thermodynamic limit, reducing the subthreshold swing (SS) to below 60 mV / dec at room temperature while maintaining its on / off current ratio (IS). ON / I OFF It can also be increased.

[0004] Currently, in practical manufacturing processes, CMOS transistors are classified into inversion mode and junctionless mode based on the doping method within the channel. In recent years, junctionless field-effect transistors have attracted significant research interest due to their simple manufacturing process, unique structure, good scalability, low heat loss, and ability to suppress short-channel effects (SCE). However, due to diffusion and ion implantation processes, achieving uniform doping within junctionless transistors is difficult. Therefore, Gaussian doping is easier to achieve in practice than uniform doping, but traditional Gaussian doping methods involve vertical distribution within the channel. Lateral Gaussian doping within the channel can reduce the device's subthreshold swing and increase the on / off current ratio. Asymmetric structures with a drain extension region longer than the source extension region further improve the device's on / off current ratio and switching speed, while significantly reducing transistor power consumption. Summary of the Invention

[0005] To address current issues such as power consumption and surface-cemented emission (SCE) in transistors, this invention provides an asymmetric lateral Gaussian-doped junctionless ring-gate transistor with reduced power consumption and suppressed SCE.

[0006] This invention is based on a negative capacitance junctionless gate transistor, and introduces a lateral Gaussian doping method and an asymmetric structure. Lateral Gaussian doping is performed in the entire channel and drain extension region of the negative capacitance junctionless gate transistor to form a global lateral Gaussian doped structure.

[0007] This invention provides an asymmetric lateral doped negative capacitance junctionless ring-gate transistor, comprising: a drain, a source, a drain extension region, a source extension region, a gate, and a channel; the gate comprises a three-layer ring structure: the innermost layer is a gate oxide layer, comprising a SiO2 layer and a high-k dielectric HfO2 layer, wherein the high-k dielectric HfO2 layer is located on the outer layer and the SiO2 layer is located on the inner layer; the middle layer is a gate ferroelectric layer, which is doped hafnium-based oxide Zr-HfO2; the outermost layer is a gate metal layer made of titanium nitride; the three-layer ring structure covers the channel, and one end of the source extension region and one end of the drain extension region are respectively connected to the two ends of the channel; The source is located at one end of the source extension region, and the drain is located at the other end of the drain extension region; the length ratio of the source extension region to the drain extension region is 1:2; the doping in the channel and drain extension regions follows a lateral Gaussian distribution, forming a global lateral Gaussian doped structure; the lateral Gaussian distribution refers to the doping concentration at the center of the junction between the channel and the drain extension region as the center, with the concentration at the center as the peak value, and the doping diffuses from the center to both sides, forming a gradient doping that follows a Gaussian distribution; the global lateral Gaussian doping refers to the fact that the entire channel and the entire drain extension region of the asymmetric laterally doped negative capacitance junctionless gate transistor are doped, and the doping follows a lateral Gaussian distribution.

[0008] Preferably, the doping concentration at the center is 2×10⁻⁶. 19 cm -3 The doping concentration of the drain electrode is the same as that of the source electrode, which is 1×10⁻⁶. 19 cm -3 .

[0009] Preferably, the source extension region is uniformly doped.

[0010] Preferably, in the gate oxide layer, the SiO2 layer has a thickness of 0.5 nm; in the gate oxide layer, the high-k dielectric HfO2 layer has a thickness of 1 nm; and in the gate ferroelectric layer, the doped hafnium oxide Zr-HfO2 has a thickness of 3 nm.

[0011] Preferably, the drain, source, drain extension region, source extension region, and channel are all columnar structures, with the channel having a length of 16 nm, the drain extension region having a length of 12 nm, and the source extension region having a length of 6 nm.

[0012] This invention also provides a method for fabricating an asymmetric lateral doped negative capacitance junctionless ring-gate transistor, comprising the following steps: fabricating a channel with single phosphorus doping using electron beam lithography; depositing SiO2 and high-k dielectric HfO2 in the outer ring region of the channel using chemical vapor deposition to form a gate oxide layer; crystallizing a ferroelectric material Zr-HfO2 outside the gate oxide layer using rapid thermal annealing, followed by another rapid thermal annealing to form a gate ferroelectric layer; depositing metal outside the gate ferroelectric layer using atomic layer deposition, followed by another rapid thermal annealing to obtain a gate metal layer; growing source / drain epitaxial regions and doping with phosphorus on both sides of the channel region to obtain source extension regions and drain extension regions, respectively; the doping includes Gaussian doping of phosphorus in both the channel and drain extension regions, with the doping concentration following the following expression:

[0013]

[0014] Where N(x) represents the doping concentration, N peak For the peak doping concentration, N peak The specific value is 2×10 19 cm -3 x represents the position along the direction from the source to the drain. peak The peak concentration of Gaussian doping is located at the boundary between the two regions, diffusing from the center to both sides to form a Gaussian gradient doping, where σ is the standard deviation in the Gaussian distribution. The source and drain extension regions are exposed to a chemical etching material to ensure that they remain unchanged in the axial direction perpendicular to the columnar structure during growth. The ends of the source and drain extension regions away from the channel are exposed to hydrogen to lengthen them along the axial direction of the columnar structure. Hydrogen treatment is used to control the growth of the extension region structure, ensuring that the ratio of the source extension region length to the drain extension region length is 1:2. The ends of the source and drain extension regions away from the channel are rapidly annealed at 1050°C, followed by laser annealing at 1398°C for 1.0 ms to obtain the source / drain regions. The electrode contacts of the source and drain regions are nickel-siliconized to obtain the source / drain electrodes.

[0015] In the asymmetric structure of the junctionless gate-ring transistor (LGD NC-JL-GAAFET) with lateral Gaussian doping proposed in this invention, although the asymmetric structure represents different lengths of the source and drain extension regions, Gaussian doping is performed throughout the channel and drain extension regions, while uniform doping is performed on the source extension region, which also leads to an asymmetric distribution of doping concentration.

[0016] In the asymmetric, laterally Gaussian-doped LGD NC-JL-GAAFET proposed in this invention, the presence of Gaussian doping results in different concentrations within the channel and drain extension regions, leading to diffusion phenomena within the transistor. When an asymmetric structure exists, the electron diffusion density changes, causing variations in the device current. Furthermore, the different lengths of the source / drain extension regions result in differences in the resistance between the channel and the source / drain regions, which also affects the device current. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below.

[0018] Figure 1 A schematic diagram of an N-type negative capacitance junctionless gate field-effect transistor (NC-JL-GAAFET);

[0019] Figure 2 This is a schematic diagram of an asymmetric lateral Gaussian-doped negative capacitance junction-ring-free gate field-effect transistor (Asymmetric LGD NC-JL-GAAFET). The reference numerals are explained as follows: 101-Source; 102-Source extension region; 103-Gate; 104-Drain extension region; 105-Drain; 106-Channel; 201-Gate metal layer; 202-Gate ferroelectric layer; 203-High-k dielectric layer; 204-Gate oxide layer.

[0020] Figures 3 to 6 This reflects the performance advantages of the present invention compared to the negative capacitance junctionless gate transistor, specifically the asymmetric lateral Gaussian-doped negative capacitance junctionless gate field-effect transistor.

[0021] Figure 3 The transfer characteristic curves for the two different structures show that the structure proposed in this invention has a smaller off-state current and a larger on-state current.

[0022] Figure 4 The diagram shows a comparison of the subthreshold swing and switching current ratio for two different structures. It can be seen that the present invention can overcome the Boltzmann limitation and reduce the subthreshold swing to below 60mV / dec. At the same time, the switching current ratio is two orders of magnitude higher than that of ordinary junctionless gate-ring transistors, which improves the switching speed.

[0023] Figure 5 The diagram shows a comparison of the on-state current and off-state current for two different structures. The present invention has a lower off-state current, which can effectively reduce device power consumption; at the same time, it has a higher on-state current and a higher driving capability.

[0024] Figure 6 This diagram illustrates the effect of two different structures on the drain-induced barrier reduction effect. The present invention has a significant suppressive effect on the drain-induced barrier reduction effect and can effectively reduce the impact of the short-channel effect on the device. Detailed Implementation

[0025] This embodiment proposes a doping method for an asymmetric negative capacitance junctionless gate-ring transistor. By performing global lateral Gaussian doping inside the transistor, the concentration of charge carriers in different regions is affected, thereby improving its electrical characteristics such as mobility and enhancing device performance.

[0026] The specific technical solution of this embodiment can be found in [link to embodiment]. Figure 2 The transistor structure includes: channel, drain, source, drain extension region, source extension region, gate oxide layer, high-k dielectric layer, gate ferroelectric layer, and gate metal layer.

[0027] The gate oxide is SiO2 and high-k dielectric HfO2.

[0028] The gate ferroelectric layer is a doped hafnium oxide Zr-HfO2.

[0029] The gate metal layer is titanium nitride (T). i N) material.

[0030] The transistor process steps in this embodiment are mainly as follows:

[0031] Channels with a single phosphorus element doping were fabricated using electron beam lithography.

[0032] SiO2 and high-k dielectric HfO2 are deposited in the outer ring region of the channel by chemical vapor deposition to form the gate oxide layer;

[0033] Using rapid thermal annealing (RTA) technology, a ferroelectric material Zr-HfO2 is crystallized outside the gate oxide layer. After crystallization, another rapid thermal annealing is performed to form the gate ferroelectric layer.

[0034] Atomic layer deposition technology is used to deposit metal outside the gate ferroelectric layer. After deposition, a rapid thermal annealing is performed to obtain the gate metal layer.

[0035] Source / drain epitaxial regions are grown on both sides of the channel region and elemental phosphorus is doped to obtain source / drain extension regions.

[0036] The doping involves Gaussian doping of phosphorus in two regions: the channel and the drain extension region. The doping concentration follows the expression below:

[0037]

[0038] Where N(x) represents the doping concentration, N peak For the peak doping concentration, N peak The specific value is 2×10 19 cm -3 x represents the position along the direction from the source to the drain. peak The peak concentration of Gaussian doping is located at the boundary between two regions, and it diffuses from the center to both sides to form a Gaussian gradient doping. σ is the standard deviation in the Gaussian distribution.

[0039] The source extension region and the drain extension region are exposed to a chemical etching material so that the source extension region and the drain extension region remain unchanged in the axial direction perpendicular to the columnar structure during the growth process; the ends of the source extension region and the drain extension region away from the channel are exposed to hydrogen so that the source extension region and the drain extension region grow longer along the axial direction of the columnar structure.

[0040] Hydrogen treatment is used to control the growth of the extended region structure, so that the ratio of the source extension region length to the drain extension region length is 1:2.

[0041] The ends of the source and drain extension regions away from the channel are rapidly annealed at 1050°C, and then laser annealed at 1398°C for 1.0ms to obtain the source / drain regions.

[0042] Nickel siliconization of the electrode contacts in the source and drain regions is performed to obtain source / drain electrodes.

[0043] The difference between this invention and the traditional NC-JL-GAAFET is that it performs lateral Gaussian doping throughout the entire channel and drain extension region; that is, the Gaussian doping distribution is along the channel direction, with the peak doping concentration located at the boundary between the channel and drain extension region. This invention first performs Gaussian doping throughout the entire channel and drain extension region, thereby causing a difference in carrier concentration distribution throughout the channel, which is then... Figure 3-6 It is evident that this influences the potential distribution, resulting in a higher on / off current ratio and a lower subthreshold swing, while also suppressing the drain-induced barrier reduction (DIBL) effect caused by SCE. Furthermore, introducing an asymmetric structure can effectively reduce the transistor's off-state current, thereby reducing device power consumption. Its characteristic is that this doping method is the same as the commonly used Gaussian doping method in the industry, only the direction of the doping distribution is changed.

[0044] Furthermore, the details regarding the Gaussian doping concentration are as follows: the maximum concentration throughout the doping region is 2 × 10⁻⁶. 19 cm -3 Furthermore, the Gaussian doping distribution region terminates at the drain electrode, and the doping concentration of the drain electrode is the same as that of the source electrode, which is 1×10⁻⁶. 19 cm -3 .

[0045] The main principle of this invention is as follows: Since there are two fundamental transport mechanisms in semiconductor crystals—drift motion induced by an electric field and diffusion motion induced by a concentration gradient—carrier transport phenomena are the basis for ultimately determining the current-voltage characteristics of semiconductor devices. This invention involves lateral Gaussian doping of the channel and drain extension regions, with the concentration peak located at the boundary between the two regions. Due to the concentration gradient, carriers diffuse outwards from the peak region into both regions within the transistor. When there is an asymmetric structure where the drain extension region is longer than the source extension region, the electron diffusion density increases, meaning the current from the drain extension region to the channel increases, thereby increasing the on-state current of the device and giving the transistor better driving capability. Furthermore, when the distance between the gate and drain electrodes is greater than the distance between the gate and source electrodes, the series resistance between the gate and drain is greater than the resistance between the gate and source. When the applied voltage to the gate is small, the large resistance between the gate and drain makes it difficult for electrons to move from the drain to the source, resulting in a smaller off-state current and thus reducing the device's power loss.

[0046] Those skilled in the art should recognize that the above implementation steps and solutions are only used to illustrate and explain the present invention, and are not intended to limit the present invention. Any changes or modifications to the above implementation steps and solutions that are within the scope of the present invention will fall within the protection scope of the present invention.

Claims

1. An asymmetric lateral doped negative capacitance junctionless gate-ring transistor, characterized in that: include: Drain, source, drain extension region, source extension region, gate, channel; The gate comprises a three-layer ring structure: The innermost layer is a gate oxide layer, which includes a SiO2 layer and a high-k dielectric HfO2 layer, wherein the high-k dielectric HfO2 layer is located on the outer layer and the SiO2 layer is located on the inner layer; The intermediate layer is a gate ferroelectric layer, which is a doped hafnium-based oxide Zr-HfO2; The outermost layer is a gate metal layer made of titanium nitride; The three-layer annular structure covers the channel, and one end of the source extension region and one end of the drain extension region are respectively connected to the two ends of the channel; The source is located at the other end of the source extension region, and the drain is located at the other end of the drain extension region; The length ratio of the source extension region to the drain extension region is 1:2; The doping in the channel and drain extension regions follows a lateral Gaussian distribution, forming a global lateral Gaussian doped structure. The lateral Gaussian distribution refers to a gradual doping distribution that diffuses from the center outwards from the boundary between the channel and the drain extension region, with the doping concentration at the center as the peak value. The global lateral Gaussian doping refers to the fact that the entire channel and the entire drain extension region of the asymmetric lateral doped negative capacitance junctionless gate transistor are doped, and the doping follows a lateral Gaussian distribution.

2. The asymmetric lateral doped negative capacitance junctionless gate transistor as described in claim 1, characterized in that, The doping concentration at the center is 2×10⁻⁶. 19 cm -3 The doping concentration of the drain electrode is the same as that of the source electrode, which is 1×10⁻⁶. 19 cm -3 .

3. The asymmetric lateral doped negative capacitance junctionless gate transistor as described in claim 2, characterized in that, The source extension region is uniformly doped.

4. The asymmetric lateral doped negative capacitance junctionless gate transistor as described in claim 2, characterized in that, In the gate oxide layer, the SiO2 layer has a thickness of 0.5 nm; In the gate oxide layer, the thickness of the high-k dielectric HfO2 layer is 1 nm; In the gate ferroelectric layer, the thickness of the doped hafnium oxide Zr-HfO2 is 3 nm.

5. An asymmetric lateral doped negative capacitance junctionless gate transistor as described in claim 4, characterized in that, The drain, source, drain extension region, source extension region, and channel are all columnar structures, with the channel having a length of 16 nm, the drain extension region having a length of 12 nm, and the source extension region having a length of 6 nm.

6. The method for fabricating an asymmetric lateral doped negative capacitance junctionless ring-gate transistor as described in claim 5, characterized in that, Includes the following steps: Channels with a single phosphorus element doping were fabricated using electron beam lithography. SiO2 and high-k dielectric HfO2 are deposited in the outer ring region of the channel using chemical vapor deposition to form the gate oxide layer. By using a rapid thermal annealing method, a ferroelectric material Zr-HfO2 is crystallized outside the gate oxide layer. After crystallization, another rapid thermal annealing is performed to form a gate ferroelectric layer. Metal is deposited outside the gate ferroelectric layer using atomic layer deposition (ALD), followed by rapid thermal annealing to obtain the gate metal layer. Source / drain epitaxial regions were grown on both sides of the channel region and elemental phosphorus was doped to obtain source extension region and drain extension region, respectively. The doping involves Gaussian doping of phosphorus in two regions: the channel and the drain extension region. The doping concentration follows the expression below: Where N(x) represents the doping concentration, N peak For the peak doping concentration, N peak The specific value is 2×10 19 cm -3 x represents the position along the direction from the source to the drain. peak The peak concentration of Gaussian doping is located at the boundary between two regions, and it diffuses from the center to both sides to form a Gaussian gradient doping. σ is the standard deviation in the Gaussian distribution. The source extension region and the drain extension region are exposed to a chemical etching material so that the source extension region and the drain extension region remain unchanged in the axial direction perpendicular to the columnar structure during the growth process; the ends of the source extension region and the drain extension region away from the channel are exposed to hydrogen so that the source extension region and the drain extension region grow longer along the axial direction of the columnar structure. Hydrogen treatment is used to control the growth of the extended region structure, so that the ratio of the source extension region length to the drain extension region length is 1:

2. The ends of the source and drain extension regions away from the channel are rapidly annealed at 1050°C, and then laser annealed at 1398°C for 1.0ms to obtain the source / drain regions. Nickel siliconization of the electrode contacts in the source and drain regions is performed to obtain source / drain electrodes.

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