Semiconductor device

Abstract

The semiconductor device of one embodiment includes a first electrode, a first semiconductor layer of a first conductivity type over the first electrode, a second semiconductor layer of a second conductivity type over the first semiconductor layer, a second electrode over the second semiconductor layer, a first trench reaching the first semiconductor layer from the second semiconductor layer, a first semiconductor region provided in the second semiconductor layer in contact with the first trench, the first semiconductor region having a higher impurity concentration of the second conductivity type than the second semiconductor layer, and a first insulating film provided in the second semiconductor layer in contact with the first semiconductor region.

Description

[0001] Related applications

[0002] This application enjoys priority based on Japanese Patent Application No. 2021-154468 (filed on September 22, 2021). This application incorporates all contents of the basic application by reference to that basic application. Technical Field

[0003] The implementation methods mainly involve semiconductor devices. Background Technology

[0004] Development is underway to improve the reverse recovery characteristics of diodes. In recent years, IGBTs (Insulated Gate Bipolar Transistors) and diodes have been used in semiconductor devices for power conversion equipment such as inverters. Diodes are typically connected in anti-parallel to IGBTs and used as return current diodes. Therefore, diodes are called FWDs (Free Wheeling Diodes).

[0005] To improve the characteristics of power conversion devices such as inverters, improving the characteristics of IGBTs and, consequently, the FWD (Front-End Voltage Regulator) becomes important. Key characteristics of the FWD include turn-on voltage (i.e., voltage drop during the on-state), recovery time (i.e., the time it takes for the recovery current to disappear during reverse recovery), and the safe operating region during recovery (i.e., the region where the current does not change even when voltage is applied while the recovery current is flowing). Furthermore, less current-voltage oscillation during recovery is preferable. Among these, it is important to both shorten the recovery time and expand the safe operating region during recovery. Summary of the Invention

[0006] The implementation provides a semiconductor device that reduces recovery loss and expands the safe operating area.

[0007] The semiconductor device of the embodiment includes: a first electrode; a first semiconductor layer of a first conductivity type disposed on the first electrode; a second semiconductor layer of a second conductivity type disposed on the first semiconductor layer; a second electrode disposed on the second semiconductor layer; a first trench extending from the second semiconductor layer to the first semiconductor layer; a first semiconductor region disposed in the second semiconductor layer and grounded to the first trench, wherein the impurity concentration of the second conductivity type is higher than the impurity concentration of the second conductivity type in the second semiconductor layer; and a first insulating film disposed in the second semiconductor layer and grounded to the first semiconductor region. Attached Figure Description

[0008] Figure 1 This is a schematic cross-sectional view of the semiconductor device according to the first embodiment.

[0009] Figure 2 This is a schematic perspective view of the semiconductor device according to the first embodiment.

[0010] Figure 3 This is an example of a schematic cross-sectional view of the main part of the semiconductor device according to the first embodiment.

[0011] Figure 4 This is another example of a schematic cross-sectional view of the main part of the semiconductor device of the first embodiment.

[0012] Figures 5-7 This is a schematic cross-sectional view showing a part of the manufacturing process of the semiconductor device according to the first embodiment.

[0013] Figure 8 This is a schematic cross-sectional view of the main parts of the semiconductor device in the comparative embodiment of the first embodiment.

[0014] Figure 9 (a) and (b) are schematic diagrams used to illustrate the effects of the semiconductor device in the first embodiment.

[0015] Figure 10 This is a schematic perspective view of the semiconductor device according to the second embodiment.

[0016] Figure 11 This is a schematic perspective view of the semiconductor device according to the third embodiment.

[0017] Figure 12 This is a schematic perspective view of the semiconductor device according to the fourth embodiment.

[0018] Figure 13 This is a schematic perspective view of the semiconductor device according to the fifth embodiment.

[0019] Figure 14 This is a schematic perspective view of the semiconductor device according to the sixth embodiment.

[0020] Figure 15 This is a schematic perspective view of the semiconductor device according to the seventh embodiment. Detailed Implementation

[0021] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. Furthermore, in the following description, the same reference numerals will be used to denote the same parts, and descriptions of parts that have been described previously will be omitted as appropriate.

[0022] In the following explanation, n + n, n － and p + p, p － The markings indicate the relative concentration of impurities in each conductivity type. That is, n +This indicates that the impurity concentration of type n is relatively higher compared to type n. － This indicates that the impurity concentration of the n-type is relatively low compared to the n-type. Additionally, p... + This indicates that the impurity concentration of p-type is relatively higher compared to p-type. － This indicates that the impurity concentration of p-type is relatively low compared to p-type. Additionally, sometimes n-type is used... + Type, n － The type is only recorded as type n, and p is recorded as type n. + Type, p － The type is only recorded as p.

[0023] In this specification, to indicate the positional relationship of components, the direction from the cathode electrode 2 toward the drift layer 6 is referred to as "up," and the reverse direction is referred to as "down." In this specification, the concepts of "up" and "down" are not necessarily terms indicating their relationship to the direction of gravity.

[0024] The following explanation will be based on the case where the first conductivity type is n-type and the second conductivity type is p-type.

[0025] (First Implementation)

[0026] The semiconductor device of this embodiment includes: a first electrode; a first semiconductor layer of a first conductivity type disposed on the first electrode; a second semiconductor layer of a second conductivity type disposed on the first semiconductor layer; a second electrode disposed on the second semiconductor layer; a first trench extending from the second semiconductor layer to the first semiconductor layer; a first semiconductor region disposed in the second semiconductor layer and grounded to the first trench, wherein the impurity concentration of the second conductivity type is higher than the impurity concentration of the second conductivity type of the second semiconductor layer; and a first insulating film disposed in the second semiconductor layer and grounded to the first semiconductor region.

[0027] Figure 1 This is a schematic cross-sectional view of the semiconductor device 100 of this embodiment. Figure 2 This is a schematic perspective view of the main parts of the semiconductor device 100 according to this embodiment. For ease of explanation, Figure 2 Yes Figure 1 The semiconductor device 100 shown is illustrated with the anode electrode 10 removed.

[0028] The semiconductor device 100 is a PIN diode with a trench 12. For example, in an RC-IGBT (Reverse Conducting IGBT) that has both an IGBT and a PIN diode in a single chip, the semiconductor device 100 has the same trench 12 as the trench 12 provided for the operation of the IGBT. However, the semiconductor device 100 of this embodiment is not limited to the PIN diode described above.

[0029] use Figure 1as well as Figure 2 This describes the semiconductor device 100 of this embodiment.

[0030] The cathode electrode (an example of the first electrode) 2 is the electrode that functions as the cathode electrode of the PIN diode. The cathode electrode 2 may contain conductive materials such as Al (aluminum) or Cu (copper).

[0031] n + A cathode layer 4 is disposed above the cathode electrode 2. The cathode layer 4 functions as the cathode layer of the PIN diode. For example, the cathode layer 4 preferably contains 3 × 10⁻⁶ ppm. 17 atoms / cm 3 The above are n-type impurities.

[0032] n － A drift layer 6 (an example of a first semiconductor layer) is disposed above the cathode layer 4. The drift layer 6 functions as a drift layer for a PIN diode. For example, the drift layer 6 preferably contains 1×10⁻⁶ ppm. 12 atoms / cm 3 Above and 1×10 15 atoms / cm 3 The following are n-type impurities. The thickness of drift layer 6 is, for example, 40 μm or more and 700 μm or less.

[0033] Here, we define the X direction (an example of a second direction), the Y direction (an example of a third direction) which intersects the X direction perpendicularly, and the Z direction (an example of a first direction) which intersects both the X and Y directions perpendicularly. The cathode electrode 2, the cathode layer 4, and the drift layer 6 are formed in a layered shape parallel to an XY plane parallel to the X and Y directions. The Z direction is the direction from the cathode electrode 2 toward the drift layer 6.

[0034] p － An anode layer (an example of a second semiconductor layer) 8 is disposed on top of the drift layer 6. The anode layer 8 functions as the anode layer of a PIN diode. For example, the anode layer 8 preferably contains 1×10⁻⁶ ppm. 16 atoms / cm 3 Above and 5×10 17 atoms / cm 3 The following are p-type impurities. The film thickness of the anode layer 8 is, for example, 2 μm or more and 8 μm or less. Figure 1 The anode layers 8a, 8b, and 8c are shown.

[0035] An anode electrode (an example of a second electrode) 10 is disposed on the anode layer 8. The anode electrode 10 functions as the anode electrode of a PIN diode. The anode electrode 10 may contain a conductive material such as Al (aluminum) or Cu (copper). The anode electrode 10 may be in a Schottky contact with the anode layer 8.

[0036] The trench (an example of the first trench) 12 is arranged such that it extends parallel to the Z-direction from the anode layer 8 toward the cathode electrode 2 and reaches the drift layer 6. Figure 1 In the example of groove 12, grooves 12a, 12b, 12c, and 12d are provided. Figure 2 As shown, grooves 12a, 12b, 12c, and 12d extend in the Y direction. In this embodiment, grooves 12a, 12b, 12c, and 12d are the first grooves.

[0037] Electrode 16 is disposed within trench 12. Electrode 16 may contain, for example, polycrystalline silicon containing impurities. Insulating film 14 is disposed within trench 12 surrounding electrode 16. Insulating film 14 may contain, for example, an insulating material such as silicon oxide. Alternatively, electrode 16 may not be disposed within trench 12.

[0038] p + A semiconductor region 18 (an example of a first semiconductor region) is provided in the anode layer 8 in the X direction to be grounded to the sidewall of the trench 12. The semiconductor region 18 also functions as the anode layer of a PIN diode. In the semiconductor device 100, a semiconductor region 18a is provided in the anode layer 8a in the X direction to be grounded to the sidewall of the trench 12a. A semiconductor region 18b is provided in the anode layer 8a in the X direction to be grounded to the sidewall of the trench 12b. A semiconductor region 18c is provided in the anode layer 8b in the X direction to be grounded to the sidewall of the trench 12b. A semiconductor region 18d is provided in the anode layer 8b in the X direction to be grounded to the sidewall of the trench 12c. A semiconductor region 18e is provided in the anode layer 8c in the X direction to be grounded to the sidewall of the trench 12c. A semiconductor region 18f is provided in the anode layer 8c in the X direction to be grounded to the sidewall of the trench 12d. The trench 12b is provided between the semiconductor regions 18b and 18c in the X direction. Trench 12c is disposed in the X direction between semiconductor region 18d and semiconductor region 18e. For example, Figure 2 As shown, semiconductor regions 18a, 18b, 18c, 18d, 18e, and 18f extend in the Y direction along the sidewalls of trench 12. The length of the anode layer 8 in the Z direction is longer than the length of the semiconductor region 18 in the Z direction. For example, semiconductor region 18 preferably contains 1×10 17 atoms / cm 3 Above and 1×1021 atoms / cm 3 The following are p-type impurities.

[0039] Here, the operation of the semiconductor device 100 will be explained.

[0040] First, the electron current flowing from the cathode side to the anode side will be explained.

[0041] In the ON (ON) state, a positive voltage is applied between the cathode and anode. That is, a voltage is applied between the cathode and anode so that the potential of the anode electrode 10 is higher than the potential of the cathode electrode 2.

[0042] Here, n + The cathode layer 4 is ohmically bonded to the cathode electrode 2. Therefore, electrons move from n... + Type 4 cathode layer via n － Type 6 drift layer reaches p － Type 8 anode layer.

[0043] p － The anode layer 8 is resistively contacted or Schottky-junctioned with the anode electrode 10. That is, it is based on a resistive contact or Schottky-junction between a p-type semiconductor and a metal. Therefore, p... － The anode layer 8 and the anode electrode 10 form an energy barrier for holes, but not for electrons.

[0044] Therefore, electrons from n + Type 4 cathode layer via n － Type drift layer 6, p － Type 8 anode layer flows into anode electrode 10.

[0045] Next, the hole current flowing from the anode side to the cathode side will be explained.

[0046] As mentioned above, p － The anode layer 8 and the anode electrode 10 do not form an energy barrier for electrons. However, p + Type 18 semiconductor region and p － The space between the 8-layer anode and the 8-layer anode forms an energy barrier for electrons. Therefore, the flow to p... － Electrons in the type 8 anode layer are difficult to flow into p + Type 18 semiconductor region.

[0047] Therefore, after electrons flow from the cathode side to the anode side, if they reach p... + Near semiconductor region 18 of type 18, then in p + The semiconductor region 18 of the type moves laterally (in the X direction) below it.

[0048] Through this p －The movement of electrons near the 8th anode layer, p + The lower portion of the semiconductor region 18 of the type is relative to the p-type contacting the anode electrode 10. + The semiconductor region 18, i.e. the anode electrode 10, is biased in a manner that makes it a negative electrode.

[0049] Through p + The bias formed between the lower portion of the type semiconductor region 18 and the anode electrode 10, in p + Below the type of semiconductor region 18, for p － Type 8 anode layer and p + The energy barrier for holes between semiconductor regions 18 of the p-type is lowered. Therefore, from p + Type 18 p-type semiconductor region － Holes are injected into the anode layer 8.

[0050] p + The width, or p, of the semiconductor region 18 in the X direction + The larger the contact area between the semiconductor region 18 and the anode electrode, the larger the hole current. In other words, the injection amount of holes from the anode side can be adjusted by its width or its contact area.

[0051] Thus, in the on-state, holes flow from the anode side to the cathode side, and electrons flow from the cathode side to the anode side. Here, on the anode side, from p... + Holes are injected into the semiconductor region 18 of the type, in contrast to p － The type 8 anode layer generally facilitates electron ejection. Therefore, compared to not setting p... － Compared to semiconductor devices with anode layer 8, the amount of hole injection is suppressed. As a result, fewer holes are discharged during recovery, enabling faster recovery operations and reducing recovery losses.

[0052] Next, the actions (restoration actions) in the disconnected state will be explained.

[0053] From the state where a positive voltage is applied between the cathode and anode, a reverse voltage is applied between the cathode and anode. This exists in n. － Holes in the drift layer 6 move toward the anode electrode 10 via p + The semiconductor region 18 of the type flows into the anode electrode 10, and electrons move towards the cathode electrode 2, via n + The cathode layer 4 flows into the cathode electrode 2.

[0054] During recovery, with electrons flowing towards the cathode electrode 2 and holes flowing towards the anode electrode 10, p － Type 8 and n anode layer － Starting from the junction of drift layer 6, the depletion layer moves towards n －Type drift layer 6 and p － The anode layer 8 expands. As a result, the conduction between the cathode and the anode is gradually cut off.

[0055] However, in PIN diodes, during recovery, an electric field concentration sometimes occurs at a certain location in the pn junction, causing avalanche breakdown. In a structure with trench 12 as in this embodiment, the electric field at the bottom of trench 12 becomes stronger, leading to avalanche breakdown at the bottom of trench 12. Due to the current concentration caused by avalanche breakdown, thermal damage and other issues may sometimes occur, resulting in component failure.

[0056] Here, the cavities created at the bottom of trench 12 due to avalanche penetration are also transmitted via p + The type of semiconductor region 18 flows into the anode electrode 10. Therefore, p + The length L2 of the semiconductor region 18 near the bottom of the trench 12 in the Z direction increases, which enhances the discharge of holes and thus can suppress the damage of the device.

[0057] An insulating film (an example of a first insulating film) 20 is disposed within the anode layer 8 in the X direction, grounded to the semiconductor region 18. As described above, via p... + The width, or p, of the semiconductor region 18 in the X direction + The contact area between the semiconductor region 18 and the anode electrode 10 is adjusted to control the amount of holes injected from the anode side. However, as in this embodiment, if p + If the length L2 in the Z direction of the semiconductor region 18 increases, then in p + The side of the semiconductor region 18 of the type is also due to p + The same effect occurs in the lower portion of the semiconductor region 18, resulting in hole injection, making it difficult to suppress the amount of hole injection. The insulating film 20 is provided to suppress hole injection in the X direction within the semiconductor region 18.

[0058] In the semiconductor device 100, an insulating film 20a is provided in the anode layer 8a, grounded in the X direction to the semiconductor region 18a. An insulating film 20b is provided in the anode layer 8a, grounded in the X direction to the semiconductor region 18b. An insulating film 20c is provided in the anode layer 8b, grounded in the X direction to the semiconductor region 18c. An insulating film 20d is provided in the anode layer 8b, grounded in the X direction to the semiconductor region 18d. An insulating film 20e is provided in the anode layer 8c, grounded in the X direction to the semiconductor region 18e. An insulating film 20f is provided in the anode layer 8c, grounded in the X direction to the semiconductor region 18f. A trench 12b is provided between the insulating films 20b and 20c. A trench 12d is provided between the insulating films 20d and 20e. Figure 2As shown, insulating films 20a, 20b, 20c, 20d, 20e, and 20f extend along semiconductor region 18 in the Y direction. The insulating film 20 comprises, for example, an insulating material such as silicon oxide, silicon nitride, or carbon.

[0059] The length L3 of the insulating film 20 in the Z direction is preferably 0.6 times or more and 1.5 times or less than the length L2 of the semiconductor region 18 in the Z direction. Furthermore, in Figure 1 In the diagram, let L2 = L3. Figure 3 This is an example of a schematic cross-sectional view of the main part of the semiconductor device according to this embodiment. The diagram is shown with L3 = L2 × 0.6. Figure 4 This is another example of a schematic cross-sectional view of the main part of the semiconductor device in this embodiment. The diagram is shown with L3 = L2 × 1.5.

[0060] Preferably, the length L1 of the anode layer 8 in the Z direction is longer than the length L3 of the insulating film 20 in the Z direction. Similarly, preferably, the length L1 of the anode layer 8 in the Z direction is longer than the length L2 of the semiconductor region 18 in the Z direction.

[0061] like Figure 1 As shown in the diagram, the distance between trench 12a and trench 12b in the X direction is set to D1. The length of semiconductor region 18 in the X direction is set to D2. The length of insulating film 20 in the X direction is set to D3. The distance between insulating film 20a and insulating film 20b in the X direction is set to D4. At this time, in order to suppress holes from p... + The lower portion of the semiconductor region 18 is implanted, preferably with D2 < D4.

[0062] The semiconductor material used in the cathode layer 4, drift layer 6, anode layer 8, and semiconductor region 18 is, for example, silicon (Si). However, the semiconductor material used in the cathode layer 4, drift layer 6, anode layer 8, and semiconductor region 18 may also be other semiconductor materials such as silicon carbide (SiC), gallium nitride (GaN), or gallium arsenide (GaAs).

[0063] When silicon is used as the semiconductor material, arsenic (As), phosphorus (P) or antimony (Sb) can be used as n-type impurities, and boron (B) can be used as p-type impurities.

[0064] Figures 5 to 7 This is a schematic cross-sectional view showing a part of the manufacturing process of the semiconductor device according to this embodiment.

[0065] First, a drift layer 6 is used as a semiconductor substrate, for example. Next, an anode layer 8 is formed on the surface of the drift layer 6, for example, by ion implantation. Next, a trench 12 is formed on the anode layer 8, for example, using photolithography and RIE (Reactive Ion Etching). Next, an insulating film 14 and an electrode 16 are formed inside the trench 12, for example, by CVD (Chemical Vapor Deposition). Next, a portion of the insulating film 14 and a portion of the electrode 16 are removed, for example, by etching back, exposing the anode layer 8, the insulating film 14, and the electrode 16. Next, a photomask M, for example, containing silicon oxide, is formed on the anode layer 8, the insulating film 14, and the electrode 16.

[0066] Next, for example, by means of RIE, a groove 30 is formed in the anode layer 8. Figure 5 ).exist Figure 5 In the anode layer 8a, grooves 30a and 30b are formed. Additionally, grooves 30c and 30d are formed on the anode layer 8b. Furthermore, grooves 30e and 30f are formed on the anode layer 8c.

[0067] In addition, Figure 5 The following are examples Figure 6 And the following shown Figure 7 In the illustration, a portion of the insulating film 14 disposed on the electrode 16 is shown as a different component from the photomask M. However, for example, the portion of the insulating film 14 disposed on the electrode 16 may also be formed by the same manufacturing process as the photomask M. Alternatively, the portion of the insulating film 14 disposed on the electrode 16 may also be formed by a different manufacturing process than the photomask M described above.

[0068] The distances between slots 30a and 30b, slots 30c and 30d, and slots 30e and 30f in the X direction are, for example, about 2 μm. The opening width of the slots 30 in the X direction is, for example, about 0.4 μm. The depth of the slots 30 in the Z direction is, for example, 1 μm. However, the distances between the slots 30 in the X direction, the opening width of the slots 30 in the X direction, and the depth of the slots 30 in the Z direction are not limited to those described above.

[0069] Next, for example, an insulating film 20 is formed in the trench 30 by CVD. Figure 6 ).exist Figure 6 An insulating film 20a is formed in groove 30a. An insulating film 20b is formed in groove 30b. An insulating film 20c is formed in groove 30c. An insulating film 20d is formed in groove 30d. An insulating film 20e is formed in groove 30e. An insulating film 20f is formed in groove 30f.

[0070] Next, the photomask M is removed. Next, a photoresist R is formed over the anode layer 8, the insulating film 14, and the electrode 16. Next, for example, a p-type photoresist is formed between the trench 12 and the insulating film 20 by ion implantation. + Type 18 semiconductor region ( Figure 7 ).exist Figure 7 In this structure, a semiconductor region 18a is formed between trench 12a and insulating film 20a. A semiconductor region 18b is formed between trench 12b and insulating film 20b. A semiconductor region 18c is formed between trench 12b and insulating film 20c. A semiconductor region 18d is formed between trench 12c and insulating film 20d. A semiconductor region 18e is formed between trench 12c and insulating film 20e. A semiconductor region 18f is formed between trench 12d and insulating film 20f.

[0071] Next, the photoresist R is removed. Next, a heat treatment is performed to activate the impurities. Next, a cathode electrode 2 is formed below the cathode layer 4, and an anode electrode 10 is formed above the anode layer 8, above the insulating film 14, and above the electrode 16, thus obtaining the semiconductor device 100 of this embodiment.

[0072] Next, the effects of the semiconductor device in this embodiment will be described.

[0073] As with the semiconductor device of this embodiment, in a semiconductor device using a diode having a trench 12, in order to promote the discharge of holes generated at the bottom of the trench 12 to the anode electrode 10 when avalanche breakdown occurs at the bottom of the trench 12, it is considered to provide a p-shaped groove with a predetermined depth on the sidewall of the trench 12. + Semiconductor region 18. In p + In semiconductor region 18, the resistance to holes is reduced. Therefore, when a reverse voltage is applied, holes can easily escape from n... － Drift layer 6 via the sidewall of trench 12 p + The semiconductor region 18 removes the holes generated at the bottom of the trench 12.

[0074] However, by setting this p + In semiconductor region 18, more holes are injected from the anode when a forward voltage is applied. When a reverse voltage is applied, more holes need to be injected from the n... － Drift layer 6 removes a significant number of holes, but this results in a corresponding increase in recovery loss.

[0075] Figure 8This is a schematic cross-sectional view showing the hole current when a forward voltage is applied to the main part of the semiconductor device 800, which is the comparative embodiment of this invention. No insulating film 20 is provided in the semiconductor device 800. When a forward current flows through the semiconductor device 800, the largest hole current flows in region 8a1 within the anode layer 8a. Furthermore, the hole current decreases in the order of region 8a1, region 8a2, region 8a3, 8a4, ... . Additionally, the hole current also decreases in the X direction from p... + Type 18 p-type semiconductor region － Holes are injected into the anode layer 8. It is believed that by suppressing the injection of holes in this X direction, the increase in recovery loss can be suppressed.

[0076] Therefore, the semiconductor device 100 of this embodiment includes an insulating film 20 disposed in the anode layer 8 and grounded to the semiconductor region 18.

[0077] Holes cannot be formed from p + The semiconductor region 18 of the type is transmitted to p through the insulating film 20. － A type 8 anode layer is implanted. This enables the provision of a semiconductor device that suppresses hole injection on the anode side.

[0078] Figure 9 This is a schematic diagram illustrating the effect of the semiconductor device 100 in this embodiment. Figure 9 (a) and Figure 9 (b) is a graph showing the relationship between recovery loss Err and forward voltage VF.

[0079] Figure 9 Comparison method A's semiconductor device (a) has a semiconductor region 18 on the sidewall of the trench. Comparison method A's semiconductor device does not have an insulating film 20. In contrast, Figure 9 The semiconductor device of embodiment (a) A includes a semiconductor region 18 and an insulating film 20.

[0080] In the case of the semiconductor device in Embodiment A, since hole injection is further suppressed, the forward voltage VF becomes higher, and the recovery loss Err decreases. Therefore, compared with the semiconductor device in Comparative Embodiment A, the semiconductor device 100 of this embodiment can suppress anode injection and reduce recovery loss Err.

[0081] The length L3 of the insulating film 20 in the Z direction is preferably 0.6 times or more and 1.5 times or less than the length L2 of the semiconductor region 18 in the Z direction. If the length L3 of the insulating film 20 in the Z direction is less than 0.6 times the length L2 of the semiconductor region 18 in the Z direction, the length of the insulating film 20 is too short and cannot sufficiently suppress the hole current in the X direction.

[0082] exist Figure 9 In the semiconductor device of embodiment (b) B, the length L3 of the insulating film 20 in the Z direction is 0.6 times the length L2 of the semiconductor region 18 in the Z direction. Figure 9 In the semiconductor device of embodiment (b) C, the length L3 of the insulating film 20 in the Z direction is 1.0 times the length L2 of the semiconductor region 18 in the Z direction. Figure 9 In the semiconductor device of embodiment (b) D, the length L3 of the insulating film 20 in the Z direction is 1.5 times the length L2 of the semiconductor region 18 in the Z direction. Furthermore, in Figure 9 In (b), the semiconductor device of comparison method B is also shown. The semiconductor device of comparison method B does not have an insulating film 20. In this way, when the length L3 of the insulating film 20 in the Z direction is more than 0.6 times and less than 1.5 times the length L2 of the semiconductor region 18 in the Z direction, the forward voltage VF becomes higher and the recovery loss Err decreases due to further suppression of hole injection.

[0083] Preferably, the length L1 of the anode layer 8 in the Z direction is longer than the length L3 of the insulating film 20 in the Z direction. This is because when the length L3 of the insulating film 20 in the Z direction is greater than or equal to the length L1 of the anode layer 8, the insulating film 20 becomes trapped in the drift layer 6, resulting in electric field concentration at the lower front end of the insulating film 20. Similarly, preferably, the length L1 of the anode layer 8 in the Z direction is longer than the length L2 of the semiconductor region 18 in the Z direction.

[0084] The insulating film 20 preferably contains silicon oxide. This is because it can be easily manufactured.

[0085] When the length of the semiconductor region 18 in the X direction is D2 and the distance between the insulating films 20a and 20b in the X direction is D4, it is preferable that D2 < D4. This is because, when D2 ≥ D4, from p + The semiconductor region 18 of the type is injected with more holes, thus increasing the recovery loss when a reverse voltage is applied.

[0086] The semiconductor device according to this embodiment can provide a semiconductor device that achieves reduced recovery loss and expanded safe operating area.

[0087] (Second Implementation)

[0088] The semiconductor device of this embodiment differs from the semiconductor device of the first embodiment in that it further comprises: a plurality of first semiconductor regions, which are respectively connected to and separated from each other in the second semiconductor layer and are disposed separately, wherein the concentration of the second conductivity type impurity is higher than the concentration of the second conductivity type impurity in the second semiconductor layer; and a plurality of first insulating films, which are respectively connected to and separated from each other in the second semiconductor layer and are disposed separately. Here, the description of content that is repeated with the semiconductor device of the first embodiment is omitted.

[0089] Figure 10 This is a schematic perspective view of the semiconductor device 110 of this embodiment.

[0090] The length of the semiconductor region 18b in the Y direction is shorter than the length of the semiconductor region 18a in the Y direction and the length of the insulating film 20a in the Y direction. Furthermore, the length of the insulating film 20b in the Y direction is shorter than the length of the semiconductor region 18a in the Y direction and the length of the insulating film 20a in the Y direction.

[0091] Similarly, the length of the semiconductor region 18c in the Y direction is shorter than the length of the semiconductor region 18a in the Y direction and the length of the insulating film 20a in the Y direction. Furthermore, the length of the insulating film 20c in the Y direction is shorter than the length of the semiconductor region 18a in the Y direction and the length of the insulating film 20a in the Y direction.

[0092] Similarly, the length of the semiconductor region 18f in the Y direction is shorter than the length of the semiconductor region 18a in the Y direction and the length of the insulating film 20a in the Y direction. Furthermore, the length of the insulating film 20f in the Y direction is shorter than the length of the semiconductor region 18a in the Y direction and the length of the insulating film 20a in the Y direction.

[0093] In addition, Figure 10 In the illustration, the length of the insulating film 20b in the Y direction is the same as the length of the semiconductor region 18b in the Y direction. However, the length of the insulating film 20b in the Y direction may also differ from the length of the semiconductor region 18b in the Y direction. For example, the length of the insulating film 20b in the Y direction may be longer than the length of the semiconductor region 18b in the Y direction. Alternatively, the length of the insulating film 20b in the Y direction may be shorter than the length of the semiconductor region 18b in the Y direction. However, from the viewpoint of low anode implantation, it is preferable that the length of the insulating film 20b in the Y direction is greater than or equal to the length of the semiconductor region 18b in the Y direction. The semiconductor region 18c, the insulating film 20c, the semiconductor region 18f, and the insulating film 20f are also the same.

[0094] Alternatively, for example, multiple semiconductor regions 18b, separated from each other, may be provided along the Y direction and grounded to the sidewalls of trench 12b. For example, multiple insulating films 20b, separated from each other, may be provided along the Y direction and grounded to the multiple semiconductor regions 18b. For example, multiple semiconductor regions 18c, separated from each other, may be provided along the Y direction and grounded to the multiple semiconductor regions 18c. For example, multiple insulating films 20c, separated from each other, may be provided along the Y direction and grounded to the multiple semiconductor regions 18c. For example, multiple semiconductor regions 18f, separated from each other, may be provided along the Y direction and grounded to the multiple semiconductor regions 18f. For example, multiple insulating films 20f, separated from each other, may be provided along the Y direction and grounded to the multiple semiconductor regions 18f. In this case, trench 12b is an example of a first trench. The multiple semiconductor regions 18b and the multiple insulating films 20b are examples of multiple first semiconductor regions and multiple first insulating films, respectively.

[0095] In addition, Figure 10 The diagram illustrates semiconductor regions 18 and 20 extending along the Y direction, such as semiconductor region 18a, insulating film 20a, semiconductor region 18d, insulating film 20d, semiconductor region 18e, and insulating film 20e, as well as semiconductor regions 18b, insulating film 20b, semiconductor region 18c, insulating film 20c, semiconductor region 18f, and insulating film 20f, which are shorter in the Y direction. Their arrangement order in the X direction is not particularly limited. Figure 10 As shown. Moreover, in Figure 10 The diagram shows multiple semiconductor regions 18 with shorter lengths in the Y direction and insulating films 20, but even one semiconductor region 18 with shorter lengths in the Y direction and insulating film 20 can be implemented.

[0096] In other words, at least a portion of trench 12b has a portion within the anode layer 8 that is not in contact with semiconductor regions 18b and 18c in the X direction. Additionally, trench 12b has a portion that is in contact with semiconductor regions 18b and 18c in the X direction. In this case, trench 12b is an example of a second trench.

[0097] In other words, at least a portion of the trench 12d has a portion that is not in contact with the semiconductor region 18f in the X direction within the anode layer 8. Additionally, the trench 12d has a portion that is in contact with the semiconductor region 18f in the X direction.

[0098] To reduce the amount of holes injected into the semiconductor device and thus achieve low anode injection, it is preferable to minimize the volume of the semiconductor region 18. Therefore, in the semiconductor device 110, the length of the semiconductor region 18b in the Y direction is further shortened. This further reduces the volume of the semiconductor region 18 in the anode layer 8a. Furthermore, within the anode layer 8b, the length of the semiconductor region 18c in the Y direction is further shortened. This further reduces the volume of the semiconductor region 18 within the anode layer 8b. Additionally, within the anode layer 8c, the length of the semiconductor region 18f in the Y direction is further shortened. This further reduces the volume of the semiconductor region 18 within the anode layer 8c. Thus, a semiconductor device that reduces recovery loss while maintaining a safe operating region can be provided.

[0099] Regarding the length of the insulating film 20b in the Y direction, it only needs to be set to suppress the influence of p in the X direction. + The length of the hole injection in semiconductor region 18b is sufficient. Therefore, the length of insulating film 20b in the Y direction is shorter than the length of semiconductor region 18a and insulating film 20a in the Y direction. Similarly, the lengths of insulating film 20c and insulating film 20f in the Y direction are also shorter. Furthermore, by providing multiple semiconductor regions 18b, multiple insulating films 20b, multiple semiconductor regions 18c, multiple insulating films 20c, multiple semiconductor regions 18f, and multiple insulating films 20f, better control of the hole injection from p... + Hole injection and hole diffusion in semiconductor region 18f.

[0100] In the semiconductor device of this embodiment, it is also possible to provide a semiconductor device that achieves reduced recovery loss and expanded safe operating area.

[0101] (Third Implementation)

[0102] The semiconductor device of this embodiment differs from the semiconductor devices of the first and second embodiments in that it does not have a second semiconductor region disposed within the second semiconductor layer and grounded to the second trench, and the concentration of the second conductivity type impurity is higher than that of the second semiconductor layer; nor does it have a second insulating film disposed within the second semiconductor layer and connected to the second semiconductor region. Here, descriptions that are repeated in the first and second embodiments are omitted.

[0103] Figure 11This is a schematic perspective view of the semiconductor device 120 according to this embodiment. In this embodiment, trenches 12a and 12c are described as examples of first trenches, and trenches 12b and 12d are described as examples of second trenches. Unlike semiconductor devices 100 and 110, semiconductor device 120 does not have semiconductor regions 18b (an example of a second semiconductor region) and 18c (an example of a second semiconductor region) that are in contact with the sidewalls of trench 12b, nor does it have semiconductor region 18f that is in contact with the sidewalls of trench 12d. Furthermore, it also does not have insulating films 20b (an example of a second insulating film) in contact with semiconductor region 18b, 20c (an example of a second insulating film) in contact with semiconductor region 18c, nor 20f in contact with semiconductor region 18f.

[0104] In other words, at least a portion of trench 12b has a portion within the anode layer 8 that is not in contact with semiconductor region 18b and semiconductor region 18c in the X direction. Additionally, trench 12b does not have a portion in contact with semiconductor region 18b and semiconductor region 18c in the X direction.

[0105] In other words, at least a portion of the trench 12d has a portion that is not in contact with the semiconductor region 18f in the X direction within the anode layer 8. Additionally, the trench 12d does not have a portion that is in contact with the semiconductor region 18f in the X direction.

[0106] Furthermore, in the X direction, the arrangement of the first trench (trench 12a and trench 12c) and the second trench (trench 12b and trench 12d) is not limited to... Figure 11 The arrangement shown.

[0107] As described above, in order to reduce the amount of holes injected into the semiconductor device and thus achieve low anode injection, it is preferable to minimize the volume of the semiconductor region 18. Therefore, the semiconductor device 120 includes a trench 12b in which the semiconductor region 18 is not provided. In the absence of the semiconductor region 18, it is not necessary to provide an insulating film 20 in contact with it.

[0108] In the semiconductor device of this embodiment, it is also possible to provide a semiconductor device that achieves reduced recovery loss and expanded safe operating area.

[0109] (Fourth Implementation)

[0110] The semiconductor device of this embodiment differs from that of the semiconductor device of the second embodiment in that the insulating film 20b in contact with the semiconductor region 18b extends in the Y direction. Here, descriptions that are repeated in the first to third embodiments are omitted.

[0111] Figure 12This is a schematic perspective view of the semiconductor device 130 of this embodiment.

[0112] Insulating films 20a, 20b, 20c, 20d, 20e, and 20f extend in the Y direction. The lengths of semiconductor regions 18b, 18c, and 18f in the Y direction are shorter than the lengths of semiconductor regions 18a, 18e, and 18f in the Y direction.

[0113] In other words, semiconductor device 130 and Figure 10 Unlike the semiconductor device 110 shown, the insulating film 20b, which is connected to the semiconductor region 18b, the insulating film 20c, which is connected to the semiconductor region 18c, and the insulating film 20f, which are connected to the semiconductor region 18f, extend in the Y direction. Therefore, the diffusion of holes in the X direction within the semiconductor region 18 can be further suppressed.

[0114] In the semiconductor device of this embodiment, it is also possible to provide a semiconductor device that achieves reduced recovery loss and expanded safe operating area.

[0115] (Fifth Implementation)

[0116] Figure 13 This is a schematic perspective view of the semiconductor device 140 of this embodiment.

[0117] Semiconductor device 140 includes semiconductor regions 18a, 18c, and 18e. It also includes insulating films 20a, 20c, and 20e. However, semiconductor regions 18b, 18d, and 18f are not included in semiconductor device 140. Furthermore, insulating films 20b, 20d, and 20f are also not included in semiconductor device 140.

[0118] The semiconductor device in this embodiment is described below. That is, in Figure 13 On the paper, a semiconductor region 18 and an insulating film 20 are provided in the right-side sidewall of each trench 12. On the other hand, no semiconductor region 18 and insulating film 20 are provided in the left-side sidewall of each trench 12.

[0119] In other words, in Figure 13 On the paper, in the sidewall on the left side of the trench 12b, at least a portion of the trench 12b has a portion that is not in contact with the semiconductor region 18b in the X direction within the anode layer 8a. Additionally, in Figure 13 On the paper, in the sidewall on the left side of the trench 12b, the trench 12b does not have a portion that connects to the semiconductor region 18b in the X direction.

[0120] In other words, in Figure 13 On the paper, in the sidewall on the left side of the trench 12c, at least a portion of the trench 12c has a portion that is not in contact with the semiconductor region 18c in the X direction within the anode layer 8b. Additionally, in Figure 13 On the paper, in the sidewall on the left side of the trench 12c, the trench 12c does not have a portion that is connected to the semiconductor region 18c in the X direction.

[0121] In other words, in Figure 13 On the paper, in the sidewall on the left side of the trench 12d, at least a portion of the trench 12d has a portion that is not in contact with the semiconductor region 18d in the X direction within the anode layer 8c. Additionally, in Figure 13 On the paper, in the sidewall on the left side of the trench 12d, the trench 12d does not have a portion that is connected to the semiconductor region 18d in the X direction.

[0122] In the semiconductor device 140 of this embodiment, the volume of the semiconductor region 18 is smaller than that of the semiconductor device 100 of the first embodiment, so the amount of holes injected into the semiconductor device can be reduced, thereby reducing anode injection.

[0123] In the semiconductor device of this embodiment, it is also possible to provide a semiconductor device that achieves reduced recovery loss and expanded safe operating area.

[0124] (Sixth Implementation Method)

[0125] Figure 14 This is a schematic perspective view of the semiconductor device 150 of this embodiment.

[0126] In the semiconductor device 140, semiconductor regions 18c and 18d are provided. Additionally, insulating films 20c and 20d are provided in the semiconductor device 140. On the other hand, semiconductor regions 18a, 18b, 18e, and 18f are not provided in the semiconductor device 140. Furthermore, insulating films 20a, 20b, 20e, and 20f are not provided in the semiconductor device 140.

[0127] In the semiconductor device 150 of this embodiment, insulating films 20c and 20d are provided opposite each other in the X direction, separated by an anode layer 8b. Semiconductor regions 18c and 18d are also provided opposite each other in the X direction, separated by an anode layer 8b. On the other hand, neither semiconductor region 18 nor insulating film 20 is provided in anode layer 8a or anode layer 8c.

[0128] In other words, in Figure 14In the paper, on the sidewall of the right side of the trench 12a, at least a portion of the trench 12a has a portion that is not in contact with the semiconductor region 18a in the X direction within the anode layer 8a. Additionally, in Figure 14 On the paper, in the sidewall on the right side of the trench 12a, the trench 12a does not have a portion that is connected to the semiconductor region 18a in the X direction.

[0129] In other words, in Figure 14 On the paper, in the sidewall on the left side of the trench 12b, at least a portion of the trench 12b has a portion that is not in contact with the semiconductor region 18b in the X direction within the anode layer 8a. Additionally, in Figure 14 On the paper, in the sidewall on the left side of the trench 12b, the trench 12a does not have a portion that connects to the semiconductor region 18b in the X direction.

[0130] In other words, in Figure 14 On the paper, in the sidewall on the right side of the trench 12c, at least a portion of the trench 12c has a portion that is not in contact with the semiconductor region 18e in the X direction within the anode layer 8c. Additionally, in Figure 14 In the paper, in the sidewall on the right side of the trench 12c, the trench 12c does not have a portion that is connected to the semiconductor region 18e in the X direction.

[0131] In other words, in Figure 14 On the paper, in the sidewall on the left side of the trench 12d, at least a portion of the trench 12d has a portion that is not in contact with the semiconductor region 18f in the X direction within the anode layer 8c. Additionally, in Figure 14 In the paper, in the sidewall on the left side of the trench 12d, the trench 12d does not have a portion that is connected to the semiconductor region 18f in the X direction.

[0132] In the semiconductor device 150 of this embodiment, the volume of the semiconductor region 18 is smaller than that of the semiconductor device 100 of the first embodiment, so the amount of holes injected into the semiconductor device can be reduced, thereby reducing anode injection.

[0133] In the semiconductor device of this embodiment, it is also possible to provide a semiconductor device that achieves reduced recovery loss and expanded safe operating area.

[0134] (Seventh Implementation)

[0135] The semiconductor device of this embodiment differs from the semiconductor devices of the first to sixth embodiments in that it includes: a second trench, which extends from the second semiconductor layer toward the first semiconductor layer but does not reach the first semiconductor layer and is disposed separately from the first insulating film; a second semiconductor region, which is disposed within the second semiconductor layer and grounded to the second trench, and has a higher concentration of second conductivity type impurities than the concentration of second conductivity type impurities in the second semiconductor layer; and a second insulating film, which is disposed within the second semiconductor layer and grounded to the second semiconductor region. Descriptions that are repeated in the first to sixth embodiments are omitted here.

[0136] Figure 15 This is a schematic perspective view of the semiconductor device 160 according to this embodiment. Trench 12b (an example of a second trench) and trench 12c do not reach the drift layer 6. In other words, the bottom of trench 12b and the bottom of trench 12c are located within the anode layer 8. On the other hand, trench 12a and trench 12d reach the drift layer 6.

[0137] Additionally, a semiconductor region 18a is provided that is in contact with the sidewall of trench 12a, and a semiconductor region 18f is provided that is in contact with the sidewall of trench 12d. On the other hand, the length in the Y direction of the semiconductor region 18c (an example of a third semiconductor region) which is in contact with the sidewall of trench 12b is shorter than the length of semiconductor region 18a in the Y direction. Furthermore, semiconductor regions 18b, 18d, and 18e are not provided in the semiconductor device 160. Additionally, semiconductor region 18c may extend along the sidewall of trench 12b in the Y direction. In other words, the length of semiconductor region 18c in the Y direction may be equal to the length of semiconductor region 18a in the Y direction. Furthermore, the length of insulating film 20c (an example of a second insulating film) in the Y direction may, for example, be equal to the length of semiconductor region 18c in the Y direction. Moreover, for example, multiple semiconductor regions 18c that are separated from each other may be provided in contact with the sidewall of trench 12b along the Y direction. For example, multiple insulating films 20c, which are separated from each other, can be grounded along the Y direction and connected to multiple semiconductor regions 18c respectively.

[0138] In other words, in Figure 15 On the paper, in the sidewall on the left side of the trench 12b, at least a portion of the trench 12b has a portion that is not in contact with the semiconductor region 18b in the X direction within the anode layer 8a. Additionally, in Figure 14 On the paper, in the sidewall on the left side of the trench 12b, the trench 12a does not have a portion that connects to the semiconductor region 18b in the X direction.

[0139] In other words, in Figure 15On the paper, in the sidewall on the left side of the trench 12c, at least a portion of the trench 12c has a portion that is not in contact with the semiconductor region 18d in the X direction within the anode layer 8b. Additionally, in Figure 14 On the paper, in the sidewall on the left side of the trench 12b, the trench 12a does not have a portion that connects to the semiconductor region 18b in the X direction.

[0140] In other words, in Figure 15 On the paper, in the sidewall on the right side of the trench 12c, at least a portion of the trench 12c has a portion that is not in contact with the semiconductor region 18e in the X direction within the anode layer 8c. Additionally, in Figure 15 On the paper, in the sidewall on the right side of the trench 12c, the trench 12c does not have a portion that is connected to the semiconductor region 18e in the X direction.

[0141] To enhance the removal of holes generated by avalanche breakdown, it is preferable that avalanche breakdown occurs at the bottom of trench 12a and the bottom of trench 12d, which are longer in the Z direction than trench 12b and trench 12c, to effectively remove holes. If a semiconductor region 18c with a shorter length in the Y direction is provided, then p + The proportion of the semiconductor region 18 is reduced, enabling low anode injection. On the other hand, during recovery, hole discharge near the trench 12b where the semiconductor region 18c is located is weakened. That is, hole discharge during recovery needs to occur near the trenches 12a and 12d. In this embodiment, avalanche breakdown is more likely to occur at the bottom of the trench 12a and the bottom of the trench 12d, which are longer in the Z direction than the trenches 12b and 12c. As a result, holes generated by avalanche breakdown can be effectively discharged. This is because, compared to trench structures of the same overall length, holes are more easily discharged from the bottom of the trench, which is stably aligned. On the other hand, in the shorter trenches 12b and 12c in the Z direction, avalanche breakdown at the bottom of the trench is less likely to occur, thus reducing the number of hole discharge paths.

[0142] In the semiconductor device of this embodiment, it is also possible to provide a semiconductor device that achieves reduced recovery loss and expanded safe operating area.

[0143] Several embodiments and examples of the present invention have been described, but these embodiments and examples are provided by way of example and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope or spirit of the invention, and are included in the scope of the invention and its equivalents as set forth in the claims.

Claims

1. A semiconductor device, characterized in that, have: First electrode; A first semiconductor layer of a first conductivity type is disposed on the first electrode; A second semiconductor layer of a second conductivity type is disposed on the first semiconductor layer; The second electrode is disposed on the second semiconductor layer; A first trench extends from the second semiconductor layer to the first semiconductor layer; A first semiconductor region is disposed in the second semiconductor layer and grounded to the first trench, wherein the second conductivity type impurity concentration of the first semiconductor region is higher than the second conductivity type impurity concentration of the second semiconductor layer; as well as A first insulating film is disposed within the second semiconductor layer and grounded to the first semiconductor region. When the direction from the first semiconductor layer toward the second semiconductor layer is taken as the first direction, and the direction perpendicular to the first direction and parallel to the first semiconductor layer is taken as the second direction, the first trench, the first semiconductor region, the first insulating film, and the second semiconductor layer are sequentially arranged in the second direction.

2. The semiconductor device as claimed in claim 1, characterized in that, The length of the first insulating film in the first direction is more than 0.6 times and less than 1.5 times the length of the first semiconductor region in the first direction.

3. The semiconductor device as claimed in claim 1, characterized in that, The length of the second semiconductor layer in the first direction is longer than the length of the first insulating film in the first direction.

4. The semiconductor device as claimed in claim 1, characterized in that, The length of the second semiconductor layer in the first direction is longer than the length of the first semiconductor region in the first direction.

5. The semiconductor device as claimed in claim 1, characterized in that, The first insulating film contains silicon oxide.

6. The semiconductor device as claimed in claim 1, characterized in that, The semiconductor device further includes a plurality of first semiconductor regions, which are disposed separately from each other within the second semiconductor layer.

7. The semiconductor device as claimed in claim 1, characterized in that, The semiconductor device also includes: A plurality of the first semiconductor regions are disposed separately within the second semiconductor layer; and Multiple first insulating films are disposed separately within the second semiconductor layer.

8. The semiconductor device as claimed in claim 1, characterized in that, The semiconductor device includes: The second trench is connected to the second semiconductor layer in the second direction; The second semiconductor region is grounded within the second semiconductor layer and connected to the second trench. The second conductivity type impurity concentration in the second semiconductor region is higher than that in the second semiconductor layer. as well as The second insulating film is disposed within the second semiconductor layer and grounded to the second semiconductor region.

9. The semiconductor device as claimed in claim 8, characterized in that, The first groove and the second groove extend upward at a third point intersecting the first direction and the second direction, respectively. The length of the second semiconductor region in the third direction is shorter than the length of the first semiconductor region in the third direction.

10. The semiconductor device as claimed in claim 9, characterized in that, The length of the second semiconductor region in the third direction is shorter than the length of the second insulating film in the second direction.

11. The semiconductor device as claimed in claim 1, characterized in that, The semiconductor device further includes a second trench that is connected to the second semiconductor layer in the second direction. At least a portion of the second trench has a portion that is not connected to the second semiconductor region within the second semiconductor layer, wherein the second conductivity type impurity concentration in the second semiconductor region is higher than the second conductivity type impurity concentration in the second semiconductor layer.

12. The semiconductor device as claimed in claim 11, characterized in that, The second trench has a portion that is in contact with the second semiconductor region.

13. The semiconductor device as claimed in claim 8, characterized in that, The semiconductor device further includes a plurality of second semiconductor regions disposed separately within the second semiconductor layer.

14. The semiconductor device as claimed in claim 8, characterized in that, The semiconductor device also includes: A plurality of second semiconductor regions are disposed separately within the second semiconductor layer; and Multiple second insulating films are disposed separately from each other within the second semiconductor layer.

15. The semiconductor device as claimed in claim 8, characterized in that, The second trench reaches the first semiconductor layer.

16. The semiconductor device as claimed in claim 8, characterized in that, The bottom of the second trench is located within the second semiconductor layer.

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