Circuit for USB fast charging

Abstract

The application provides a circuit for USB fast charging, comprising: a fast charging control circuit and a plurality of fast charging protocol circuits connected to the fast charging control circuit, wherein each of the plurality of fast charging protocol circuits is configured to be connected to a respective load and detect a load voltage required by the respective load according to a USB protocol; the fast charging control circuit is configured to generate an input voltage according to the load voltage detected by each of the plurality of fast charging protocol circuits, wherein each of the plurality of fast charging protocol circuits uses the input voltage to charge the respective load.

Description

[0001] Related applications

[0002] This application claims priority to Chinese patent application 202211030611.1, entitled "Circuit for USB Fast Charging", filed on August 26, 2022. Technical Field

[0003] This invention relates to the field of circuits, and in particular, to a circuit for USB (Universal Serial Bus) fast charging. Background Technology

[0004] As the battery capacity of electronic devices continues to increase and the USB (Universal Serial Bus) fast charging protocol continues to develop, the circuits used for USB fast charging are also constantly evolving.

[0005] In particular, to improve charging efficiency, fast charging circuits have been developed that simultaneously charge multiple loads using multiple fast charging protocol circuits. However, to meet the charging needs of all fast charging protocol circuits, very large voltage and / or power redundancy is typically required for the fast charging control circuits connected to these protocol circuits. This necessitates larger transformers and high-specification power devices, resulting in a larger circuit footprint and higher cost. Furthermore, such fast charging circuits cannot adapt to the charging requirements (e.g., voltage and / or power requirements) of the loads connected to each fast charging protocol circuit.

[0006] Therefore, a circuit for USB fast charging is needed that can adapt to the charging requirements of various loads. Summary of the Invention

[0007] An exemplary embodiment of the present invention provides a circuit for USB fast charging, comprising: a fast charging control circuit and a plurality of fast charging protocol circuits connected to the fast charging control circuit, wherein each of the plurality of fast charging protocol circuits is configured to be connected to a respective load and to detect a load voltage required by the respective load according to a USB protocol; the fast charging control circuit is configured to generate an input voltage based on the respective load voltages detected by the plurality of fast charging protocol circuits, wherein each of the fast charging protocol circuits uses the input voltage to charge its respective load.

[0008] The circuit for USB fast charging according to an exemplary embodiment of the present invention can generate a charging voltage for charging each load according to the load voltage required by the loads connected to the multiple fast charging protocol circuits, thereby flexibly and accurately adapting to the charging needs of the loads without significantly increasing the circuit's footprint and cost. Attached Figure Description

[0009] The invention can be better understood from the following description of specific embodiments of the invention in conjunction with the accompanying drawings, wherein:

[0010] Figure 1 A schematic circuit diagram of a circuit for USB fast charging according to an exemplary embodiment is shown.

[0011] Figure 2 A schematic circuit diagram of a circuit for USB fast charging according to another exemplary embodiment is shown.

[0012] Figure 3 A schematic circuit diagram of a circuit for USB fast charging according to yet another exemplary embodiment is shown.

[0013] Figure 4 A schematic circuit diagram of a circuit for USB fast charging according to an exemplary embodiment of the present invention is shown.

[0014] Figure 5 A schematic circuit diagram of a fast charging control circuit according to an exemplary embodiment of the present invention is shown.

[0015] Figure 6 A schematic circuit diagram of a fast charging protocol circuit according to an exemplary embodiment of the present invention is shown.

[0016] Figure 7 A schematic circuit diagram of a circuit for USB fast charging according to another exemplary embodiment of the present invention is shown.

[0017] Figure 8 A timing diagram of the signals of a circuit for USB fast charging according to an exemplary embodiment of the present invention is shown during the power-on detection phase.

[0018] Figure 9 A timing diagram of the signals of a circuit for USB fast charging according to an exemplary embodiment of the present invention is shown during the power regulation phase.

[0019] Figure 10 A timing diagram of the signals of a circuit for USB fast charging according to an exemplary embodiment of the present invention is shown when power protection occurs.

[0020] Figure 11 A timing diagram of the signals of a circuit for USB fast charging according to an exemplary embodiment of the present invention is shown when the power protection is released.

[0021] Figure 12 A schematic circuit diagram of a circuit for USB fast charging according to yet another exemplary embodiment of the present invention is shown.

[0022] Figure 13A schematic circuit diagram of a fast charging protocol circuit according to another exemplary embodiment of the present invention is shown.

[0023] Figure 14 A schematic circuit diagram of a circuit for USB fast charging according to yet another exemplary embodiment of the present invention is shown. Detailed Implementation

[0024] The features and exemplary embodiments of various aspects of the present invention will now be described in detail. Numerous specific details are set forth in the following detailed description to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without requiring some of these specific details. The following description of embodiments is merely intended to provide a better understanding of the invention by illustrating examples of the invention. The invention is by no means limited to any specific configurations and algorithms presented below, but covers any modifications, substitutions, and improvements to elements, components, and algorithms without departing from the spirit of the invention. Well-known structures and techniques are not shown in the drawings and the following description in order to avoid unnecessarily obscuring the invention.

[0025] Figure 1 A schematic circuit diagram of a circuit for USB fast charging according to an exemplary embodiment is shown.

[0026] Figure 1 A circuit for USB fast charging is shown, the circuit including a fast charging control circuit 110 and multiple ( Figure 1 The diagram shows N fast charging protocol circuits 120-1 to 120-N (where N can be any integer) connected to the fast charging control circuit 110. The voltage input pin VIN of each of the fast charging protocol circuits 120-1 to 120-N is connected to the voltage output pin VOUT of the fast charging control circuit 110, so that each fast charging protocol circuit can use the voltage output from the voltage output pin VOUT of the fast charging control circuit 110 as the voltage for its connected circuit (e.g., via...). Figure 1 The USB Type C 1-N connection shown is used to charge the load. For example, the fast charging protocol circuits 120-1 to 120-N can generate the output voltage VOUT for charging the corresponding load by the switching regulators based on the voltage input to the voltage input pin VIN.

[0027] However, the various fast charging protocol circuits in this USB fast charging circuit are independent of each other, except that they are all connected to the voltage output pin VOUT of the fast charging control circuit 110 via the voltage input pin VIN. Therefore, in order for the fast charging control circuit 110 to meet the charging requirements of all fast charging protocol circuits, the fast charging control circuit 110 needs to have a large voltage and / or power redundancy. This results in the circuit for USB fast charging requiring a large transformer and high-specification power devices, leading to a large circuit footprint, high cost, and the inability of the circuit for USB fast charging to adapt to the charging requirements (e.g., voltage and / or power requirements) of each fast charging protocol circuit, i.e., each connected load.

[0028] Figure 2 A schematic circuit diagram of a circuit for USB fast charging according to another exemplary embodiment is shown.

[0029] Figure 2 Another circuit for USB fast charging is shown, which includes a fast charging control circuit 210 and multiple ( Figure 2 The diagram shows N fast charging protocol circuits 220-1 to 220-N connected to the fast charging control circuit 210. Figure 2 The fast charging control circuit 210 and the fast charging protocol circuits 220-1 to 220-N are respectively connected to... Figure 1 The fast charging control circuit 110 and the fast charging protocol circuits 120-1 to 120-N are similar, except that: Figure 2 The various fast charging protocol circuits 220-1 to 220-N are also connected to the fast charging control circuit 210's pin VDET via pin ID, and pin VDET is connected to reference ground via resistor Rd. This connection method is used to: detect a USB port (e.g., Figure 2 When any one or more of the USB type C 1-N in the circuit are connected to a load, the corresponding fast charging protocol circuit outputs a fixed current Id on pin ID, so that the magnitude of the current flowing through resistor Rd can be used to determine whether the circuit is charging a single load or multiple loads simultaneously.

[0030] However, this type of circuit for USB fast charging also requires a large voltage and / or power redundancy, which also leads to the need for a large transformer and high-specification power devices, resulting in a large circuit footprint, high cost, and inability to adapt to the charging needs of various fast charging protocol circuits, i.e., various connected loads.

[0031] Figure 3 A schematic circuit diagram of a circuit for USB fast charging according to yet another exemplary embodiment is shown.

[0032] Figure 3This illustrates yet another circuit for USB fast charging, which includes a fast charging control circuit 310 and multiple ( Figure 3 The diagram shows N fast charging protocol circuits 320-1 to 320-N connected to the fast charging control circuit 310. Figure 3 The fast charging control circuit 310 and the fast charging protocol circuits 320-1 to 320-N are respectively connected to... Figure 1 The fast charging control circuit 110 and the fast charging protocol circuits 120-1 to 120-N are similar, except that: Figure 3 Each fast charging protocol circuit 320-1 to 320-N is also connected to the fast charging control circuit 310 via an MCU (microcontroller unit) 330. The MCU 330 can configure the voltage and / or power input to each fast charging protocol circuit 320-1 to 320-N according to the charging requirements of the loads connected to each fast charging protocol circuit 320-1 to 320-N.

[0033] However, this circuit for USB fast charging requires an additional MCU 330 and its associated circuitry (not shown), resulting in higher circuit costs and a larger circuit footprint.

[0034] In order to meet the charging needs of the load without increasing the circuit footprint and cost, the following circuit for USB fast charging is proposed according to an embodiment of the present invention.

[0035] Figure 4 A schematic circuit diagram of a circuit for USB fast charging according to an exemplary embodiment of the present invention is shown.

[0036] like Figure 4 As shown, the circuit for USB fast charging according to an exemplary embodiment of the present invention includes a fast charging control circuit 410 and a plurality of ( ) connected to the fast charging control circuit 410. Figure 4 The diagram shows N fast charging protocol circuits 420-1 to 420-N.

[0037] Each of the multiple fast charging protocol circuits 420-1 to 420-N is configured to be connected to its respective load (e.g., via...). Figure 4 The USB Type-C 1-N connection shown in the diagram detects the required load voltage (e.g., V) for each load according to the USB protocol. REF2 ).

[0038] The fast charging control circuit 410 is configured to detect various load voltages (e.g., according to multiple fast charging protocol circuits 420-1 to 420-N) based on the respective load voltages. Figure 4 The voltage at pin VOUTID or pin VID (as shown) generates the input voltage (e.g., Figure 4 The voltage at pin VIN shown is VIN = f1(VVID Each fast charging protocol circuit 420-1 to 420-N uses an input voltage (VIN = f1(V)). VID To charge their respective loads.

[0039] In one embodiment, each fast charging protocol circuit 420-1 to 420-N can detect its respective load voltage (V) during the power-on detection phase. REF2 As an example, the power-on detection phase may correspond to the time period after multiple fast charging protocol circuits 420-1 to 420-N are connected to the fast charging control circuit 410 and before the fast charging control circuit 410 completes the generation of the input voltage (i.e., the time period during which each fast charging protocol circuit 420-1 to 420-N has not yet output charging power to its respective load).

[0040] In one embodiment, the circuit for USB fast charging according to an embodiment of the present invention may further include an AC-to-DC switching regulator 440 (e.g., Figure 7 (As shown). The fast charging control circuit 410 can be configured to detect the highest load voltage (V) among various load voltages detected by multiple fast charging protocol circuits 420-1 to 420-N. VID =MAX(V VOUTID V VOUTID =f2(V REF2 The input voltage is generated using an AC-to-DC switching regulator 440.

[0041] In one embodiment, the circuit for USB fast charging according to the present invention may further include multiple DC-to-DC switching regulators 430-1 to 430-N (e.g., Figure 7 (As shown). Multiple DC-to-DC switching regulators 430-1 to 430-N can correspond one-to-one with multiple fast charging protocol circuits 420-1 to 420-N. In this case, each fast charging protocol circuit 420-1 to 420-N can also be configured to: during the power-on detection phase, detect the load current (I0) required by its respective load. REF Each DC-to-DC switching regulator 430-1 to 430-N can be configured to detect the load current and load voltage based on the corresponding fast charging protocol circuitry (e.g., via pin I of the fast charging protocol circuitry). REF The output load current is transmitted through pin V of the fast charging protocol circuit. REF Output load voltage), which generates the output voltage from the input voltage (VIN) (e.g., Figure 4 or Figure 7 The voltage at pin VOUT in the circuit is used to enable the corresponding fast charging protocol circuit to use the output voltage to charge the connected load.

[0042] Furthermore, to prevent the total charging power of multiple fast charging protocol circuits 420-1 to 420-N from exceeding the maximum power of the fast charging control circuit 410 and causing circuit overload failure, in one embodiment, during the power-on detection phase, the fast charging control circuit 410 may also be configured to generate a reference power indicating the maximum output power of the fast charging control circuit 410, and each fast charging protocol circuit 420-1 to 420-N may also be configured to detect and store this reference power (e.g., in...). Figure 6 V PMAX express).

[0043] In one embodiment, to facilitate the output and detection of the reference power and subsequent adaptive adjustment of the charging power of each fast charging protocol circuit 420-1 to 420-N to charge the load, the first power pin PID of the fast charging control circuit 410 can be connected to the second power pin POUTID of the fast charging protocol circuit. During the power-on detection phase, the fast charging control circuit 410 can output the reference power through the first power pin PID, and each fast charging protocol circuit 420-1 to 420-N can detect the reference power through its respective second power pin POUTID.

[0044] To adaptively adjust the charging power of each fast charging protocol circuit 420-1 to 420-N when charging the load, in one embodiment, during the power-on detection phase and the power adjustment phase following the power-on detection phase, each fast charging protocol circuit 420-1 to 420-N may also be configured to detect the actual load power of its respective load according to the USB protocol. During the power adjustment phase, each fast charging protocol circuit 420-1 to 420-N may also be configured to: input the detected actual load power to its respective second power pin POUTID; and detect the total actual load power of the multiple fast charging protocol circuits 420-1 to 420-N through their respective second power pin POUTID (e.g., in...). Figure 6 V POUTID (Indicated); When the total actual load power is greater than the above reference power, reduce the actual load power of each load so that the total actual load power of the multiple fast charging protocol circuits 420-1 to 420-N is less than the above reference power.

[0045] In one embodiment, the individual fast charging protocol circuits 420-1 to 420-N that are reducing the actual load power can reduce the actual load power of their respective loads at the same rate.

[0046] To prevent the power of any fast charging protocol circuit from being reduced too much to meet the minimum charging requirements of the connected load (e.g., potentially causing the load to malfunction, such as causing screen flickering in electronic devices), in one embodiment, for any one of the multiple fast charging protocol circuits 420-1 to 420-N, when the actual load power of any fast charging protocol circuit is reduced to the minimum power threshold of the corresponding load, that fast charging protocol circuit charges the corresponding load at the minimum power threshold to protect the power of the corresponding load. At this time, the other fast charging protocol circuits that are not under power protection can continue to reduce (e.g., at the same rate) the actual load power of their respective loads so that the total actual load power of the multiple fast charging protocol circuits is less than the reference power.

[0047] Furthermore, during this power adjustment phase, there may be situations where, for example, one (or more) loads disconnect from their respective fast-charging protocol circuits upon completion of charging, causing a sudden decrease in the total actual load power. In such cases, the actual load power of each fast-charging protocol circuit can be further reduced, and the power protection of the fast-charging protocol circuits that have been configured for power protection can be released. For example, in one embodiment, during the power adjustment phase, each fast-charging protocol circuit can also be configured to: after reducing the actual load power of its respective load, increase the actual load power of its respective load when the total actual load power is detected to be less than the minimum power protection threshold, so that the total actual load power is greater than the minimum power protection threshold and less than the reference power. In one embodiment, each fast-charging protocol circuit can increase the actual load power of its respective load at the same rate.

[0048] The following describes in detail the operation of the fast charging control circuit and the fast charging protocol circuit during the power-on detection phase and the power adjustment phase, with reference to the circuit diagrams of the fast charging control circuit and the fast charging protocol circuit used in USB fast charging circuits.

[0049] Figure 5 A schematic circuit diagram of a fast charging control circuit according to an exemplary embodiment of the present invention is shown. Figure 6 A schematic circuit diagram of a fast charging protocol circuit according to an exemplary embodiment of the present invention is shown. Figure 7 A schematic circuit diagram of a circuit for USB fast charging according to another exemplary embodiment of the present invention is shown.

[0050] Reference Figure 4 or Figure 7The fast charging control circuit 410 is connected to the AC-to-DC switching regulator 440 via its input pins OPTO, IFB, VFB, VIN, and ISP. The fast charging control circuit 410 is connected to the pins VIN, VOUTID, and POUTID of each of the fast charging protocol circuits 420-1 to 420-N via its output pins VIN, VID, and PID, respectively. The PID pin of the fast charging control circuit 410 is connected via a filter capacitor C. VID Connected to reference ground, the PID pin of the fast charging control circuit 410 is connected via the sense resistor R. PID Connect to the reference location.

[0051] Each fast charging protocol circuit 420-1 to 420-N is connected via pin V REF and I REF Each circuit is connected to its respective DC-to-DC switching regulator 430-1 to 430-N. Each fast-charging protocol circuit 420-1 to 420-N outputs charging voltage to the load via pin VOUT (via the VBUS pin). Each fast-charging protocol circuit 420-1 to 420-N detects the required load voltage, load current, and load power of its respective load via pins D-, D+, CC1, and CC2.

[0052] Reference Figure 5 , Figure 5 The internal circuit diagram of the fast charging control circuit 410 is shown. Pin VID of the fast charging control circuit 410 is connected to a gain network 411. The gain network 411 is used to increase the voltage V at pin VID. VID (V VID =MAX(V VOUTID V VOUTID =f2(V REF2 (This will be explained further below) is converted to voltage V. REF1 .

[0053] Voltage V REF1 The input voltage VIN is fed into the compensation network 412, which then controls the AC-to-DC switching regulator 430 to generate the input voltage VIN. That is, the input voltage VIN is the voltage V... VID The function, which can be expressed as VIN = f1(V VID The input voltage VIN is the input voltage of the DC-to-DC switching regulators 430-1 to 430-N controlled by all subsequent fast charging protocol circuits 420-1 to 420-N.

[0054] The voltage VIN at the input pin VIN of the fast charging control circuit 410 is changed to voltage VIN_fb via voltage divider network 413. Voltage VIN_fb is input to the positive input of comparator CMP0 and the negative input of comparator CMP1.

[0055] The negative input terminal of comparator CMP0 receives the comparator threshold voltage VIN_PG, and the output terminal of comparator CMP0 is connected to the enable terminal EN of comparator CMP1. For example, the enable terminal EN of comparator CMP1 is active high; that is, comparator CMP1 operates when the enable terminal EN is high, and stops operating and outputs a low level when the enable terminal EN is low.

[0056] The positive input of comparator CMP1 is connected to the power-on threshold voltage VIN_POR, and VIN_POR can be set to be greater than VIN_PG. The output of comparator CMP1 is connected to the fall-delay circuit 414. The fall-delay circuit 414 is connected to the control terminal of switch S1. For example, switch S1 is turned on when the fall-delay circuit 414 outputs a high level, and switch S1 is turned off when the fall-delay circuit 414 outputs a low level.

[0057] Switch S1 is connected to current source I PMAX And the PID pin. When switch S1 is turned on, the current flowing into the PID pin is I. PID =I PMAX When switch S1 is open, the current I flowing into the PID pin... PID =0.

[0058] Reference Figure 6 , Figure 6 An internal circuit diagram of a fast charging protocol circuit 420 (hereinafter, reference numeral 420 may be used to denote any of the fast charging protocol circuits 420-1 to 420-N) is shown.

[0059] The fast charging protocol communication module 421 in the fast charging protocol circuit 420 communicates with the connected load through physical communication lines D+, D-, CC1, and CC2 (e.g., via USB Type C) to detect information such as load power, load voltage, and load current. The detected information is then converted into a voltage V, representing the load voltage, via the DAC (digital-to-analog converter) in the fast charging protocol circuit 420. REF2 Voltage V, representing load power POUT and the current I that characterizes the load current. REF .

[0060] Voltage V REF2 and current I REF via pin V REF and pin I REFThe output is sent to a DC-to-DC switching regulator 430 (hereinafter, reference numeral 430 may be used to denote the DC-to-DC switching regulator corresponding to the fast charging protocol circuit 420) to control the output voltage VOUT and output current IOUT of the DC-to-DC switching regulator 430.

[0061] Voltage V POUT Controlled current source I POUT The input signal, i.e., the controlled current source I POUT Output current I POUT It is voltage V POUT The function, which can be represented as I POUT =f3(V POUT ).

[0062] The VIN pin of the fast charging protocol circuit 420 is connected to a voltage divider network 422, which is exactly the same as the voltage divider network 413 in the fast charging control circuit 410. The voltage VIN is changed to voltage VIN_fb by the voltage divider network 422, and the voltage VIN_fb is input to the positive input terminal of the comparator CMP2.

[0063] The negative input of comparator CMP2 receives the power-on threshold voltage VIN_POR, which is the same as the power-on threshold voltage VIN_POR in the fast charging control circuit 410. The output of comparator CMP2 is connected to the power-on delay circuit 424 and V... PMAX The trigger terminal of the ADC (analog-to-digital converter) of the detection module 423.

[0064] When the input level of the Trigger terminal of the VPMAX detection module 423 changes from low to high, the ADC of the VPMAX detection module 423 is triggered to respond to the voltage V. POUTID Sample the voltage V of the ADC. POUTID The result of the AD conversion is latched and output to the DAC (digital-to-analog converter) of the VPMAX detection module 423, which converts the latched digital signal into an analog signal V. PMAX (Corresponding to the reference power above). Analog signal V PMAX It is input to the negative input terminal of comparator CMP3.

[0065] The output of the power-on delay circuit 424 is connected to the enable terminal EN of the fast charging protocol communication module 421 and the input of the AND gate &. The DIS terminal of the fast charging protocol communication module 421 is connected to the other input of the AND gate &. The output of the AND gate & is connected to the enable terminal EN of the comparator CMP3.

[0066] The enable terminal EN of the fast charging protocol communication module 421 controls its operation. For example, when the enable terminal EN of the fast charging protocol communication module 421 is high, the fast charging protocol communication module 421 is working; when the enable terminal EN of the fast charging protocol communication module 421 is low, the fast charging protocol communication module 421 is not working. When it is not working, its input is in a high impedance state, and its output is always low.

[0067] The enable pin EN of comparator CMP3 controls its operation. For example, when the enable pin EN of comparator CMP3 is high, comparator CMP3 is active; when the enable pin EN is low, comparator CMP3 is inactive. When comparator CMP3 is inactive, its input is in a high-impedance state, and its output is always low. The positive input of comparator CMP3 is connected to pin POUTID of the fast charging protocol circuit 420, the drain of linear MOSFET Q1, and V... PMAX The ADC input terminal of the detection module 423. The negative input terminal of the comparator CMP3 is connected to the DAC output terminal of the VPMAX detection module 423; the output terminal of the comparator CMP3 is connected to the gate of the linear MOSFET Q1 and the Trigger terminal of the fast charging protocol communication module 421 via resistor R1.

[0068] The gate of linear MOSFET Q1 is connected to ground via capacitor C1, and the source of linear MOSFET Q1 is also connected to ground. The gate voltage V of linear MOSFET Q1... G It is converted into a compensated power voltage V by the gain network 425. P_fb , can be represented as V P_fb =f4(V G ).

[0069] When the input voltage at the Trigger terminal of the fast charging protocol communication module 421 changes from high level to low level, the falling edge triggers the ADC of the fast charging protocol communication module 421 to sample and store the voltage V at this moment. P_fb .

[0070] The negative input of comparator CMP4 is connected to pin POUTID of the fast charging protocol circuit 420, and the positive input of comparator CMP4 receives the minimum power protection release voltage V. PMIN_RELEASE (Corresponding to the minimum power protection threshold above). The output of comparator CMP4 is connected to the V of the fast charging protocol communication module 421. PMIN_RE end.

[0071] The VOUTID pin of the fast charging protocol circuit 420 is connected to the cathode of diode D1, and the anode of diode D1 is connected to the controlled voltage source V. VOUTID The positive terminal. Controlled voltage source V VOUTIDThe negative terminal is connected to the reference ground. The controlled voltage source V VOUTID The output voltage V VOUTID is the load voltage V REF2 function, which can be expressed as V VOUTID = f2(V REF2 ).

[0072] Next, referring to the timing diagrams of the signals of the fast charging control circuit 410 and the fast charging protocol circuit 420 shown above, the specific working process of the fast charging control circuit 410 and the fast charging protocol circuit 420 will be described.

[0073] Figure 8 The timing diagram of the signals of the circuit for USB fast charging in the power-on detection stage according to an exemplary embodiment of the present invention is shown. Figure 9 The timing diagram of the signals of the circuit for USB fast charging in the power regulation stage according to an exemplary embodiment of the present invention is shown. Figure 10 The timing diagram of the signals of the circuit for USB fast charging when power protection occurs according to an exemplary embodiment of the present invention is shown.

[0074] 1) Power-on initialization power detection phase (i.e., the power-on detection phase mentioned above)

[0075] Refer to Figure 8 and Figure 5 and Figure 6 , before the circuit is powered on, the default state is VIN_fb = 0, the outputs of the comparators CMP0 - CMP3 are all 0, V REF1 = 0, V REF2 = 0, V POUT = 0, V PID = V POUTID = 0.

[0076] After power-on occurs, the voltage VIN_fb increases as the voltage VIN increases. When VIN_fb > VIN_PG, the output voltage of the comparator CMP0 changes from low level to high level. Therefore, the comparator CMP1 starts to work, and its output voltage changes from low level to high level. Thus, the control signal of the switch S1 changes from low level to high level, the switch S1 is turned on, and thus the current I PMAX flows through the switch S1 into the pin PID. Since at this time VIN_fb < VIN_POR, therefore, V POUT = 0, I POUT = f3(V POUT ) = 0. According to Kirchhoff's law, the voltage V PID on the resistor R PID = I PMAX ×R PIDBecause the POUTID pin of the fast charging protocol circuit 420 is directly connected to the PID pin of the fast charging control circuit 410, therefore V POUTID =V PID .

[0077] Subsequently, when VIN_fb > VIN_POR, the output voltage of comparator CMP1 changes from high to low, and the power-on delay circuit 424 delays for T. D1 Then, the control signal of switch S1 changes from high level to low level. That is, after a delay T on the falling edge of the output voltage of comparator CMP1... D1 Afterwards, the PID pin of the fast charging control circuit 410 stops flowing current, at which point V POUTID =V PID =0.

[0078] Furthermore, when VIN_fb > VIN_POR, the output voltage of comparator CMP2 changes from low to high. The rising edge of this voltage triggers the ADC of the VPMAX detection module 423, causing the ADC to sample and latch the VPOUTID voltage at this time, and represent the sampled voltage as V. PMAX (This voltage corresponds to a reference power indicating the maximum output power of the fast charging control circuit 410) and is output to the negative input of comparator CMP3 via a DAC. Furthermore, the output voltage of comparator CMP2, which changes from low to high, is delayed by a time T by the power-on delay circuit 424. D2 Afterwards, the control terminal of comparator CMP3 and the enable signal EN of fast charging protocol communication module 421 both go high, and both comparator CMP3 and fast charging protocol communication module 421 begin to work. The delay time TD2 is set to be greater than TD1. At this point, the power-on initialization power detection phase ends, and the adaptive power adjustment phase (the power adjustment phase mentioned above) can begin.

[0079] 2) Adaptive output power adjustment stage

[0080] Reference Figure 9 as well as Figure 5 and Figure 6 The output voltage of comparator CMP2, which changes from low to high, is delayed by T by the power-on delay circuit 424. D2 After that, the enable signal EN of both comparator CMP3 and fast charging protocol communication module 421 goes high, and both comparator CMP3 and fast charging protocol communication module 421 start working.

[0081] The fast charging protocol communication module 421 obtains information about the load power, load voltage, and load current required by the load through the communication signals on the physical connection lines D+, D-, CC1, and CC2 on the USB port, and outputs this information as a voltage V representing the load voltage through the DAC of the fast charging protocol communication module 421. REF2 Voltage V, representing load power POUT and the current I that characterizes the load current. REF Voltage V REF2 and current I REF It is output to the reference terminal of the DC-to-DC switching regulator 430 to control the output voltage and output current of the switching regulator 430.

[0082] V REF2 It is also used to control the controlled voltage source V VOUTID V can be set. VOUTID =V REF0 +K1×V REF2 Where K1 is a positive coefficient greater than 0, V REF0 Used as the initial voltage reference. For example, when V REF0 When applied to pin VID of the fast charging control circuit 410, the fast charging control circuit 410 can control the AC-to-DC switching regulator 440 to generate an input voltage VIN of 5V.

[0083] When multiple fast charging protocol circuits exist, diode D1 ensures that the voltage on pin VID of fast charging control circuit 410 is the same as the voltage of all fast charging protocol circuits 420. VOUTID The maximum value in, which can be expressed as V VID =MAX(V VOUTID Because during this stage, switch S1 in the fast charging control circuit 410 is open, i.e., I PID =0, therefore the resistance R PID The voltage across the terminals is only related to I POUTID Related. According to Kirchhoff's laws, V PID =V POUTID =∑I POUTID ×R PID At this time, the voltage V POUTID It can represent the total load power of all fast charging protocol circuits.

[0084] When V POUTID <V PMAX At this time, comparator CMP3 outputs a low level. If there is no charge in capacitor C1 at this time, then V G =0, correspondingly, VP_fb=0, Q1 is cut off, Idischarge=0. Each fast charging protocol communication module control module 421 controls the DC-to-DC switching regulator 430 to output the power required by the load according to the charging needs of its respective load.

[0085] When V POUTID ≥V PMAX When the sum of the load power of all fast charging protocol circuits is higher than the maximum output power of the fast charging control circuit 410, each fast charging protocol circuit can monotonically reduce its own load power at the same rate of change until the sum of the load power of all fast charging protocol circuits is lower than the maximum output power of the fast charging control circuit 410.

[0086] The specific working principle can be summarized as follows: when V POUTID ≥V PMAX At this time, the output voltage of comparator CMP3 changes from low level to high level. This output voltage passes through a first-order low-pass filter network composed of resistor R1 and capacitor C1, causing V to... G The current gradually increases. Simultaneously, because MOSFET Q1 operates in the constant current region, the current Idischarge gradually increases. Correspondingly, due to I... POUTID =I POUT -Idischarge, and V POUTID =∑I POUTID ×R PID Therefore, V POUTID Gradually decrease until V POUTID <V PMAX -V TH Voltage V TH The hysteresis voltage of comparator CMP3 (should be understood, V) POUTID <V PMAX -V TH This is just an example; it could also be V. POUTID <V PMAX ).

[0087] When V POUTID <V PMAX -V TH When the comparator CMP3 output voltage changes from high to low, the falling edge of this voltage triggers the ADC of the fast charging protocol communication module 421 to check the voltage V. P_fb Sampling is performed. This voltage V P_fb This represents the reduced load power required by the fast charging protocol circuit 420, which can be expressed as Pm = f5(V P_fb The fast charging protocol communication module 421 accordingly reconfigures the load power to P. adj =P OUT -Pm.

[0088] Reference Figure 10 Minimum power protection function (power protection mentioned above): When the fast charging protocol communication module 421 detects that its current load power has been reduced to the minimum power threshold P MINTime (e.g., minimum power threshold P) MIN Generally set to 5W), the fast charging protocol communication module 421 can control the DIS terminal to output a signal with a level of 0, so that the comparator CMP3 stops working and outputs a low level, and then Idischarge = 0. At this time, the fast charging protocol circuit 420 controls the DC-to-DC switching regulator 430 to output the minimum power P. MIN Meanwhile, other fast charging protocol circuits continue to monotonically reduce their load power at the same rate of change until the sum of the load power of all fast charging protocol circuits is lower than the maximum output power of the fast charging control circuit.

[0089] In addition, refer to Figure 11 When comparator CMP4 detects voltage V POUTID Below the minimum power protection threshold (minimum power threshold) V PMIN_RELEASE -V TH2 When the comparator CMP4 output voltage changes from low to high, the rising edge of this voltage is input to the V signal of the fast charging protocol communication module 421. PMIN_RE The input is connected to the DIS terminal, causing it to change from low to high. This causes the CMP3's enable terminal EN to change from low to high, and the CMP3 resumes operation. At this point, the aforementioned minimum power protection function is deactivated.

[0090] It should be understood that the above figures only show example circuit diagrams of a circuit for USB fast charging according to the present invention, and any circuit capable of achieving the above functions can be used to implement the circuit for USB fast charging according to the present invention.

[0091] Figure 12 A schematic circuit diagram of a circuit for USB fast charging according to yet another exemplary embodiment of the present invention is shown.

[0092] Figure 12 Circuitry for USB fast charging and Figure 4 or Figure 7 The difference in the circuitry used for USB fast charging is that: Figure 12 The fast charging control circuit 410 does not have a VIN pin at its output terminal, but... Figure 12 The input pin VIN of the fast charging control circuit 410 is directly connected via a resistor to the pin VIN of each fast charging protocol circuit 420-1 to 420-N and each (DC to DC) switching regulator 430-1 to 430-N. Figure 12 In this case, N = 3, but it should be understood that N can be any integer. Furthermore, Figure 12 An AC-to-DC switching regulator 440 including a primary controller and a secondary synchronous rectifier IC is shown; however, it should be understood that the AC-to-DC switching regulator 440 may have the same... Figure 12 The diagram shows different arbitrary circuit configurations.

[0093] It should be understood that the above references Figures 4 to 12 The circuit shown for USB fast charging is merely an example; any other method can be used to implement the circuit for USB fast charging according to embodiments of the present invention. For example, to save costs and improve efficiency, simple devices such as TL431 and resistors can be used in the fast charging control circuit and the AC-to-DC switching regulator to generate the input voltage based on the various load voltages (e.g., the highest load voltage) detected by multiple fast charging protocol circuits. The following... Figure 13 and Figure 14 An example describing this implementation method is provided.

[0094] Figure 13 A schematic circuit diagram of a fast charging protocol circuit according to another exemplary embodiment of the present invention is shown. Figure 14 A schematic circuit diagram of a circuit for USB fast charging according to yet another exemplary embodiment of the present invention is shown.

[0095] Typically, when using a circuit containing a TL431 device to generate one voltage from another based on one voltage, a voltage inversely proportional to the first voltage is generated. Therefore, when the TL431 device is applied to a fast-charging control circuit and an AC-to-DC switching regulator, the fast-charging protocol circuit can output a voltage inversely proportional to the load voltage, enabling the fast-charging control circuit and the AC-to-DC switching regulator to generate a voltage inversely proportional to this inverse voltage, i.e., to generate an input voltage related to the highest of the various load voltages.

[0096] Reference Figure 13 and Figure 14 , Figure 13 The fast charging protocol circuit 420' in the middle and Figure 6 The difference in the fast charging protocol circuit 420 is: Figure 13 The fast charging protocol circuit 420' in the middle uses an inverse proportional module 426 to replace the Figure 6 The diode D1 in the fast charging protocol circuit 420.

[0097] Figure 6 In the fast charging protocol circuit 420, diode D1 is used to make the pin VIN of the fast charging control circuit 410 have the maximum voltage output from the pin VOUID of each fast charging protocol circuit.

[0098] Figure 13 The inverse module 426 in the circuit can be used to: output a voltage (V) that is (linearly or non-linearly) inversely proportional to the voltage of the connected load at the VOUID pin of the fast charging protocol circuit 420'. VOUTID =f2'(V REF2 )), and make Figure 14The fast charging control circuit 410' shown has the minimum voltage (i.e., V) output from the VIN pin of each fast charging protocol circuit (420'-1, 420'-2) at the pin VOUID pin. VID =MIN(V VOUTID At this point, the minimum voltage corresponds to the highest load voltage among the various load voltages of each fast charging protocol circuit 420'.

[0099] Figure 14 The fast charging control circuit 410' and AC-to-DC switching regulator 440' shown can generate the input voltage VIN using the minimum voltage (the voltage at VID), for example, as shown in the following equation (1):

[0100]

[0101] In equation (1), VIN represents the generated input voltage, V TL431 R11, R12, and R13 represent the voltage limit of the TL431 device, and R11, R12, and R13 represent the resistance values ​​of resistors R11, R12, and R13, respectively.

[0102] It can be seen from the above equation that, Figure 13 and Figure 14 The circuit shown for USB fast charging can also generate an input voltage based on the individual load voltages detected by multiple fast charging protocol circuits, for example, by generating an output voltage based on the maximum voltage among the various load voltages.

[0103] It should be understood that, although Figure 14 Only two fast charging protocol circuits, 420'-1 and 420'-2, are shown in the figure, but in practical applications, any number of fast charging protocol circuits can be used.

[0104] Furthermore, the inverse proportional module 426 in the fast charging protocol circuit 420' can be any module capable of implementing the above functions.

[0105] Furthermore, to further simplify control, the inverse proportional module 426 in the fast charging protocol circuit 420' can also generate a voltage V of 0V when the load voltage is greater than a predetermined value. OUTID In this case, the fast charging control circuit 410' and the AC-to-DC switching regulator 440' can use equation (1) to generate the corresponding input voltage VID, which is the maximum input voltage of the circuit used for USB fast charging.

[0106] For example, as an example, the above predetermined value could be 12V, the voltage V defined by the TL431 device. TL431The voltage can be 2.5V. The resistance value of resistor R11 can be R11=200KΩ, the resistance value of resistor R12 can be R12=51KΩ, and the resistance value of resistor R13 can be R13=51KΩ.

[0107] In one example, if the load voltage of fast charging protocol circuit 420'-1 is 15V and the load voltage of fast charging protocol circuit 420'-2 is 5V, then 15V > 12V, meaning the voltage at pin VOUTID of fast charging protocol circuit 420'-1 can be 0V, while 5V < 12V, meaning the voltage at pin VOUTID of fast charging protocol circuit 420'-2 can be a value greater than 0V (e.g., 2.5V). Because V VID =MIN(V VOUTID Therefore, the voltage at pin VID of the fast charging control circuit 410' is 0V. From the above equation (1), it can be concluded that the input voltage VIN generated at this time is 22.1V, which can meet the load requirements of each fast charging protocol circuit.

[0108] In another example, if the load voltage of both fast charging protocol circuits 420'-1 and 420'-2 is 5V, and the voltage at pin VOUTID of the corresponding fast charging protocol circuit 420'-1 is 2.5V (or other values), then the generated input voltage VIN is 12.3V, which can meet the load requirements of each fast charging protocol circuit.

[0109] It should be understood that the above-mentioned predetermined values, resistance values, load voltage values, and corresponding voltage values ​​at pin VOUTID are only examples, and these values ​​can be set to any other values ​​according to actual needs.

[0110] pass Figure 13 and Figure 14 The circuitry used for USB fast charging can reduce circuit costs. Furthermore, because the voltage at pin VID is relatively low, Figure 13 and Figure 14 The circuitry used for USB fast charging can reduce switching losses and improve the overall system efficiency.

[0111] It should be understood that the circuit for USB fast charging according to exemplary embodiments of the present invention is not limited to the implementation shown above, and can be implemented in any other way according to actual needs.

[0112] The circuit for USB fast charging according to an exemplary embodiment of the present invention can generate a charging voltage for charging each load according to the load voltage required by the loads connected to the multiple fast charging protocol circuits, thereby flexibly and accurately adapting to the charging needs of the loads without significantly increasing the circuit's footprint and cost.

[0113] This invention can be implemented in other specific forms without departing from its spirit and essential characteristics. For example, the algorithm described in a particular embodiment can be modified without departing from the basic spirit of the invention. Therefore, the present embodiments are to be regarded as exemplary rather than limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and all changes falling within the meaning and scope of the claims and their equivalents are thus included within the scope of the invention.

Claims

1. A circuit for USB fast charging, comprising: Fast charging control circuit and multiple fast charging protocol circuits connected to the fast charging control circuit. Each of the multiple fast charging protocol circuits is configured to be connected to its respective load and to detect the load voltage required by its respective load according to the USB protocol. The fast charging control circuit is configured to generate an input voltage based on the respective load voltages detected by the plurality of fast charging protocol circuits, wherein each of the fast charging protocol circuits uses the input voltage to charge its respective load. The multiple fast charging protocol circuits perform inverse transformation on their respective detected load voltages to obtain corresponding inverse voltages. The fast charging control circuit is configured to generate an input voltage based on the lowest inverse voltage among the various inverse voltages.

2. The circuit according to claim 1, wherein, Each of the fast charging protocol circuits detects its own load voltage during the power-on detection phase, wherein the power-on detection phase corresponds to the time period after the plurality of fast charging protocol circuits are connected to the fast charging control circuit and before the fast charging control circuit completes the generation of the input voltage.

3. The circuit according to claim 2, wherein, During the power-on detection phase, the fast charging control circuit is further configured to generate a reference power indicating the maximum output power of the fast charging control circuit, and each of the fast charging protocol circuits is further configured to detect and store the reference power.

4. The circuit according to claim 3, wherein, The first power pin of the fast charging control circuit is connected to the second power pin of each of the fast charging protocol circuits. During the power-on detection phase, the fast charging control circuit outputs the reference power through the first power pin, and each of the fast charging protocol circuits detects the reference power through its respective second power pin.

5. The circuit according to claim 4, wherein, During the power-on detection phase and the subsequent power adjustment phase, each of the fast charging protocol circuits is further configured to detect the actual load power of its respective load according to the USB protocol. During the power adjustment phase, each of the fast charging protocol circuits is further configured as follows: The detected actual load power is input to the respective second power pin; The total actual load power of the plurality of fast charging protocol circuits is detected by their respective second power pins. When the total actual load power is greater than the reference power, the actual load power of each individual load is reduced so that the total actual load power of the plurality of fast charging protocol circuits is less than the reference power.

6. The circuit according to claim 5, wherein, For any one of the plurality of fast charging protocol circuits, when the actual load power of any fast charging protocol circuit is reduced to the minimum power threshold of the corresponding load, the fast charging protocol circuit charges the corresponding load at the minimum power threshold to protect the power of the corresponding load. Among them, the other fast charging protocol circuits that have not performed power protection continue to reduce the actual load power of their respective loads so that the total actual load power of the multiple fast charging protocol circuits is less than the reference power.

7. The circuit according to claim 5 or 6, wherein, Each of the fast charging protocol circuits that is reducing the actual load power reduces the actual load power of its respective load at the same rate.

8. The circuit according to claim 5, wherein during the power adjustment phase, each of the fast charging protocol circuits is further configured as follows: After reducing the actual load power of each load, when the total actual load power is detected to be less than the minimum power protection threshold, the actual load power of each load is increased so that the total actual load power is greater than the minimum power protection threshold and less than the reference power.

9. The circuit according to claim 8, wherein, Each of the aforementioned fast charging protocol circuits increases the actual load power of its respective load at the same rate.

10. The circuit according to claim 5, wherein, The circuit also includes multiple DC-to-DC switching regulators, wherein each of the multiple DC-to-DC switching regulators corresponds one-to-one with the multiple fast charging protocol circuits. Each of the fast charging protocol circuits is further configured to: during the power-on detection phase, detect the load current required by its respective load. Each DC-to-DC switching regulator is configured to generate an output voltage based on the load current and load voltage detected by the corresponding fast charging protocol circuit, so that the corresponding fast charging protocol circuit uses the output voltage to charge the connected load.

11. The circuit according to claim 1, wherein, The circuit also includes an AC-to-DC switching regulator, wherein the fast charging control circuit is configured to use the AC-to-DC switching regulator to generate the input voltage based on the highest load voltage among the various load voltages detected by the plurality of fast charging protocol circuits.

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