A three-level anpc topology wave-by-wave current limiting method based on FPGA

Abstract

The application discloses a three-level ANPC topology wave-by-wave current limiting method based on FPGA, and through hierarchical setting of a first overcurrent value interval, a second overcurrent value interval and a third overcurrent value interval of wave-by-wave current limiting from small to large, hierarchical overcurrent judgment is completed; in combination with the different principles of zero level or equivalent P level and N level on the degree of current limiting effect, wave-by-wave current limiting of different overcurrent levels is realized; when the overcurrent signal is small, 0+ or 0- level is used for wave-by-wave current limiting processing; when the overcurrent signal is large, equivalent P level or N level is used for wave-by-wave current limiting processing; when the upper limit of overcurrent is reached, PWM envelope protection processing is carried out. The application not only can effectively realize the wave-by-wave current limiting function of hierarchical current limiting control according to specific conditions through zero level or equivalent P level or N level, but also can realize the wave-by-wave current limiting recovery timing of PWM output, so that the whole wave-by-wave current limiting process is a short commutation path scheme.

Description

Technical Field

[0001] This application relates to the field of power electronics technology, and in particular to a wave-by-wave current limiting method based on a three-level ANPC topology using FPGA. Background Technology

[0002] In power electronic control technologies such as rectification and inversion, overcurrent situations often occur due to short-term loading. The application of current-by-wave (CBC) technology effectively suppresses short-term overcurrent in the system, improves the robustness of the system, and allows the system to continue operating without shutting down under the premise that the short-term overcurrent is controllable. The purpose of current limiting is achieved by controlling the corresponding PWM pulse for a short time, and then the normal PWM is output after the overcurrent recovers to ensure the stable operation of the system.

[0003] Currently, mainstream wave-by-wave current limiting methods mainly fall into two categories: hardware implementation and software implementation. For example, Chinese Patent 201910906127.2 proposes a hardware-based wave-by-wave current limiting scheme. Another example is the DSP-based scheme implemented in Chinese Patent 201810195593.X, which operates in each switching cycle. Upon detecting an overcurrent signal, it triggers a TRIP event and sends it to the TZ module of the PWM module. The TZ module immediately blocks the PWM waveform to achieve wave-by-wave current limiting. Once the TRIP event is cleared and the PWM carrier counter is reset to zero, the TZ module reopens, enabling PWM waveform output. Yet another example is the wave-by-wave current limiting scheme for a three-level ANPC topology mentioned in Chinese Patent 202210207793.9. When the current and modulation wave are in the same direction, a zero-level freewheeling path is used to achieve CBC wave-by-wave current limiting. When the current and modulation wave are in opposite directions, an equivalent P or N-level freewheeling path is used to achieve CBC wave-by-wave current limiting.

[0004] All of the above-mentioned existing technologies have certain drawbacks. The wave-by-wave current limiting method in Chinese patent 201810195593.X is mainly aimed at two-level topologies. In three-level control, it is not permissible to directly block the PWM pulse. Moreover, after each wave-by-wave current limiting blocking, it is necessary to wait until the carrier counter returns to zero before the PWM output can be enabled again. This can lead to excessive current limiting, thereby increasing the current harmonics introduced by wave-by-wave current limiting. Although patent 202210207793.9 considers wave-by-wave current limiting schemes for both rectification and inversion scenarios, this scheme only considers zero-level current limiting control when the voltage modulation wave and current are in the same direction. When the current exceeds the limit significantly, zero-level current limiting will occupy a lot of current limiting time. Furthermore, the existing technical solutions do not mention the PWM wave recovery sequence after overcurrent recovery. In three-level control of ANPC topologies, the switching sequence of internal and external transistors and clamping transistors especially needs to be considered. Summary of the Invention

[0005] This invention primarily addresses the issues of hardware interference, short-term recurring overcurrent, and PWM recovery timing problems in existing three-level topologies. It proposes a wave-by-wave current limiting method for three-level ANPC topologies based on FPGA. This method employs a graded overcurrent judgment approach, utilizing the different degrees of current limiting effect of zero-level or equivalent P-level and N-level signals to achieve different wave-by-wave current limiting processes. Furthermore, after implementing the wave-by-wave current limiting function, specific wave-blocking protection and transistor recovery timing designs are implemented for the wave-by-wave current limiting exit scenario, thus effectively realizing the exit mechanism for the wave-by-wave current limiting function.

[0006] This invention specifically solves the above-mentioned technical problems through the following technical solution: a wave-by-wave current limiting method for a three-level ANPC topology based on FPGA, comprising the following steps: S1: Set the first, second, and third overcurrent value ranges for wave-by-wave current limiting according to the overcurrent value from small to large. S2: The FPGA generates wave-by-wave current limiting instructions based on the current signals in the three-level ANPC topology; S3: If the current signal enters the first overcurrent value range, the FPGA generates the first-level wave-by-wave current limiting instruction and performs wave-by-wave current limiting processing through 0+ or ​​0- level; S4: If the current signal enters the second overcurrent value range, the FPGA generates a second-level wave-by-wave current limiting instruction. After ensuring that the outer tube is effectively blocked, the inner tube and clamping tube of the phase are blocked, and wave-by-wave current limiting is performed through equivalent P level or N level. S5: If the current signal enters the third overcurrent value range, the FPGA generates a third-level wave-by-wave current limiting instruction to perform PWM wave blocking protection.

[0007] This invention achieves graded overcurrent judgment by setting the first, second, and third overcurrent value ranges for wave-by-wave current limiting from small to large. Combining the principle that zero level or equivalent P level and N level have different effects on the degree of current limiting, it realizes wave-by-wave current limiting of different overcurrent levels. When the overcurrent signal is small, wave-by-wave current limiting is performed using 0+ or ​​0- level. When the overcurrent signal is large, after ensuring that the outer tube is effectively blocked, the inner tube and clamping tube of the phase are blocked, and wave-by-wave current limiting is performed using equivalent P level or N level. When the overcurrent limit is reached, PWM wave blocking protection is performed. Based on the above scheme, the three-level ANPC topology system can not only effectively realize the wave-by-wave current limiting function of graded current limiting control by zero level or equivalent P level or N level according to specific situations, but also realize the wave-by-wave current limiting recovery timing of PWM output, so that the entire wave-by-wave current limiting process is a short commutation path scheme.

[0008] Preferably, step S1 specifically includes: setting a first overcurrent value I1 and a first hysteresis value di1, setting a second overcurrent value I2 and a second hysteresis value di2, and setting a third overcurrent value I3; the first overcurrent value range of the current signal I is I1 + di1 ≤ I < I2 + di2; the second overcurrent value range of the current signal I is I2 + di2 ≤ I < I3; and the third overcurrent value range of the current signal I is I ≥ I3. Different levels of overcurrent ranges are defined by different overcurrent values ​​and hysteresis values ​​in order to adopt corresponding wave-by-wave current limiting strategies.

[0009] Preferably, if the current signal I ≤ I1 - di1, the FPGA clears the wave-by-wave current limiting command, and the switching state of the wave-by-wave current limiting of the three-level ANPC topology switches to the enabled PWM normal waveform state at the zero-crossing point of the next carrier wave. When the current signal leaves the overcurrent range, the FPGA clears the wave-by-wave current limiting command in a timely manner to prevent excessive current limiting.

[0010] Preferably, when performing wave-by-wave current limiting at the P level of a three-level ANPC topology, if the current is negative, current limiting is achieved through the P level itself and the transient state between the P level and the 0+ level, without additional operation. If the current is positive, proceed to step S2, and wave-by-wave current limiting is achieved through the N level when the current signal enters the second overcurrent value range. When performing wave-by-wave current limiting at the P level, if the current is negative, the P level itself and the transient state between the P level and the 0+ level have the strongest limiting effect on the negative current, without additional operation.

[0011] Preferably, when performing wave-by-wave current limiting at the N-level of a three-level ANPC topology, if the current is positive, current limiting is achieved through the N-level and the transient state between the N-level and 0-level, requiring no additional operation. If the current is negative, proceed to step S2, and if the current signal enters the second overcurrent value range, wave-by-wave current limiting is achieved through the P-level. When performing wave-by-wave current limiting at the N-level, if the current is negative, the N-level itself and the transient state between the N-level and 0-level have the strongest limiting effect on the negative current, requiring no additional operation.

[0012] Preferably, when performing wave-by-wave current limiting under 0+, 0-, or 0+0- transient levels, if the current signal enters the second overcurrent value range, after ensuring effective blocking of the outer tube, the inner tube is turned off first, and then the clamping tube is turned off after a delay. When performing wave-by-wave current limiting under 0+, 0-, or 0+0- transient levels, the zero level itself has a limiting effect on the current, so when in the first overcurrent value range, no additional action is required; it is sufficient to maintain the zero-level current limiting.

[0013] Preferably, the present invention further includes: setting a maximum time limit tmax for wave-by-wave current limiting; if the wave-by-wave current limiting processing time exceeds tmax, the FPGA generates a third-level wave-by-wave current limiting instruction to perform PWM waveform blocking protection processing. By setting the maximum time limit tmax for wave-by-wave current limiting, circuit safety is ensured.

[0014] Preferably, the present invention further includes: setting a maximum execution time t1 for the first-level wave-by-wave current limiting instruction; if the execution time of the first-level wave-by-wave current limiting instruction exceeds t1, the FPGA generates a second-level wave-by-wave current limiting instruction, and after ensuring effective blocking of the external transistor, blocks the internal transistor and clamping transistor of the corresponding phase, performing wave-by-wave current limiting processing through equivalent P-level or N-level. Setting a maximum execution time t1 for the first-level wave-by-wave current limiting instruction allows for timely adoption of methods with better current limiting effects when the current limiting effect is inadequate.

[0015] Preferably, step S4 further includes: setting a maximum execution time t2 for the second-level wave-by-wave current limiting instruction; if the execution time of the second-level wave-by-wave current limiting instruction exceeds t2, the FPGA generates a third-level wave-by-wave current limiting instruction to perform PWM blocking protection processing. By setting a maximum execution time t2 for the second-level wave-by-wave current limiting instruction, PWM blocking is used to complete circuit protection processing when the current limiting effect cannot be achieved.

[0016] The present invention has the following beneficial effects: the three-level ANPC topology system can effectively realize the wave-by-wave current limiting function of hierarchical current limiting control by zero level or equivalent P level or N level according to specific circumstances, realize the wave-by-wave current limiting recovery timing of PWM output, and make the entire wave-by-wave current limiting process a short commutation path scheme. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the current value range in an embodiment of the present invention.

[0018] Figure 2 This is a waveform diagram of the wave-by-wave current limiting enable flag and the PWM enable flag in an embodiment of the present invention.

[0019] Figure 3 This is a schematic diagram of the switching waveforms before and after wave-by-wave current limiting in the first overcurrent interval under P-level in an embodiment of the present invention.

[0020] Figure 4 This is a schematic diagram of the switching waveforms before and after wave-by-wave current limiting in the second overcurrent interval under P level in an embodiment of the present invention.

[0021] Figure 5 This is a schematic diagram of the switching waveforms before and after wave-by-wave current limiting in the first overcurrent interval under N-level in an embodiment of the present invention.

[0022] Figure 6This is a schematic diagram of the switching waveforms before and after wave-by-wave current limiting in the second overcurrent interval under N-level in an embodiment of the present invention.

[0023] Figure 7 This is a schematic diagram of the switching waveforms before and after wave-by-wave current limiting in the first overcurrent interval under the 0+ level in an embodiment of the present invention.

[0024] Figure 8 This is a schematic diagram of the switching waveforms before and after wave-by-wave current limiting in the second overcurrent interval under the 0+ level in an embodiment of the present invention.

[0025] Figure 9 This is a schematic diagram of the switching waveforms before and after wave-by-wave current limiting in the first overcurrent interval under the 0-level condition in an embodiment of the present invention.

[0026] Figure 10 This is a schematic diagram of the switching waveforms before and after wave-by-wave current limiting in the second overcurrent interval under the 0-level condition in an embodiment of the present invention.

[0027] Figure 11 The schematic diagram of the ANPC three-level inverter topology circuit in this embodiment of the invention is shown. Detailed Implementation

[0028] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0029] Example 1: This embodiment of a wave-by-wave current limiting method for a three-level ANPC topology based on FPGA includes the following steps: S1: The first, second, and third overcurrent value intervals are set according to the overcurrent value from smallest to largest. Specifically, this includes setting a first overcurrent value I1 and a first hysteresis value di1, setting a second overcurrent value I2 and a second hysteresis value di2, and setting a third overcurrent value I3, where 0 < I1 < I2 < I3. The first overcurrent value interval for current signal I is I1 + di1 ≤ I < I2 + di2; the second overcurrent value interval for current signal I is I2 + di2 ≤ I < I3; and the third overcurrent value interval for current signal I is I ≥ I3. Different levels of overcurrent intervals are defined by different overcurrent values ​​and hysteresis values ​​to allow for the implementation of corresponding wave-by-wave current limiting strategies. Figure 1As shown, in this embodiment, I0=0A represents the reference point where the current is zero, and I1 or -I1 is the overcurrent value for the first time to enter the wave-by-wave current limiting function. When the current is greater than I1+dI1 or less than -I1-dI1, the wave-by-wave current limiting function is entered, and the wave-by-wave current limiting command is valid at this time. When the current is less than I1-dI1 or greater than -I1+dI1, the wave-by-wave current limiting function is exited, and the wave-by-wave current limiting command is cleared to zero at this time.

[0030] S2: As Figure 2 As shown, the FPGA generates wave-by-wave current limiting instructions based on the current signal in the three-level ANPC topology. If the current signal I ≤ I1 - di1, the FPGA clears the wave-by-wave current limiting instructions. When the current is greater than I1 + di1, the overcurrent signal is captured, and the wave-by-wave current limiting instruction CBCEn is immediately set. At the next carrier zero-crossing point, as... Figure 2 At time t2, the current limiting signal is switched from the current limiting state to the PWM normal waveform enabling state; when the current is greater than I2+di2, the overcurrent signal is captured and the current limiting is enabled at the equivalent P level or equivalent N level; when the current is greater than I3 or when the current limiting reaches the maximum time, it is considered to have timed out, and the protection logic is entered. All PWM waveforms are blocked according to the timing requirements, and the current limiting instruction is cleared, i.e., subsequent steps S3-S5.

[0031] S3: If the current signal enters the first overcurrent value range, the FPGA generates the first-level wave-by-wave current limiting instruction and performs wave-by-wave current limiting processing through 0+ or ​​0- level; S4: If the current signal enters the second overcurrent value range, the FPGA generates a second-level wave-by-wave current limiting instruction. After ensuring that the outer tube is effectively blocked, the inner tube and clamping tube of the phase are blocked, and wave-by-wave current limiting is performed through equivalent P level or equivalent N level. S5: If the current signal enters the third overcurrent value range, the FPGA generates a third-level wave-by-wave current limiting instruction to perform PWM wave blocking protection.

[0032] More specifically, this embodiment employs an existing ANPC three-level inverter topology circuit, such as... Figure 11 As shown, the circuit includes six switching transistors Q1-Q6 and their respective anti-parallel diodes D1-D6. During wave-by-wave current limiting under P-level, when the current is negative, the P-level itself and the transient state between P and 0+ levels have the strongest limiting effect on the negative current, requiring no additional operation. When the current is positive, it is controlled in stages according to the degree of overcurrent: when the wave-by-wave current limiting command is triggered when the current reaches the first overcurrent value interval, the corresponding external transistor Q1 is turned off, and wave-by-wave current limiting is performed through a zero level. When the wave-by-wave current limiting command is triggered when the current reaches the overcurrent point of the second overcurrent value interval, the external transistor Q1 is turned off, the internal transistor Q2 is turned off after a delay, and the clamping transistor Q6 is turned off after another delay. At this time, the equivalent N level limits the positive current overcurrent. Figure 3As shown, the zero-level current limiting and its overcurrent recovery timing diagram correspond to the first overcurrent interval when the positive modulation wave P level is displayed. When wave-by-wave current limiting recovers, the modulation wave value is latched at the start point of the next carrier wave, and the system switches from the switching state of wave-by-wave current limiting to the normal transmission mode. Figure 4 The diagram shows the timing of the N-level current limiting and its recovery for the second overcurrent value interval when the modulated wave is at level P. Wave-by-wave current limiting occurs at time t0. At this time, the corresponding external transistor Q1 is turned off first, and the internal transistor is turned off after a delay to time t1. Then, the clamping transistor is turned off after another delay to time t2. Wave-by-wave current limiting recovers at time t3. The carrier synchronization point is at time t4, that is, the clamping transistors Q5 and Q6 are turned on at time t4. The internal transistor Q2 is turned on after a delay to time t5, thus entering the normal transmission mode. That is, at time t6, the clamping transistor Q5 is turned off according to the comparison value between the modulated wave and the carrier, and then the external transistor Q1 is turned on.

[0033] When current is limited wave-by-wave under N-level, if the current is positive, the N-level itself and the transient state between N-level and 0-level have the strongest limiting effect on the negative current, requiring no additional operation. If the current is negative, it is controlled in stages according to the degree of overcurrent. When the wave-by-wave current limiting command is triggered when the current reaches the first overcurrent value range, the external transistor Q4 is turned off, and wave-by-wave current limiting is performed through zero level. When the wave-by-wave current limiting command is triggered when the current reaches the second overcurrent value range, the external transistor Q4 is turned off, the internal transistor Q3 is turned off after a delay, and the clamping transistor Q5 is turned off after another delay. At this time, the equivalent P-level limits the overcurrent of the negative current. Figure 5 The diagram shows the zero-level current limiting and its overcurrent recovery timing for the first overcurrent value interval when the negative modulation wave is at level N. When the wave-by-wave current limiting recovers, the modulation wave value is latched at the start point of the next carrier wave, and the system switches from the switching state of wave-by-wave current limiting to the normal transmission mode. Figure 6 The diagram shows the equivalent P-level current limiting and its recovery timing for the second overcurrent value range when the N-level of the negative modulation wave is present. Wave-by-wave current limiting occurs at time t0. At this time, the corresponding external transistor Q4 is turned off first, and the internal transistor is turned off after a delay to time t1. Then, the clamping transistor is turned off after another delay to time t2. Wave-by-wave current limiting recovers at time t3. The carrier synchronization point is at time t4, that is, the clamping transistors Q5 and Q6 are turned on at time t4. The internal transistor Q3 is turned on after a delay to time t5, thus entering the normal transmission mode. That is, at time t6, the clamping transistor Q6 is turned off according to the comparison value between the modulation wave and the carrier wave, and then the external transistor Q4 is turned on.

[0034] like Figure 7 The diagram shows the zero-level current limiting and its recovery timing for the first overcurrent value interval when the positive modulation wave is at 0+ level. When the wave-by-wave current limiting recovers, the modulation wave value is latched at the start point of the next carrier wave, and the system switches from the switching state of wave-by-wave current limiting to the normal transmission mode. Figure 8The diagram shows the timing of current limiting and overcurrent recovery for the second overcurrent value interval when the modulated wave is at level 0+. Wave-by-wave current limiting occurs at time t0, at which time the corresponding inner tube Q2 is turned off first, and then the clamping tubes Q5 and Q6 are turned off at time t1. Wave-by-wave current limiting recovers at time t2, and the carrier synchronization point is at time t3. That is, the clamping tubes Q5 and Q6 are turned on at time t3, and the inner tube Q2 is turned on at time t4, thus entering the normal transmission mode. That is, at time t5, the clamping tube Q5 is turned off according to the comparison value between the modulated wave and the carrier, and then the corresponding outer tube Q1 is turned on.

[0035] like Figure 9 The diagram shows the zero-level current limiting and its overcurrent recovery timing for the first overcurrent value interval when the negative modulation wave is at 0-level. When wave-by-wave current limiting recovers, the modulation wave value is latched at the start point of the next carrier wave, and the system switches from the switching state of wave-by-wave current limiting to the normal transmission mode. Figure 10 The diagram shows the timing of current limiting and overcurrent recovery for the second overcurrent value range when the negative modulation wave is at level 0-. Wave-by-wave current limiting occurs at time t0, at which time the corresponding inner tube Q3 is turned off first, and then the clamping tubes Q5 and Q6 are turned off at time t1. Wave-by-wave current limiting recovers at time t2, and the carrier synchronization point is at time t3. That is, the clamping tubes Q5 and Q6 are turned on at time t3, and the inner tube Q3 is turned on at time t4, thus entering the normal transmission mode. That is, at time t5, the clamping tube Q6 is turned off according to the comparison value between the modulation wave and the carrier, and then the corresponding outer tube Q4 is turned on.

[0036] During wave-by-wave current limiting in the 0+0- level transient state, the zero level itself limits the current. Therefore, when entering the first overcurrent range, no additional action is needed; simply maintaining the zero-level current limiting is sufficient. When entering the second overcurrent range, the internal transistor is turned off first, followed by a delay before the clamping transistor is turned off. When the wave-by-wave current limiting command caused by the first overcurrent range is cleared, the corresponding internal transistor is first turned off at carrier synchronization time based on the positive or negative of the modulation wave. Then, the actual wave transmission logic is used for transmission processing. If it is a positive modulation wave, the corresponding internal transistor is turned off first. For delay control of the switches, see [link to relevant documentation]. Figure 7 The switching timing recovery logic, if it is a negative modulation wave, first turns off the corresponding internal transistor. For switch delay control, see [link to relevant documentation]. Figure 9 Switching timing recovery logic. When the wave-by-wave current limiting command is cleared due to the second overcurrent value interval, the corresponding clamping transistor is first turned on at the carrier synchronization time according to the positive or negative of the modulation wave. Then, the corresponding inner transistor is turned on after a delay. Finally, the corresponding outer transistor is turned on according to the transmission logic and timing. The specific timing can be found by referring to the corresponding timing for the positive or negative of the modulation wave. Figure 8 or Figure 10 Switching timing recovery logic.

[0037] Meanwhile, this embodiment also sets a maximum time limit tmax for wave-by-wave current limiting. If the wave-by-wave current limiting processing time exceeds tmax, the FPGA generates a third-level wave-by-wave current limiting instruction to perform PWM wave blocking protection processing.

[0038] Example 2: The difference between this embodiment and Embodiment 1 lies in the following steps: setting a maximum execution time t1 for the first-level wave-by-wave current limiting instruction; if the execution time of the first-level wave-by-wave current limiting instruction exceeds t1, the FPGA generates a second-level wave-by-wave current limiting instruction to block the internal transistors and clamping transistors of the corresponding phase, performing wave-by-wave current limiting processing through equivalent P-level or N-level; setting a maximum execution time t2 for the second-level wave-by-wave current limiting instruction; if the execution time of the second-level wave-by-wave current limiting instruction exceeds t2, the FPGA generates a third-level wave-by-wave current limiting instruction to perform PWM blocking protection processing. By setting a maximum execution time t1 for the first-level wave-by-wave current limiting instruction, a better current limiting method is adopted in a timely manner when the current limiting effect is poor. Furthermore, when the first-level wave-by-wave current limiting instruction fails to achieve the current limiting effect, PWM blocking is used to complete the circuit protection processing.

[0039] The embodiments described above are merely preferred embodiments of the present invention and are not intended to limit the present invention in any way. Other variations and modifications are possible without departing from the technical solutions described in the claims.

Claims

1. A wave-by-wave current limiting method for a three-level ANPC topology based on FPGA, characterized in that, Includes the following steps: S1: Set the first, second, and third overcurrent value ranges for wave-by-wave current limiting according to the overcurrent value from small to large. S2: The FPGA generates wave-by-wave current limiting instructions based on the current signals in the three-level ANPC topology; S3: If the current signal enters the first overcurrent value range, the FPGA generates the first-level wave-by-wave current limiting instruction and performs wave-by-wave current limiting processing through 0+ or ​​0- level; S4: If the current signal enters the second overcurrent value range, the FPGA generates a second-level wave-by-wave current limiting instruction. After effectively blocking the outer tube, it blocks the inner tube and clamping tube of the phase. Wave-by-wave current limiting is performed through equivalent P level or equivalent N level. S5: If the current signal enters the third overcurrent value range, the FPGA generates a third-level wave-by-wave current limiting instruction to perform PWM wave blocking protection.

2. The wave-by-wave current limiting method for a three-level ANPC topology based on FPGA according to claim 1, characterized in that, Step S1 specifically includes: setting a first overcurrent value I1 and a first hysteresis value di1, setting a second overcurrent value I2 and a second hysteresis value di2, and setting a third overcurrent value I3; the first overcurrent value range of the current signal I is I1 + di1 ≤ |I| < I2 + di2; the second overcurrent value range of the current signal I is I2 + di2 ≤ |I| < I3; and the third overcurrent value range of the current signal I is |I| ≥ I3.

3. The wave-by-wave current limiting method for a three-level ANPC topology based on FPGA according to claim 2, characterized in that, Also includes: If the current signal |I|≤I1-di1, the FPGA clears the wave-by-wave current limiting instruction, and the switching state of the wave-by-wave current limiting of the three-level ANPC topology switches to the enabled PWM normal wave generation state at the time of the next carrier zero crossing.

4. A wave-by-wave current limiting method for a three-level ANPC topology based on FPGA according to claim 1, 2, or 3, characterized in that, When performing wave-by-wave current limiting under the P level of a three-level ANPC topology, if the current is negative, the current limiting is performed through the P level itself and the transient state between the P level and the 0+ level, without any additional operation; if the current is positive, then proceed to step S2, and when the current signal enters the second overcurrent value range, wave-by-wave current limiting is performed through the equivalent N level.

5. A wave-by-wave current limiting method for a three-level ANPC topology based on FPGA according to claim 1, 2, or 3, characterized in that, When performing wave-by-wave current limiting under the N-level of a three-level ANPC topology, if the current is positive, the current limiting is performed through the N-level and the transient state between the N-level and the 0-level, without any additional operation; if the current is negative, proceed to step S2, and when the current signal enters the second overcurrent value range, wave-by-wave current limiting is performed through the equivalent P-level.

6. A wave-by-wave current limiting method for a three-level ANPC topology based on FPGA according to claim 1, 2, or 3, characterized in that, When performing wave-by-wave current limiting under transient conditions of 0+ or ​​0- or 0+0-, if the current signal enters the second overcurrent value range, the inner tube is turned off after the outer tube is effectively blocked, and then the clamping tube is turned off after a delay.

7. A wave-by-wave current limiting method for a three-level ANPC topology based on FPGA according to claim 1, 2, or 3, characterized in that, Also includes: Set the maximum time limit tmax for wave-by-wave current limiting. If the wave-by-wave current limiting processing time exceeds tmax, the FPGA generates a third-level wave-by-wave current limiting instruction to perform PWM wave blocking protection processing.

8. The wave-by-wave current limiting method for a three-level ANPC topology based on FPGA according to claim 1, characterized in that, Also includes: Set the maximum execution time t1 for the first-level wave-by-wave current limiting instruction; if the execution time of the first-level wave-by-wave current limiting instruction exceeds t1, the FPGA generates a second-level wave-by-wave current limiting instruction, which blocks the inner tube and clamping tube of the phase after effectively blocking the outer tube, and performs wave-by-wave current limiting processing through equivalent P level or equivalent N level.

9. A wave-by-wave current limiting method for a three-level ANPC topology based on FPGA as described in claim 1 or 8, characterized in that, Step S4 also includes: setting the maximum execution time t2 for the second-level wave-by-wave current limiting instruction; if the execution time of the second-level wave-by-wave current limiting instruction exceeds t2, the FPGA generates a third-level wave-by-wave current limiting instruction to perform PWM wave blocking protection processing.

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