Charge pump start-up circuit and drive circuit

Abstract

A charge pump starting circuit and driving circuit, the charge pump starting circuit comprises a comparator unit and a first switch unit, wherein: the comparator unit, the first input end inputs the positive pressure of the charge pump output, the second input end inputs the power supply voltage, the output end is coupled with the control end of the first switch unit, and the power supply end inputs the positive pressure of the charge pump output; the first switch unit, the first end inputs the positive pressure of the charge pump output, and the second end inputs the power supply voltage. By adopting the above scheme, the rapid establishment of the charge pump can be realized.

Description

Technical Field

[0001] This invention relates to the field of circuit technology, and in particular to a charge pump start-up circuit and drive circuit. Background Technology

[0002] A charge pump is a type of capacitive DC-DC converter that uses only capacitors to transfer and store energy. Due to its advantages such as small footprint, high efficiency, high reliability, low noise, and no electromagnetic interference, it is widely used in communication systems. For example, it can be used for programming and erasing non-volatile memory, driving LCD backlights, driving RF switches, and driving various portable electronic products.

[0003] The build-up time of a charge pump directly affects the drive speed. In the prior art, the build-up speed of charge pumps is relatively slow. Summary of the Invention

[0004] The embodiments of the present invention address the technical problem of slow charge pump build-up time.

[0005] To solve the above-mentioned technical problems, this invention provides a charge pump start-up circuit, characterized in that it includes: a comparator unit and a first switching unit, wherein: the comparator unit has a first input terminal receiving the positive voltage output by the charge pump, a second input terminal receiving a power supply voltage, an output terminal coupled to the control terminal of the first switching unit, and a power supply terminal receiving the positive voltage output by the charge pump; the first switching unit has a first terminal receiving the positive voltage output by the charge pump, and a second terminal receiving the power supply voltage.

[0006] Optionally, the charge pump start-up circuit further includes an impedance unit disposed between the output terminal of the comparator unit and the control terminal of the first switching unit.

[0007] Optionally, the first switching unit includes: a first PMOS transistor; wherein: the gate of the first PMOS transistor is coupled to the output terminal of the comparator unit, the source is input to the positive voltage output by the charge pump, and the drain is input to the power supply voltage.

[0008] Optionally, the comparator unit includes: a first-stage output module, a differential pair module, a tail current source module, and a mirror module, wherein: the first-stage output module has its input terminal coupled to the first input terminal of the comparator unit and its output terminal coupled to the output terminal of the comparator unit; the differential pair module has its first terminal coupled to the second input terminal of the comparator unit and its second terminal coupled to the power supply terminal of the comparator unit; the tail current source module is coupled between the differential pair module and ground, and its control terminal is coupled to the bias current terminal of the comparator unit; the mirror module has one end coupled to the bias current terminal of the comparator unit and the other end coupled to the tail current source module.

[0009] Optionally, the first-stage output unit includes a second PMOS transistor and a third PMOS transistor; the differential pair module includes a first NMOS transistor and a second NMOS transistor; the mirror module includes a third NMOS transistor; and the tail current source module includes a fourth NMOS transistor; wherein: the source of the second PMOS transistor is coupled to the first input terminal of the comparator unit, the gate is coupled to the gate of the third PMOS transistor and the drain of the first NMOS transistor, and the drain is coupled to the drain of the first NMOS transistor; the source of the third PMOS transistor is coupled to the source of the second PMOS transistor, and the drain is coupled to the comparator... The output terminal of the unit is coupled; the gate of the first NMOS transistor is coupled to the second input terminal of the comparator unit, and the source is coupled to the drain of the fourth NMOS transistor; the drain of the second NMOS transistor is coupled to the output terminal of the comparator unit, the gate is coupled to the power supply terminal of the comparator unit, and the source is coupled to the source of the first NMOS transistor; the drain of the third NMOS transistor is coupled to the bias current terminal of the comparator unit, the gate is coupled to the gate of the fourth NMOS transistor, and the source is coupled to the source of the fourth NMOS transistor; the source of the fourth NMOS transistor is coupled to the ground terminal of the comparator unit.

[0010] Optionally, the comparator unit further includes: a second-stage output module; the second-stage output module has its input terminal coupled to the first-stage output module and its output terminal coupled to the output terminal of the comparator unit.

[0011] Optionally, the second-stage output module includes a sixth PMOS transistor and a fifth NMOS transistor; the first-stage output module further includes a fourth PMOS transistor and a fifth PMOS transistor; wherein: the source of the fourth PMOS transistor is coupled to the drain of the second PMOS transistor, the gate is coupled to the gate of the third PMOS transistor and the gate of the fifth PMOS transistor, and the drain is coupled to the drain of the first NMOS transistor; the source of the fifth PMOS transistor is coupled to the drain of the third PMOS transistor, the gate is coupled to the drain of the fourth PMOS transistor, and the drain is coupled to the drain of the second NMOS transistor; the source of the sixth PMOS transistor receives the positive voltage output by the charge pump, the gate is coupled to the drain of the fifth PMOS transistor, the drain is coupled to the drain of the fifth NMOS transistor, and the output terminal of the comparator unit is coupled; the gate of the fifth NMOS transistor is coupled to the gate of the fourth NMOS transistor, and the source is grounded.

[0012] Optionally, the comparator unit further includes: an inverter unit, a second switching unit, and a first pull-down unit, wherein: the input terminal of the inverter unit is coupled to the output terminal of the comparator unit, and the output terminal is coupled to the control terminal of the second switching unit; the second switching unit has a first terminal coupled to the first pull-down unit and a second terminal grounded; the first pull-down unit has a control terminal coupled to the bias current terminal of the comparator unit, a first terminal coupled to the output terminal of the comparator unit, and a second terminal coupled to the first terminal of the second switching unit.

[0013] Optionally, the first pull-down unit includes a sixth NMOS transistor, the second switching unit includes a seventh NMOS transistor, and the inverter unit includes an eighth NMOS transistor and a seventh PMOS transistor, wherein: the drain of the sixth NMOS transistor is coupled to the output terminal of the comparator unit, the gate is coupled to the bias current terminal of the comparator unit, and the source is coupled to the gate of the seventh NMOS transistor; the drain of the seventh NMOS transistor is coupled to the source of the sixth NMOS transistor, and the source is grounded; the source of the seventh PMOS transistor receives the positive voltage output by the charge pump, the gate is coupled to the output terminal of the comparator unit, and the drain is coupled to the drain of the eighth NMOS transistor; the gate of the eighth NMOS transistor is coupled to the gate of the seventh PMOS transistor, and the source is grounded.

[0014] Optionally, the comparator unit further includes: a first pull-up unit; wherein: the first pull-up unit has a first terminal coupled to the second input terminal of the comparator unit, a second terminal coupled to the control terminal of the tail current source module, and the control terminal coupled to the power supply terminal of the comparator unit.

[0015] Optionally, the first pull-up unit includes an eighth PMOS transistor, wherein: the source of the eighth PMOS transistor is coupled to the second input terminal of the comparator unit, the gate is coupled to the power supply terminal of the comparator unit, and the drain is coupled to the control terminal of the tail current source module.

[0016] Optionally, the comparator unit further includes a ninth NMOS transistor and a tenth NMOS transistor, wherein: the drain of the ninth NMOS transistor is coupled to the source of the second NMOS transistor, and the source is coupled to the drain of the tenth NMOS transistor; the gate of the tenth NMOS transistor is coupled to the control terminal of the tail current source module, and the source is grounded.

[0017] This invention also provides a driving circuit, including a charge pump and any of the charge pump start-up circuits described above, wherein the charge pump start-up circuit is coupled to the charge pump and is adapted to drive the charge pump to start.

[0018] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0019] The comparator unit receives the positive voltage output from the charge pump at its first input terminal and the power supply voltage at its second input terminal. The output terminal of the comparator unit is coupled to the control terminal of the first switching unit. When the positive voltage output by the charge pump is less than the power supply voltage, the first switching unit is turned on, allowing the positive voltage output by the charge pump to quickly reach the power supply voltage, effectively improving the charge pump's build-up speed.

[0020] Furthermore, the comparator unit includes an inverter unit, a second switching unit, and a first pull-down unit. The output of the inverter unit controls the second switching unit. When the second switching unit is turned on, the first pull-down unit quickly pulls down the output voltage of the comparator unit, which can prevent the output voltage of the comparator unit from establishing a large initial value at the moment of power-on, thereby avoiding affecting the build-up speed of the charge pump. Attached Figure Description

[0021] Figure 1 This is a circuit structure diagram of a charge pump start-up circuit according to an embodiment of the present invention;

[0022] Figure 2 This is a circuit structure diagram of a comparator unit in an embodiment of the present invention;

[0023] Figure 3 This is a circuit structure diagram of another comparator unit in an embodiment of the present invention. Detailed Implementation

[0024] As mentioned above, in the prior art, the build-up time of charge pumps is relatively slow.

[0025] In this embodiment of the invention, the first input terminal of the comparator unit receives the positive voltage output by the charge pump, the second input terminal of the comparator unit receives the power supply voltage, and the output terminal of the comparator unit is coupled to the control terminal of the first switching unit. When the positive voltage output by the charge pump is less than the power supply voltage, the first switching unit is turned on, thereby enabling the positive voltage output by the charge pump to quickly reach the power supply voltage, effectively improving the charge pump's build-up speed.

[0026] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0027] In this embodiment of the invention, the charge pump starting unit can be coupled to the charge pump and start the charge pump according to the output of the charge pump.

[0028] In practice, the charge pump setup process can be divided into two stages: the first stage is from 0 to the power supply voltage VDD, and the second stage is from VDD to twice VDD. The setup time of the second stage depends on the performance of the charge pump itself. This embodiment of the invention focuses on the rapid start-up of the first stage.

[0029] In this embodiment of the invention, the charge pump start-up unit may include: a comparator unit and a first switching unit, wherein:

[0030] The first input terminal of the comparator unit receives the positive voltage output from the charge pump, the second input terminal of the comparator unit receives the power supply voltage, the output terminal of the comparator unit is coupled to the control terminal of the first switching unit, and the power supply terminal of the comparator unit receives the positive voltage output from the charge pump.

[0031] The first input terminal of the first switching unit receives the positive voltage output by the charge pump, and the second input terminal of the first switching unit receives the power supply voltage.

[0032] In this embodiment of the invention, when the positive voltage output by the charge pump is less than the power supply voltage, the first switching unit is turned on under the control of the output voltage of the comparator unit, thereby enabling the positive voltage output by the charge pump to be quickly boosted to the power supply voltage.

[0033] In specific implementations, the first switching unit may include a PMOS transistor or a group of PMOS transistors, or an NMOS transistor or a group of NMOS transistors. It is understood that the first switching unit may also be other types of switching units, as long as they satisfy the following conditions: having one control terminal and two input terminals; and being turned on under the control of the comparator unit's output voltage when the positive voltage output by the charge pump is less than the power supply voltage; and being turned off under the control of the comparator unit's output voltage when the positive voltage output by the charge pump is greater than the power supply voltage.

[0034] In practice, the power supply voltage can be twice the positive voltage generated by the charge pump, i.e., VDD = 2 × VPOS.

[0035] In this embodiment of the invention, the charge pump start-up circuit may further include an impedance unit, which may be disposed between the output terminal of the comparator unit and the control terminal of the first switching unit.

[0036] In practical implementation, the impedance unit can be a high-precision resistor. The first end of the high-precision resistor can be coupled to the output terminal of the comparator unit, and the second end of the high-precision resistor can be coupled to the control terminal of the first switching unit.

[0037] Reference Figure 1 The present invention provides a charge pump start-up unit according to an embodiment. The impedance device is a resistor R1. The first switching unit includes a first PMOS transistor MP1.

[0038] In a specific implementation, the first input terminal (VIP terminal, i.e. "+" input terminal) of the comparator unit COMP is input with the positive voltage VPOS output by the charge pump, the second input terminal (VIN terminal, i.e. "-" input terminal) of the comparator unit is input with the power supply voltage VDD, the power supply terminal of the comparator unit COMP is input with the positive voltage VPOS output by the charge pump, and the output terminal of the comparator unit COMP is coupled to the first terminal of the resistor R1.

[0039] The second end of resistor R1 is coupled to the gate of the first PMOS transistor MP1;

[0040] The source input of the first PMOS transistor MP1 is the positive voltage VPOS output by the charge pump, and the drain input of the first PMOS transistor MP1 is the power supply voltage VDD.

[0041] Depend on Figure 1 The charge pump startup unit provided in the diagram operates as follows: when the positive voltage VPOS output by the charge pump is less than the power supply voltage VDD, the output voltage of the comparator unit COMP is 0. The first PMOS transistor MP1 is turned on with its gate at a low level, thus enabling the positive voltage VPOS output by the charge pump to quickly equalize the power supply voltage VDD. When the positive voltage VPOS output by the charge pump is greater than the power supply voltage VDD, the output voltage of the comparator unit COMP is high, and the first PMOS transistor MP1 is turned off with its control terminal at a high level, thereby completing the charge pump startup.

[0042] In this embodiment of the invention, the comparator unit COMP may further include a bias current terminal, which receives a bias current IB.

[0043] In this embodiment of the invention, the comparator unit COMP may include a first output module, a differential pair module, a tail current source module, and a mirror module.

[0044] In a specific implementation, the input terminal of the first output module can be coupled to the first input terminal of the comparator unit COMP, and the output terminal of the first output module can be coupled to the output terminal of the comparator unit COMP.

[0045] The first terminal of the differential pair module can be coupled to the second input terminal of the comparator unit COMP, and the second terminal of the differential pair module can be coupled to the power supply terminal of the comparator unit COMP.

[0046] The tail current source module can be coupled between the differential pair module and ground GND, and the control terminal of the tail current source module can be coupled to the bias current terminal of the comparator unit COMP.

[0047] One end of the mirror module can be coupled to the bias current source of the comparator unit COMP, and the other end of the mirror module can be coupled to the tail current source module.

[0048] The specific structure of the comparison unit provided above is explained below. (Refer to...) Figure 2 The present invention provides a circuit structure diagram of a comparator unit in an embodiment of the present invention.

[0049] In this embodiment of the invention, the first-stage output unit may include a second PMOS transistor MP2 and a third PMOS transistor MP3, the differential pair module may include a first NMOS transistor MN1 and a second NMOS transistor MN2, the mirror module may include a third NMOS transistor MN3, and the tail current source module may include a fourth NMOS transistor MN4, wherein:

[0050] The source of the second PMOS transistor MP2 can be coupled to the first input terminal of the comparator unit. The gate of the second PMOS transistor MP2 is coupled to the gate of the third PMOS transistor MP3 and the drain of the first NMOS transistor MN1. The drain of the second PMOS transistor MP2 is coupled to the gate of the second PMOS transistor MP2 and the drain of the first NMOS transistor MN1.

[0051] The source of the third PMOS transistor MP3 is coupled to the source of the second PMOS transistor MP2, and the drain of the third PMOS transistor MP3 is coupled to the drain of the second NMOS transistor MN2. The output of the comparator unit is between the drain of the third PMOS transistor MP3 and the drain of the second NMOS transistor MN2. Therefore, the drain of the third PMOS transistor MP3 can be considered to be coupled to the output of the comparator unit. The output of the comparator unit is VOUT.

[0052] The drain of the first NMOS transistor MN1 is coupled to the gate and drain of the second PMOS transistor MP2. The gate of the first NMOS transistor MN1 is coupled to the second input terminal of the comparator unit. The source of the first NMOS transistor MN1 is coupled to the drain of the fourth NMOS transistor MN4. The gate of the first NMOS transistor MN1 is connected to the power supply voltage VDD.

[0053] The drain of the second NMOS transistor MN2 is coupled to the output terminal of the comparator unit COMP, the gate of the second NMOS transistor MN2 is coupled to the power supply terminal of the comparator unit, and the source of the second NMOS transistor MN2 is coupled to the drain of the fourth NMOS transistor MN4. The gate of the second NMOS transistor MN2 receives the positive voltage VPOS output by the charge pump. The substrates of the first NMOS transistor MN1 and the second NMOS transistor MN2 are grounded.

[0054] The drain of the third NMOS transistor MN3 is coupled to the bias current terminal of the comparator unit, the gate of the third NMOS transistor MN3 is coupled to the gate of the fourth NMOS transistor MN4, and the source of the third NMOS transistor MN3 is coupled to the source of the fourth NMOS transistor MN4.

[0055] The drain of the fourth NMOS transistor MN4 is coupled to the drain of the first NMOS transistor MN1 and the drain of the second NMOS transistor MN2. The gate of the fourth NMOS transistor MN4 is coupled to the gate of the third NMOS transistor MN3. The source of the fourth NMOS transistor MN4 is coupled to the ground terminal of the comparator unit. Since the ground terminal of the comparator unit is grounded, the source of the fourth NMOS transistor MN4 is actually grounded.

[0056] In the embodiments of the present invention, the above Figure 2 The comparator units provided can be existing comparator units. Those skilled in the art can understand the specific working principle, timing and functions that each corresponding module can achieve, which will not be elaborated here.

[0057] In a specific implementation, the comparator unit may also include a second-stage output module; the input terminal of the second-stage output module may be coupled to the first-stage output module, and the output terminal of the second-stage output module may be coupled to the output terminal of the comparator unit.

[0058] In other words, the comparator unit can include two stages of output: a first-stage output module and a second-stage output module.

[0059] In this embodiment of the invention, the second-stage output module may include a sixth PMOS transistor MP6 and a fifth NMOS transistor MN5. When a second-stage output module exists, the first-stage output module may further include a fourth PMOS transistor MP4 and a fifth PMOS transistor MP5, wherein:

[0060] The source of the fourth PMOS transistor MP4 can be coupled to the drain of the second PMOS transistor MP2, the gate of the fourth PMOS transistor MP4 can be coupled to the gate of the third PMOS transistor MP3 and the gate of the fifth PMOS transistor MP5, and the drain of the fourth PMOS transistor MP4 can be coupled to the drain of the first NMOS transistor MN1.

[0061] The source of the fifth PMOS transistor MP5 can be coupled to the drain of the third PMOS transistor MP3, the gate of the fifth PMOS transistor MP5 can be coupled to the drain of the fourth PMOS transistor MP4, and the drain of the fifth PMOS transistor MP5 can be coupled to the drain of the second NMOS transistor MN2.

[0062] The source of the sixth PMOS transistor MP6 can be connected to the positive voltage VPOS output by the charge pump. The gate of the sixth PMOS transistor MP6 can be coupled to the drain of the fifth PMOS transistor MP5. The drain of the sixth PMOS transistor MP6 can be coupled to the drain of the fifth NMOS transistor MN5 and the output of the comparator unit.

[0063] The gate of the fifth NMOS transistor MN5 can be coupled to the gate of the fourth NMOS transistor MN4, both of which are biased by input current; the source of the fifth PMOS transistor MP5 can be grounded.

[0064] In this embodiment of the invention, the comparator unit may further include an inverter unit, a second switching unit, and a first pull-down unit, wherein:

[0065] The input terminal of the inverter unit can be coupled to the output terminal of the comparator unit, and the output terminal of the inverter unit can be coupled to the control terminal of the second switching unit; the inverter unit can invert the voltage output from the output terminal of the comparator unit and output the inverted voltage to the control terminal of the second switching unit.

[0066] The first terminal of the second switching unit can be coupled to the first pull-down unit, and the second terminal of the second switching unit can be grounded;

[0067] The control terminal of the first pull-down unit can be coupled to the bias current terminal of the comparator unit, the first terminal of the first pull-down unit can be coupled to the output terminal of the comparator unit, and the second terminal of the first pull-down unit can be coupled to the first terminal of the second switch unit.

[0068] In this embodiment of the invention, the output of the inverter unit controls the second switching unit. When the second switching unit is turned on, the first pull-down unit quickly pulls down the output voltage of the comparator unit, which can prevent the output voltage of the comparator unit from establishing a large initial value at the moment of power-on, thereby avoiding the impact on the build-up speed of the charge pump.

[0069] In this embodiment of the invention, reference is made to Figure 3 The first pull-down unit may include the sixth NMOS transistor MN6, the second switching unit may include the seventh NMOS transistor MN7, and the inverter unit may include the eighth NMOS transistor MN8 and the seventh PMOS transistor MP7, wherein:

[0070] The drain of the sixth NMOS transistor MN6 is coupled to the output terminal of the comparator unit, the gate of the sixth NMOS transistor MN6 is coupled to the bias current terminal of the comparator unit, and the source of the sixth NMOS transistor MN6 is coupled to the gate of the seventh NMOS transistor MN7.

[0071] The drain of the seventh NMOS transistor MN7 is coupled to the source of the sixth NMOS transistor MN6, and the source of the seventh NMOS transistor MN7 is grounded.

[0072] The source of the seventh PMOS transistor MP7 is input to the positive voltage VPOS output by the charge pump. The gate of the seventh PMOS transistor MP7 is coupled to the output terminal of the comparator unit. The drain of the seventh PMOS transistor MP7 is coupled to the drain of the eighth NMOS transistor MN8.

[0073] The gate of the eighth NMOS transistor MN8 is coupled to the gate of the seventh PMOS transistor MP7, and the source of the eighth NMOS transistor MN8 is grounded.

[0074] In this embodiment of the invention, the comparator unit may further include a first pull-up unit. The first terminal of the first pull-up unit is coupled to the second input terminal of the comparator unit, the second terminal of the first pull-up unit is coupled to the control terminal of the tail current source module, and the control terminal of the first pull-up unit is coupled to the power supply terminal of the comparator unit.

[0075] In a specific implementation, the first pull-up unit may include an eighth PMOS transistor MP8. The source of the eighth PMOS transistor MP8 may be coupled to the second input terminal of the comparator unit, the gate of the eighth PMOS transistor MP8 may be coupled to the power supply terminal of the comparator unit, and the drain of the eighth PMOS transistor MP8 may be coupled to the control terminal of the tail current source module.

[0076] In a specific implementation, the comparator unit may also include a ninth NMOS transistor MN9 and a tenth NMOS transistor MN10, wherein:

[0077] The drain of the ninth NMOS transistor MN9 is coupled to the source of the second NMOS transistor MN2, and the source of the ninth NMOS transistor MN9 is coupled to the drain of the tenth NMOS transistor MN10.

[0078] The gate of the tenth NMOS transistor MN10 is coupled to the control terminal of the tail current source module, and the source of the tenth NMOS transistor MN10 is grounded.

[0079] The following is about the above. Figure 3 The working process of the comparator unit provided in the document will be explained.

[0080] In this embodiment of the invention, at the moment of power-on, the positive voltage VPOS output by the charge pump is equal to 0. The eighth PMOS transistor MP8 turns on, pulling up the gate voltages of the third NMOS transistor MN3, the fourth NMOS transistor MN4, the sixth NMOS transistor MN6, and the tenth NMOS transistor MN10. The tail current source is composed of the fourth NMOS transistor MN4 and the tenth NMOS transistor MN10, which is used to speed up the comparison time. At the same time, the sixth NMOS transistor MN6 and the seventh NMOS transistor MN7 can quickly pull the initially established VOUT to 0, completing the comparison. The above state is maintained until the positive voltage VPOS output by the charge pump is greater than the power supply voltage VDD. At this time, VOUT flips, and its magnitude is equal to the positive voltage VPOS output by the charge pump. The output of the inverter turns off the ninth NMOS transistor MN9 and the seventh NMOS transistor MN7. The tail current source is only the fourth NMOS transistor MN4. The small current will ensure that there is almost no voltage drop between VOUT and the positive voltage VPOS output by the charge pump, so that the first PMOS transistor MP1 remains in the off state thereafter, and the charge pump starts up.

[0081] It is understandable that the above Figure 3 If the comparator unit provided in the diagram is modified by removing the eighth PMOS transistor MP8, the ninth NMOS transistor MN9, the tenth NMOS transistor MN10, the sixth NMOS transistor MN6, the seventh NMOS transistor MN7, the eighth NMOS transistor, and the seventh PMOS transistor MP7, the remaining structure can be considered as a schematic diagram of a conventional two-stage output comparator unit.

[0082] This invention also provides a driving circuit, including the charge pump driving circuit and charge pump provided in any of the above embodiments, wherein: the charge pump start-up circuit can be coupled to the charge pump and is suitable for driving the charge pump to start.

[0083] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A charge pump starting circuit, characterized in that, include: The comparator unit and the first switching unit, wherein: The comparator unit has a first input terminal receiving the positive voltage output by the charge pump, a second input terminal receiving the power supply voltage, an output terminal coupled to the control terminal of the first switching unit, and a power supply terminal receiving the positive voltage output by the charge pump. The comparator unit includes an inverter unit, a second switching unit, and a first pull-down unit. Specifically: the inverter unit's input terminal is coupled to the output terminal of the comparator unit, and its output terminal is coupled to the control terminal of the second switching unit; the second switching unit has a first terminal coupled to the first pull-down unit and a second terminal grounded; the first pull-down unit has a control terminal coupled to the bias current terminal of the comparator unit, a first terminal coupled to the output terminal of the comparator unit, and a second terminal coupled to the first terminal of the second switching unit; the comparator unit further includes a first pull-up unit, with a first terminal coupled to the second input terminal of the comparator unit, a second terminal coupled to the control terminal of the tail current source module in the comparator unit, and the control terminal coupled to the power supply terminal of the comparator unit. The first pull-down unit includes a sixth NMOS transistor, the second switching unit includes a seventh NMOS transistor, and the inverter unit includes an eighth NMOS transistor and a seventh PMOS transistor. Specifically: the drain of the sixth NMOS transistor is coupled to the output terminal of the comparator unit, its gate is coupled to the bias current terminal of the comparator unit, and its source is coupled to the gate of the seventh NMOS transistor; the drain of the seventh NMOS transistor is coupled to the source of the sixth NMOS transistor, and its source is grounded; the source of the seventh PMOS transistor receives the positive voltage output from the charge pump, its gate is coupled to the output terminal of the comparator unit, and its drain is coupled to the drain of the eighth NMOS transistor; the gate of the eighth NMOS transistor is coupled to the gate of the seventh PMOS transistor, and its source is grounded. The first pull-up unit includes an eighth PMOS transistor, the source of which is coupled to the second input terminal of the comparator unit, the gate of which is coupled to the power supply terminal of the comparator unit, and the drain of which is coupled to the control terminal of the tail current source module. The comparator unit further includes a ninth NMOS transistor and a tenth NMOS transistor, wherein: the drain of the ninth NMOS transistor is coupled to the differential pair module of the comparator unit, and the source is coupled to the drain of the tenth NMOS transistor; the gate of the tenth NMOS transistor is coupled to the control terminal of the tail current source module, and the source is grounded; The first switching unit has a first terminal receiving the positive voltage output by the charge pump and a second terminal receiving the power supply voltage.

2. The charge pump start-up circuit as described in claim 1, characterized in that, Also includes: An impedance unit is disposed between the output terminal of the comparator unit and the control terminal of the first switching unit.

3. The charge pump start-up circuit as described in claim 1, characterized in that, The first switching unit includes: a first PMOS transistor; wherein: The first PMOS transistor has its gate coupled to the output terminal of the comparator unit, its source input is the positive voltage output by the charge pump, and its drain input is the power supply voltage.

4. The charge pump start-up circuit as described in claim 1, characterized in that, The comparator unit includes: a first-stage output module, a differential pair transistor module, a tail current source module, and a mirror module, wherein: The first-stage output module has its input terminal coupled to the first input terminal of the comparator unit, and its output terminal coupled to the output terminal of the comparator unit. The differential pair module has a first terminal coupled to the second input terminal of the comparator unit, and a second terminal coupled to the power supply terminal of the comparator unit. The tail current source module is coupled between the differential pair transistor module and ground, and the control terminal is coupled to the bias current terminal of the comparator unit. The mirror module is coupled at one end to the bias current terminal of the comparator unit and at the other end to the tail current source module.

5. The charge pump start-up circuit as described in claim 4, characterized in that, The first-stage output module includes a second PMOS transistor and a third PMOS transistor; the differential pair module includes a first NMOS transistor and a second NMOS transistor; the mirror module includes a third NMOS transistor; and the tail current source module includes a fourth NMOS transistor; wherein: The source of the second PMOS transistor is coupled to the first input terminal of the comparator unit, and the gate is coupled to the gate of the third PMOS transistor and the drain of the first NMOS transistor, and the drain is coupled to the drain of the first NMOS transistor. The source of the third PMOS transistor is coupled to the source of the second PMOS transistor, and the drain is coupled to the output of the comparator unit. The gate of the first NMOS transistor is coupled to the second input terminal of the comparator unit, and the source is coupled to the drain of the fourth NMOS transistor. The drain of the second NMOS transistor is coupled to the output terminal of the comparator unit, the gate is coupled to the power supply terminal of the comparator unit, and the source is coupled to the source of the first NMOS transistor. The drain of the third NMOS transistor is coupled to the bias current terminal of the comparator unit, the gate is coupled to the gate of the fourth NMOS transistor, and the source is coupled to the source of the fourth NMOS transistor. The source of the fourth NMOS transistor is coupled to the ground terminal of the comparator unit.

6. The charge pump start-up circuit as described in claim 5, characterized in that, The comparator unit further includes: a second-stage output module; The second-stage output module has its input terminal coupled to the first-stage output module and its output terminal coupled to the output terminal of the comparator unit.

7. The charge pump start-up circuit as described in claim 6, characterized in that, The second-stage output module includes a sixth PMOS transistor and a fifth NMOS transistor; the first-stage output module also includes a fourth PMOS transistor and a fifth PMOS transistor; wherein: The source of the fourth PMOS transistor is coupled to the drain of the second PMOS transistor, the gate is coupled to the gate of the third PMOS transistor and the gate of the fifth PMOS transistor, and the drain is coupled to the drain of the first NMOS transistor. The source of the fifth PMOS transistor is coupled to the drain of the third PMOS transistor, the gate is coupled to the drain of the fourth PMOS transistor, and the drain is coupled to the drain of the second NMOS transistor. The sixth PMOS transistor receives the positive voltage output by the charge pump at its source, its gate is coupled to the drain of the fifth PMOS transistor, its drain is coupled to the drain of the fifth NMOS transistor, and its output terminal is coupled to the comparator unit. The fifth NMOS transistor has its gate coupled to the gate of the fourth NMOS transistor, and its source is grounded.

8. A driving circuit, characterized in that, include: A charge pump, and a charge pump start-up circuit as described in any one of claims 1 to 7, wherein: the charge pump start-up circuit is coupled to the charge pump and is adapted to drive the charge pump to start.

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